?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.19-rc7
[linux-2.6/btrfs-unstable.git] / drivers / spi / spi-sh-msiof.c
blob101cd6aae2ea520afcac89671071cdabe2341f8f
1 /*
2 * SuperH MSIOF SPI Master Interface
3 *
4 * Copyright (c) 2009 Magnus Damm
5 * Copyright (C) 2014 Renesas Electronics Corporation
6 * Copyright (C) 2014-2017 Glider bvba
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14 #include <linux/bitmap.h>
15 #include <linux/clk.h>
16 #include <linux/completion.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/dmaengine.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/interrupt.h>
24 #include <linux/io.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/of.h>
28 #include <linux/of_device.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/sh_dma.h>
32
33 #include <linux/spi/sh_msiof.h>
34 #include <linux/spi/spi.h>
35
36 #include <asm/unaligned.h>
37
38 struct sh_msiof_chipdata {
39 u16 tx_fifo_size;
40 u16 rx_fifo_size;
41 u16 master_flags;
42 u16 min_div_pow;
43 };
44
45 struct sh_msiof_spi_priv {
46 struct spi_master *master;
47 void __iomem *mapbase;
48 struct clk *clk;
49 struct platform_device *pdev;
50 struct sh_msiof_spi_info *info;
51 struct completion done;
52 struct completion done_txdma;
53 unsigned int tx_fifo_size;
54 unsigned int rx_fifo_size;
55 unsigned int min_div_pow;
56 void *tx_dma_page;
57 void *rx_dma_page;
58 dma_addr_t tx_dma_addr;
59 dma_addr_t rx_dma_addr;
60 unsigned short unused_ss;
61 bool native_cs_inited;
62 bool native_cs_high;
63 bool slave_aborted;
64 };
65
66 #define MAX_SS 3 /* Maximum number of native chip selects */
67
68 #define TMDR1 0x00 /* Transmit Mode Register 1 */
69 #define TMDR2 0x04 /* Transmit Mode Register 2 */
70 #define TMDR3 0x08 /* Transmit Mode Register 3 */
71 #define RMDR1 0x10 /* Receive Mode Register 1 */
72 #define RMDR2 0x14 /* Receive Mode Register 2 */
73 #define RMDR3 0x18 /* Receive Mode Register 3 */
74 #define TSCR 0x20 /* Transmit Clock Select Register */
75 #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
76 #define CTR 0x28 /* Control Register */
77 #define FCTR 0x30 /* FIFO Control Register */
78 #define STR 0x40 /* Status Register */
79 #define IER 0x44 /* Interrupt Enable Register */
80 #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
81 #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
82 #define TFDR 0x50 /* Transmit FIFO Data Register */
83 #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
84 #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
85 #define RFDR 0x60 /* Receive FIFO Data Register */
86
87 /* TMDR1 and RMDR1 */
88 #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */
89 #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */
90 #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */
91 #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
92 #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
93 #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
94 #define MDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
95 #define MDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
96 #define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */
97 #define MDR1_FLD_SHIFT 2
98 #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
99 /* TMDR1 */
100 #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */
101 #define TMDR1_SYNCCH_MASK 0xc000000 /* Synchronization Signal Channel Select */
102 #define TMDR1_SYNCCH_SHIFT 26 /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
103
104 /* TMDR2 and RMDR2 */
105 #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
106 #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
107 #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */
108
109 /* TSCR and RSCR */
110 #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */
111 #define SCR_BRPS(i) (((i) - 1) << 8)
112 #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */
113 #define SCR_BRDV_DIV_2 0x0000
114 #define SCR_BRDV_DIV_4 0x0001
115 #define SCR_BRDV_DIV_8 0x0002
116 #define SCR_BRDV_DIV_16 0x0003
117 #define SCR_BRDV_DIV_32 0x0004
118 #define SCR_BRDV_DIV_1 0x0007
119
120 /* CTR */
121 #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */
122 #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */
123 #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
124 #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */
125 #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */
126 #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
127 #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
128 #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
129 #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */
130 #define CTR_TXDIZ_LOW 0x00000000 /* 0 */
131 #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */
132 #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */
133 #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */
134 #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */
135 #define CTR_TXE 0x00000200 /* Transmit Enable */
136 #define CTR_RXE 0x00000100 /* Receive Enable */
137
138 /* FCTR */
139 #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */
140 #define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */
141 #define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */
142 #define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */
143 #define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */
144 #define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */
145 #define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */
146 #define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */
147 #define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */
148 #define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */
149 #define FCTR_TFUA_SHIFT 20
150 #define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT)
151 #define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */
152 #define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */
153 #define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */
154 #define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */
155 #define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */
156 #define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */
157 #define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */
158 #define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */
159 #define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */
160 #define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */
161 #define FCTR_RFUA_SHIFT 4
162 #define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT)
163
164 /* STR */
165 #define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */
166 #define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */
167 #define STR_TEOF 0x00800000 /* Frame Transmission End */
168 #define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */
169 #define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */
170 #define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */
171 #define STR_RFFUL 0x00002000 /* Receive FIFO Full */
172 #define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */
173 #define STR_REOF 0x00000080 /* Frame Reception End */
174 #define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */
175 #define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */
176 #define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */
177
178 /* IER */
179 #define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */
180 #define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */
181 #define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */
182 #define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */
183 #define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */
184 #define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */
185 #define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */
186 #define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */
187 #define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */
188 #define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */
189 #define IER_REOFE 0x00000080 /* Frame Reception End Enable */
190 #define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */
191 #define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */
192 #define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */
193
194
195 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
196 {
197 switch (reg_offs) {
198 case TSCR:
199 case RSCR:
200 return ioread16(p->mapbase + reg_offs);
201 default:
202 return ioread32(p->mapbase + reg_offs);
203 }
204 }
205
206 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
207 u32 value)
208 {
209 switch (reg_offs) {
210 case TSCR:
211 case RSCR:
212 iowrite16(value, p->mapbase + reg_offs);
213 break;
214 default:
215 iowrite32(value, p->mapbase + reg_offs);
216 break;
217 }
218 }
219
220 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
221 u32 clr, u32 set)
222 {
223 u32 mask = clr | set;
224 u32 data;
225 int k;
226
227 data = sh_msiof_read(p, CTR);
228 data &= ~clr;
229 data |= set;
230 sh_msiof_write(p, CTR, data);
231
232 for (k = 100; k > 0; k--) {
233 if ((sh_msiof_read(p, CTR) & mask) == set)
234 break;
235
236 udelay(10);
237 }
238
239 return k > 0 ? 0 : -ETIMEDOUT;
240 }
241
242 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
243 {
244 struct sh_msiof_spi_priv *p = data;
245
246 /* just disable the interrupt and wake up */
247 sh_msiof_write(p, IER, 0);
248 complete(&p->done);
249
250 return IRQ_HANDLED;
251 }
252
253 static const u32 sh_msiof_spi_div_array[] = {
254 SCR_BRDV_DIV_1, SCR_BRDV_DIV_2, SCR_BRDV_DIV_4,
255 SCR_BRDV_DIV_8, SCR_BRDV_DIV_16, SCR_BRDV_DIV_32,
256 };
257
258 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
259 unsigned long parent_rate, u32 spi_hz)
260 {
261 unsigned long div;
262 u32 brps, scr;
263 unsigned int div_pow = p->min_div_pow;
264
265 if (!spi_hz || !parent_rate) {
266 WARN(1, "Invalid clock rate parameters %lu and %u\n",
267 parent_rate, spi_hz);
268 return;
269 }
270
271 div = DIV_ROUND_UP(parent_rate, spi_hz);
272 if (div <= 1024) {
273 /* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
274 if (!div_pow && div <= 32 && div > 2)
275 div_pow = 1;
276
277 if (div_pow)
278 brps = (div + 1) >> div_pow;
279 else
280 brps = div;
281
282 for (; brps > 32; div_pow++)
283 brps = (brps + 1) >> 1;
284 } else {
285 /* Set transfer rate composite divisor to 2^5 * 32 = 1024 */
286 dev_err(&p->pdev->dev,
287 "Requested SPI transfer rate %d is too low\n", spi_hz);
288 div_pow = 5;
289 brps = 32;
290 }
291
292 scr = sh_msiof_spi_div_array[div_pow] | SCR_BRPS(brps);
293 sh_msiof_write(p, TSCR, scr);
294 if (!(p->master->flags & SPI_MASTER_MUST_TX))
295 sh_msiof_write(p, RSCR, scr);
296 }
297
298 static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
299 {
300 /*
301 * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl
302 * b'000 : 0
303 * b'001 : 100
304 * b'010 : 200
305 * b'011 (SYNCDL only) : 300
306 * b'101 : 50
307 * b'110 : 150
308 */
309 if (dtdl_or_syncdl % 100)
310 return dtdl_or_syncdl / 100 + 5;
311 else
312 return dtdl_or_syncdl / 100;
313 }
314
315 static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
316 {
317 u32 val;
318
319 if (!p->info)
320 return 0;
321
322 /* check if DTDL and SYNCDL is allowed value */
323 if (p->info->dtdl > 200 || p->info->syncdl > 300) {
324 dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n");
325 return 0;
326 }
327
328 /* check if the sum of DTDL and SYNCDL becomes an integer value */
329 if ((p->info->dtdl + p->info->syncdl) % 100) {
330 dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n");
331 return 0;
332 }
333
334 val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT;
335 val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT;
336
337 return val;
338 }
339
340 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss,
341 u32 cpol, u32 cpha,
342 u32 tx_hi_z, u32 lsb_first, u32 cs_high)
343 {
344 u32 tmp;
345 int edge;
346
347 /*
348 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
349 * 0 0 10 10 1 1
350 * 0 1 10 10 0 0
351 * 1 0 11 11 0 0
352 * 1 1 11 11 1 1
353 */
354 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
355 tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
356 tmp |= lsb_first << MDR1_BITLSB_SHIFT;
357 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
358 if (spi_controller_is_slave(p->master)) {
359 sh_msiof_write(p, TMDR1, tmp | TMDR1_PCON);
360 } else {
361 sh_msiof_write(p, TMDR1,
362 tmp | MDR1_TRMD | TMDR1_PCON |
363 (ss < MAX_SS ? ss : 0) << TMDR1_SYNCCH_SHIFT);
364 }
365 if (p->master->flags & SPI_MASTER_MUST_TX) {
366 /* These bits are reserved if RX needs TX */
367 tmp &= ~0x0000ffff;
368 }
369 sh_msiof_write(p, RMDR1, tmp);
370
371 tmp = 0;
372 tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
373 tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
374
375 edge = cpol ^ !cpha;
376
377 tmp |= edge << CTR_TEDG_SHIFT;
378 tmp |= edge << CTR_REDG_SHIFT;
379 tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
380 sh_msiof_write(p, CTR, tmp);
381 }
382
383 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
384 const void *tx_buf, void *rx_buf,
385 u32 bits, u32 words)
386 {
387 u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
388
389 if (tx_buf || (p->master->flags & SPI_MASTER_MUST_TX))
390 sh_msiof_write(p, TMDR2, dr2);
391 else
392 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
393
394 if (rx_buf)
395 sh_msiof_write(p, RMDR2, dr2);
396 }
397
398 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
399 {
400 sh_msiof_write(p, STR,
401 sh_msiof_read(p, STR) & ~(STR_TDREQ | STR_RDREQ));
402 }
403
404 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
405 const void *tx_buf, int words, int fs)
406 {
407 const u8 *buf_8 = tx_buf;
408 int k;
409
410 for (k = 0; k < words; k++)
411 sh_msiof_write(p, TFDR, buf_8[k] << fs);
412 }
413
414 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
415 const void *tx_buf, int words, int fs)
416 {
417 const u16 *buf_16 = tx_buf;
418 int k;
419
420 for (k = 0; k < words; k++)
421 sh_msiof_write(p, TFDR, buf_16[k] << fs);
422 }
423
424 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
425 const void *tx_buf, int words, int fs)
426 {
427 const u16 *buf_16 = tx_buf;
428 int k;
429
430 for (k = 0; k < words; k++)
431 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
432 }
433
434 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
435 const void *tx_buf, int words, int fs)
436 {
437 const u32 *buf_32 = tx_buf;
438 int k;
439
440 for (k = 0; k < words; k++)
441 sh_msiof_write(p, TFDR, buf_32[k] << fs);
442 }
443
444 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
445 const void *tx_buf, int words, int fs)
446 {
447 const u32 *buf_32 = tx_buf;
448 int k;
449
450 for (k = 0; k < words; k++)
451 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
452 }
453
454 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
455 const void *tx_buf, int words, int fs)
456 {
457 const u32 *buf_32 = tx_buf;
458 int k;
459
460 for (k = 0; k < words; k++)
461 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
462 }
463
464 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
465 const void *tx_buf, int words, int fs)
466 {
467 const u32 *buf_32 = tx_buf;
468 int k;
469
470 for (k = 0; k < words; k++)
471 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
472 }
473
474 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
475 void *rx_buf, int words, int fs)
476 {
477 u8 *buf_8 = rx_buf;
478 int k;
479
480 for (k = 0; k < words; k++)
481 buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
482 }
483
484 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
485 void *rx_buf, int words, int fs)
486 {
487 u16 *buf_16 = rx_buf;
488 int k;
489
490 for (k = 0; k < words; k++)
491 buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
492 }
493
494 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
495 void *rx_buf, int words, int fs)
496 {
497 u16 *buf_16 = rx_buf;
498 int k;
499
500 for (k = 0; k < words; k++)
501 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
502 }
503
504 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
505 void *rx_buf, int words, int fs)
506 {
507 u32 *buf_32 = rx_buf;
508 int k;
509
510 for (k = 0; k < words; k++)
511 buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
512 }
513
514 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
515 void *rx_buf, int words, int fs)
516 {
517 u32 *buf_32 = rx_buf;
518 int k;
519
520 for (k = 0; k < words; k++)
521 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
522 }
523
524 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
525 void *rx_buf, int words, int fs)
526 {
527 u32 *buf_32 = rx_buf;
528 int k;
529
530 for (k = 0; k < words; k++)
531 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
532 }
533
534 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
535 void *rx_buf, int words, int fs)
536 {
537 u32 *buf_32 = rx_buf;
538 int k;
539
540 for (k = 0; k < words; k++)
541 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
542 }
543
544 static int sh_msiof_spi_setup(struct spi_device *spi)
545 {
546 struct device_node *np = spi->master->dev.of_node;
547 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
548 u32 clr, set, tmp;
549
550 if (!np) {
551 /*
552 * Use spi->controller_data for CS (same strategy as spi_gpio),
553 * if any. otherwise let HW control CS
554 */
555 spi->cs_gpio = (uintptr_t)spi->controller_data;
556 }
557
558 if (gpio_is_valid(spi->cs_gpio)) {
559 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
560 return 0;
561 }
562
563 if (spi_controller_is_slave(p->master))
564 return 0;
565
566 if (p->native_cs_inited &&
567 (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH)))
568 return 0;
569
570 /* Configure native chip select mode/polarity early */
571 clr = MDR1_SYNCMD_MASK;
572 set = MDR1_SYNCMD_SPI;
573 if (spi->mode & SPI_CS_HIGH)
574 clr |= BIT(MDR1_SYNCAC_SHIFT);
575 else
576 set |= BIT(MDR1_SYNCAC_SHIFT);
577 pm_runtime_get_sync(&p->pdev->dev);
578 tmp = sh_msiof_read(p, TMDR1) & ~clr;
579 sh_msiof_write(p, TMDR1, tmp | set | MDR1_TRMD | TMDR1_PCON);
580 tmp = sh_msiof_read(p, RMDR1) & ~clr;
581 sh_msiof_write(p, RMDR1, tmp | set);
582 pm_runtime_put(&p->pdev->dev);
583 p->native_cs_high = spi->mode & SPI_CS_HIGH;
584 p->native_cs_inited = true;
585 return 0;
586 }
587
588 static int sh_msiof_prepare_message(struct spi_master *master,
589 struct spi_message *msg)
590 {
591 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
592 const struct spi_device *spi = msg->spi;
593 u32 ss, cs_high;
594
595 /* Configure pins before asserting CS */
596 if (gpio_is_valid(spi->cs_gpio)) {
597 ss = p->unused_ss;
598 cs_high = p->native_cs_high;
599 } else {
600 ss = spi->chip_select;
601 cs_high = !!(spi->mode & SPI_CS_HIGH);
602 }
603 sh_msiof_spi_set_pin_regs(p, ss, !!(spi->mode & SPI_CPOL),
604 !!(spi->mode & SPI_CPHA),
605 !!(spi->mode & SPI_3WIRE),
606 !!(spi->mode & SPI_LSB_FIRST), cs_high);
607 return 0;
608 }
609
610 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
611 {
612 bool slave = spi_controller_is_slave(p->master);
613 int ret = 0;
614
615 /* setup clock and rx/tx signals */
616 if (!slave)
617 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
618 if (rx_buf && !ret)
619 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
620 if (!ret)
621 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
622
623 /* start by setting frame bit */
624 if (!ret && !slave)
625 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
626
627 return ret;
628 }
629
630 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
631 {
632 bool slave = spi_controller_is_slave(p->master);
633 int ret = 0;
634
635 /* shut down frame, rx/tx and clock signals */
636 if (!slave)
637 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
638 if (!ret)
639 ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
640 if (rx_buf && !ret)
641 ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
642 if (!ret && !slave)
643 ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
644
645 return ret;
646 }
647
648 static int sh_msiof_slave_abort(struct spi_master *master)
649 {
650 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
651
652 p->slave_aborted = true;
653 complete(&p->done);
654 complete(&p->done_txdma);
655 return 0;
656 }
657
658 static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p,
659 struct completion *x)
660 {
661 if (spi_controller_is_slave(p->master)) {
662 if (wait_for_completion_interruptible(x) ||
663 p->slave_aborted) {
664 dev_dbg(&p->pdev->dev, "interrupted\n");
665 return -EINTR;
666 }
667 } else {
668 if (!wait_for_completion_timeout(x, HZ)) {
669 dev_err(&p->pdev->dev, "timeout\n");
670 return -ETIMEDOUT;
671 }
672 }
673
674 return 0;
675 }
676
677 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
678 void (*tx_fifo)(struct sh_msiof_spi_priv *,
679 const void *, int, int),
680 void (*rx_fifo)(struct sh_msiof_spi_priv *,
681 void *, int, int),
682 const void *tx_buf, void *rx_buf,
683 int words, int bits)
684 {
685 int fifo_shift;
686 int ret;
687
688 /* limit maximum word transfer to rx/tx fifo size */
689 if (tx_buf)
690 words = min_t(int, words, p->tx_fifo_size);
691 if (rx_buf)
692 words = min_t(int, words, p->rx_fifo_size);
693
694 /* the fifo contents need shifting */
695 fifo_shift = 32 - bits;
696
697 /* default FIFO watermarks for PIO */
698 sh_msiof_write(p, FCTR, 0);
699
700 /* setup msiof transfer mode registers */
701 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
702 sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE);
703
704 /* write tx fifo */
705 if (tx_buf)
706 tx_fifo(p, tx_buf, words, fifo_shift);
707
708 reinit_completion(&p->done);
709 p->slave_aborted = false;
710
711 ret = sh_msiof_spi_start(p, rx_buf);
712 if (ret) {
713 dev_err(&p->pdev->dev, "failed to start hardware\n");
714 goto stop_ier;
715 }
716
717 /* wait for tx fifo to be emptied / rx fifo to be filled */
718 ret = sh_msiof_wait_for_completion(p, &p->done);
719 if (ret)
720 goto stop_reset;
721
722 /* read rx fifo */
723 if (rx_buf)
724 rx_fifo(p, rx_buf, words, fifo_shift);
725
726 /* clear status bits */
727 sh_msiof_reset_str(p);
728
729 ret = sh_msiof_spi_stop(p, rx_buf);
730 if (ret) {
731 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
732 return ret;
733 }
734
735 return words;
736
737 stop_reset:
738 sh_msiof_reset_str(p);
739 sh_msiof_spi_stop(p, rx_buf);
740 stop_ier:
741 sh_msiof_write(p, IER, 0);
742 return ret;
743 }
744
745 static void sh_msiof_dma_complete(void *arg)
746 {
747 complete(arg);
748 }
749
750 static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
751 void *rx, unsigned int len)
752 {
753 u32 ier_bits = 0;
754 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
755 dma_cookie_t cookie;
756 int ret;
757
758 /* First prepare and submit the DMA request(s), as this may fail */
759 if (rx) {
760 ier_bits |= IER_RDREQE | IER_RDMAE;
761 desc_rx = dmaengine_prep_slave_single(p->master->dma_rx,
762 p->rx_dma_addr, len, DMA_DEV_TO_MEM,
763 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
764 if (!desc_rx)
765 return -EAGAIN;
766
767 desc_rx->callback = sh_msiof_dma_complete;
768 desc_rx->callback_param = &p->done;
769 cookie = dmaengine_submit(desc_rx);
770 if (dma_submit_error(cookie))
771 return cookie;
772 }
773
774 if (tx) {
775 ier_bits |= IER_TDREQE | IER_TDMAE;
776 dma_sync_single_for_device(p->master->dma_tx->device->dev,
777 p->tx_dma_addr, len, DMA_TO_DEVICE);
778 desc_tx = dmaengine_prep_slave_single(p->master->dma_tx,
779 p->tx_dma_addr, len, DMA_MEM_TO_DEV,
780 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
781 if (!desc_tx) {
782 ret = -EAGAIN;
783 goto no_dma_tx;
784 }
785
786 desc_tx->callback = sh_msiof_dma_complete;
787 desc_tx->callback_param = &p->done_txdma;
788 cookie = dmaengine_submit(desc_tx);
789 if (dma_submit_error(cookie)) {
790 ret = cookie;
791 goto no_dma_tx;
792 }
793 }
794
795 /* 1 stage FIFO watermarks for DMA */
796 sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1);
797
798 /* setup msiof transfer mode registers (32-bit words) */
799 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
800
801 sh_msiof_write(p, IER, ier_bits);
802
803 reinit_completion(&p->done);
804 if (tx)
805 reinit_completion(&p->done_txdma);
806 p->slave_aborted = false;
807
808 /* Now start DMA */
809 if (rx)
810 dma_async_issue_pending(p->master->dma_rx);
811 if (tx)
812 dma_async_issue_pending(p->master->dma_tx);
813
814 ret = sh_msiof_spi_start(p, rx);
815 if (ret) {
816 dev_err(&p->pdev->dev, "failed to start hardware\n");
817 goto stop_dma;
818 }
819
820 if (tx) {
821 /* wait for tx DMA completion */
822 ret = sh_msiof_wait_for_completion(p, &p->done_txdma);
823 if (ret)
824 goto stop_reset;
825 }
826
827 if (rx) {
828 /* wait for rx DMA completion */
829 ret = sh_msiof_wait_for_completion(p, &p->done);
830 if (ret)
831 goto stop_reset;
832
833 sh_msiof_write(p, IER, 0);
834 } else {
835 /* wait for tx fifo to be emptied */
836 sh_msiof_write(p, IER, IER_TEOFE);
837 ret = sh_msiof_wait_for_completion(p, &p->done);
838 if (ret)
839 goto stop_reset;
840 }
841
842 /* clear status bits */
843 sh_msiof_reset_str(p);
844
845 ret = sh_msiof_spi_stop(p, rx);
846 if (ret) {
847 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
848 return ret;
849 }
850
851 if (rx)
852 dma_sync_single_for_cpu(p->master->dma_rx->device->dev,
853 p->rx_dma_addr, len,
854 DMA_FROM_DEVICE);
855
856 return 0;
857
858 stop_reset:
859 sh_msiof_reset_str(p);
860 sh_msiof_spi_stop(p, rx);
861 stop_dma:
862 if (tx)
863 dmaengine_terminate_all(p->master->dma_tx);
864 no_dma_tx:
865 if (rx)
866 dmaengine_terminate_all(p->master->dma_rx);
867 sh_msiof_write(p, IER, 0);
868 return ret;
869 }
870
871 static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words)
872 {
873 /* src or dst can be unaligned, but not both */
874 if ((unsigned long)src & 3) {
875 while (words--) {
876 *dst++ = swab32(get_unaligned(src));
877 src++;
878 }
879 } else if ((unsigned long)dst & 3) {
880 while (words--) {
881 put_unaligned(swab32(*src++), dst);
882 dst++;
883 }
884 } else {
885 while (words--)
886 *dst++ = swab32(*src++);
887 }
888 }
889
890 static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words)
891 {
892 /* src or dst can be unaligned, but not both */
893 if ((unsigned long)src & 3) {
894 while (words--) {
895 *dst++ = swahw32(get_unaligned(src));
896 src++;
897 }
898 } else if ((unsigned long)dst & 3) {
899 while (words--) {
900 put_unaligned(swahw32(*src++), dst);
901 dst++;
902 }
903 } else {
904 while (words--)
905 *dst++ = swahw32(*src++);
906 }
907 }
908
909 static void copy_plain32(u32 *dst, const u32 *src, unsigned int words)
910 {
911 memcpy(dst, src, words * 4);
912 }
913
914 static int sh_msiof_transfer_one(struct spi_master *master,
915 struct spi_device *spi,
916 struct spi_transfer *t)
917 {
918 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
919 void (*copy32)(u32 *, const u32 *, unsigned int);
920 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
921 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
922 const void *tx_buf = t->tx_buf;
923 void *rx_buf = t->rx_buf;
924 unsigned int len = t->len;
925 unsigned int bits = t->bits_per_word;
926 unsigned int bytes_per_word;
927 unsigned int words;
928 int n;
929 bool swab;
930 int ret;
931
932 /* setup clocks (clock already enabled in chipselect()) */
933 if (!spi_controller_is_slave(p->master))
934 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
935
936 while (master->dma_tx && len > 15) {
937 /*
938 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit
939 * words, with byte resp. word swapping.
940 */
941 unsigned int l = 0;
942
943 if (tx_buf)
944 l = min(len, p->tx_fifo_size * 4);
945 if (rx_buf)
946 l = min(len, p->rx_fifo_size * 4);
947
948 if (bits <= 8) {
949 if (l & 3)
950 break;
951 copy32 = copy_bswap32;
952 } else if (bits <= 16) {
953 if (l & 3)
954 break;
955 copy32 = copy_wswap32;
956 } else {
957 copy32 = copy_plain32;
958 }
959
960 if (tx_buf)
961 copy32(p->tx_dma_page, tx_buf, l / 4);
962
963 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l);
964 if (ret == -EAGAIN) {
965 dev_warn_once(&p->pdev->dev,
966 "DMA not available, falling back to PIO\n");
967 break;
968 }
969 if (ret)
970 return ret;
971
972 if (rx_buf) {
973 copy32(rx_buf, p->rx_dma_page, l / 4);
974 rx_buf += l;
975 }
976 if (tx_buf)
977 tx_buf += l;
978
979 len -= l;
980 if (!len)
981 return 0;
982 }
983
984 if (bits <= 8 && len > 15 && !(len & 3)) {
985 bits = 32;
986 swab = true;
987 } else {
988 swab = false;
989 }
990
991 /* setup bytes per word and fifo read/write functions */
992 if (bits <= 8) {
993 bytes_per_word = 1;
994 tx_fifo = sh_msiof_spi_write_fifo_8;
995 rx_fifo = sh_msiof_spi_read_fifo_8;
996 } else if (bits <= 16) {
997 bytes_per_word = 2;
998 if ((unsigned long)tx_buf & 0x01)
999 tx_fifo = sh_msiof_spi_write_fifo_16u;
1000 else
1001 tx_fifo = sh_msiof_spi_write_fifo_16;
1002
1003 if ((unsigned long)rx_buf & 0x01)
1004 rx_fifo = sh_msiof_spi_read_fifo_16u;
1005 else
1006 rx_fifo = sh_msiof_spi_read_fifo_16;
1007 } else if (swab) {
1008 bytes_per_word = 4;
1009 if ((unsigned long)tx_buf & 0x03)
1010 tx_fifo = sh_msiof_spi_write_fifo_s32u;
1011 else
1012 tx_fifo = sh_msiof_spi_write_fifo_s32;
1013
1014 if ((unsigned long)rx_buf & 0x03)
1015 rx_fifo = sh_msiof_spi_read_fifo_s32u;
1016 else
1017 rx_fifo = sh_msiof_spi_read_fifo_s32;
1018 } else {
1019 bytes_per_word = 4;
1020 if ((unsigned long)tx_buf & 0x03)
1021 tx_fifo = sh_msiof_spi_write_fifo_32u;
1022 else
1023 tx_fifo = sh_msiof_spi_write_fifo_32;
1024
1025 if ((unsigned long)rx_buf & 0x03)
1026 rx_fifo = sh_msiof_spi_read_fifo_32u;
1027 else
1028 rx_fifo = sh_msiof_spi_read_fifo_32;
1029 }
1030
1031 /* transfer in fifo sized chunks */
1032 words = len / bytes_per_word;
1033
1034 while (words > 0) {
1035 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf,
1036 words, bits);
1037 if (n < 0)
1038 return n;
1039
1040 if (tx_buf)
1041 tx_buf += n * bytes_per_word;
1042 if (rx_buf)
1043 rx_buf += n * bytes_per_word;
1044 words -= n;
1045 }
1046
1047 return 0;
1048 }
1049
1050 static const struct sh_msiof_chipdata sh_data = {
1051 .tx_fifo_size = 64,
1052 .rx_fifo_size = 64,
1053 .master_flags = 0,
1054 .min_div_pow = 0,
1055 };
1056
1057 static const struct sh_msiof_chipdata rcar_gen2_data = {
1058 .tx_fifo_size = 64,
1059 .rx_fifo_size = 64,
1060 .master_flags = SPI_MASTER_MUST_TX,
1061 .min_div_pow = 0,
1062 };
1063
1064 static const struct sh_msiof_chipdata rcar_gen3_data = {
1065 .tx_fifo_size = 64,
1066 .rx_fifo_size = 64,
1067 .master_flags = SPI_MASTER_MUST_TX,
1068 .min_div_pow = 1,
1069 };
1070
1071 static const struct of_device_id sh_msiof_match[] = {
1072 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
1073 { .compatible = "renesas,msiof-r8a7743", .data = &rcar_gen2_data },
1074 { .compatible = "renesas,msiof-r8a7745", .data = &rcar_gen2_data },
1075 { .compatible = "renesas,msiof-r8a7790", .data = &rcar_gen2_data },
1076 { .compatible = "renesas,msiof-r8a7791", .data = &rcar_gen2_data },
1077 { .compatible = "renesas,msiof-r8a7792", .data = &rcar_gen2_data },
1078 { .compatible = "renesas,msiof-r8a7793", .data = &rcar_gen2_data },
1079 { .compatible = "renesas,msiof-r8a7794", .data = &rcar_gen2_data },
1080 { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data },
1081 { .compatible = "renesas,msiof-r8a7796", .data = &rcar_gen3_data },
1082 { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data },
1083 { .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */
1084 {},
1085 };
1086 MODULE_DEVICE_TABLE(of, sh_msiof_match);
1087
1088 #ifdef CONFIG_OF
1089 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1090 {
1091 struct sh_msiof_spi_info *info;
1092 struct device_node *np = dev->of_node;
1093 u32 num_cs = 1;
1094
1095 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
1096 if (!info)
1097 return NULL;
1098
1099 info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_SLAVE
1100 : MSIOF_SPI_MASTER;
1101
1102 /* Parse the MSIOF properties */
1103 if (info->mode == MSIOF_SPI_MASTER)
1104 of_property_read_u32(np, "num-cs", &num_cs);
1105 of_property_read_u32(np, "renesas,tx-fifo-size",
1106 &info->tx_fifo_override);
1107 of_property_read_u32(np, "renesas,rx-fifo-size",
1108 &info->rx_fifo_override);
1109 of_property_read_u32(np, "renesas,dtdl", &info->dtdl);
1110 of_property_read_u32(np, "renesas,syncdl", &info->syncdl);
1111
1112 info->num_chipselect = num_cs;
1113
1114 return info;
1115 }
1116 #else
1117 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1118 {
1119 return NULL;
1120 }
1121 #endif
1122
1123 static int sh_msiof_get_cs_gpios(struct sh_msiof_spi_priv *p)
1124 {
1125 struct device *dev = &p->pdev->dev;
1126 unsigned int used_ss_mask = 0;
1127 unsigned int cs_gpios = 0;
1128 unsigned int num_cs, i;
1129 int ret;
1130
1131 ret = gpiod_count(dev, "cs");
1132 if (ret <= 0)
1133 return 0;
1134
1135 num_cs = max_t(unsigned int, ret, p->master->num_chipselect);
1136 for (i = 0; i < num_cs; i++) {
1137 struct gpio_desc *gpiod;
1138
1139 gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1140 if (!IS_ERR(gpiod)) {
1141 cs_gpios++;
1142 continue;
1143 }
1144
1145 if (PTR_ERR(gpiod) != -ENOENT)
1146 return PTR_ERR(gpiod);
1147
1148 if (i >= MAX_SS) {
1149 dev_err(dev, "Invalid native chip select %d\n", i);
1150 return -EINVAL;
1151 }
1152 used_ss_mask |= BIT(i);
1153 }
1154 p->unused_ss = ffz(used_ss_mask);
1155 if (cs_gpios && p->unused_ss >= MAX_SS) {
1156 dev_err(dev, "No unused native chip select available\n");
1157 return -EINVAL;
1158 }
1159 return 0;
1160 }
1161
1162 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
1163 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
1164 {
1165 dma_cap_mask_t mask;
1166 struct dma_chan *chan;
1167 struct dma_slave_config cfg;
1168 int ret;
1169
1170 dma_cap_zero(mask);
1171 dma_cap_set(DMA_SLAVE, mask);
1172
1173 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1174 (void *)(unsigned long)id, dev,
1175 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1176 if (!chan) {
1177 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1178 return NULL;
1179 }
1180
1181 memset(&cfg, 0, sizeof(cfg));
1182 cfg.direction = dir;
1183 if (dir == DMA_MEM_TO_DEV) {
1184 cfg.dst_addr = port_addr;
1185 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1186 } else {
1187 cfg.src_addr = port_addr;
1188 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1189 }
1190
1191 ret = dmaengine_slave_config(chan, &cfg);
1192 if (ret) {
1193 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1194 dma_release_channel(chan);
1195 return NULL;
1196 }
1197
1198 return chan;
1199 }
1200
1201 static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
1202 {
1203 struct platform_device *pdev = p->pdev;
1204 struct device *dev = &pdev->dev;
1205 const struct sh_msiof_spi_info *info = dev_get_platdata(dev);
1206 unsigned int dma_tx_id, dma_rx_id;
1207 const struct resource *res;
1208 struct spi_master *master;
1209 struct device *tx_dev, *rx_dev;
1210
1211 if (dev->of_node) {
1212 /* In the OF case we will get the slave IDs from the DT */
1213 dma_tx_id = 0;
1214 dma_rx_id = 0;
1215 } else if (info && info->dma_tx_id && info->dma_rx_id) {
1216 dma_tx_id = info->dma_tx_id;
1217 dma_rx_id = info->dma_rx_id;
1218 } else {
1219 /* The driver assumes no error */
1220 return 0;
1221 }
1222
1223 /* The DMA engine uses the second register set, if present */
1224 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1225 if (!res)
1226 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1227
1228 master = p->master;
1229 master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
1230 dma_tx_id,
1231 res->start + TFDR);
1232 if (!master->dma_tx)
1233 return -ENODEV;
1234
1235 master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
1236 dma_rx_id,
1237 res->start + RFDR);
1238 if (!master->dma_rx)
1239 goto free_tx_chan;
1240
1241 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1242 if (!p->tx_dma_page)
1243 goto free_rx_chan;
1244
1245 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1246 if (!p->rx_dma_page)
1247 goto free_tx_page;
1248
1249 tx_dev = master->dma_tx->device->dev;
1250 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
1251 DMA_TO_DEVICE);
1252 if (dma_mapping_error(tx_dev, p->tx_dma_addr))
1253 goto free_rx_page;
1254
1255 rx_dev = master->dma_rx->device->dev;
1256 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
1257 DMA_FROM_DEVICE);
1258 if (dma_mapping_error(rx_dev, p->rx_dma_addr))
1259 goto unmap_tx_page;
1260
1261 dev_info(dev, "DMA available");
1262 return 0;
1263
1264 unmap_tx_page:
1265 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE);
1266 free_rx_page:
1267 free_page((unsigned long)p->rx_dma_page);
1268 free_tx_page:
1269 free_page((unsigned long)p->tx_dma_page);
1270 free_rx_chan:
1271 dma_release_channel(master->dma_rx);
1272 free_tx_chan:
1273 dma_release_channel(master->dma_tx);
1274 master->dma_tx = NULL;
1275 return -ENODEV;
1276 }
1277
1278 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
1279 {
1280 struct spi_master *master = p->master;
1281
1282 if (!master->dma_tx)
1283 return;
1284
1285 dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr,
1286 PAGE_SIZE, DMA_FROM_DEVICE);
1287 dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr,
1288 PAGE_SIZE, DMA_TO_DEVICE);
1289 free_page((unsigned long)p->rx_dma_page);
1290 free_page((unsigned long)p->tx_dma_page);
1291 dma_release_channel(master->dma_rx);
1292 dma_release_channel(master->dma_tx);
1293 }
1294
1295 static int sh_msiof_spi_probe(struct platform_device *pdev)
1296 {
1297 struct resource *r;
1298 struct spi_master *master;
1299 const struct sh_msiof_chipdata *chipdata;
1300 struct sh_msiof_spi_info *info;
1301 struct sh_msiof_spi_priv *p;
1302 int i;
1303 int ret;
1304
1305 chipdata = of_device_get_match_data(&pdev->dev);
1306 if (chipdata) {
1307 info = sh_msiof_spi_parse_dt(&pdev->dev);
1308 } else {
1309 chipdata = (const void *)pdev->id_entry->driver_data;
1310 info = dev_get_platdata(&pdev->dev);
1311 }
1312
1313 if (!info) {
1314 dev_err(&pdev->dev, "failed to obtain device info\n");
1315 return -ENXIO;
1316 }
1317
1318 if (info->mode == MSIOF_SPI_SLAVE)
1319 master = spi_alloc_slave(&pdev->dev,
1320 sizeof(struct sh_msiof_spi_priv));
1321 else
1322 master = spi_alloc_master(&pdev->dev,
1323 sizeof(struct sh_msiof_spi_priv));
1324 if (master == NULL)
1325 return -ENOMEM;
1326
1327 p = spi_master_get_devdata(master);
1328
1329 platform_set_drvdata(pdev, p);
1330 p->master = master;
1331 p->info = info;
1332 p->min_div_pow = chipdata->min_div_pow;
1333
1334 init_completion(&p->done);
1335 init_completion(&p->done_txdma);
1336
1337 p->clk = devm_clk_get(&pdev->dev, NULL);
1338 if (IS_ERR(p->clk)) {
1339 dev_err(&pdev->dev, "cannot get clock\n");
1340 ret = PTR_ERR(p->clk);
1341 goto err1;
1342 }
1343
1344 i = platform_get_irq(pdev, 0);
1345 if (i < 0) {
1346 dev_err(&pdev->dev, "cannot get platform IRQ\n");
1347 ret = -ENOENT;
1348 goto err1;
1349 }
1350
1351 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1352 p->mapbase = devm_ioremap_resource(&pdev->dev, r);
1353 if (IS_ERR(p->mapbase)) {
1354 ret = PTR_ERR(p->mapbase);
1355 goto err1;
1356 }
1357
1358 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
1359 dev_name(&pdev->dev), p);
1360 if (ret) {
1361 dev_err(&pdev->dev, "unable to request irq\n");
1362 goto err1;
1363 }
1364
1365 p->pdev = pdev;
1366 pm_runtime_enable(&pdev->dev);
1367
1368 /* Platform data may override FIFO sizes */
1369 p->tx_fifo_size = chipdata->tx_fifo_size;
1370 p->rx_fifo_size = chipdata->rx_fifo_size;
1371 if (p->info->tx_fifo_override)
1372 p->tx_fifo_size = p->info->tx_fifo_override;
1373 if (p->info->rx_fifo_override)
1374 p->rx_fifo_size = p->info->rx_fifo_override;
1375
1376 /* Setup GPIO chip selects */
1377 master->num_chipselect = p->info->num_chipselect;
1378 ret = sh_msiof_get_cs_gpios(p);
1379 if (ret)
1380 goto err1;
1381
1382 /* init master code */
1383 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1384 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
1385 master->flags = chipdata->master_flags;
1386 master->bus_num = pdev->id;
1387 master->dev.of_node = pdev->dev.of_node;
1388 master->setup = sh_msiof_spi_setup;
1389 master->prepare_message = sh_msiof_prepare_message;
1390 master->slave_abort = sh_msiof_slave_abort;
1391 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
1392 master->auto_runtime_pm = true;
1393 master->transfer_one = sh_msiof_transfer_one;
1394
1395 ret = sh_msiof_request_dma(p);
1396 if (ret < 0)
1397 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1398
1399 ret = devm_spi_register_master(&pdev->dev, master);
1400 if (ret < 0) {
1401 dev_err(&pdev->dev, "spi_register_master error.\n");
1402 goto err2;
1403 }
1404
1405 return 0;
1406
1407 err2:
1408 sh_msiof_release_dma(p);
1409 pm_runtime_disable(&pdev->dev);
1410 err1:
1411 spi_master_put(master);
1412 return ret;
1413 }
1414
1415 static int sh_msiof_spi_remove(struct platform_device *pdev)
1416 {
1417 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1418
1419 sh_msiof_release_dma(p);
1420 pm_runtime_disable(&pdev->dev);
1421 return 0;
1422 }
1423
1424 static const struct platform_device_id spi_driver_ids[] = {
1425 { "spi_sh_msiof", (kernel_ulong_t)&sh_data },
1426 {},
1427 };
1428 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1429
1430 #ifdef CONFIG_PM_SLEEP
1431 static int sh_msiof_spi_suspend(struct device *dev)
1432 {
1433 struct platform_device *pdev = to_platform_device(dev);
1434 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1435
1436 return spi_master_suspend(p->master);
1437 }
1438
1439 static int sh_msiof_spi_resume(struct device *dev)
1440 {
1441 struct platform_device *pdev = to_platform_device(dev);
1442 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1443
1444 return spi_master_resume(p->master);
1445 }
1446
1447 static SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend,
1448 sh_msiof_spi_resume);
1449 #define DEV_PM_OPS &sh_msiof_spi_pm_ops
1450 #else
1451 #define DEV_PM_OPS NULL
1452 #endif /* CONFIG_PM_SLEEP */
1453
1454 static struct platform_driver sh_msiof_spi_drv = {
1455 .probe = sh_msiof_spi_probe,
1456 .remove = sh_msiof_spi_remove,
1457 .id_table = spi_driver_ids,
1458 .driver = {
1459 .name = "spi_sh_msiof",
1460 .pm = DEV_PM_OPS,
1461 .of_match_table = of_match_ptr(sh_msiof_match),
1462 },
1463 };
1464 module_platform_driver(sh_msiof_spi_drv);
1465
1466 MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
1467 MODULE_AUTHOR("Magnus Damm");
1468 MODULE_LICENSE("GPL v2");
1469 MODULE_ALIAS("platform:spi_sh_msiof");
(deprecated) Btrfs devel tree