| blob | cfd7de67e3e34b6e46ad0713d13125141e25c238 |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A77965 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 * Copyright (C) 2016 Renesas Electronics Corp.
7 *
8 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
9 *
10 * R-Car Gen3 processor support - PFC hardware block.
11 *
12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */
15 #include <linux/kernel.h>
20 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
21 SH_PFC_PIN_CFG_PULL_UP | \
22 SH_PFC_PIN_CFG_PULL_DOWN)
24 #define CPU_ALL_PORT(fn, sfx) \
25 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
29 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
34 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
37 /*
38 * F_() : just information
39 * FM() : macro for FN_xxx / xxx_MARK
40 */
42 /* GPSR0 */
43 #define GPSR0_15 F_(D15, IP7_11_8)
44 #define GPSR0_14 F_(D14, IP7_7_4)
45 #define GPSR0_13 F_(D13, IP7_3_0)
46 #define GPSR0_12 F_(D12, IP6_31_28)
47 #define GPSR0_11 F_(D11, IP6_27_24)
48 #define GPSR0_10 F_(D10, IP6_23_20)
49 #define GPSR0_9 F_(D9, IP6_19_16)
50 #define GPSR0_8 F_(D8, IP6_15_12)
51 #define GPSR0_7 F_(D7, IP6_11_8)
52 #define GPSR0_6 F_(D6, IP6_7_4)
53 #define GPSR0_5 F_(D5, IP6_3_0)
54 #define GPSR0_4 F_(D4, IP5_31_28)
55 #define GPSR0_3 F_(D3, IP5_27_24)
56 #define GPSR0_2 F_(D2, IP5_23_20)
57 #define GPSR0_1 F_(D1, IP5_19_16)
58 #define GPSR0_0 F_(D0, IP5_15_12)
60 /* GPSR1 */
61 #define GPSR1_28 FM(CLKOUT)
62 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
63 #define GPSR1_26 F_(WE1_N, IP5_7_4)
64 #define GPSR1_25 F_(WE0_N, IP5_3_0)
65 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
66 #define GPSR1_23 F_(RD_N, IP4_27_24)
67 #define GPSR1_22 F_(BS_N, IP4_23_20)
68 #define GPSR1_21 F_(CS1_N, IP4_19_16)
69 #define GPSR1_20 F_(CS0_N, IP4_15_12)
70 #define GPSR1_19 F_(A19, IP4_11_8)
71 #define GPSR1_18 F_(A18, IP4_7_4)
72 #define GPSR1_17 F_(A17, IP4_3_0)
73 #define GPSR1_16 F_(A16, IP3_31_28)
74 #define GPSR1_15 F_(A15, IP3_27_24)
75 #define GPSR1_14 F_(A14, IP3_23_20)
76 #define GPSR1_13 F_(A13, IP3_19_16)
77 #define GPSR1_12 F_(A12, IP3_15_12)
78 #define GPSR1_11 F_(A11, IP3_11_8)
79 #define GPSR1_10 F_(A10, IP3_7_4)
80 #define GPSR1_9 F_(A9, IP3_3_0)
81 #define GPSR1_8 F_(A8, IP2_31_28)
82 #define GPSR1_7 F_(A7, IP2_27_24)
83 #define GPSR1_6 F_(A6, IP2_23_20)
84 #define GPSR1_5 F_(A5, IP2_19_16)
85 #define GPSR1_4 F_(A4, IP2_15_12)
86 #define GPSR1_3 F_(A3, IP2_11_8)
87 #define GPSR1_2 F_(A2, IP2_7_4)
88 #define GPSR1_1 F_(A1, IP2_3_0)
89 #define GPSR1_0 F_(A0, IP1_31_28)
91 /* GPSR2 */
92 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
93 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
94 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
95 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
96 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
97 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
98 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
99 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
100 #define GPSR2_6 F_(PWM0, IP1_19_16)
101 #define GPSR2_5 F_(IRQ5, IP1_15_12)
102 #define GPSR2_4 F_(IRQ4, IP1_11_8)
103 #define GPSR2_3 F_(IRQ3, IP1_7_4)
104 #define GPSR2_2 F_(IRQ2, IP1_3_0)
105 #define GPSR2_1 F_(IRQ1, IP0_31_28)
106 #define GPSR2_0 F_(IRQ0, IP0_27_24)
108 /* GPSR3 */
109 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
110 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
111 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
112 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
113 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
114 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
115 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
116 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
117 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
118 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
119 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
120 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
121 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
122 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
123 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
124 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
126 /* GPSR4 */
127 #define GPSR4_17 F_(SD3_DS, IP11_7_4)
128 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
129 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
130 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
131 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
132 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
133 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
134 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
135 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
136 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
137 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
138 #define GPSR4_6 F_(SD2_DS, IP9_27_24)
139 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
140 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
141 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
142 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
143 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
144 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
146 /* GPSR5 */
147 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
148 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
149 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
150 #define GPSR5_22 FM(MSIOF0_RXD)
151 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
152 #define GPSR5_20 FM(MSIOF0_TXD)
153 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
154 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
155 #define GPSR5_17 FM(MSIOF0_SCK)
156 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
157 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
158 #define GPSR5_14 F_(HTX0, IP13_19_16)
159 #define GPSR5_13 F_(HRX0, IP13_15_12)
160 #define GPSR5_12 F_(HSCK0, IP13_11_8)
161 #define GPSR5_11 F_(RX2_A, IP13_7_4)
162 #define GPSR5_10 F_(TX2_A, IP13_3_0)
163 #define GPSR5_9 F_(SCK2, IP12_31_28)
164 #define GPSR5_8 F_(RTS1_N, IP12_27_24)
165 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
166 #define GPSR5_6 F_(TX1_A, IP12_19_16)
167 #define GPSR5_5 F_(RX1_A, IP12_15_12)
168 #define GPSR5_4 F_(RTS0_N, IP12_11_8)
169 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
170 #define GPSR5_2 F_(TX0, IP12_3_0)
171 #define GPSR5_1 F_(RX0, IP11_31_28)
172 #define GPSR5_0 F_(SCK0, IP11_27_24)
174 /* GPSR6 */
175 #define GPSR6_31 F_(GP6_31, IP18_7_4)
176 #define GPSR6_30 F_(GP6_30, IP18_3_0)
177 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
178 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
179 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
180 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
181 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
182 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
183 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
184 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
185 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
186 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
187 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
188 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
189 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
190 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
191 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
192 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
193 #define GPSR6_13 FM(SSI_SDATA5)
194 #define GPSR6_12 FM(SSI_WS5)
195 #define GPSR6_11 FM(SSI_SCK5)
196 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
197 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
198 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
199 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
200 #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
201 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
202 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
203 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
204 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
205 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
206 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
208 /* GPSR7 */
209 #define GPSR7_3 FM(GP7_03)
210 #define GPSR7_2 FM(HDMI0_CEC)
211 #define GPSR7_1 FM(AVS2)
212 #define GPSR7_0 FM(AVS1)
215 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
216 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
245 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
276 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
312 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
333 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
342 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
362 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
363 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
364 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
365 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
366 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
368 #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
370 #define PINMUX_GPSR \
371 \
372 GPSR6_31 \
373 GPSR6_30 \
374 GPSR6_29 \
375 GPSR1_28 GPSR6_28 \
376 GPSR1_27 GPSR6_27 \
377 GPSR1_26 GPSR6_26 \
378 GPSR1_25 GPSR5_25 GPSR6_25 \
379 GPSR1_24 GPSR5_24 GPSR6_24 \
380 GPSR1_23 GPSR5_23 GPSR6_23 \
381 GPSR1_22 GPSR5_22 GPSR6_22 \
382 GPSR1_21 GPSR5_21 GPSR6_21 \
383 GPSR1_20 GPSR5_20 GPSR6_20 \
384 GPSR1_19 GPSR5_19 GPSR6_19 \
385 GPSR1_18 GPSR5_18 GPSR6_18 \
386 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
387 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
388 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
389 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
390 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
391 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
392 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
393 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
394 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
395 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
396 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
397 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
398 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
399 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
400 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
401 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
402 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
403 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
405 #define PINMUX_IPSR \
406 \
407 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
408 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
409 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
410 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
411 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
412 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
413 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
414 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
415 \
416 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
417 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
418 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
419 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
420 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
421 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
422 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
423 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
424 \
425 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
426 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
427 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
428 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
429 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
430 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
431 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
432 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
433 \
434 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
435 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
436 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
437 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
438 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
439 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
440 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
441 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
442 \
443 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
444 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
445 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
446 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
447 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
448 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
449 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
450 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
453 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
454 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
455 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
456 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
457 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
458 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
459 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
460 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
461 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
462 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
463 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
464 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
465 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
466 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
467 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
468 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
469 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
470 #define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
473 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
474 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
475 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
476 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
477 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
478 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
479 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
480 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
481 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
482 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
483 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
484 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
485 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
486 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
487 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
488 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
489 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
490 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
491 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
492 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
493 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
494 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
497 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
498 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
499 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
500 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
501 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
502 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
503 #define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
504 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
505 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
506 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
507 #define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
508 #define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
509 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
511 #define PINMUX_MOD_SELS \
512 \
513 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
514 MOD_SEL2_30 \
515 MOD_SEL1_29_28_27 MOD_SEL2_29 \
516 MOD_SEL0_28_27 MOD_SEL2_28_27 \
517 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
518 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
519 MOD_SEL0_23 MOD_SEL1_23_22_21 \
520 MOD_SEL0_22 MOD_SEL2_22 \
521 MOD_SEL0_21 MOD_SEL2_21 \
522 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
523 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
524 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
525 MOD_SEL2_17 \
526 MOD_SEL0_16 MOD_SEL1_16 \
527 MOD_SEL1_15_14 \
528 MOD_SEL0_14_13 \
529 MOD_SEL1_13 \
530 MOD_SEL0_12 MOD_SEL1_12 \
531 MOD_SEL0_11 MOD_SEL1_11 \
532 MOD_SEL0_10 MOD_SEL1_10 \
533 MOD_SEL0_9_8 MOD_SEL1_9 \
534 MOD_SEL0_7_6 \
535 MOD_SEL1_6 \
536 MOD_SEL0_5 MOD_SEL1_5 \
537 MOD_SEL0_4_3 MOD_SEL1_4 \
538 MOD_SEL1_3 \
539 MOD_SEL1_2 \
540 MOD_SEL1_1 \
541 MOD_SEL1_0 MOD_SEL2_0
543 /*
544 * These pins are not able to be muxed but have other properties
545 * that can be set, such as drive-strength or pull-up/pull-down enable.
546 */
547 #define PINMUX_STATIC \
548 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
549 FM(QSPI0_IO2) FM(QSPI0_IO3) \
550 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
551 FM(QSPI1_IO2) FM(QSPI1_IO3) \
552 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
553 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
554 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
555 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
556 FM(PRESETOUT) \
557 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
558 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
563 PINMUX_DATA_BEGIN,
565 PINMUX_DATA_END,
567 #define F_(x, y)
568 #define FM(x) FN_##x,
569 PINMUX_FUNCTION_BEGIN,
571 PINMUX_GPSR
572 PINMUX_IPSR
573 PINMUX_MOD_SELS
574 PINMUX_FUNCTION_END,
575 #undef F_
576 #undef FM
578 #define F_(x, y)
579 #define FM(x) x##_MARK,
580 PINMUX_MARK_BEGIN,
581 PINMUX_GPSR
582 PINMUX_IPSR
583 PINMUX_MOD_SELS
584 PINMUX_STATIC
585 PINMUX_MARK_END,
586 #undef F_
587 #undef FM
588 };
605 /* IPSR0 */
646 /* IPSR1 */
697 /* IPSR2 */
758 /* IPSR3 */
812 /* IPSR4 */
858 /* IPSR5 */
908 /* IPSR6 */
960 /* IPSR7 */
1002 /* IPSR8 */
1051 /* IPSR9 */
1077 /* IPSR10 */
1105 /* IPSR11 */
1147 /* IPSR12 */
1208 /* IPSR13 */
1268 /* IPSR14 */
1309 /* IPSR15 */
1356 /* IPSR16 */
1409 /* IPSR17 */
1476 /* IPSR18 */
1497 /* I2C */
1502 /*
1503 * Static pins can not be muxed between different functions but
1504 * still need mark entries in the pinmux list. Add each static
1505 * pin to the list without an associated function. The sh-pfc
1506 * core will do the right thing and skip trying to mux the pin
1507 * while still applying configuration to it.
1508 */
1509 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1510 PINMUX_STATIC
1511 #undef FM
1512 };
1514 /*
1515 * R8A77965 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1516 * Physical layout rows: A - AW, cols: 1 - 39.
1517 */
1520 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1521 #define PIN_NONE U16_MAX
1526 /*
1527 * Pins not associated with a GPIO port.
1528 *
1529 * The pin positions are different between different r8a77965
1530 * packages, all that is needed for the pfc driver is a unique
1531 * number for each pin. To this end use the pin layout from
1532 * R-Car M3SiP to calculate a unique number for each pin.
1533 */
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1576 };
1578 /* - EtherAVB --------------------------------------------------------------- */
1580 /* AVB_LINK */
1582 };
1584 AVB_LINK_MARK,
1585 };
1587 /* AVB_MAGIC_ */
1589 };
1591 AVB_MAGIC_MARK,
1592 };
1594 /* AVB_PHY_INT */
1596 };
1598 AVB_PHY_INT_MARK,
1599 };
1601 /* AVB_MDC, AVB_MDIO */
1603 };
1606 };
1608 /*
1609 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1610 * AVB_TD1, AVB_TD2, AVB_TD3,
1611 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1612 * AVB_RD1, AVB_RD2, AVB_RD3,
1613 * AVB_TXCREFCLK
1614 */
1621 };
1627 AVB_TXCREFCLK_MARK,
1628 };
1630 /* AVB_AVTP_PPS */
1632 };
1634 AVB_AVTP_PPS_MARK,
1635 };
1637 /* AVB_AVTP_MATCH_A */
1639 };
1641 AVB_AVTP_MATCH_A_MARK,
1642 };
1644 /* AVB_AVTP_CAPTURE_A */
1646 };
1648 AVB_AVTP_CAPTURE_A_MARK,
1649 };
1651 /* AVB_AVTP_MATCH_B */
1653 };
1655 AVB_AVTP_MATCH_B_MARK,
1656 };
1658 /* AVB_AVTP_CAPTURE_B */
1660 };
1662 AVB_AVTP_CAPTURE_B_MARK,
1663 };
1665 /* - DU --------------------------------------------------------------------- */
1667 /* R[7:2], G[7:2], B[7:2] */
1674 };
1683 };
1686 /* R[7:0], G[7:0], B[7:0] */
1696 };
1705 };
1708 /* CLKOUT */
1710 };
1713 DU_DOTCLKOUT0_MARK
1714 };
1717 /* CLKOUT */
1719 };
1722 DU_DOTCLKOUT1_MARK
1723 };
1726 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1728 };
1731 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
1732 };
1735 /* EXDISP/EXODDF/EXCDE */
1737 };
1740 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1741 };
1744 /* CDE */
1746 };
1749 DU_CDE_MARK,
1750 };
1753 /* DISP */
1755 };
1758 DU_DISP_MARK,
1759 };
1761 /* - HSCIF0 ----------------------------------------------------------------- */
1763 /* RX, TX */
1765 };
1769 };
1772 /* SCK */
1774 };
1777 HSCK0_MARK,
1778 };
1781 /* RTS, CTS */
1783 };
1787 };
1789 /* - HSCIF1 ----------------------------------------------------------------- */
1791 /* RX, TX */
1793 };
1797 };
1800 /* SCK */
1802 };
1805 HSCK1_A_MARK,
1806 };
1809 /* RTS, CTS */
1811 };
1815 };
1818 /* RX, TX */
1820 };
1824 };
1827 /* SCK */
1829 };
1832 HSCK1_B_MARK,
1833 };
1836 /* RTS, CTS */
1838 };
1842 };
1844 /* - HSCIF2 ----------------------------------------------------------------- */
1846 /* RX, TX */
1848 };
1852 };
1855 /* SCK */
1857 };
1860 HSCK2_A_MARK,
1861 };
1864 /* RTS, CTS */
1866 };
1870 };
1873 /* RX, TX */
1875 };
1879 };
1882 /* SCK */
1884 };
1887 HSCK2_B_MARK,
1888 };
1891 /* RTS, CTS */
1893 };
1897 };
1900 /* RX, TX */
1902 };
1906 };
1909 /* SCK */
1911 };
1914 HSCK2_C_MARK,
1915 };
1918 /* RTS, CTS */
1920 };
1924 };
1926 /* - HSCIF3 ----------------------------------------------------------------- */
1928 /* RX, TX */
1930 };
1934 };
1937 /* SCK */
1939 };
1942 HSCK3_MARK,
1943 };
1946 /* RTS, CTS */
1948 };
1952 };
1955 /* RX, TX */
1957 };
1961 };
1964 /* RX, TX */
1966 };
1970 };
1973 /* RX, TX */
1975 };
1979 };
1981 /* - HSCIF4 ----------------------------------------------------------------- */
1983 /* RX, TX */
1985 };
1989 };
1992 /* SCK */
1994 };
1997 HSCK4_MARK,
1998 };
2001 /* RTS, CTS */
2003 };
2007 };
2010 /* RX, TX */
2012 };
2016 };
2018 /* - I2C -------------------------------------------------------------------- */
2020 /* SDA, SCL */
2022 };
2025 };
2027 /* SDA, SCL */
2029 };
2032 };
2034 /* SDA, SCL */
2036 };
2039 };
2041 /* SDA, SCL */
2043 };
2046 };
2048 /* SDA, SCL */
2050 };
2053 };
2055 /* SDA, SCL */
2057 };
2060 };
2062 /* SDA, SCL */
2064 };
2067 };
2069 /* - INTC-EX ---------------------------------------------------------------- */
2071 /* IRQ0 */
2073 };
2075 IRQ0_MARK,
2076 };
2078 /* IRQ1 */
2080 };
2082 IRQ1_MARK,
2083 };
2085 /* IRQ2 */
2087 };
2089 IRQ2_MARK,
2090 };
2092 /* IRQ3 */
2094 };
2096 IRQ3_MARK,
2097 };
2099 /* IRQ4 */
2101 };
2103 IRQ4_MARK,
2104 };
2106 /* IRQ5 */
2108 };
2110 IRQ5_MARK,
2111 };
2113 /* - MSIOF0 ----------------------------------------------------------------- */
2115 /* SCK */
2117 };
2119 MSIOF0_SCK_MARK,
2120 };
2122 /* SYNC */
2124 };
2126 MSIOF0_SYNC_MARK,
2127 };
2129 /* SS1 */
2131 };
2133 MSIOF0_SS1_MARK,
2134 };
2136 /* SS2 */
2138 };
2140 MSIOF0_SS2_MARK,
2141 };
2143 /* TXD */
2145 };
2147 MSIOF0_TXD_MARK,
2148 };
2150 /* RXD */
2152 };
2154 MSIOF0_RXD_MARK,
2155 };
2156 /* - MSIOF1 ----------------------------------------------------------------- */
2158 /* SCK */
2160 };
2162 MSIOF1_SCK_A_MARK,
2163 };
2165 /* SYNC */
2167 };
2169 MSIOF1_SYNC_A_MARK,
2170 };
2172 /* SS1 */
2174 };
2176 MSIOF1_SS1_A_MARK,
2177 };
2179 /* SS2 */
2181 };
2183 MSIOF1_SS2_A_MARK,
2184 };
2186 /* TXD */
2188 };
2190 MSIOF1_TXD_A_MARK,
2191 };
2193 /* RXD */
2195 };
2197 MSIOF1_RXD_A_MARK,
2198 };
2200 /* SCK */
2202 };
2204 MSIOF1_SCK_B_MARK,
2205 };
2207 /* SYNC */
2209 };
2211 MSIOF1_SYNC_B_MARK,
2212 };
2214 /* SS1 */
2216 };
2218 MSIOF1_SS1_B_MARK,
2219 };
2221 /* SS2 */
2223 };
2225 MSIOF1_SS2_B_MARK,
2226 };
2228 /* TXD */
2230 };
2232 MSIOF1_TXD_B_MARK,
2233 };
2235 /* RXD */
2237 };
2239 MSIOF1_RXD_B_MARK,
2240 };
2242 /* SCK */
2244 };
2246 MSIOF1_SCK_C_MARK,
2247 };
2249 /* SYNC */
2251 };
2253 MSIOF1_SYNC_C_MARK,
2254 };
2256 /* SS1 */
2258 };
2260 MSIOF1_SS1_C_MARK,
2261 };
2263 /* SS2 */
2265 };
2267 MSIOF1_SS2_C_MARK,
2268 };
2270 /* TXD */
2272 };
2274 MSIOF1_TXD_C_MARK,
2275 };
2277 /* RXD */
2279 };
2281 MSIOF1_RXD_C_MARK,
2282 };
2284 /* SCK */
2286 };
2288 MSIOF1_SCK_D_MARK,
2289 };
2291 /* SYNC */
2293 };
2295 MSIOF1_SYNC_D_MARK,
2296 };
2298 /* SS1 */
2300 };
2302 MSIOF1_SS1_D_MARK,
2303 };
2305 /* SS2 */
2307 };
2309 MSIOF1_SS2_D_MARK,
2310 };
2312 /* TXD */
2314 };
2316 MSIOF1_TXD_D_MARK,
2317 };
2319 /* RXD */
2321 };
2323 MSIOF1_RXD_D_MARK,
2324 };
2326 /* SCK */
2328 };
2330 MSIOF1_SCK_E_MARK,
2331 };
2333 /* SYNC */
2335 };
2337 MSIOF1_SYNC_E_MARK,
2338 };
2340 /* SS1 */
2342 };
2344 MSIOF1_SS1_E_MARK,
2345 };
2347 /* SS2 */
2349 };
2351 MSIOF1_SS2_E_MARK,
2352 };
2354 /* TXD */
2356 };
2358 MSIOF1_TXD_E_MARK,
2359 };
2361 /* RXD */
2363 };
2365 MSIOF1_RXD_E_MARK,
2366 };
2368 /* SCK */
2370 };
2372 MSIOF1_SCK_F_MARK,
2373 };
2375 /* SYNC */
2377 };
2379 MSIOF1_SYNC_F_MARK,
2380 };
2382 /* SS1 */
2384 };
2386 MSIOF1_SS1_F_MARK,
2387 };
2389 /* SS2 */
2391 };
2393 MSIOF1_SS2_F_MARK,
2394 };
2396 /* TXD */
2398 };
2400 MSIOF1_TXD_F_MARK,
2401 };
2403 /* RXD */
2405 };
2407 MSIOF1_RXD_F_MARK,
2408 };
2410 /* SCK */
2412 };
2414 MSIOF1_SCK_G_MARK,
2415 };
2417 /* SYNC */
2419 };
2421 MSIOF1_SYNC_G_MARK,
2422 };
2424 /* SS1 */
2426 };
2428 MSIOF1_SS1_G_MARK,
2429 };
2431 /* SS2 */
2433 };
2435 MSIOF1_SS2_G_MARK,
2436 };
2438 /* TXD */
2440 };
2442 MSIOF1_TXD_G_MARK,
2443 };
2445 /* RXD */
2447 };
2449 MSIOF1_RXD_G_MARK,
2450 };
2451 /* - MSIOF2 ----------------------------------------------------------------- */
2453 /* SCK */
2455 };
2457 MSIOF2_SCK_A_MARK,
2458 };
2460 /* SYNC */
2462 };
2464 MSIOF2_SYNC_A_MARK,
2465 };
2467 /* SS1 */
2469 };
2471 MSIOF2_SS1_A_MARK,
2472 };
2474 /* SS2 */
2476 };
2478 MSIOF2_SS2_A_MARK,
2479 };
2481 /* TXD */
2483 };
2485 MSIOF2_TXD_A_MARK,
2486 };
2488 /* RXD */
2490 };
2492 MSIOF2_RXD_A_MARK,
2493 };
2495 /* SCK */
2497 };
2499 MSIOF2_SCK_B_MARK,
2500 };
2502 /* SYNC */
2504 };
2506 MSIOF2_SYNC_B_MARK,
2507 };
2509 /* SS1 */
2511 };
2513 MSIOF2_SS1_B_MARK,
2514 };
2516 /* SS2 */
2518 };
2520 MSIOF2_SS2_B_MARK,
2521 };
2523 /* TXD */
2525 };
2527 MSIOF2_TXD_B_MARK,
2528 };
2530 /* RXD */
2532 };
2534 MSIOF2_RXD_B_MARK,
2535 };
2537 /* SCK */
2539 };
2541 MSIOF2_SCK_C_MARK,
2542 };
2544 /* SYNC */
2546 };
2548 MSIOF2_SYNC_C_MARK,
2549 };
2551 /* SS1 */
2553 };
2555 MSIOF2_SS1_C_MARK,
2556 };
2558 /* SS2 */
2560 };
2562 MSIOF2_SS2_C_MARK,
2563 };
2565 /* TXD */
2567 };
2569 MSIOF2_TXD_C_MARK,
2570 };
2572 /* RXD */
2574 };
2576 MSIOF2_RXD_C_MARK,
2577 };
2579 /* SCK */
2581 };
2583 MSIOF2_SCK_D_MARK,
2584 };
2586 /* SYNC */
2588 };
2590 MSIOF2_SYNC_D_MARK,
2591 };
2593 /* SS1 */
2595 };
2597 MSIOF2_SS1_D_MARK,
2598 };
2600 /* SS2 */
2602 };
2604 MSIOF2_SS2_D_MARK,
2605 };
2607 /* TXD */
2609 };
2611 MSIOF2_TXD_D_MARK,
2612 };
2614 /* RXD */
2616 };
2618 MSIOF2_RXD_D_MARK,
2619 };
2620 /* - MSIOF3 ----------------------------------------------------------------- */
2622 /* SCK */
2624 };
2626 MSIOF3_SCK_A_MARK,
2627 };
2629 /* SYNC */
2631 };
2633 MSIOF3_SYNC_A_MARK,
2634 };
2636 /* SS1 */
2638 };
2640 MSIOF3_SS1_A_MARK,
2641 };
2643 /* SS2 */
2645 };
2647 MSIOF3_SS2_A_MARK,
2648 };
2650 /* TXD */
2652 };
2654 MSIOF3_TXD_A_MARK,
2655 };
2657 /* RXD */
2659 };
2661 MSIOF3_RXD_A_MARK,
2662 };
2664 /* SCK */
2666 };
2668 MSIOF3_SCK_B_MARK,
2669 };
2671 /* SYNC */
2673 };
2675 MSIOF3_SYNC_B_MARK,
2676 };
2678 /* SS1 */
2680 };
2682 MSIOF3_SS1_B_MARK,
2683 };
2685 /* SS2 */
2687 };
2689 MSIOF3_SS2_B_MARK,
2690 };
2692 /* TXD */
2694 };
2696 MSIOF3_TXD_B_MARK,
2697 };
2699 /* RXD */
2701 };
2703 MSIOF3_RXD_B_MARK,
2704 };
2706 /* SCK */
2708 };
2710 MSIOF3_SCK_C_MARK,
2711 };
2713 /* SYNC */
2715 };
2717 MSIOF3_SYNC_C_MARK,
2718 };
2720 /* TXD */
2722 };
2724 MSIOF3_TXD_C_MARK,
2725 };
2727 /* RXD */
2729 };
2731 MSIOF3_RXD_C_MARK,
2732 };
2734 /* SCK */
2736 };
2738 MSIOF3_SCK_D_MARK,
2739 };
2741 /* SYNC */
2743 };
2745 MSIOF3_SYNC_D_MARK,
2746 };
2748 /* SS1 */
2750 };
2752 MSIOF3_SS1_D_MARK,
2753 };
2755 /* TXD */
2757 };
2759 MSIOF3_TXD_D_MARK,
2760 };
2762 /* RXD */
2764 };
2766 MSIOF3_RXD_D_MARK,
2767 };
2769 /* SCK */
2771 };
2773 MSIOF3_SCK_E_MARK,
2774 };
2776 /* SYNC */
2778 };
2780 MSIOF3_SYNC_E_MARK,
2781 };
2783 /* SS1 */
2785 };
2787 MSIOF3_SS1_E_MARK,
2788 };
2790 /* SS2 */
2792 };
2794 MSIOF3_SS2_E_MARK,
2795 };
2797 /* TXD */
2799 };
2801 MSIOF3_TXD_E_MARK,
2802 };
2804 /* RXD */
2806 };
2808 MSIOF3_RXD_E_MARK,
2809 };
2811 /* - PWM0 --------------------------------------------------------------------*/
2813 /* PWM */
2815 };
2817 PWM0_MARK,
2818 };
2819 /* - PWM1 --------------------------------------------------------------------*/
2821 /* PWM */
2823 };
2825 PWM1_A_MARK,
2826 };
2828 /* PWM */
2830 };
2832 PWM1_B_MARK,
2833 };
2834 /* - PWM2 --------------------------------------------------------------------*/
2836 /* PWM */
2838 };
2840 PWM2_A_MARK,
2841 };
2843 /* PWM */
2845 };
2847 PWM2_B_MARK,
2848 };
2849 /* - PWM3 --------------------------------------------------------------------*/
2851 /* PWM */
2853 };
2855 PWM3_A_MARK,
2856 };
2858 /* PWM */
2860 };
2862 PWM3_B_MARK,
2863 };
2864 /* - PWM4 --------------------------------------------------------------------*/
2866 /* PWM */
2868 };
2870 PWM4_A_MARK,
2871 };
2873 /* PWM */
2875 };
2877 PWM4_B_MARK,
2878 };
2879 /* - PWM5 --------------------------------------------------------------------*/
2881 /* PWM */
2883 };
2885 PWM5_A_MARK,
2886 };
2888 /* PWM */
2890 };
2892 PWM5_B_MARK,
2893 };
2894 /* - PWM6 --------------------------------------------------------------------*/
2896 /* PWM */
2898 };
2900 PWM6_A_MARK,
2901 };
2903 /* PWM */
2905 };
2907 PWM6_B_MARK,
2908 };
2910 /* - SCIF0 ------------------------------------------------------------------ */
2912 /* RX, TX */
2914 };
2917 };
2919 /* SCK */
2921 };
2923 SCK0_MARK,
2924 };
2926 /* RTS, CTS */
2928 };
2931 };
2932 /* - SCIF1 ------------------------------------------------------------------ */
2934 /* RX, TX */
2936 };
2939 };
2941 /* SCK */
2943 };
2945 SCK1_MARK,
2946 };
2948 /* RTS, CTS */
2950 };
2953 };
2955 /* RX, TX */
2957 };
2960 };
2961 /* - SCIF2 ------------------------------------------------------------------ */
2963 /* RX, TX */
2965 };
2968 };
2970 /* SCK */
2972 };
2974 SCK2_MARK,
2975 };
2977 /* RX, TX */
2979 };
2982 };
2983 /* - SCIF3 ------------------------------------------------------------------ */
2985 /* RX, TX */
2987 };
2990 };
2992 /* SCK */
2994 };
2996 SCK3_MARK,
2997 };
2999 /* RTS, CTS */
3001 };
3004 };
3006 /* RX, TX */
3008 };
3011 };
3012 /* - SCIF4 ------------------------------------------------------------------ */
3014 /* RX, TX */
3016 };
3019 };
3021 /* SCK */
3023 };
3025 SCK4_A_MARK,
3026 };
3028 /* RTS, CTS */
3030 };
3033 };
3035 /* RX, TX */
3037 };
3040 };
3042 /* SCK */
3044 };
3046 SCK4_B_MARK,
3047 };
3049 /* RTS, CTS */
3051 };
3054 };
3056 /* RX, TX */
3058 };
3061 };
3063 /* SCK */
3065 };
3067 SCK4_C_MARK,
3068 };
3070 /* RTS, CTS */
3072 };
3075 };
3076 /* - SCIF5 ------------------------------------------------------------------ */
3078 /* RX, TX */
3080 };
3083 };
3085 /* SCK */
3087 };
3089 SCK5_A_MARK,
3090 };
3092 /* RX, TX */
3094 };
3097 };
3099 /* SCK */
3101 };
3103 SCK5_B_MARK,
3104 };
3105 /* - SCIF Clock ------------------------------------------------------------- */
3107 /* SCIF_CLK */
3109 };
3111 SCIF_CLK_A_MARK,
3112 };
3114 /* SCIF_CLK */
3116 };
3118 SCIF_CLK_B_MARK,
3119 };
3121 /* - SDHI0 ------------------------------------------------------------------ */
3123 /* D0 */
3125 };
3128 SD0_DAT0_MARK,
3129 };
3132 /* D[0:3] */
3135 };
3140 };
3143 /* CLK, CMD */
3145 };
3149 };
3152 /* CD */
3154 };
3157 SD0_CD_MARK,
3158 };
3161 /* WP */
3163 };
3166 SD0_WP_MARK,
3167 };
3169 /* - SDHI1 ------------------------------------------------------------------ */
3171 /* D0 */
3173 };
3176 SD1_DAT0_MARK,
3177 };
3180 /* D[0:3] */
3183 };
3188 };
3191 /* CLK, CMD */
3193 };
3197 };
3200 /* CD */
3202 };
3205 SD1_CD_MARK,
3206 };
3209 /* WP */
3211 };
3214 SD1_WP_MARK,
3215 };
3217 /* - SDHI2 ------------------------------------------------------------------ */
3219 /* D0 */
3221 };
3224 SD2_DAT0_MARK,
3225 };
3228 /* D[0:3] */
3231 };
3236 };
3239 /* D[0:7] */
3244 };
3251 };
3254 /* CLK, CMD */
3256 };
3260 };
3263 /* CD */
3265 };
3268 SD2_CD_A_MARK,
3269 };
3272 /* CD */
3274 };
3277 SD2_CD_B_MARK,
3278 };
3281 /* WP */
3283 };
3286 SD2_WP_A_MARK,
3287 };
3290 /* WP */
3292 };
3295 SD2_WP_B_MARK,
3296 };
3299 /* DS */
3301 };
3304 SD2_DS_MARK,
3305 };
3307 /* - SDHI3 ------------------------------------------------------------------ */
3309 /* D0 */
3311 };
3314 SD3_DAT0_MARK,
3315 };
3318 /* D[0:3] */
3321 };
3326 };
3329 /* D[0:7] */
3334 };
3341 };
3344 /* CLK, CMD */
3346 };
3350 };
3353 /* CD */
3355 };
3358 SD3_CD_MARK,
3359 };
3362 /* WP */
3364 };
3367 SD3_WP_MARK,
3368 };
3371 /* DS */
3373 };
3376 SD3_DS_MARK,
3377 };
3379 /* - USB0 ------------------------------------------------------------------- */
3381 /* PWEN, OVC */
3383 };
3387 };
3389 /* - USB1 ------------------------------------------------------------------- */
3391 /* PWEN, OVC */
3393 };
3397 };
3399 /* - USB30 ------------------------------------------------------------------ */
3401 /* PWEN, OVC */
3403 };
3407 };
3640 };
3654 };
3665 };
3671 };
3680 };
3692 };
3701 };
3708 };
3713 };
3718 };
3724 };
3733 };
3742 };
3787 };
3814 };
3844 };
3848 };
3853 };
3858 };
3863 };
3868 };
3873 };
3878 };
3884 };
3891 };
3896 };
3903 };
3915 };
3922 };
3927 };
3935 };
3943 };
3955 };
3965 };
3969 };
3973 };
3977 };
4016 };
4019 #define F_(x, y) FN_##y
4020 #define FM(x) FN_##x
4054 },
4088 },
4122 },
4156 },
4190 },
4224 },
4258 },
4292 },
4293 #undef F_
4294 #undef FM
4296 #define F_(x, y) x,
4297 #define FM(x) FN_##x,
4299 IP0_31_28
4300 IP0_27_24
4301 IP0_23_20
4302 IP0_19_16
4303 IP0_15_12
4304 IP0_11_8
4305 IP0_7_4
4306 IP0_3_0 }
4307 },
4309 IP1_31_28
4310 IP1_27_24
4311 IP1_23_20
4312 IP1_19_16
4313 IP1_15_12
4314 IP1_11_8
4315 IP1_7_4
4316 IP1_3_0 }
4317 },
4319 IP2_31_28
4320 IP2_27_24
4321 IP2_23_20
4322 IP2_19_16
4323 IP2_15_12
4324 IP2_11_8
4325 IP2_7_4
4326 IP2_3_0 }
4327 },
4329 IP3_31_28
4330 IP3_27_24
4331 IP3_23_20
4332 IP3_19_16
4333 IP3_15_12
4334 IP3_11_8
4335 IP3_7_4
4336 IP3_3_0 }
4337 },
4339 IP4_31_28
4340 IP4_27_24
4341 IP4_23_20
4342 IP4_19_16
4343 IP4_15_12
4344 IP4_11_8
4345 IP4_7_4
4346 IP4_3_0 }
4347 },
4349 IP5_31_28
4350 IP5_27_24
4351 IP5_23_20
4352 IP5_19_16
4353 IP5_15_12
4354 IP5_11_8
4355 IP5_7_4
4356 IP5_3_0 }
4357 },
4359 IP6_31_28
4360 IP6_27_24
4361 IP6_23_20
4362 IP6_19_16
4363 IP6_15_12
4364 IP6_11_8
4365 IP6_7_4
4366 IP6_3_0 }
4367 },
4369 IP7_31_28
4370 IP7_27_24
4371 IP7_23_20
4372 IP7_19_16
4374 IP7_11_8
4375 IP7_7_4
4376 IP7_3_0 }
4377 },
4379 IP8_31_28
4380 IP8_27_24
4381 IP8_23_20
4382 IP8_19_16
4383 IP8_15_12
4384 IP8_11_8
4385 IP8_7_4
4386 IP8_3_0 }
4387 },
4389 IP9_31_28
4390 IP9_27_24
4391 IP9_23_20
4392 IP9_19_16
4393 IP9_15_12
4394 IP9_11_8
4395 IP9_7_4
4396 IP9_3_0 }
4397 },
4399 IP10_31_28
4400 IP10_27_24
4401 IP10_23_20
4402 IP10_19_16
4403 IP10_15_12
4404 IP10_11_8
4405 IP10_7_4
4406 IP10_3_0 }
4407 },
4409 IP11_31_28
4410 IP11_27_24
4411 IP11_23_20
4412 IP11_19_16
4413 IP11_15_12
4414 IP11_11_8
4415 IP11_7_4
4416 IP11_3_0 }
4417 },
4419 IP12_31_28
4420 IP12_27_24
4421 IP12_23_20
4422 IP12_19_16
4423 IP12_15_12
4424 IP12_11_8
4425 IP12_7_4
4426 IP12_3_0 }
4427 },
4429 IP13_31_28
4430 IP13_27_24
4431 IP13_23_20
4432 IP13_19_16
4433 IP13_15_12
4434 IP13_11_8
4435 IP13_7_4
4436 IP13_3_0 }
4437 },
4439 IP14_31_28
4440 IP14_27_24
4441 IP14_23_20
4442 IP14_19_16
4443 IP14_15_12
4444 IP14_11_8
4445 IP14_7_4
4446 IP14_3_0 }
4447 },
4449 IP15_31_28
4450 IP15_27_24
4451 IP15_23_20
4452 IP15_19_16
4453 IP15_15_12
4454 IP15_11_8
4455 IP15_7_4
4456 IP15_3_0 }
4457 },
4459 IP16_31_28
4460 IP16_27_24
4461 IP16_23_20
4462 IP16_19_16
4463 IP16_15_12
4464 IP16_11_8
4465 IP16_7_4
4466 IP16_3_0 }
4467 },
4469 IP17_31_28
4470 IP17_27_24
4471 IP17_23_20
4472 IP17_19_16
4473 IP17_15_12
4474 IP17_11_8
4475 IP17_7_4
4476 IP17_3_0 }
4477 },
4485 IP18_7_4
4486 IP18_3_0 }
4487 },
4488 #undef F_
4489 #undef FM
4491 #define F_(x, y) x,
4492 #define FM(x) FN_##x,
4496 MOD_SEL0_31_30_29
4497 MOD_SEL0_28_27
4498 MOD_SEL0_26_25_24
4499 MOD_SEL0_23
4500 MOD_SEL0_22
4501 MOD_SEL0_21
4502 MOD_SEL0_20
4503 MOD_SEL0_19
4504 MOD_SEL0_18_17
4505 MOD_SEL0_16
4507 MOD_SEL0_14_13
4508 MOD_SEL0_12
4509 MOD_SEL0_11
4510 MOD_SEL0_10
4511 MOD_SEL0_9_8
4512 MOD_SEL0_7_6
4513 MOD_SEL0_5
4514 MOD_SEL0_4_3
4515 /* RESERVED 2, 1, 0 */
4517 },
4521 MOD_SEL1_31_30
4522 MOD_SEL1_29_28_27
4523 MOD_SEL1_26
4524 MOD_SEL1_25_24
4525 MOD_SEL1_23_22_21
4526 MOD_SEL1_20
4527 MOD_SEL1_19
4528 MOD_SEL1_18_17
4529 MOD_SEL1_16
4530 MOD_SEL1_15_14
4531 MOD_SEL1_13
4532 MOD_SEL1_12
4533 MOD_SEL1_11
4534 MOD_SEL1_10
4535 MOD_SEL1_9
4537 MOD_SEL1_6
4538 MOD_SEL1_5
4539 MOD_SEL1_4
4540 MOD_SEL1_3
4541 MOD_SEL1_2
4542 MOD_SEL1_1
4543 MOD_SEL1_0 }
4544 },
4548 MOD_SEL2_31
4549 MOD_SEL2_30
4550 MOD_SEL2_29
4551 MOD_SEL2_28_27
4552 MOD_SEL2_26
4553 MOD_SEL2_25_24_23
4554 MOD_SEL2_22
4555 MOD_SEL2_21
4556 MOD_SEL2_20
4557 MOD_SEL2_19
4558 MOD_SEL2_18
4559 MOD_SEL2_17
4560 /* RESERVED 16 */
4562 /* RESERVED 15, 14, 13, 12 */
4565 /* RESERVED 11, 10, 9, 8 */
4568 /* RESERVED 7, 6, 5, 4 */
4571 /* RESERVED 3, 2, 1 */
4573 MOD_SEL2_0 }
4574 },
4575 { },
4576 };
4588 } },
4598 } },
4608 } },
4618 } },
4628 } },
4638 } },
4648 } },
4658 } },
4668 } },
4678 } },
4688 } },
4698 } },
4703 } },
4713 } },
4723 } },
4733 } },
4743 } },
4753 } },
4763 } },
4773 } },
4783 } },
4793 } },
4803 } },
4813 } },
4822 } },
4823 { },
4824 };
4827 POCCTRL,
4828 };
4833 };
4836 {
4848 }
4884 } },
4918 } },
4952 } },
4986 } },
5020 } },
5054 } },
5088 } },
5090 };
5094 {
5106 else
5108 }
5112 {
5131 }
5137 };
5160 };