1 // SPDX-License-Identifier: GPL-2.0
3 * Intel pinctrl/GPIO core driver.
5 * Copyright (C) 2015, Intel Corporation
6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>
10 #include <linux/module.h>
11 #include <linux/interrupt.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/log2.h>
14 #include <linux/platform_device.h>
15 #include <linux/pinctrl/pinctrl.h>
16 #include <linux/pinctrl/pinmux.h>
17 #include <linux/pinctrl/pinconf.h>
18 #include <linux/pinctrl/pinconf-generic.h>
21 #include "pinctrl-intel.h"
23 /* Offset from regs */
25 #define REVID_SHIFT 16
26 #define REVID_MASK GENMASK(31, 16)
32 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
33 #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
34 #define PADOWN_GPP(p) ((p) / 8)
36 /* Offset from pad_regs */
38 #define PADCFG0_RXEVCFG_SHIFT 25
39 #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT)
40 #define PADCFG0_RXEVCFG_LEVEL 0
41 #define PADCFG0_RXEVCFG_EDGE 1
42 #define PADCFG0_RXEVCFG_DISABLED 2
43 #define PADCFG0_RXEVCFG_EDGE_BOTH 3
44 #define PADCFG0_PREGFRXSEL BIT(24)
45 #define PADCFG0_RXINV BIT(23)
46 #define PADCFG0_GPIROUTIOXAPIC BIT(20)
47 #define PADCFG0_GPIROUTSCI BIT(19)
48 #define PADCFG0_GPIROUTSMI BIT(18)
49 #define PADCFG0_GPIROUTNMI BIT(17)
50 #define PADCFG0_PMODE_SHIFT 10
51 #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT)
52 #define PADCFG0_GPIORXDIS BIT(9)
53 #define PADCFG0_GPIOTXDIS BIT(8)
54 #define PADCFG0_GPIORXSTATE BIT(1)
55 #define PADCFG0_GPIOTXSTATE BIT(0)
58 #define PADCFG1_TERM_UP BIT(13)
59 #define PADCFG1_TERM_SHIFT 10
60 #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT)
61 #define PADCFG1_TERM_20K 4
62 #define PADCFG1_TERM_2K 3
63 #define PADCFG1_TERM_5K 2
64 #define PADCFG1_TERM_1K 1
67 #define PADCFG2_DEBEN BIT(0)
68 #define PADCFG2_DEBOUNCE_SHIFT 1
69 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1)
71 #define DEBOUNCE_PERIOD 31250 /* ns */
73 struct intel_pad_context
{
79 struct intel_community_context
{
83 struct intel_pinctrl_context
{
84 struct intel_pad_context
*pads
;
85 struct intel_community_context
*communities
;
89 * struct intel_pinctrl - Intel pinctrl private structure
90 * @dev: Pointer to the device structure
91 * @lock: Lock to serialize register access
92 * @pctldesc: Pin controller description
93 * @pctldev: Pointer to the pin controller device
94 * @chip: GPIO chip in this pin controller
95 * @soc: SoC/PCH specific pin configuration data
96 * @communities: All communities in this pin controller
97 * @ncommunities: Number of communities in this pin controller
98 * @context: Configuration saved over system sleep
99 * @irq: pinctrl/GPIO chip irq number
101 struct intel_pinctrl
{
104 struct pinctrl_desc pctldesc
;
105 struct pinctrl_dev
*pctldev
;
106 struct gpio_chip chip
;
107 const struct intel_pinctrl_soc_data
*soc
;
108 struct intel_community
*communities
;
110 struct intel_pinctrl_context context
;
114 #define pin_to_padno(c, p) ((p) - (c)->pin_base)
115 #define padgroup_offset(g, p) ((p) - (g)->base)
117 static struct intel_community
*intel_get_community(struct intel_pinctrl
*pctrl
,
120 struct intel_community
*community
;
123 for (i
= 0; i
< pctrl
->ncommunities
; i
++) {
124 community
= &pctrl
->communities
[i
];
125 if (pin
>= community
->pin_base
&&
126 pin
< community
->pin_base
+ community
->npins
)
130 dev_warn(pctrl
->dev
, "failed to find community for pin %u\n", pin
);
134 static const struct intel_padgroup
*
135 intel_community_get_padgroup(const struct intel_community
*community
,
140 for (i
= 0; i
< community
->ngpps
; i
++) {
141 const struct intel_padgroup
*padgrp
= &community
->gpps
[i
];
143 if (pin
>= padgrp
->base
&& pin
< padgrp
->base
+ padgrp
->size
)
150 static void __iomem
*intel_get_padcfg(struct intel_pinctrl
*pctrl
, unsigned pin
,
153 const struct intel_community
*community
;
157 community
= intel_get_community(pctrl
, pin
);
161 padno
= pin_to_padno(community
, pin
);
162 nregs
= (community
->features
& PINCTRL_FEATURE_DEBOUNCE
) ? 4 : 2;
164 if (reg
== PADCFG2
&& !(community
->features
& PINCTRL_FEATURE_DEBOUNCE
))
167 return community
->pad_regs
+ reg
+ padno
* nregs
* 4;
170 static bool intel_pad_owned_by_host(struct intel_pinctrl
*pctrl
, unsigned pin
)
172 const struct intel_community
*community
;
173 const struct intel_padgroup
*padgrp
;
174 unsigned gpp
, offset
, gpp_offset
;
175 void __iomem
*padown
;
177 community
= intel_get_community(pctrl
, pin
);
180 if (!community
->padown_offset
)
183 padgrp
= intel_community_get_padgroup(community
, pin
);
187 gpp_offset
= padgroup_offset(padgrp
, pin
);
188 gpp
= PADOWN_GPP(gpp_offset
);
189 offset
= community
->padown_offset
+ padgrp
->padown_num
* 4 + gpp
* 4;
190 padown
= community
->regs
+ offset
;
192 return !(readl(padown
) & PADOWN_MASK(gpp_offset
));
195 static bool intel_pad_acpi_mode(struct intel_pinctrl
*pctrl
, unsigned pin
)
197 const struct intel_community
*community
;
198 const struct intel_padgroup
*padgrp
;
199 unsigned offset
, gpp_offset
;
200 void __iomem
*hostown
;
202 community
= intel_get_community(pctrl
, pin
);
205 if (!community
->hostown_offset
)
208 padgrp
= intel_community_get_padgroup(community
, pin
);
212 gpp_offset
= padgroup_offset(padgrp
, pin
);
213 offset
= community
->hostown_offset
+ padgrp
->reg_num
* 4;
214 hostown
= community
->regs
+ offset
;
216 return !(readl(hostown
) & BIT(gpp_offset
));
219 static bool intel_pad_locked(struct intel_pinctrl
*pctrl
, unsigned pin
)
221 struct intel_community
*community
;
222 const struct intel_padgroup
*padgrp
;
223 unsigned offset
, gpp_offset
;
226 community
= intel_get_community(pctrl
, pin
);
229 if (!community
->padcfglock_offset
)
232 padgrp
= intel_community_get_padgroup(community
, pin
);
236 gpp_offset
= padgroup_offset(padgrp
, pin
);
239 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
240 * the pad is considered unlocked. Any other case means that it is
241 * either fully or partially locked and we don't touch it.
243 offset
= community
->padcfglock_offset
+ padgrp
->reg_num
* 8;
244 value
= readl(community
->regs
+ offset
);
245 if (value
& BIT(gpp_offset
))
248 offset
= community
->padcfglock_offset
+ 4 + padgrp
->reg_num
* 8;
249 value
= readl(community
->regs
+ offset
);
250 if (value
& BIT(gpp_offset
))
256 static bool intel_pad_usable(struct intel_pinctrl
*pctrl
, unsigned pin
)
258 return intel_pad_owned_by_host(pctrl
, pin
) &&
259 !intel_pad_locked(pctrl
, pin
);
262 static int intel_get_groups_count(struct pinctrl_dev
*pctldev
)
264 struct intel_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
266 return pctrl
->soc
->ngroups
;
269 static const char *intel_get_group_name(struct pinctrl_dev
*pctldev
,
272 struct intel_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
274 return pctrl
->soc
->groups
[group
].name
;
277 static int intel_get_group_pins(struct pinctrl_dev
*pctldev
, unsigned group
,
278 const unsigned **pins
, unsigned *npins
)
280 struct intel_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
282 *pins
= pctrl
->soc
->groups
[group
].pins
;
283 *npins
= pctrl
->soc
->groups
[group
].npins
;
287 static void intel_pin_dbg_show(struct pinctrl_dev
*pctldev
, struct seq_file
*s
,
290 struct intel_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
291 void __iomem
*padcfg
;
292 u32 cfg0
, cfg1
, mode
;
295 if (!intel_pad_owned_by_host(pctrl
, pin
)) {
296 seq_puts(s
, "not available");
300 cfg0
= readl(intel_get_padcfg(pctrl
, pin
, PADCFG0
));
301 cfg1
= readl(intel_get_padcfg(pctrl
, pin
, PADCFG1
));
303 mode
= (cfg0
& PADCFG0_PMODE_MASK
) >> PADCFG0_PMODE_SHIFT
;
305 seq_puts(s
, "GPIO ");
307 seq_printf(s
, "mode %d ", mode
);
309 seq_printf(s
, "0x%08x 0x%08x", cfg0
, cfg1
);
311 /* Dump the additional PADCFG registers if available */
312 padcfg
= intel_get_padcfg(pctrl
, pin
, PADCFG2
);
314 seq_printf(s
, " 0x%08x", readl(padcfg
));
316 locked
= intel_pad_locked(pctrl
, pin
);
317 acpi
= intel_pad_acpi_mode(pctrl
, pin
);
319 if (locked
|| acpi
) {
322 seq_puts(s
, "LOCKED");
332 static const struct pinctrl_ops intel_pinctrl_ops
= {
333 .get_groups_count
= intel_get_groups_count
,
334 .get_group_name
= intel_get_group_name
,
335 .get_group_pins
= intel_get_group_pins
,
336 .pin_dbg_show
= intel_pin_dbg_show
,
339 static int intel_get_functions_count(struct pinctrl_dev
*pctldev
)
341 struct intel_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
343 return pctrl
->soc
->nfunctions
;
346 static const char *intel_get_function_name(struct pinctrl_dev
*pctldev
,
349 struct intel_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
351 return pctrl
->soc
->functions
[function
].name
;
354 static int intel_get_function_groups(struct pinctrl_dev
*pctldev
,
356 const char * const **groups
,
357 unsigned * const ngroups
)
359 struct intel_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
361 *groups
= pctrl
->soc
->functions
[function
].groups
;
362 *ngroups
= pctrl
->soc
->functions
[function
].ngroups
;
366 static int intel_pinmux_set_mux(struct pinctrl_dev
*pctldev
, unsigned function
,
369 struct intel_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
370 const struct intel_pingroup
*grp
= &pctrl
->soc
->groups
[group
];
374 raw_spin_lock_irqsave(&pctrl
->lock
, flags
);
377 * All pins in the groups needs to be accessible and writable
378 * before we can enable the mux for this group.
380 for (i
= 0; i
< grp
->npins
; i
++) {
381 if (!intel_pad_usable(pctrl
, grp
->pins
[i
])) {
382 raw_spin_unlock_irqrestore(&pctrl
->lock
, flags
);
387 /* Now enable the mux setting for each pin in the group */
388 for (i
= 0; i
< grp
->npins
; i
++) {
389 void __iomem
*padcfg0
;
392 padcfg0
= intel_get_padcfg(pctrl
, grp
->pins
[i
], PADCFG0
);
393 value
= readl(padcfg0
);
395 value
&= ~PADCFG0_PMODE_MASK
;
398 value
|= grp
->modes
[i
] << PADCFG0_PMODE_SHIFT
;
400 value
|= grp
->mode
<< PADCFG0_PMODE_SHIFT
;
402 writel(value
, padcfg0
);
405 raw_spin_unlock_irqrestore(&pctrl
->lock
, flags
);
410 static void __intel_gpio_set_direction(void __iomem
*padcfg0
, bool input
)
414 value
= readl(padcfg0
);
416 value
&= ~PADCFG0_GPIORXDIS
;
417 value
|= PADCFG0_GPIOTXDIS
;
419 value
&= ~PADCFG0_GPIOTXDIS
;
420 value
|= PADCFG0_GPIORXDIS
;
422 writel(value
, padcfg0
);
425 static void intel_gpio_set_gpio_mode(void __iomem
*padcfg0
)
429 /* Put the pad into GPIO mode */
430 value
= readl(padcfg0
) & ~PADCFG0_PMODE_MASK
;
431 /* Disable SCI/SMI/NMI generation */
432 value
&= ~(PADCFG0_GPIROUTIOXAPIC
| PADCFG0_GPIROUTSCI
);
433 value
&= ~(PADCFG0_GPIROUTSMI
| PADCFG0_GPIROUTNMI
);
434 writel(value
, padcfg0
);
437 static int intel_gpio_request_enable(struct pinctrl_dev
*pctldev
,
438 struct pinctrl_gpio_range
*range
,
441 struct intel_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
442 void __iomem
*padcfg0
;
445 raw_spin_lock_irqsave(&pctrl
->lock
, flags
);
447 if (!intel_pad_usable(pctrl
, pin
)) {
448 raw_spin_unlock_irqrestore(&pctrl
->lock
, flags
);
452 padcfg0
= intel_get_padcfg(pctrl
, pin
, PADCFG0
);
453 intel_gpio_set_gpio_mode(padcfg0
);
454 /* Disable TX buffer and enable RX (this will be input) */
455 __intel_gpio_set_direction(padcfg0
, true);
457 raw_spin_unlock_irqrestore(&pctrl
->lock
, flags
);
462 static int intel_gpio_set_direction(struct pinctrl_dev
*pctldev
,
463 struct pinctrl_gpio_range
*range
,
464 unsigned pin
, bool input
)
466 struct intel_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
467 void __iomem
*padcfg0
;
470 raw_spin_lock_irqsave(&pctrl
->lock
, flags
);
472 padcfg0
= intel_get_padcfg(pctrl
, pin
, PADCFG0
);
473 __intel_gpio_set_direction(padcfg0
, input
);
475 raw_spin_unlock_irqrestore(&pctrl
->lock
, flags
);
480 static const struct pinmux_ops intel_pinmux_ops
= {
481 .get_functions_count
= intel_get_functions_count
,
482 .get_function_name
= intel_get_function_name
,
483 .get_function_groups
= intel_get_function_groups
,
484 .set_mux
= intel_pinmux_set_mux
,
485 .gpio_request_enable
= intel_gpio_request_enable
,
486 .gpio_set_direction
= intel_gpio_set_direction
,
489 static int intel_config_get(struct pinctrl_dev
*pctldev
, unsigned pin
,
490 unsigned long *config
)
492 struct intel_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
493 enum pin_config_param param
= pinconf_to_config_param(*config
);
494 const struct intel_community
*community
;
498 if (!intel_pad_owned_by_host(pctrl
, pin
))
501 community
= intel_get_community(pctrl
, pin
);
502 value
= readl(intel_get_padcfg(pctrl
, pin
, PADCFG1
));
503 term
= (value
& PADCFG1_TERM_MASK
) >> PADCFG1_TERM_SHIFT
;
506 case PIN_CONFIG_BIAS_DISABLE
:
511 case PIN_CONFIG_BIAS_PULL_UP
:
512 if (!term
|| !(value
& PADCFG1_TERM_UP
))
516 case PADCFG1_TERM_1K
:
519 case PADCFG1_TERM_2K
:
522 case PADCFG1_TERM_5K
:
525 case PADCFG1_TERM_20K
:
532 case PIN_CONFIG_BIAS_PULL_DOWN
:
533 if (!term
|| value
& PADCFG1_TERM_UP
)
537 case PADCFG1_TERM_1K
:
538 if (!(community
->features
& PINCTRL_FEATURE_1K_PD
))
542 case PADCFG1_TERM_5K
:
545 case PADCFG1_TERM_20K
:
552 case PIN_CONFIG_INPUT_DEBOUNCE
: {
553 void __iomem
*padcfg2
;
556 padcfg2
= intel_get_padcfg(pctrl
, pin
, PADCFG2
);
561 if (!(v
& PADCFG2_DEBEN
))
564 v
= (v
& PADCFG2_DEBOUNCE_MASK
) >> PADCFG2_DEBOUNCE_SHIFT
;
565 arg
= BIT(v
) * DEBOUNCE_PERIOD
/ 1000;
574 *config
= pinconf_to_config_packed(param
, arg
);
578 static int intel_config_set_pull(struct intel_pinctrl
*pctrl
, unsigned pin
,
579 unsigned long config
)
581 unsigned param
= pinconf_to_config_param(config
);
582 unsigned arg
= pinconf_to_config_argument(config
);
583 const struct intel_community
*community
;
584 void __iomem
*padcfg1
;
589 raw_spin_lock_irqsave(&pctrl
->lock
, flags
);
591 community
= intel_get_community(pctrl
, pin
);
592 padcfg1
= intel_get_padcfg(pctrl
, pin
, PADCFG1
);
593 value
= readl(padcfg1
);
596 case PIN_CONFIG_BIAS_DISABLE
:
597 value
&= ~(PADCFG1_TERM_MASK
| PADCFG1_TERM_UP
);
600 case PIN_CONFIG_BIAS_PULL_UP
:
601 value
&= ~PADCFG1_TERM_MASK
;
603 value
|= PADCFG1_TERM_UP
;
607 value
|= PADCFG1_TERM_20K
<< PADCFG1_TERM_SHIFT
;
610 value
|= PADCFG1_TERM_5K
<< PADCFG1_TERM_SHIFT
;
613 value
|= PADCFG1_TERM_2K
<< PADCFG1_TERM_SHIFT
;
616 value
|= PADCFG1_TERM_1K
<< PADCFG1_TERM_SHIFT
;
624 case PIN_CONFIG_BIAS_PULL_DOWN
:
625 value
&= ~(PADCFG1_TERM_UP
| PADCFG1_TERM_MASK
);
629 value
|= PADCFG1_TERM_20K
<< PADCFG1_TERM_SHIFT
;
632 value
|= PADCFG1_TERM_5K
<< PADCFG1_TERM_SHIFT
;
635 if (!(community
->features
& PINCTRL_FEATURE_1K_PD
)) {
639 value
|= PADCFG1_TERM_1K
<< PADCFG1_TERM_SHIFT
;
649 writel(value
, padcfg1
);
651 raw_spin_unlock_irqrestore(&pctrl
->lock
, flags
);
656 static int intel_config_set_debounce(struct intel_pinctrl
*pctrl
, unsigned pin
,
659 void __iomem
*padcfg0
, *padcfg2
;
664 padcfg2
= intel_get_padcfg(pctrl
, pin
, PADCFG2
);
668 padcfg0
= intel_get_padcfg(pctrl
, pin
, PADCFG0
);
670 raw_spin_lock_irqsave(&pctrl
->lock
, flags
);
672 value0
= readl(padcfg0
);
673 value2
= readl(padcfg2
);
675 /* Disable glitch filter and debouncer */
676 value0
&= ~PADCFG0_PREGFRXSEL
;
677 value2
&= ~(PADCFG2_DEBEN
| PADCFG2_DEBOUNCE_MASK
);
682 v
= order_base_2(debounce
* 1000 / DEBOUNCE_PERIOD
);
683 if (v
< 3 || v
> 15) {
687 /* Enable glitch filter and debouncer */
688 value0
|= PADCFG0_PREGFRXSEL
;
689 value2
|= v
<< PADCFG2_DEBOUNCE_SHIFT
;
690 value2
|= PADCFG2_DEBEN
;
694 writel(value0
, padcfg0
);
695 writel(value2
, padcfg2
);
698 raw_spin_unlock_irqrestore(&pctrl
->lock
, flags
);
703 static int intel_config_set(struct pinctrl_dev
*pctldev
, unsigned pin
,
704 unsigned long *configs
, unsigned nconfigs
)
706 struct intel_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
709 if (!intel_pad_usable(pctrl
, pin
))
712 for (i
= 0; i
< nconfigs
; i
++) {
713 switch (pinconf_to_config_param(configs
[i
])) {
714 case PIN_CONFIG_BIAS_DISABLE
:
715 case PIN_CONFIG_BIAS_PULL_UP
:
716 case PIN_CONFIG_BIAS_PULL_DOWN
:
717 ret
= intel_config_set_pull(pctrl
, pin
, configs
[i
]);
722 case PIN_CONFIG_INPUT_DEBOUNCE
:
723 ret
= intel_config_set_debounce(pctrl
, pin
,
724 pinconf_to_config_argument(configs
[i
]));
737 static const struct pinconf_ops intel_pinconf_ops
= {
739 .pin_config_get
= intel_config_get
,
740 .pin_config_set
= intel_config_set
,
743 static const struct pinctrl_desc intel_pinctrl_desc
= {
744 .pctlops
= &intel_pinctrl_ops
,
745 .pmxops
= &intel_pinmux_ops
,
746 .confops
= &intel_pinconf_ops
,
747 .owner
= THIS_MODULE
,
751 * intel_gpio_to_pin() - Translate from GPIO offset to pin number
752 * @pctrl: Pinctrl structure
753 * @offset: GPIO offset from gpiolib
754 * @commmunity: Community is filled here if not %NULL
755 * @padgrp: Pad group is filled here if not %NULL
757 * When coming through gpiolib irqchip, the GPIO offset is not
758 * automatically translated to pinctrl pin number. This function can be
759 * used to find out the corresponding pinctrl pin.
761 static int intel_gpio_to_pin(struct intel_pinctrl
*pctrl
, unsigned offset
,
762 const struct intel_community
**community
,
763 const struct intel_padgroup
**padgrp
)
767 for (i
= 0; i
< pctrl
->ncommunities
; i
++) {
768 const struct intel_community
*comm
= &pctrl
->communities
[i
];
771 for (j
= 0; j
< comm
->ngpps
; j
++) {
772 const struct intel_padgroup
*pgrp
= &comm
->gpps
[j
];
774 if (pgrp
->gpio_base
< 0)
777 if (offset
>= pgrp
->gpio_base
&&
778 offset
< pgrp
->gpio_base
+ pgrp
->size
) {
781 pin
= pgrp
->base
+ offset
- pgrp
->gpio_base
;
795 static int intel_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
797 struct intel_pinctrl
*pctrl
= gpiochip_get_data(chip
);
802 pin
= intel_gpio_to_pin(pctrl
, offset
, NULL
, NULL
);
806 reg
= intel_get_padcfg(pctrl
, pin
, PADCFG0
);
810 padcfg0
= readl(reg
);
811 if (!(padcfg0
& PADCFG0_GPIOTXDIS
))
812 return !!(padcfg0
& PADCFG0_GPIOTXSTATE
);
814 return !!(padcfg0
& PADCFG0_GPIORXSTATE
);
817 static void intel_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
819 struct intel_pinctrl
*pctrl
= gpiochip_get_data(chip
);
825 pin
= intel_gpio_to_pin(pctrl
, offset
, NULL
, NULL
);
829 reg
= intel_get_padcfg(pctrl
, pin
, PADCFG0
);
833 raw_spin_lock_irqsave(&pctrl
->lock
, flags
);
834 padcfg0
= readl(reg
);
836 padcfg0
|= PADCFG0_GPIOTXSTATE
;
838 padcfg0
&= ~PADCFG0_GPIOTXSTATE
;
839 writel(padcfg0
, reg
);
840 raw_spin_unlock_irqrestore(&pctrl
->lock
, flags
);
843 static int intel_gpio_get_direction(struct gpio_chip
*chip
, unsigned int offset
)
845 struct intel_pinctrl
*pctrl
= gpiochip_get_data(chip
);
850 pin
= intel_gpio_to_pin(pctrl
, offset
, NULL
, NULL
);
854 reg
= intel_get_padcfg(pctrl
, pin
, PADCFG0
);
858 padcfg0
= readl(reg
);
860 if (padcfg0
& PADCFG0_PMODE_MASK
)
863 return !!(padcfg0
& PADCFG0_GPIOTXDIS
);
866 static int intel_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
868 return pinctrl_gpio_direction_input(chip
->base
+ offset
);
871 static int intel_gpio_direction_output(struct gpio_chip
*chip
, unsigned offset
,
874 intel_gpio_set(chip
, offset
, value
);
875 return pinctrl_gpio_direction_output(chip
->base
+ offset
);
878 static const struct gpio_chip intel_gpio_chip
= {
879 .owner
= THIS_MODULE
,
880 .request
= gpiochip_generic_request
,
881 .free
= gpiochip_generic_free
,
882 .get_direction
= intel_gpio_get_direction
,
883 .direction_input
= intel_gpio_direction_input
,
884 .direction_output
= intel_gpio_direction_output
,
885 .get
= intel_gpio_get
,
886 .set
= intel_gpio_set
,
887 .set_config
= gpiochip_generic_config
,
890 static void intel_gpio_irq_ack(struct irq_data
*d
)
892 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
893 struct intel_pinctrl
*pctrl
= gpiochip_get_data(gc
);
894 const struct intel_community
*community
;
895 const struct intel_padgroup
*padgrp
;
898 pin
= intel_gpio_to_pin(pctrl
, irqd_to_hwirq(d
), &community
, &padgrp
);
900 unsigned gpp
, gpp_offset
, is_offset
;
902 gpp
= padgrp
->reg_num
;
903 gpp_offset
= padgroup_offset(padgrp
, pin
);
904 is_offset
= community
->is_offset
+ gpp
* 4;
906 raw_spin_lock(&pctrl
->lock
);
907 writel(BIT(gpp_offset
), community
->regs
+ is_offset
);
908 raw_spin_unlock(&pctrl
->lock
);
912 static void intel_gpio_irq_enable(struct irq_data
*d
)
914 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
915 struct intel_pinctrl
*pctrl
= gpiochip_get_data(gc
);
916 const struct intel_community
*community
;
917 const struct intel_padgroup
*padgrp
;
920 pin
= intel_gpio_to_pin(pctrl
, irqd_to_hwirq(d
), &community
, &padgrp
);
922 unsigned gpp
, gpp_offset
, is_offset
;
926 gpp
= padgrp
->reg_num
;
927 gpp_offset
= padgroup_offset(padgrp
, pin
);
928 is_offset
= community
->is_offset
+ gpp
* 4;
930 raw_spin_lock_irqsave(&pctrl
->lock
, flags
);
931 /* Clear interrupt status first to avoid unexpected interrupt */
932 writel(BIT(gpp_offset
), community
->regs
+ is_offset
);
934 value
= readl(community
->regs
+ community
->ie_offset
+ gpp
* 4);
935 value
|= BIT(gpp_offset
);
936 writel(value
, community
->regs
+ community
->ie_offset
+ gpp
* 4);
937 raw_spin_unlock_irqrestore(&pctrl
->lock
, flags
);
941 static void intel_gpio_irq_mask_unmask(struct irq_data
*d
, bool mask
)
943 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
944 struct intel_pinctrl
*pctrl
= gpiochip_get_data(gc
);
945 const struct intel_community
*community
;
946 const struct intel_padgroup
*padgrp
;
949 pin
= intel_gpio_to_pin(pctrl
, irqd_to_hwirq(d
), &community
, &padgrp
);
951 unsigned gpp
, gpp_offset
;
956 gpp
= padgrp
->reg_num
;
957 gpp_offset
= padgroup_offset(padgrp
, pin
);
959 reg
= community
->regs
+ community
->ie_offset
+ gpp
* 4;
961 raw_spin_lock_irqsave(&pctrl
->lock
, flags
);
964 value
&= ~BIT(gpp_offset
);
966 value
|= BIT(gpp_offset
);
968 raw_spin_unlock_irqrestore(&pctrl
->lock
, flags
);
972 static void intel_gpio_irq_mask(struct irq_data
*d
)
974 intel_gpio_irq_mask_unmask(d
, true);
977 static void intel_gpio_irq_unmask(struct irq_data
*d
)
979 intel_gpio_irq_mask_unmask(d
, false);
982 static int intel_gpio_irq_type(struct irq_data
*d
, unsigned type
)
984 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
985 struct intel_pinctrl
*pctrl
= gpiochip_get_data(gc
);
986 unsigned pin
= intel_gpio_to_pin(pctrl
, irqd_to_hwirq(d
), NULL
, NULL
);
991 reg
= intel_get_padcfg(pctrl
, pin
, PADCFG0
);
996 * If the pin is in ACPI mode it is still usable as a GPIO but it
997 * cannot be used as IRQ because GPI_IS status bit will not be
998 * updated by the host controller hardware.
1000 if (intel_pad_acpi_mode(pctrl
, pin
)) {
1001 dev_warn(pctrl
->dev
, "pin %u cannot be used as IRQ\n", pin
);
1005 raw_spin_lock_irqsave(&pctrl
->lock
, flags
);
1007 intel_gpio_set_gpio_mode(reg
);
1011 value
&= ~(PADCFG0_RXEVCFG_MASK
| PADCFG0_RXINV
);
1013 if ((type
& IRQ_TYPE_EDGE_BOTH
) == IRQ_TYPE_EDGE_BOTH
) {
1014 value
|= PADCFG0_RXEVCFG_EDGE_BOTH
<< PADCFG0_RXEVCFG_SHIFT
;
1015 } else if (type
& IRQ_TYPE_EDGE_FALLING
) {
1016 value
|= PADCFG0_RXEVCFG_EDGE
<< PADCFG0_RXEVCFG_SHIFT
;
1017 value
|= PADCFG0_RXINV
;
1018 } else if (type
& IRQ_TYPE_EDGE_RISING
) {
1019 value
|= PADCFG0_RXEVCFG_EDGE
<< PADCFG0_RXEVCFG_SHIFT
;
1020 } else if (type
& IRQ_TYPE_LEVEL_MASK
) {
1021 if (type
& IRQ_TYPE_LEVEL_LOW
)
1022 value
|= PADCFG0_RXINV
;
1024 value
|= PADCFG0_RXEVCFG_DISABLED
<< PADCFG0_RXEVCFG_SHIFT
;
1029 if (type
& IRQ_TYPE_EDGE_BOTH
)
1030 irq_set_handler_locked(d
, handle_edge_irq
);
1031 else if (type
& IRQ_TYPE_LEVEL_MASK
)
1032 irq_set_handler_locked(d
, handle_level_irq
);
1034 raw_spin_unlock_irqrestore(&pctrl
->lock
, flags
);
1039 static int intel_gpio_irq_wake(struct irq_data
*d
, unsigned int on
)
1041 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
1042 struct intel_pinctrl
*pctrl
= gpiochip_get_data(gc
);
1043 unsigned pin
= intel_gpio_to_pin(pctrl
, irqd_to_hwirq(d
), NULL
, NULL
);
1046 enable_irq_wake(pctrl
->irq
);
1048 disable_irq_wake(pctrl
->irq
);
1050 dev_dbg(pctrl
->dev
, "%sable wake for pin %u\n", on
? "en" : "dis", pin
);
1054 static irqreturn_t
intel_gpio_community_irq_handler(struct intel_pinctrl
*pctrl
,
1055 const struct intel_community
*community
)
1057 struct gpio_chip
*gc
= &pctrl
->chip
;
1058 irqreturn_t ret
= IRQ_NONE
;
1061 for (gpp
= 0; gpp
< community
->ngpps
; gpp
++) {
1062 const struct intel_padgroup
*padgrp
= &community
->gpps
[gpp
];
1063 unsigned long pending
, enabled
, gpp_offset
;
1065 pending
= readl(community
->regs
+ community
->is_offset
+
1066 padgrp
->reg_num
* 4);
1067 enabled
= readl(community
->regs
+ community
->ie_offset
+
1068 padgrp
->reg_num
* 4);
1070 /* Only interrupts that are enabled */
1073 for_each_set_bit(gpp_offset
, &pending
, padgrp
->size
) {
1076 irq
= irq_find_mapping(gc
->irq
.domain
,
1077 padgrp
->gpio_base
+ gpp_offset
);
1078 generic_handle_irq(irq
);
1087 static irqreturn_t
intel_gpio_irq(int irq
, void *data
)
1089 const struct intel_community
*community
;
1090 struct intel_pinctrl
*pctrl
= data
;
1091 irqreturn_t ret
= IRQ_NONE
;
1094 /* Need to check all communities for pending interrupts */
1095 for (i
= 0; i
< pctrl
->ncommunities
; i
++) {
1096 community
= &pctrl
->communities
[i
];
1097 ret
|= intel_gpio_community_irq_handler(pctrl
, community
);
1103 static struct irq_chip intel_gpio_irqchip
= {
1104 .name
= "intel-gpio",
1105 .irq_enable
= intel_gpio_irq_enable
,
1106 .irq_ack
= intel_gpio_irq_ack
,
1107 .irq_mask
= intel_gpio_irq_mask
,
1108 .irq_unmask
= intel_gpio_irq_unmask
,
1109 .irq_set_type
= intel_gpio_irq_type
,
1110 .irq_set_wake
= intel_gpio_irq_wake
,
1111 .flags
= IRQCHIP_MASK_ON_SUSPEND
,
1114 static int intel_gpio_add_pin_ranges(struct intel_pinctrl
*pctrl
,
1115 const struct intel_community
*community
)
1119 for (i
= 0; i
< community
->ngpps
; i
++) {
1120 const struct intel_padgroup
*gpp
= &community
->gpps
[i
];
1122 if (gpp
->gpio_base
< 0)
1125 ret
= gpiochip_add_pin_range(&pctrl
->chip
, dev_name(pctrl
->dev
),
1126 gpp
->gpio_base
, gpp
->base
,
1135 static unsigned intel_gpio_ngpio(const struct intel_pinctrl
*pctrl
)
1137 const struct intel_community
*community
;
1141 for (i
= 0; i
< pctrl
->ncommunities
; i
++) {
1142 community
= &pctrl
->communities
[i
];
1143 for (j
= 0; j
< community
->ngpps
; j
++) {
1144 const struct intel_padgroup
*gpp
= &community
->gpps
[j
];
1146 if (gpp
->gpio_base
< 0)
1149 if (gpp
->gpio_base
+ gpp
->size
> ngpio
)
1150 ngpio
= gpp
->gpio_base
+ gpp
->size
;
1157 static int intel_gpio_probe(struct intel_pinctrl
*pctrl
, int irq
)
1161 pctrl
->chip
= intel_gpio_chip
;
1163 pctrl
->chip
.ngpio
= intel_gpio_ngpio(pctrl
);
1164 pctrl
->chip
.label
= dev_name(pctrl
->dev
);
1165 pctrl
->chip
.parent
= pctrl
->dev
;
1166 pctrl
->chip
.base
= -1;
1169 ret
= devm_gpiochip_add_data(pctrl
->dev
, &pctrl
->chip
, pctrl
);
1171 dev_err(pctrl
->dev
, "failed to register gpiochip\n");
1175 for (i
= 0; i
< pctrl
->ncommunities
; i
++) {
1176 struct intel_community
*community
= &pctrl
->communities
[i
];
1178 ret
= intel_gpio_add_pin_ranges(pctrl
, community
);
1180 dev_err(pctrl
->dev
, "failed to add GPIO pin range\n");
1186 * We need to request the interrupt here (instead of providing chip
1187 * to the irq directly) because on some platforms several GPIO
1188 * controllers share the same interrupt line.
1190 ret
= devm_request_irq(pctrl
->dev
, irq
, intel_gpio_irq
,
1191 IRQF_SHARED
| IRQF_NO_THREAD
,
1192 dev_name(pctrl
->dev
), pctrl
);
1194 dev_err(pctrl
->dev
, "failed to request interrupt\n");
1198 ret
= gpiochip_irqchip_add(&pctrl
->chip
, &intel_gpio_irqchip
, 0,
1199 handle_bad_irq
, IRQ_TYPE_NONE
);
1201 dev_err(pctrl
->dev
, "failed to add irqchip\n");
1205 gpiochip_set_chained_irqchip(&pctrl
->chip
, &intel_gpio_irqchip
, irq
,
1210 static int intel_pinctrl_add_padgroups(struct intel_pinctrl
*pctrl
,
1211 struct intel_community
*community
)
1213 struct intel_padgroup
*gpps
;
1214 unsigned npins
= community
->npins
;
1215 unsigned padown_num
= 0;
1218 if (community
->gpps
)
1219 ngpps
= community
->ngpps
;
1221 ngpps
= DIV_ROUND_UP(community
->npins
, community
->gpp_size
);
1223 gpps
= devm_kcalloc(pctrl
->dev
, ngpps
, sizeof(*gpps
), GFP_KERNEL
);
1227 for (i
= 0; i
< ngpps
; i
++) {
1228 if (community
->gpps
) {
1229 gpps
[i
] = community
->gpps
[i
];
1231 unsigned gpp_size
= community
->gpp_size
;
1233 gpps
[i
].reg_num
= i
;
1234 gpps
[i
].base
= community
->pin_base
+ i
* gpp_size
;
1235 gpps
[i
].size
= min(gpp_size
, npins
);
1236 npins
-= gpps
[i
].size
;
1239 if (gpps
[i
].size
> 32)
1242 if (!gpps
[i
].gpio_base
)
1243 gpps
[i
].gpio_base
= gpps
[i
].base
;
1245 gpps
[i
].padown_num
= padown_num
;
1248 * In older hardware the number of padown registers per
1249 * group is fixed regardless of the group size.
1251 if (community
->gpp_num_padown_regs
)
1252 padown_num
+= community
->gpp_num_padown_regs
;
1254 padown_num
+= DIV_ROUND_UP(gpps
[i
].size
* 4, 32);
1257 community
->ngpps
= ngpps
;
1258 community
->gpps
= gpps
;
1263 static int intel_pinctrl_pm_init(struct intel_pinctrl
*pctrl
)
1265 #ifdef CONFIG_PM_SLEEP
1266 const struct intel_pinctrl_soc_data
*soc
= pctrl
->soc
;
1267 struct intel_community_context
*communities
;
1268 struct intel_pad_context
*pads
;
1271 pads
= devm_kcalloc(pctrl
->dev
, soc
->npins
, sizeof(*pads
), GFP_KERNEL
);
1275 communities
= devm_kcalloc(pctrl
->dev
, pctrl
->ncommunities
,
1276 sizeof(*communities
), GFP_KERNEL
);
1281 for (i
= 0; i
< pctrl
->ncommunities
; i
++) {
1282 struct intel_community
*community
= &pctrl
->communities
[i
];
1285 intmask
= devm_kcalloc(pctrl
->dev
, community
->ngpps
,
1286 sizeof(*intmask
), GFP_KERNEL
);
1290 communities
[i
].intmask
= intmask
;
1293 pctrl
->context
.pads
= pads
;
1294 pctrl
->context
.communities
= communities
;
1300 int intel_pinctrl_probe(struct platform_device
*pdev
,
1301 const struct intel_pinctrl_soc_data
*soc_data
)
1303 struct intel_pinctrl
*pctrl
;
1309 pctrl
= devm_kzalloc(&pdev
->dev
, sizeof(*pctrl
), GFP_KERNEL
);
1313 pctrl
->dev
= &pdev
->dev
;
1314 pctrl
->soc
= soc_data
;
1315 raw_spin_lock_init(&pctrl
->lock
);
1318 * Make a copy of the communities which we can use to hold pointers
1321 pctrl
->ncommunities
= pctrl
->soc
->ncommunities
;
1322 pctrl
->communities
= devm_kcalloc(&pdev
->dev
, pctrl
->ncommunities
,
1323 sizeof(*pctrl
->communities
), GFP_KERNEL
);
1324 if (!pctrl
->communities
)
1327 for (i
= 0; i
< pctrl
->ncommunities
; i
++) {
1328 struct intel_community
*community
= &pctrl
->communities
[i
];
1329 struct resource
*res
;
1333 *community
= pctrl
->soc
->communities
[i
];
1335 res
= platform_get_resource(pdev
, IORESOURCE_MEM
,
1337 regs
= devm_ioremap_resource(&pdev
->dev
, res
);
1339 return PTR_ERR(regs
);
1342 * Determine community features based on the revision if
1343 * not specified already.
1345 if (!community
->features
) {
1348 rev
= (readl(regs
+ REVID
) & REVID_MASK
) >> REVID_SHIFT
;
1350 community
->features
|= PINCTRL_FEATURE_DEBOUNCE
;
1351 community
->features
|= PINCTRL_FEATURE_1K_PD
;
1355 /* Read offset of the pad configuration registers */
1356 padbar
= readl(regs
+ PADBAR
);
1358 community
->regs
= regs
;
1359 community
->pad_regs
= regs
+ padbar
;
1361 if (!community
->is_offset
)
1362 community
->is_offset
= GPI_IS
;
1364 ret
= intel_pinctrl_add_padgroups(pctrl
, community
);
1369 irq
= platform_get_irq(pdev
, 0);
1371 dev_err(&pdev
->dev
, "failed to get interrupt number\n");
1375 ret
= intel_pinctrl_pm_init(pctrl
);
1379 pctrl
->pctldesc
= intel_pinctrl_desc
;
1380 pctrl
->pctldesc
.name
= dev_name(&pdev
->dev
);
1381 pctrl
->pctldesc
.pins
= pctrl
->soc
->pins
;
1382 pctrl
->pctldesc
.npins
= pctrl
->soc
->npins
;
1384 pctrl
->pctldev
= devm_pinctrl_register(&pdev
->dev
, &pctrl
->pctldesc
,
1386 if (IS_ERR(pctrl
->pctldev
)) {
1387 dev_err(&pdev
->dev
, "failed to register pinctrl driver\n");
1388 return PTR_ERR(pctrl
->pctldev
);
1391 ret
= intel_gpio_probe(pctrl
, irq
);
1395 platform_set_drvdata(pdev
, pctrl
);
1399 EXPORT_SYMBOL_GPL(intel_pinctrl_probe
);
1401 #ifdef CONFIG_PM_SLEEP
1402 static bool intel_pinctrl_should_save(struct intel_pinctrl
*pctrl
, unsigned pin
)
1404 const struct pin_desc
*pd
= pin_desc_get(pctrl
->pctldev
, pin
);
1406 if (!pd
|| !intel_pad_usable(pctrl
, pin
))
1410 * Only restore the pin if it is actually in use by the kernel (or
1411 * by userspace). It is possible that some pins are used by the
1412 * BIOS during resume and those are not always locked down so leave
1415 if (pd
->mux_owner
|| pd
->gpio_owner
||
1416 gpiochip_line_is_irq(&pctrl
->chip
, pin
))
1422 int intel_pinctrl_suspend(struct device
*dev
)
1424 struct platform_device
*pdev
= to_platform_device(dev
);
1425 struct intel_pinctrl
*pctrl
= platform_get_drvdata(pdev
);
1426 struct intel_community_context
*communities
;
1427 struct intel_pad_context
*pads
;
1430 pads
= pctrl
->context
.pads
;
1431 for (i
= 0; i
< pctrl
->soc
->npins
; i
++) {
1432 const struct pinctrl_pin_desc
*desc
= &pctrl
->soc
->pins
[i
];
1433 void __iomem
*padcfg
;
1436 if (!intel_pinctrl_should_save(pctrl
, desc
->number
))
1439 val
= readl(intel_get_padcfg(pctrl
, desc
->number
, PADCFG0
));
1440 pads
[i
].padcfg0
= val
& ~PADCFG0_GPIORXSTATE
;
1441 val
= readl(intel_get_padcfg(pctrl
, desc
->number
, PADCFG1
));
1442 pads
[i
].padcfg1
= val
;
1444 padcfg
= intel_get_padcfg(pctrl
, desc
->number
, PADCFG2
);
1446 pads
[i
].padcfg2
= readl(padcfg
);
1449 communities
= pctrl
->context
.communities
;
1450 for (i
= 0; i
< pctrl
->ncommunities
; i
++) {
1451 struct intel_community
*community
= &pctrl
->communities
[i
];
1455 base
= community
->regs
+ community
->ie_offset
;
1456 for (gpp
= 0; gpp
< community
->ngpps
; gpp
++)
1457 communities
[i
].intmask
[gpp
] = readl(base
+ gpp
* 4);
1462 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend
);
1464 static void intel_gpio_irq_init(struct intel_pinctrl
*pctrl
)
1468 for (i
= 0; i
< pctrl
->ncommunities
; i
++) {
1469 const struct intel_community
*community
;
1473 community
= &pctrl
->communities
[i
];
1474 base
= community
->regs
;
1476 for (gpp
= 0; gpp
< community
->ngpps
; gpp
++) {
1477 /* Mask and clear all interrupts */
1478 writel(0, base
+ community
->ie_offset
+ gpp
* 4);
1479 writel(0xffff, base
+ community
->is_offset
+ gpp
* 4);
1484 int intel_pinctrl_resume(struct device
*dev
)
1486 struct platform_device
*pdev
= to_platform_device(dev
);
1487 struct intel_pinctrl
*pctrl
= platform_get_drvdata(pdev
);
1488 const struct intel_community_context
*communities
;
1489 const struct intel_pad_context
*pads
;
1492 /* Mask all interrupts */
1493 intel_gpio_irq_init(pctrl
);
1495 pads
= pctrl
->context
.pads
;
1496 for (i
= 0; i
< pctrl
->soc
->npins
; i
++) {
1497 const struct pinctrl_pin_desc
*desc
= &pctrl
->soc
->pins
[i
];
1498 void __iomem
*padcfg
;
1501 if (!intel_pinctrl_should_save(pctrl
, desc
->number
))
1504 padcfg
= intel_get_padcfg(pctrl
, desc
->number
, PADCFG0
);
1505 val
= readl(padcfg
) & ~PADCFG0_GPIORXSTATE
;
1506 if (val
!= pads
[i
].padcfg0
) {
1507 writel(pads
[i
].padcfg0
, padcfg
);
1508 dev_dbg(dev
, "restored pin %u padcfg0 %#08x\n",
1509 desc
->number
, readl(padcfg
));
1512 padcfg
= intel_get_padcfg(pctrl
, desc
->number
, PADCFG1
);
1513 val
= readl(padcfg
);
1514 if (val
!= pads
[i
].padcfg1
) {
1515 writel(pads
[i
].padcfg1
, padcfg
);
1516 dev_dbg(dev
, "restored pin %u padcfg1 %#08x\n",
1517 desc
->number
, readl(padcfg
));
1520 padcfg
= intel_get_padcfg(pctrl
, desc
->number
, PADCFG2
);
1522 val
= readl(padcfg
);
1523 if (val
!= pads
[i
].padcfg2
) {
1524 writel(pads
[i
].padcfg2
, padcfg
);
1525 dev_dbg(dev
, "restored pin %u padcfg2 %#08x\n",
1526 desc
->number
, readl(padcfg
));
1531 communities
= pctrl
->context
.communities
;
1532 for (i
= 0; i
< pctrl
->ncommunities
; i
++) {
1533 struct intel_community
*community
= &pctrl
->communities
[i
];
1537 base
= community
->regs
+ community
->ie_offset
;
1538 for (gpp
= 0; gpp
< community
->ngpps
; gpp
++) {
1539 writel(communities
[i
].intmask
[gpp
], base
+ gpp
* 4);
1540 dev_dbg(dev
, "restored mask %d/%u %#08x\n", i
, gpp
,
1541 readl(base
+ gpp
* 4));
1547 EXPORT_SYMBOL_GPL(intel_pinctrl_resume
);
1550 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1551 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1552 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1553 MODULE_LICENSE("GPL v2");