2 Samsung S5H1411 VSB/QAM demodulator driver
4 Copyright (C) 2008 Steven Toth <stoth@linuxtv.org>
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/slab.h>
27 #include <linux/delay.h>
28 #include <media/dvb_frontend.h>
31 struct s5h1411_state
{
33 struct i2c_adapter
*i2c
;
35 /* configuration settings */
36 const struct s5h1411_config
*config
;
38 struct dvb_frontend frontend
;
40 enum fe_modulation current_modulation
;
41 unsigned int first_tune
:1;
43 u32 current_frequency
;
51 #define dprintk(arg...) do { \
56 /* Register values to initialise the demod, defaults to VSB */
57 static struct init_tab
{
62 { S5H1411_I2C_TOP_ADDR
, 0x00, 0x0071, },
63 { S5H1411_I2C_TOP_ADDR
, 0x08, 0x0047, },
64 { S5H1411_I2C_TOP_ADDR
, 0x1c, 0x0400, },
65 { S5H1411_I2C_TOP_ADDR
, 0x1e, 0x0370, },
66 { S5H1411_I2C_TOP_ADDR
, 0x1f, 0x342c, },
67 { S5H1411_I2C_TOP_ADDR
, 0x24, 0x0231, },
68 { S5H1411_I2C_TOP_ADDR
, 0x25, 0x1011, },
69 { S5H1411_I2C_TOP_ADDR
, 0x26, 0x0f07, },
70 { S5H1411_I2C_TOP_ADDR
, 0x27, 0x0f04, },
71 { S5H1411_I2C_TOP_ADDR
, 0x28, 0x070f, },
72 { S5H1411_I2C_TOP_ADDR
, 0x29, 0x2820, },
73 { S5H1411_I2C_TOP_ADDR
, 0x2a, 0x102e, },
74 { S5H1411_I2C_TOP_ADDR
, 0x2b, 0x0220, },
75 { S5H1411_I2C_TOP_ADDR
, 0x2e, 0x0d0e, },
76 { S5H1411_I2C_TOP_ADDR
, 0x2f, 0x1013, },
77 { S5H1411_I2C_TOP_ADDR
, 0x31, 0x171b, },
78 { S5H1411_I2C_TOP_ADDR
, 0x32, 0x0e0f, },
79 { S5H1411_I2C_TOP_ADDR
, 0x33, 0x0f10, },
80 { S5H1411_I2C_TOP_ADDR
, 0x34, 0x170e, },
81 { S5H1411_I2C_TOP_ADDR
, 0x35, 0x4b10, },
82 { S5H1411_I2C_TOP_ADDR
, 0x36, 0x0f17, },
83 { S5H1411_I2C_TOP_ADDR
, 0x3c, 0x1577, },
84 { S5H1411_I2C_TOP_ADDR
, 0x3d, 0x081a, },
85 { S5H1411_I2C_TOP_ADDR
, 0x3e, 0x77ee, },
86 { S5H1411_I2C_TOP_ADDR
, 0x40, 0x1e09, },
87 { S5H1411_I2C_TOP_ADDR
, 0x41, 0x0f0c, },
88 { S5H1411_I2C_TOP_ADDR
, 0x42, 0x1f10, },
89 { S5H1411_I2C_TOP_ADDR
, 0x4d, 0x0509, },
90 { S5H1411_I2C_TOP_ADDR
, 0x4e, 0x0a00, },
91 { S5H1411_I2C_TOP_ADDR
, 0x50, 0x0000, },
92 { S5H1411_I2C_TOP_ADDR
, 0x5b, 0x0000, },
93 { S5H1411_I2C_TOP_ADDR
, 0x5c, 0x0008, },
94 { S5H1411_I2C_TOP_ADDR
, 0x57, 0x1101, },
95 { S5H1411_I2C_TOP_ADDR
, 0x65, 0x007c, },
96 { S5H1411_I2C_TOP_ADDR
, 0x68, 0x0512, },
97 { S5H1411_I2C_TOP_ADDR
, 0x69, 0x0258, },
98 { S5H1411_I2C_TOP_ADDR
, 0x70, 0x0004, },
99 { S5H1411_I2C_TOP_ADDR
, 0x71, 0x0007, },
100 { S5H1411_I2C_TOP_ADDR
, 0x76, 0x00a9, },
101 { S5H1411_I2C_TOP_ADDR
, 0x78, 0x3141, },
102 { S5H1411_I2C_TOP_ADDR
, 0x7a, 0x3141, },
103 { S5H1411_I2C_TOP_ADDR
, 0xb3, 0x8003, },
104 { S5H1411_I2C_TOP_ADDR
, 0xb5, 0xa6bb, },
105 { S5H1411_I2C_TOP_ADDR
, 0xb6, 0x0609, },
106 { S5H1411_I2C_TOP_ADDR
, 0xb7, 0x2f06, },
107 { S5H1411_I2C_TOP_ADDR
, 0xb8, 0x003f, },
108 { S5H1411_I2C_TOP_ADDR
, 0xb9, 0x2700, },
109 { S5H1411_I2C_TOP_ADDR
, 0xba, 0xfac8, },
110 { S5H1411_I2C_TOP_ADDR
, 0xbe, 0x1003, },
111 { S5H1411_I2C_TOP_ADDR
, 0xbf, 0x103f, },
112 { S5H1411_I2C_TOP_ADDR
, 0xce, 0x2000, },
113 { S5H1411_I2C_TOP_ADDR
, 0xcf, 0x0800, },
114 { S5H1411_I2C_TOP_ADDR
, 0xd0, 0x0800, },
115 { S5H1411_I2C_TOP_ADDR
, 0xd1, 0x0400, },
116 { S5H1411_I2C_TOP_ADDR
, 0xd2, 0x0800, },
117 { S5H1411_I2C_TOP_ADDR
, 0xd3, 0x2000, },
118 { S5H1411_I2C_TOP_ADDR
, 0xd4, 0x3000, },
119 { S5H1411_I2C_TOP_ADDR
, 0xdb, 0x4a9b, },
120 { S5H1411_I2C_TOP_ADDR
, 0xdc, 0x1000, },
121 { S5H1411_I2C_TOP_ADDR
, 0xde, 0x0001, },
122 { S5H1411_I2C_TOP_ADDR
, 0xdf, 0x0000, },
123 { S5H1411_I2C_TOP_ADDR
, 0xe3, 0x0301, },
124 { S5H1411_I2C_QAM_ADDR
, 0xf3, 0x0000, },
125 { S5H1411_I2C_QAM_ADDR
, 0xf3, 0x0001, },
126 { S5H1411_I2C_QAM_ADDR
, 0x08, 0x0600, },
127 { S5H1411_I2C_QAM_ADDR
, 0x18, 0x4201, },
128 { S5H1411_I2C_QAM_ADDR
, 0x1e, 0x6476, },
129 { S5H1411_I2C_QAM_ADDR
, 0x21, 0x0830, },
130 { S5H1411_I2C_QAM_ADDR
, 0x0c, 0x5679, },
131 { S5H1411_I2C_QAM_ADDR
, 0x0d, 0x579b, },
132 { S5H1411_I2C_QAM_ADDR
, 0x24, 0x0102, },
133 { S5H1411_I2C_QAM_ADDR
, 0x31, 0x7488, },
134 { S5H1411_I2C_QAM_ADDR
, 0x32, 0x0a08, },
135 { S5H1411_I2C_QAM_ADDR
, 0x3d, 0x8689, },
136 { S5H1411_I2C_QAM_ADDR
, 0x49, 0x0048, },
137 { S5H1411_I2C_QAM_ADDR
, 0x57, 0x2012, },
138 { S5H1411_I2C_QAM_ADDR
, 0x5d, 0x7676, },
139 { S5H1411_I2C_QAM_ADDR
, 0x04, 0x0400, },
140 { S5H1411_I2C_QAM_ADDR
, 0x58, 0x00c0, },
141 { S5H1411_I2C_QAM_ADDR
, 0x5b, 0x0100, },
144 /* VSB SNR lookup table */
145 static struct vsb_snr_tab
{
189 /* QAM64 SNR lookup table */
190 static struct qam64_snr_tab
{
193 } qam64_snr_tab
[] = {
262 /* QAM256 SNR lookup table */
263 static struct qam256_snr_tab
{
266 } qam256_snr_tab
[] = {
341 /* 8 bit registers, 16 bit values */
342 static int s5h1411_writereg(struct s5h1411_state
*state
,
343 u8 addr
, u8 reg
, u16 data
)
346 u8 buf
[] = { reg
, data
>> 8, data
& 0xff };
348 struct i2c_msg msg
= { .addr
= addr
, .flags
= 0, .buf
= buf
, .len
= 3 };
350 ret
= i2c_transfer(state
->i2c
, &msg
, 1);
353 printk(KERN_ERR
"%s: writereg error 0x%02x 0x%02x 0x%04x, ret == %i)\n",
354 __func__
, addr
, reg
, data
, ret
);
356 return (ret
!= 1) ? -1 : 0;
359 static u16
s5h1411_readreg(struct s5h1411_state
*state
, u8 addr
, u8 reg
)
365 struct i2c_msg msg
[] = {
366 { .addr
= addr
, .flags
= 0, .buf
= b0
, .len
= 1 },
367 { .addr
= addr
, .flags
= I2C_M_RD
, .buf
= b1
, .len
= 2 } };
369 ret
= i2c_transfer(state
->i2c
, msg
, 2);
372 printk(KERN_ERR
"%s: readreg error (ret == %i)\n",
374 return (b1
[0] << 8) | b1
[1];
377 static int s5h1411_softreset(struct dvb_frontend
*fe
)
379 struct s5h1411_state
*state
= fe
->demodulator_priv
;
381 dprintk("%s()\n", __func__
);
383 s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0xf7, 0);
384 s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0xf7, 1);
388 static int s5h1411_set_if_freq(struct dvb_frontend
*fe
, int KHz
)
390 struct s5h1411_state
*state
= fe
->demodulator_priv
;
392 dprintk("%s(%d KHz)\n", __func__
, KHz
);
396 s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0x38, 0x10d5);
397 s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0x39, 0x5342);
398 s5h1411_writereg(state
, S5H1411_I2C_QAM_ADDR
, 0x2c, 0x10d9);
401 s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0x38, 0x1225);
402 s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0x39, 0x1e96);
403 s5h1411_writereg(state
, S5H1411_I2C_QAM_ADDR
, 0x2c, 0x1225);
406 s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0x38, 0x14bc);
407 s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0x39, 0xb53e);
408 s5h1411_writereg(state
, S5H1411_I2C_QAM_ADDR
, 0x2c, 0x14bd);
411 dprintk("%s(%d KHz) Invalid, defaulting to 5380\n",
416 s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0x38, 0x1be4);
417 s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0x39, 0x3655);
418 s5h1411_writereg(state
, S5H1411_I2C_QAM_ADDR
, 0x2c, 0x1be4);
422 state
->if_freq
= KHz
;
427 static int s5h1411_set_mpeg_timing(struct dvb_frontend
*fe
, int mode
)
429 struct s5h1411_state
*state
= fe
->demodulator_priv
;
432 dprintk("%s(%d)\n", __func__
, mode
);
434 val
= s5h1411_readreg(state
, S5H1411_I2C_TOP_ADDR
, 0xbe) & 0xcfff;
436 case S5H1411_MPEGTIMING_CONTINUOUS_INVERTING_CLOCK
:
439 case S5H1411_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK
:
440 dprintk("%s(%d) Mode1 or Defaulting\n", __func__
, mode
);
443 case S5H1411_MPEGTIMING_NONCONTINUOUS_INVERTING_CLOCK
:
446 case S5H1411_MPEGTIMING_NONCONTINUOUS_NONINVERTING_CLOCK
:
453 /* Configure MPEG Signal Timing charactistics */
454 return s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0xbe, val
);
457 static int s5h1411_set_spectralinversion(struct dvb_frontend
*fe
, int inversion
)
459 struct s5h1411_state
*state
= fe
->demodulator_priv
;
462 dprintk("%s(%d)\n", __func__
, inversion
);
463 val
= s5h1411_readreg(state
, S5H1411_I2C_TOP_ADDR
, 0x24) & ~0x1000;
466 val
|= 0x1000; /* Inverted */
468 state
->inversion
= inversion
;
469 return s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0x24, val
);
472 static int s5h1411_set_serialmode(struct dvb_frontend
*fe
, int serial
)
474 struct s5h1411_state
*state
= fe
->demodulator_priv
;
477 dprintk("%s(%d)\n", __func__
, serial
);
478 val
= s5h1411_readreg(state
, S5H1411_I2C_TOP_ADDR
, 0xbd) & ~0x100;
483 return s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0xbd, val
);
486 static int s5h1411_enable_modulation(struct dvb_frontend
*fe
,
487 enum fe_modulation m
)
489 struct s5h1411_state
*state
= fe
->demodulator_priv
;
491 dprintk("%s(0x%08x)\n", __func__
, m
);
493 if ((state
->first_tune
== 0) && (m
== state
->current_modulation
)) {
494 dprintk("%s() Already at desired modulation. Skipping...\n",
501 dprintk("%s() VSB_8\n", __func__
);
502 s5h1411_set_if_freq(fe
, state
->config
->vsb_if
);
503 s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0x00, 0x71);
504 s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0xf6, 0x00);
505 s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0xcd, 0xf1);
510 dprintk("%s() QAM_AUTO (64/256)\n", __func__
);
511 s5h1411_set_if_freq(fe
, state
->config
->qam_if
);
512 s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0x00, 0x0171);
513 s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0xf6, 0x0001);
514 s5h1411_writereg(state
, S5H1411_I2C_QAM_ADDR
, 0x16, 0x1101);
515 s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0xcd, 0x00f0);
518 dprintk("%s() Invalid modulation\n", __func__
);
522 state
->current_modulation
= m
;
523 state
->first_tune
= 0;
524 s5h1411_softreset(fe
);
529 static int s5h1411_i2c_gate_ctrl(struct dvb_frontend
*fe
, int enable
)
531 struct s5h1411_state
*state
= fe
->demodulator_priv
;
533 dprintk("%s(%d)\n", __func__
, enable
);
536 return s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0xf5, 1);
538 return s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0xf5, 0);
541 static int s5h1411_set_gpio(struct dvb_frontend
*fe
, int enable
)
543 struct s5h1411_state
*state
= fe
->demodulator_priv
;
546 dprintk("%s(%d)\n", __func__
, enable
);
548 val
= s5h1411_readreg(state
, S5H1411_I2C_TOP_ADDR
, 0xe0) & ~0x02;
551 return s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0xe0,
554 return s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0xe0, val
);
557 static int s5h1411_set_powerstate(struct dvb_frontend
*fe
, int enable
)
559 struct s5h1411_state
*state
= fe
->demodulator_priv
;
561 dprintk("%s(%d)\n", __func__
, enable
);
564 s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0xf4, 1);
566 s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0xf4, 0);
567 s5h1411_softreset(fe
);
573 static int s5h1411_sleep(struct dvb_frontend
*fe
)
575 return s5h1411_set_powerstate(fe
, 1);
578 static int s5h1411_register_reset(struct dvb_frontend
*fe
)
580 struct s5h1411_state
*state
= fe
->demodulator_priv
;
582 dprintk("%s()\n", __func__
);
584 return s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0xf3, 0);
587 /* Talk to the demod, set the FEC, GUARD, QAM settings etc */
588 static int s5h1411_set_frontend(struct dvb_frontend
*fe
)
590 struct dtv_frontend_properties
*p
= &fe
->dtv_property_cache
;
591 struct s5h1411_state
*state
= fe
->demodulator_priv
;
593 dprintk("%s(frequency=%d)\n", __func__
, p
->frequency
);
595 s5h1411_softreset(fe
);
597 state
->current_frequency
= p
->frequency
;
599 s5h1411_enable_modulation(fe
, p
->modulation
);
601 if (fe
->ops
.tuner_ops
.set_params
) {
602 if (fe
->ops
.i2c_gate_ctrl
)
603 fe
->ops
.i2c_gate_ctrl(fe
, 1);
605 fe
->ops
.tuner_ops
.set_params(fe
);
607 if (fe
->ops
.i2c_gate_ctrl
)
608 fe
->ops
.i2c_gate_ctrl(fe
, 0);
611 /* Issue a reset to the demod so it knows to resync against the
612 newly tuned frequency */
613 s5h1411_softreset(fe
);
618 /* Reset the demod hardware and reset all of the configuration registers
619 to a default state. */
620 static int s5h1411_init(struct dvb_frontend
*fe
)
622 struct s5h1411_state
*state
= fe
->demodulator_priv
;
625 dprintk("%s()\n", __func__
);
627 s5h1411_set_powerstate(fe
, 0);
628 s5h1411_register_reset(fe
);
630 for (i
= 0; i
< ARRAY_SIZE(init_tab
); i
++)
631 s5h1411_writereg(state
, init_tab
[i
].addr
,
635 /* The datasheet says that after initialisation, VSB is default */
636 state
->current_modulation
= VSB_8
;
638 /* Although the datasheet says it's in VSB, empirical evidence
639 shows problems getting lock on the first tuning request. Make
640 sure we call enable_modulation the first time around */
641 state
->first_tune
= 1;
643 if (state
->config
->output_mode
== S5H1411_SERIAL_OUTPUT
)
645 s5h1411_set_serialmode(fe
, 1);
648 s5h1411_set_serialmode(fe
, 0);
650 s5h1411_set_spectralinversion(fe
, state
->config
->inversion
);
651 s5h1411_set_if_freq(fe
, state
->config
->vsb_if
);
652 s5h1411_set_gpio(fe
, state
->config
->gpio
);
653 s5h1411_set_mpeg_timing(fe
, state
->config
->mpeg_timing
);
654 s5h1411_softreset(fe
);
656 /* Note: Leaving the I2C gate closed. */
657 s5h1411_i2c_gate_ctrl(fe
, 0);
662 static int s5h1411_read_status(struct dvb_frontend
*fe
, enum fe_status
*status
)
664 struct s5h1411_state
*state
= fe
->demodulator_priv
;
666 u32 tuner_status
= 0;
670 /* Register F2 bit 15 = Master Lock, removed */
672 switch (state
->current_modulation
) {
675 reg
= s5h1411_readreg(state
, S5H1411_I2C_TOP_ADDR
, 0xf0);
676 if (reg
& 0x10) /* QAM FEC Lock */
677 *status
|= FE_HAS_SYNC
| FE_HAS_LOCK
;
678 if (reg
& 0x100) /* QAM EQ Lock */
679 *status
|= FE_HAS_VITERBI
| FE_HAS_CARRIER
| FE_HAS_SIGNAL
;
683 reg
= s5h1411_readreg(state
, S5H1411_I2C_TOP_ADDR
, 0xf2);
684 if (reg
& 0x1000) /* FEC Lock */
685 *status
|= FE_HAS_SYNC
| FE_HAS_LOCK
;
686 if (reg
& 0x2000) /* EQ Lock */
687 *status
|= FE_HAS_VITERBI
| FE_HAS_CARRIER
| FE_HAS_SIGNAL
;
689 reg
= s5h1411_readreg(state
, S5H1411_I2C_TOP_ADDR
, 0x53);
690 if (reg
& 0x1) /* AFC Lock */
691 *status
|= FE_HAS_SIGNAL
;
698 switch (state
->config
->status_mode
) {
699 case S5H1411_DEMODLOCKING
:
700 if (*status
& FE_HAS_VITERBI
)
701 *status
|= FE_HAS_CARRIER
| FE_HAS_SIGNAL
;
703 case S5H1411_TUNERLOCKING
:
704 /* Get the tuner status */
705 if (fe
->ops
.tuner_ops
.get_status
) {
706 if (fe
->ops
.i2c_gate_ctrl
)
707 fe
->ops
.i2c_gate_ctrl(fe
, 1);
709 fe
->ops
.tuner_ops
.get_status(fe
, &tuner_status
);
711 if (fe
->ops
.i2c_gate_ctrl
)
712 fe
->ops
.i2c_gate_ctrl(fe
, 0);
715 *status
|= FE_HAS_CARRIER
| FE_HAS_SIGNAL
;
719 dprintk("%s() status 0x%08x\n", __func__
, *status
);
724 static int s5h1411_qam256_lookup_snr(struct dvb_frontend
*fe
, u16
*snr
, u16 v
)
726 int i
, ret
= -EINVAL
;
727 dprintk("%s()\n", __func__
);
729 for (i
= 0; i
< ARRAY_SIZE(qam256_snr_tab
); i
++) {
730 if (v
< qam256_snr_tab
[i
].val
) {
731 *snr
= qam256_snr_tab
[i
].data
;
739 static int s5h1411_qam64_lookup_snr(struct dvb_frontend
*fe
, u16
*snr
, u16 v
)
741 int i
, ret
= -EINVAL
;
742 dprintk("%s()\n", __func__
);
744 for (i
= 0; i
< ARRAY_SIZE(qam64_snr_tab
); i
++) {
745 if (v
< qam64_snr_tab
[i
].val
) {
746 *snr
= qam64_snr_tab
[i
].data
;
754 static int s5h1411_vsb_lookup_snr(struct dvb_frontend
*fe
, u16
*snr
, u16 v
)
756 int i
, ret
= -EINVAL
;
757 dprintk("%s()\n", __func__
);
759 for (i
= 0; i
< ARRAY_SIZE(vsb_snr_tab
); i
++) {
760 if (v
> vsb_snr_tab
[i
].val
) {
761 *snr
= vsb_snr_tab
[i
].data
;
766 dprintk("%s() snr=%d\n", __func__
, *snr
);
770 static int s5h1411_read_snr(struct dvb_frontend
*fe
, u16
*snr
)
772 struct s5h1411_state
*state
= fe
->demodulator_priv
;
774 dprintk("%s()\n", __func__
);
776 switch (state
->current_modulation
) {
778 reg
= s5h1411_readreg(state
, S5H1411_I2C_TOP_ADDR
, 0xf1);
779 return s5h1411_qam64_lookup_snr(fe
, snr
, reg
);
781 reg
= s5h1411_readreg(state
, S5H1411_I2C_TOP_ADDR
, 0xf1);
782 return s5h1411_qam256_lookup_snr(fe
, snr
, reg
);
784 reg
= s5h1411_readreg(state
, S5H1411_I2C_TOP_ADDR
,
786 return s5h1411_vsb_lookup_snr(fe
, snr
, reg
);
794 static int s5h1411_read_signal_strength(struct dvb_frontend
*fe
,
795 u16
*signal_strength
)
797 /* borrowed from lgdt330x.c
799 * Calculate strength from SNR up to 35dB
800 * Even though the SNR can go higher than 35dB,
801 * there is some comfort factor in having a range of
802 * strong signals that can show at 100%
806 int ret
= s5h1411_read_snr(fe
, &snr
);
808 *signal_strength
= 0;
811 /* The following calculation method was chosen
812 * purely for the sake of code re-use from the
813 * other demod drivers that use this method */
815 /* Convert from SNR in dB * 10 to 8.24 fixed-point */
816 tmp
= (snr
* ((1 << 24) / 10));
818 /* Convert from 8.24 fixed-point to
819 * scale the range 0 - 35*2^24 into 0 - 65535*/
820 if (tmp
>= 8960 * 0x10000)
821 *signal_strength
= 0xffff;
823 *signal_strength
= tmp
/ 8960;
829 static int s5h1411_read_ucblocks(struct dvb_frontend
*fe
, u32
*ucblocks
)
831 struct s5h1411_state
*state
= fe
->demodulator_priv
;
833 *ucblocks
= s5h1411_readreg(state
, S5H1411_I2C_TOP_ADDR
, 0xc9);
838 static int s5h1411_read_ber(struct dvb_frontend
*fe
, u32
*ber
)
840 return s5h1411_read_ucblocks(fe
, ber
);
843 static int s5h1411_get_frontend(struct dvb_frontend
*fe
,
844 struct dtv_frontend_properties
*p
)
846 struct s5h1411_state
*state
= fe
->demodulator_priv
;
848 p
->frequency
= state
->current_frequency
;
849 p
->modulation
= state
->current_modulation
;
854 static int s5h1411_get_tune_settings(struct dvb_frontend
*fe
,
855 struct dvb_frontend_tune_settings
*tune
)
857 tune
->min_delay_ms
= 1000;
861 static void s5h1411_release(struct dvb_frontend
*fe
)
863 struct s5h1411_state
*state
= fe
->demodulator_priv
;
867 static const struct dvb_frontend_ops s5h1411_ops
;
869 struct dvb_frontend
*s5h1411_attach(const struct s5h1411_config
*config
,
870 struct i2c_adapter
*i2c
)
872 struct s5h1411_state
*state
= NULL
;
875 /* allocate memory for the internal state */
876 state
= kzalloc(sizeof(struct s5h1411_state
), GFP_KERNEL
);
880 /* setup the state */
881 state
->config
= config
;
883 state
->current_modulation
= VSB_8
;
884 state
->inversion
= state
->config
->inversion
;
886 /* check if the demod exists */
887 reg
= s5h1411_readreg(state
, S5H1411_I2C_TOP_ADDR
, 0x05);
891 /* create dvb_frontend */
892 memcpy(&state
->frontend
.ops
, &s5h1411_ops
,
893 sizeof(struct dvb_frontend_ops
));
895 state
->frontend
.demodulator_priv
= state
;
897 if (s5h1411_init(&state
->frontend
) != 0) {
898 printk(KERN_ERR
"%s: Failed to initialize correctly\n",
903 /* Note: Leaving the I2C gate open here. */
904 s5h1411_writereg(state
, S5H1411_I2C_TOP_ADDR
, 0xf5, 1);
906 /* Put the device into low-power mode until first use */
907 s5h1411_set_powerstate(&state
->frontend
, 1);
909 return &state
->frontend
;
915 EXPORT_SYMBOL(s5h1411_attach
);
917 static const struct dvb_frontend_ops s5h1411_ops
= {
918 .delsys
= { SYS_ATSC
, SYS_DVBC_ANNEX_B
},
920 .name
= "Samsung S5H1411 QAM/8VSB Frontend",
921 .frequency_min_hz
= 54 * MHz
,
922 .frequency_max_hz
= 858 * MHz
,
923 .frequency_stepsize_hz
= 62500,
924 .caps
= FE_CAN_QAM_64
| FE_CAN_QAM_256
| FE_CAN_8VSB
927 .init
= s5h1411_init
,
928 .sleep
= s5h1411_sleep
,
929 .i2c_gate_ctrl
= s5h1411_i2c_gate_ctrl
,
930 .set_frontend
= s5h1411_set_frontend
,
931 .get_frontend
= s5h1411_get_frontend
,
932 .get_tune_settings
= s5h1411_get_tune_settings
,
933 .read_status
= s5h1411_read_status
,
934 .read_ber
= s5h1411_read_ber
,
935 .read_signal_strength
= s5h1411_read_signal_strength
,
936 .read_snr
= s5h1411_read_snr
,
937 .read_ucblocks
= s5h1411_read_ucblocks
,
938 .release
= s5h1411_release
,
941 module_param(debug
, int, 0644);
942 MODULE_PARM_DESC(debug
, "Enable verbose debug messages");
944 MODULE_DESCRIPTION("Samsung S5H1411 QAM-B/ATSC Demodulator driver");
945 MODULE_AUTHOR("Steven Toth");
946 MODULE_LICENSE("GPL");