drivers/gpu/drm/i915/intel_vbt_defs.h

   1 /*
   2  * Copyright © 2006-2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 /*
  29  * This information is private to VBT parsing in intel_bios.c.
  30  *
  31  * Please do NOT include anywhere else.
  32  */
  33 #ifndef _INTEL_BIOS_PRIVATE
  34 #error "intel_vbt_defs.h is private to intel_bios.c"
  35 #endif
  36
  37 #ifndef _INTEL_VBT_DEFS_H_
  38 #define _INTEL_VBT_DEFS_H_
  39
  40 #include "intel_bios.h"
  41
  42 /**
  43  * struct vbt_header - VBT Header structure
  44  * @signature:          VBT signature, always starts with "$VBT"
  45  * @version:            Version of this structure
  46  * @header_size:        Size of this structure
  47  * @vbt_size:           Size of VBT (VBT Header, BDB Header and data blocks)
  48  * @vbt_checksum:       Checksum
  49  * @reserved0:          Reserved
  50  * @bdb_offset:         Offset of &struct bdb_header from beginning of VBT
  51  * @aim_offset:         Offsets of add-in data blocks from beginning of VBT
  52  */
  53 struct vbt_header {
  54         u8 signature[20];
  55         u16 version;
  56         u16 header_size;
  57         u16 vbt_size;
  58         u8 vbt_checksum;
  59         u8 reserved0;
  60         u32 bdb_offset;
  61         u32 aim_offset[4];
  62 } __packed;
  63
  64 /**
  65  * struct bdb_header - BDB Header structure
  66  * @signature:          BDB signature "BIOS_DATA_BLOCK"
  67  * @version:            Version of the data block definitions
  68  * @header_size:        Size of this structure
  69  * @bdb_size:           Size of BDB (BDB Header and data blocks)
  70  */
  71 struct bdb_header {
  72         u8 signature[16];
  73         u16 version;
  74         u16 header_size;
  75         u16 bdb_size;
  76 } __packed;
  77
  78 /* strictly speaking, this is a "skip" block, but it has interesting info */
  79 struct vbios_data {
  80         u8 type; /* 0 == desktop, 1 == mobile */
  81         u8 relstage;
  82         u8 chipset;
  83         u8 lvds_present:1;
  84         u8 tv_present:1;
  85         u8 rsvd2:6; /* finish byte */
  86         u8 rsvd3[4];
  87         u8 signon[155];
  88         u8 copyright[61];
  89         u16 code_segment;
  90         u8 dos_boot_mode;
  91         u8 bandwidth_percent;
  92         u8 rsvd4; /* popup memory size */
  93         u8 resize_pci_bios;
  94         u8 rsvd5; /* is crt already on ddc2 */
  95 } __packed;
  96
  97 /*
  98  * There are several types of BIOS data blocks (BDBs), each block has
  99  * an ID and size in the first 3 bytes (ID in first, size in next 2).
 100  * Known types are listed below.
 101  */
 102 #define BDB_GENERAL_FEATURES      1
 103 #define BDB_GENERAL_DEFINITIONS   2
 104 #define BDB_OLD_TOGGLE_LIST       3
 105 #define BDB_MODE_SUPPORT_LIST     4
 106 #define BDB_GENERIC_MODE_TABLE    5
 107 #define BDB_EXT_MMIO_REGS         6
 108 #define BDB_SWF_IO                7
 109 #define BDB_SWF_MMIO              8
 110 #define BDB_PSR                   9
 111 #define BDB_MODE_REMOVAL_TABLE   10
 112 #define BDB_CHILD_DEVICE_TABLE   11
 113 #define BDB_DRIVER_FEATURES      12
 114 #define BDB_DRIVER_PERSISTENCE   13
 115 #define BDB_EXT_TABLE_PTRS       14
 116 #define BDB_DOT_CLOCK_OVERRIDE   15
 117 #define BDB_DISPLAY_SELECT       16
 118 /* 17 rsvd */
 119 #define BDB_DRIVER_ROTATION      18
 120 #define BDB_DISPLAY_REMOVE       19
 121 #define BDB_OEM_CUSTOM           20
 122 #define BDB_EFP_LIST             21 /* workarounds for VGA hsync/vsync */
 123 #define BDB_SDVO_LVDS_OPTIONS    22
 124 #define BDB_SDVO_PANEL_DTDS      23
 125 #define BDB_SDVO_LVDS_PNP_IDS    24
 126 #define BDB_SDVO_LVDS_POWER_SEQ  25
 127 #define BDB_TV_OPTIONS           26
 128 #define BDB_EDP                  27
 129 #define BDB_LVDS_OPTIONS         40
 130 #define BDB_LVDS_LFP_DATA_PTRS   41
 131 #define BDB_LVDS_LFP_DATA        42
 132 #define BDB_LVDS_BACKLIGHT       43
 133 #define BDB_LVDS_POWER           44
 134 #define BDB_MIPI_CONFIG          52
 135 #define BDB_MIPI_SEQUENCE        53
 136 #define BDB_SKIP                254 /* VBIOS private block, ignore */
 137
 138 struct bdb_general_features {
 139         /* bits 1 */
 140         u8 panel_fitting:2;
 141         u8 flexaim:1;
 142         u8 msg_enable:1;
 143         u8 clear_screen:3;
 144         u8 color_flip:1;
 145
 146         /* bits 2 */
 147         u8 download_ext_vbt:1;
 148         u8 enable_ssc:1;
 149         u8 ssc_freq:1;
 150         u8 enable_lfp_on_override:1;
 151         u8 disable_ssc_ddt:1;
 152         u8 underscan_vga_timings:1;
 153         u8 display_clock_mode:1;
 154         u8 vbios_hotplug_support:1;
 155
 156         /* bits 3 */
 157         u8 disable_smooth_vision:1;
 158         u8 single_dvi:1;
 159         u8 rotate_180:1;                                        /* 181 */
 160         u8 fdi_rx_polarity_inverted:1;
 161         u8 vbios_extended_mode:1;                               /* 160 */
 162         u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1;                    /* 160 */
 163         u8 panel_best_fit_timing:1;                             /* 160 */
 164         u8 ignore_strap_state:1;                                /* 160 */
 165
 166         /* bits 4 */
 167         u8 legacy_monitor_detect;
 168
 169         /* bits 5 */
 170         u8 int_crt_support:1;
 171         u8 int_tv_support:1;
 172         u8 int_efp_support:1;
 173         u8 dp_ssc_enable:1;     /* PCH attached eDP supports SSC */
 174         u8 dp_ssc_freq:1;       /* SSC freq for PCH attached eDP */
 175         u8 dp_ssc_dongle_supported:1;
 176         u8 rsvd11:2; /* finish byte */
 177 } __packed;
 178
 179 /* pre-915 */
 180 #define GPIO_PIN_DVI_LVDS       0x03 /* "DVI/LVDS DDC GPIO pins" */
 181 #define GPIO_PIN_ADD_I2C        0x05 /* "ADDCARD I2C GPIO pins" */
 182 #define GPIO_PIN_ADD_DDC        0x04 /* "ADDCARD DDC GPIO pins" */
 183 #define GPIO_PIN_ADD_DDC_I2C    0x06 /* "ADDCARD DDC/I2C GPIO pins" */
 184
 185 /* Pre 915 */
 186 #define DEVICE_TYPE_NONE        0x00
 187 #define DEVICE_TYPE_CRT         0x01
 188 #define DEVICE_TYPE_TV          0x09
 189 #define DEVICE_TYPE_EFP         0x12
 190 #define DEVICE_TYPE_LFP         0x22
 191 /* On 915+ */
 192 #define DEVICE_TYPE_CRT_DPMS            0x6001
 193 #define DEVICE_TYPE_CRT_DPMS_HOTPLUG    0x4001
 194 #define DEVICE_TYPE_TV_COMPOSITE        0x0209
 195 #define DEVICE_TYPE_TV_MACROVISION      0x0289
 196 #define DEVICE_TYPE_TV_RF_COMPOSITE     0x020c
 197 #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
 198 #define DEVICE_TYPE_TV_SCART            0x0209
 199 #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
 200 #define DEVICE_TYPE_EFP_HOTPLUG_PWR     0x6012
 201 #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
 202 #define DEVICE_TYPE_EFP_DVI_I           0x6053
 203 #define DEVICE_TYPE_EFP_DVI_D_DUAL      0x6152
 204 #define DEVICE_TYPE_EFP_DVI_D_HDCP      0x60d2
 205 #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
 206 #define DEVICE_TYPE_OPENLDI_DUALPIX     0x6162
 207 #define DEVICE_TYPE_LFP_PANELLINK       0x5012
 208 #define DEVICE_TYPE_LFP_CMOS_PWR        0x5042
 209 #define DEVICE_TYPE_LFP_LVDS_PWR        0x5062
 210 #define DEVICE_TYPE_LFP_LVDS_DUAL       0x5162
 211 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP  0x51e2
 212
 213 /* Add the device class for LFP, TV, HDMI */
 214 #define DEVICE_TYPE_INT_LFP             0x1022
 215 #define DEVICE_TYPE_INT_TV              0x1009
 216 #define DEVICE_TYPE_HDMI                0x60D2
 217 #define DEVICE_TYPE_DP                  0x68C6
 218 #define DEVICE_TYPE_DP_DUAL_MODE        0x60D6
 219 #define DEVICE_TYPE_eDP                 0x78C6
 220
 221 #define DEVICE_TYPE_CLASS_EXTENSION     (1 << 15)
 222 #define DEVICE_TYPE_POWER_MANAGEMENT    (1 << 14)
 223 #define DEVICE_TYPE_HOTPLUG_SIGNALING   (1 << 13)
 224 #define DEVICE_TYPE_INTERNAL_CONNECTOR  (1 << 12)
 225 #define DEVICE_TYPE_NOT_HDMI_OUTPUT     (1 << 11)
 226 #define DEVICE_TYPE_MIPI_OUTPUT         (1 << 10)
 227 #define DEVICE_TYPE_COMPOSITE_OUTPUT    (1 << 9)
 228 #define DEVICE_TYPE_DUAL_CHANNEL        (1 << 8)
 229 #define DEVICE_TYPE_HIGH_SPEED_LINK     (1 << 6)
 230 #define DEVICE_TYPE_LVDS_SIGNALING      (1 << 5)
 231 #define DEVICE_TYPE_TMDS_DVI_SIGNALING  (1 << 4)
 232 #define DEVICE_TYPE_VIDEO_SIGNALING     (1 << 3)
 233 #define DEVICE_TYPE_DISPLAYPORT_OUTPUT  (1 << 2)
 234 #define DEVICE_TYPE_DIGITAL_OUTPUT      (1 << 1)
 235 #define DEVICE_TYPE_ANALOG_OUTPUT       (1 << 0)
 236
 237 /*
 238  * Bits we care about when checking for DEVICE_TYPE_eDP. Depending on the
 239  * system, the other bits may or may not be set for eDP outputs.
 240  */
 241 #define DEVICE_TYPE_eDP_BITS \
 242         (DEVICE_TYPE_INTERNAL_CONNECTOR |       \
 243          DEVICE_TYPE_MIPI_OUTPUT |              \
 244          DEVICE_TYPE_COMPOSITE_OUTPUT |         \
 245          DEVICE_TYPE_DUAL_CHANNEL |             \
 246          DEVICE_TYPE_LVDS_SIGNALING |           \
 247          DEVICE_TYPE_TMDS_DVI_SIGNALING |       \
 248          DEVICE_TYPE_VIDEO_SIGNALING |          \
 249          DEVICE_TYPE_DISPLAYPORT_OUTPUT |       \
 250          DEVICE_TYPE_ANALOG_OUTPUT)
 251
 252 #define DEVICE_TYPE_DP_DUAL_MODE_BITS \
 253         (DEVICE_TYPE_INTERNAL_CONNECTOR |       \
 254          DEVICE_TYPE_MIPI_OUTPUT |              \
 255          DEVICE_TYPE_COMPOSITE_OUTPUT |         \
 256          DEVICE_TYPE_LVDS_SIGNALING |           \
 257          DEVICE_TYPE_TMDS_DVI_SIGNALING |       \
 258          DEVICE_TYPE_VIDEO_SIGNALING |          \
 259          DEVICE_TYPE_DISPLAYPORT_OUTPUT |       \
 260          DEVICE_TYPE_DIGITAL_OUTPUT |           \
 261          DEVICE_TYPE_ANALOG_OUTPUT)
 262
 263 #define DEVICE_CFG_NONE         0x00
 264 #define DEVICE_CFG_12BIT_DVOB   0x01
 265 #define DEVICE_CFG_12BIT_DVOC   0x02
 266 #define DEVICE_CFG_24BIT_DVOBC  0x09
 267 #define DEVICE_CFG_24BIT_DVOCB  0x0a
 268 #define DEVICE_CFG_DUAL_DVOB    0x11
 269 #define DEVICE_CFG_DUAL_DVOC    0x12
 270 #define DEVICE_CFG_DUAL_DVOBC   0x13
 271 #define DEVICE_CFG_DUAL_LINK_DVOBC      0x19
 272 #define DEVICE_CFG_DUAL_LINK_DVOCB      0x1a
 273
 274 #define DEVICE_WIRE_NONE        0x00
 275 #define DEVICE_WIRE_DVOB        0x01
 276 #define DEVICE_WIRE_DVOC        0x02
 277 #define DEVICE_WIRE_DVOBC       0x03
 278 #define DEVICE_WIRE_DVOBB       0x05
 279 #define DEVICE_WIRE_DVOCC       0x06
 280 #define DEVICE_WIRE_DVOB_MASTER 0x0d
 281 #define DEVICE_WIRE_DVOC_MASTER 0x0e
 282
 283 /* dvo_port pre BDB 155 */
 284 #define DEVICE_PORT_DVOA        0x00 /* none on 845+ */
 285 #define DEVICE_PORT_DVOB        0x01
 286 #define DEVICE_PORT_DVOC        0x02
 287
 288 /* dvo_port BDB 155+ */
 289 #define DVO_PORT_HDMIA          0
 290 #define DVO_PORT_HDMIB          1
 291 #define DVO_PORT_HDMIC          2
 292 #define DVO_PORT_HDMID          3
 293 #define DVO_PORT_LVDS           4
 294 #define DVO_PORT_TV             5
 295 #define DVO_PORT_CRT            6
 296 #define DVO_PORT_DPB            7
 297 #define DVO_PORT_DPC            8
 298 #define DVO_PORT_DPD            9
 299 #define DVO_PORT_DPA            10
 300 #define DVO_PORT_DPE            11                              /* 193 */
 301 #define DVO_PORT_HDMIE          12                              /* 193 */
 302 #define DVO_PORT_DPF            13                              /* N/A */
 303 #define DVO_PORT_HDMIF          14                              /* N/A */
 304 #define DVO_PORT_MIPIA          21                              /* 171 */
 305 #define DVO_PORT_MIPIB          22                              /* 171 */
 306 #define DVO_PORT_MIPIC          23                              /* 171 */
 307 #define DVO_PORT_MIPID          24                              /* 171 */
 308
 309 #define HDMI_MAX_DATA_RATE_PLATFORM     0                       /* 204 */
 310 #define HDMI_MAX_DATA_RATE_297          1                       /* 204 */
 311 #define HDMI_MAX_DATA_RATE_165          2                       /* 204 */
 312
 313 #define LEGACY_CHILD_DEVICE_CONFIG_SIZE         33
 314
 315 /* DDC Bus DDI Type 155+ */
 316 enum vbt_gmbus_ddi {
 317         DDC_BUS_DDI_B = 0x1,
 318         DDC_BUS_DDI_C,
 319         DDC_BUS_DDI_D,
 320         DDC_BUS_DDI_F,
 321         ICL_DDC_BUS_DDI_A = 0x1,
 322         ICL_DDC_BUS_DDI_B,
 323         ICL_DDC_BUS_PORT_1 = 0x4,
 324         ICL_DDC_BUS_PORT_2,
 325         ICL_DDC_BUS_PORT_3,
 326         ICL_DDC_BUS_PORT_4,
 327 };
 328
 329 #define VBT_DP_MAX_LINK_RATE_HBR3       0
 330 #define VBT_DP_MAX_LINK_RATE_HBR2       1
 331 #define VBT_DP_MAX_LINK_RATE_HBR        2
 332 #define VBT_DP_MAX_LINK_RATE_LBR        3
 333
 334 /*
 335  * The child device config, aka the display device data structure, provides a
 336  * description of a port and its configuration on the platform.
 337  *
 338  * The child device config size has been increased, and fields have been added
 339  * and their meaning has changed over time. Care must be taken when accessing
 340  * basically any of the fields to ensure the correct interpretation for the BDB
 341  * version in question.
 342  *
 343  * When we copy the child device configs to dev_priv->vbt.child_dev, we reserve
 344  * space for the full structure below, and initialize the tail not actually
 345  * present in VBT to zeros. Accessing those fields is fine, as long as the
 346  * default zero is taken into account, again according to the BDB version.
 347  *
 348  * BDB versions 155 and below are considered legacy, and version 155 seems to be
 349  * a baseline for some of the VBT documentation. When adding new fields, please
 350  * include the BDB version when the field was added, if it's above that.
 351  */
 352 struct child_device_config {
 353         u16 handle;
 354         u16 device_type; /* See DEVICE_TYPE_* above */
 355
 356         union {
 357                 u8  device_id[10]; /* ascii string */
 358                 struct {
 359                         u8 i2c_speed;
 360                         u8 dp_onboard_redriver;                 /* 158 */
 361                         u8 dp_ondock_redriver;                  /* 158 */
 362                         u8 hdmi_level_shifter_value:5;          /* 169 */
 363                         u8 hdmi_max_data_rate:3;                /* 204 */
 364                         u16 dtd_buf_ptr;                        /* 161 */
 365                         u8 edidless_efp:1;                      /* 161 */
 366                         u8 compression_enable:1;                /* 198 */
 367                         u8 compression_method:1;                /* 198 */
 368                         u8 ganged_edp:1;                        /* 202 */
 369                         u8 reserved0:4;
 370                         u8 compression_structure_index:4;       /* 198 */
 371                         u8 reserved1:4;
 372                         u8 slave_port;                          /* 202 */
 373                         u8 reserved2;
 374                 } __packed;
 375         } __packed;
 376
 377         u16 addin_offset;
 378         u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */
 379         u8 i2c_pin;
 380         u8 slave_addr;
 381         u8 ddc_pin;
 382         u16 edid_ptr;
 383         u8 dvo_cfg; /* See DEVICE_CFG_* above */
 384
 385         union {
 386                 struct {
 387                         u8 dvo2_port;
 388                         u8 i2c2_pin;
 389                         u8 slave2_addr;
 390                         u8 ddc2_pin;
 391                 } __packed;
 392                 struct {
 393                         u8 efp_routed:1;                        /* 158 */
 394                         u8 lane_reversal:1;                     /* 184 */
 395                         u8 lspcon:1;                            /* 192 */
 396                         u8 iboost:1;                            /* 196 */
 397                         u8 hpd_invert:1;                        /* 196 */
 398                         u8 flag_reserved:3;
 399                         u8 hdmi_support:1;                      /* 158 */
 400                         u8 dp_support:1;                        /* 158 */
 401                         u8 tmds_support:1;                      /* 158 */
 402                         u8 support_reserved:5;
 403                         u8 aux_channel;
 404                         u8 dongle_detect;
 405                 } __packed;
 406         } __packed;
 407
 408         u8 pipe_cap:2;
 409         u8 sdvo_stall:1;                                        /* 158 */
 410         u8 hpd_status:2;
 411         u8 integrated_encoder:1;
 412         u8 capabilities_reserved:2;
 413         u8 dvo_wiring; /* See DEVICE_WIRE_* above */
 414
 415         union {
 416                 u8 dvo2_wiring;
 417                 u8 mipi_bridge_type;                            /* 171 */
 418         } __packed;
 419
 420         u16 extended_type;
 421         u8 dvo_function;
 422         u8 dp_usb_type_c:1;                                     /* 195 */
 423         u8 tbt:1;                                               /* 209 */
 424         u8 flags2_reserved:2;                                   /* 195 */
 425         u8 dp_port_trace_length:4;                              /* 209 */
 426         u8 dp_gpio_index;                                       /* 195 */
 427         u16 dp_gpio_pin_num;                                    /* 195 */
 428         u8 dp_iboost_level:4;                                   /* 196 */
 429         u8 hdmi_iboost_level:4;                                 /* 196 */
 430         u8 dp_max_link_rate:2;                                  /* 216 CNL+ */
 431         u8 dp_max_link_rate_reserved:6;                         /* 216 */
 432 } __packed;
 433
 434 struct bdb_general_definitions {
 435         /* DDC GPIO */
 436         u8 crt_ddc_gmbus_pin;
 437
 438         /* DPMS bits */
 439         u8 dpms_acpi:1;
 440         u8 skip_boot_crt_detect:1;
 441         u8 dpms_aim:1;
 442         u8 rsvd1:5; /* finish byte */
 443
 444         /* boot device bits */
 445         u8 boot_display[2];
 446         u8 child_dev_size;
 447
 448         /*
 449          * Device info:
 450          * If TV is present, it'll be at devices[0].
 451          * LVDS will be next, either devices[0] or [1], if present.
 452          * On some platforms the number of device is 6. But could be as few as
 453          * 4 if both TV and LVDS are missing.
 454          * And the device num is related with the size of general definition
 455          * block. It is obtained by using the following formula:
 456          * number = (block_size - sizeof(bdb_general_definitions))/
 457          *           defs->child_dev_size;
 458          */
 459         u8 devices[0];
 460 } __packed;
 461
 462 /* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
 463 #define MODE_MASK               0x3
 464
 465 struct bdb_lvds_options {
 466         u8 panel_type;
 467         u8 rsvd1;
 468         /* LVDS capabilities, stored in a dword */
 469         u8 pfit_mode:2;
 470         u8 pfit_text_mode_enhanced:1;
 471         u8 pfit_gfx_mode_enhanced:1;
 472         u8 pfit_ratio_auto:1;
 473         u8 pixel_dither:1;
 474         u8 lvds_edid:1;
 475         u8 rsvd2:1;
 476         u8 rsvd4;
 477         /* LVDS Panel channel bits stored here */
 478         u32 lvds_panel_channel_bits;
 479         /* LVDS SSC (Spread Spectrum Clock) bits stored here. */
 480         u16 ssc_bits;
 481         u16 ssc_freq;
 482         u16 ssc_ddt;
 483         /* Panel color depth defined here */
 484         u16 panel_color_depth;
 485         /* LVDS panel type bits stored here */
 486         u32 dps_panel_type_bits;
 487         /* LVDS backlight control type bits stored here */
 488         u32 blt_control_type_bits;
 489 } __packed;
 490
 491 /* LFP pointer table contains entries to the struct below */
 492 struct bdb_lvds_lfp_data_ptr {
 493         u16 fp_timing_offset; /* offsets are from start of bdb */
 494         u8 fp_table_size;
 495         u16 dvo_timing_offset;
 496         u8 dvo_table_size;
 497         u16 panel_pnp_id_offset;
 498         u8 pnp_table_size;
 499 } __packed;
 500
 501 struct bdb_lvds_lfp_data_ptrs {
 502         u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
 503         struct bdb_lvds_lfp_data_ptr ptr[16];
 504 } __packed;
 505
 506 /* LFP data has 3 blocks per entry */
 507 struct lvds_fp_timing {
 508         u16 x_res;
 509         u16 y_res;
 510         u32 lvds_reg;
 511         u32 lvds_reg_val;
 512         u32 pp_on_reg;
 513         u32 pp_on_reg_val;
 514         u32 pp_off_reg;
 515         u32 pp_off_reg_val;
 516         u32 pp_cycle_reg;
 517         u32 pp_cycle_reg_val;
 518         u32 pfit_reg;
 519         u32 pfit_reg_val;
 520         u16 terminator;
 521 } __packed;
 522
 523 struct lvds_dvo_timing {
 524         u16 clock;              /**< In 10khz */
 525         u8 hactive_lo;
 526         u8 hblank_lo;
 527         u8 hblank_hi:4;
 528         u8 hactive_hi:4;
 529         u8 vactive_lo;
 530         u8 vblank_lo;
 531         u8 vblank_hi:4;
 532         u8 vactive_hi:4;
 533         u8 hsync_off_lo;
 534         u8 hsync_pulse_width_lo;
 535         u8 vsync_pulse_width_lo:4;
 536         u8 vsync_off_lo:4;
 537         u8 vsync_pulse_width_hi:2;
 538         u8 vsync_off_hi:2;
 539         u8 hsync_pulse_width_hi:2;
 540         u8 hsync_off_hi:2;
 541         u8 himage_lo;
 542         u8 vimage_lo;
 543         u8 vimage_hi:4;
 544         u8 himage_hi:4;
 545         u8 h_border;
 546         u8 v_border;
 547         u8 rsvd1:3;
 548         u8 digital:2;
 549         u8 vsync_positive:1;
 550         u8 hsync_positive:1;
 551         u8 non_interlaced:1;
 552 } __packed;
 553
 554 struct lvds_pnp_id {
 555         u16 mfg_name;
 556         u16 product_code;
 557         u32 serial;
 558         u8 mfg_week;
 559         u8 mfg_year;
 560 } __packed;
 561
 562 struct bdb_lvds_lfp_data_entry {
 563         struct lvds_fp_timing fp_timing;
 564         struct lvds_dvo_timing dvo_timing;
 565         struct lvds_pnp_id pnp_id;
 566 } __packed;
 567
 568 struct bdb_lvds_lfp_data {
 569         struct bdb_lvds_lfp_data_entry data[16];
 570 } __packed;
 571
 572 #define BDB_BACKLIGHT_TYPE_NONE 0
 573 #define BDB_BACKLIGHT_TYPE_PWM  2
 574
 575 struct bdb_lfp_backlight_data_entry {
 576         u8 type:2;
 577         u8 active_low_pwm:1;
 578         u8 obsolete1:5;
 579         u16 pwm_freq_hz;
 580         u8 min_brightness;
 581         u8 obsolete2;
 582         u8 obsolete3;
 583 } __packed;
 584
 585 struct bdb_lfp_backlight_control_method {
 586         u8 type:4;
 587         u8 controller:4;
 588 } __packed;
 589
 590 struct bdb_lfp_backlight_data {
 591         u8 entry_size;
 592         struct bdb_lfp_backlight_data_entry data[16];
 593         u8 level[16];
 594         struct bdb_lfp_backlight_control_method backlight_control[16];
 595 } __packed;
 596
 597 struct aimdb_header {
 598         char signature[16];
 599         char oem_device[20];
 600         u16 aimdb_version;
 601         u16 aimdb_header_size;
 602         u16 aimdb_size;
 603 } __packed;
 604
 605 struct aimdb_block {
 606         u8 aimdb_id;
 607         u16 aimdb_size;
 608 } __packed;
 609
 610 struct vch_panel_data {
 611         u16 fp_timing_offset;
 612         u8 fp_timing_size;
 613         u16 dvo_timing_offset;
 614         u8 dvo_timing_size;
 615         u16 text_fitting_offset;
 616         u8 text_fitting_size;
 617         u16 graphics_fitting_offset;
 618         u8 graphics_fitting_size;
 619 } __packed;
 620
 621 struct vch_bdb_22 {
 622         struct aimdb_block aimdb_block;
 623         struct vch_panel_data panels[16];
 624 } __packed;
 625
 626 struct bdb_sdvo_lvds_options {
 627         u8 panel_backlight;
 628         u8 h40_set_panel_type;
 629         u8 panel_type;
 630         u8 ssc_clk_freq;
 631         u16 als_low_trip;
 632         u16 als_high_trip;
 633         u8 sclalarcoeff_tab_row_num;
 634         u8 sclalarcoeff_tab_row_size;
 635         u8 coefficient[8];
 636         u8 panel_misc_bits_1;
 637         u8 panel_misc_bits_2;
 638         u8 panel_misc_bits_3;
 639         u8 panel_misc_bits_4;
 640 } __packed;
 641
 642
 643 #define BDB_DRIVER_FEATURE_NO_LVDS              0
 644 #define BDB_DRIVER_FEATURE_INT_LVDS             1
 645 #define BDB_DRIVER_FEATURE_SDVO_LVDS            2
 646 #define BDB_DRIVER_FEATURE_INT_SDVO_LVDS        3
 647
 648 struct bdb_driver_features {
 649         u8 boot_dev_algorithm:1;
 650         u8 block_display_switch:1;
 651         u8 allow_display_switch:1;
 652         u8 hotplug_dvo:1;
 653         u8 dual_view_zoom:1;
 654         u8 int15h_hook:1;
 655         u8 sprite_in_clone:1;
 656         u8 primary_lfp_id:1;
 657
 658         u16 boot_mode_x;
 659         u16 boot_mode_y;
 660         u8 boot_mode_bpp;
 661         u8 boot_mode_refresh;
 662
 663         u16 enable_lfp_primary:1;
 664         u16 selective_mode_pruning:1;
 665         u16 dual_frequency:1;
 666         u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
 667         u16 nt_clone_support:1;
 668         u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
 669         u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
 670         u16 cui_aspect_scaling:1;
 671         u16 preserve_aspect_ratio:1;
 672         u16 sdvo_device_power_down:1;
 673         u16 crt_hotplug:1;
 674         u16 lvds_config:2;
 675         u16 tv_hotplug:1;
 676         u16 hdmi_config:2;
 677
 678         u8 static_display:1;
 679         u8 reserved2:7;
 680         u16 legacy_crt_max_x;
 681         u16 legacy_crt_max_y;
 682         u8 legacy_crt_max_refresh;
 683
 684         u8 hdmi_termination;
 685         u8 custom_vbt_version;
 686         /* Driver features data block */
 687         u16 rmpm_enabled:1;
 688         u16 s2ddt_enabled:1;
 689         u16 dpst_enabled:1;
 690         u16 bltclt_enabled:1;
 691         u16 adb_enabled:1;
 692         u16 drrs_enabled:1;
 693         u16 grs_enabled:1;
 694         u16 gpmt_enabled:1;
 695         u16 tbt_enabled:1;
 696         u16 psr_enabled:1;
 697         u16 ips_enabled:1;
 698         u16 reserved3:4;
 699         u16 pc_feature_valid:1;
 700 } __packed;
 701
 702 #define EDP_18BPP       0
 703 #define EDP_24BPP       1
 704 #define EDP_30BPP       2
 705 #define EDP_RATE_1_62   0
 706 #define EDP_RATE_2_7    1
 707 #define EDP_LANE_1      0
 708 #define EDP_LANE_2      1
 709 #define EDP_LANE_4      3
 710 #define EDP_PREEMPHASIS_NONE    0
 711 #define EDP_PREEMPHASIS_3_5dB   1
 712 #define EDP_PREEMPHASIS_6dB     2
 713 #define EDP_PREEMPHASIS_9_5dB   3
 714 #define EDP_VSWING_0_4V         0
 715 #define EDP_VSWING_0_6V         1
 716 #define EDP_VSWING_0_8V         2
 717 #define EDP_VSWING_1_2V         3
 718
 719
 720 struct edp_fast_link_params {
 721         u8 rate:4;
 722         u8 lanes:4;
 723         u8 preemphasis:4;
 724         u8 vswing:4;
 725 } __packed;
 726
 727 struct edp_pwm_delays {
 728         u16 pwm_on_to_backlight_enable;
 729         u16 backlight_disable_to_pwm_off;
 730 } __packed;
 731
 732 struct edp_full_link_params {
 733         u8 preemphasis:4;
 734         u8 vswing:4;
 735 } __packed;
 736
 737 struct bdb_edp {
 738         struct edp_power_seq power_seqs[16];
 739         u32 color_depth;
 740         struct edp_fast_link_params fast_link_params[16];
 741         u32 sdrrs_msa_timing_delay;
 742
 743         /* ith bit indicates enabled/disabled for (i+1)th panel */
 744         u16 edp_s3d_feature;                                    /* 162 */
 745         u16 edp_t3_optimization;                                /* 165 */
 746         u64 edp_vswing_preemph;                                 /* 173 */
 747         u16 fast_link_training;                                 /* 182 */
 748         u16 dpcd_600h_write_required;                           /* 185 */
 749         struct edp_pwm_delays pwm_delays[16];                   /* 186 */
 750         u16 full_link_params_provided;                          /* 199 */
 751         struct edp_full_link_params full_link_params[16];       /* 199 */
 752 } __packed;
 753
 754 struct psr_table {
 755         /* Feature bits */
 756         u8 full_link:1;
 757         u8 require_aux_to_wakeup:1;
 758         u8 feature_bits_rsvd:6;
 759
 760         /* Wait times */
 761         u8 idle_frames:4;
 762         u8 lines_to_wait:3;
 763         u8 wait_times_rsvd:1;
 764
 765         /* TP wake up time in multiple of 100 */
 766         u16 tp1_wakeup_time;
 767         u16 tp2_tp3_wakeup_time;
 768 } __packed;
 769
 770 struct bdb_psr {
 771         struct psr_table psr_table[16];
 772 } __packed;
 773
 774 /*
 775  * Driver<->VBIOS interaction occurs through scratch bits in
 776  * GR18 & SWF*.
 777  */
 778
 779 /* GR18 bits are set on display switch and hotkey events */
 780 #define GR18_DRIVER_SWITCH_EN   (1<<7) /* 0: VBIOS control, 1: driver control */
 781 #define GR18_HOTKEY_MASK        0x78 /* See also SWF4 15:0 */
 782 #define   GR18_HK_NONE          (0x0<<3)
 783 #define   GR18_HK_LFP_STRETCH   (0x1<<3)
 784 #define   GR18_HK_TOGGLE_DISP   (0x2<<3)
 785 #define   GR18_HK_DISP_SWITCH   (0x4<<3) /* see SWF14 15:0 for what to enable */
 786 #define   GR18_HK_POPUP_DISABLED (0x6<<3)
 787 #define   GR18_HK_POPUP_ENABLED (0x7<<3)
 788 #define   GR18_HK_PFIT          (0x8<<3)
 789 #define   GR18_HK_APM_CHANGE    (0xa<<3)
 790 #define   GR18_HK_MULTIPLE      (0xc<<3)
 791 #define GR18_USER_INT_EN        (1<<2)
 792 #define GR18_A0000_FLUSH_EN     (1<<1)
 793 #define GR18_SMM_EN             (1<<0)
 794
 795 /* Set by driver, cleared by VBIOS */
 796 #define SWF00_YRES_SHIFT        16
 797 #define SWF00_XRES_SHIFT        0
 798 #define SWF00_RES_MASK          0xffff
 799
 800 /* Set by VBIOS at boot time and driver at runtime */
 801 #define SWF01_TV2_FORMAT_SHIFT  8
 802 #define SWF01_TV1_FORMAT_SHIFT  0
 803 #define SWF01_TV_FORMAT_MASK    0xffff
 804
 805 #define SWF10_VBIOS_BLC_I2C_EN  (1<<29)
 806 #define SWF10_GTT_OVERRIDE_EN   (1<<28)
 807 #define SWF10_LFP_DPMS_OVR      (1<<27) /* override DPMS on display switch */
 808 #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
 809 #define   SWF10_OLD_TOGGLE      0x0
 810 #define   SWF10_TOGGLE_LIST_1   0x1
 811 #define   SWF10_TOGGLE_LIST_2   0x2
 812 #define   SWF10_TOGGLE_LIST_3   0x3
 813 #define   SWF10_TOGGLE_LIST_4   0x4
 814 #define SWF10_PANNING_EN        (1<<23)
 815 #define SWF10_DRIVER_LOADED     (1<<22)
 816 #define SWF10_EXTENDED_DESKTOP  (1<<21)
 817 #define SWF10_EXCLUSIVE_MODE    (1<<20)
 818 #define SWF10_OVERLAY_EN        (1<<19)
 819 #define SWF10_PLANEB_HOLDOFF    (1<<18)
 820 #define SWF10_PLANEA_HOLDOFF    (1<<17)
 821 #define SWF10_VGA_HOLDOFF       (1<<16)
 822 #define SWF10_ACTIVE_DISP_MASK  0xffff
 823 #define   SWF10_PIPEB_LFP2      (1<<15)
 824 #define   SWF10_PIPEB_EFP2      (1<<14)
 825 #define   SWF10_PIPEB_TV2       (1<<13)
 826 #define   SWF10_PIPEB_CRT2      (1<<12)
 827 #define   SWF10_PIPEB_LFP       (1<<11)
 828 #define   SWF10_PIPEB_EFP       (1<<10)
 829 #define   SWF10_PIPEB_TV        (1<<9)
 830 #define   SWF10_PIPEB_CRT       (1<<8)
 831 #define   SWF10_PIPEA_LFP2      (1<<7)
 832 #define   SWF10_PIPEA_EFP2      (1<<6)
 833 #define   SWF10_PIPEA_TV2       (1<<5)
 834 #define   SWF10_PIPEA_CRT2      (1<<4)
 835 #define   SWF10_PIPEA_LFP       (1<<3)
 836 #define   SWF10_PIPEA_EFP       (1<<2)
 837 #define   SWF10_PIPEA_TV        (1<<1)
 838 #define   SWF10_PIPEA_CRT       (1<<0)
 839
 840 #define SWF11_MEMORY_SIZE_SHIFT 16
 841 #define SWF11_SV_TEST_EN        (1<<15)
 842 #define SWF11_IS_AGP            (1<<14)
 843 #define SWF11_DISPLAY_HOLDOFF   (1<<13)
 844 #define SWF11_DPMS_REDUCED      (1<<12)
 845 #define SWF11_IS_VBE_MODE       (1<<11)
 846 #define SWF11_PIPEB_ACCESS      (1<<10) /* 0 here means pipe a */
 847 #define SWF11_DPMS_MASK         0x07
 848 #define   SWF11_DPMS_OFF        (1<<2)
 849 #define   SWF11_DPMS_SUSPEND    (1<<1)
 850 #define   SWF11_DPMS_STANDBY    (1<<0)
 851 #define   SWF11_DPMS_ON         0
 852
 853 #define SWF14_GFX_PFIT_EN       (1<<31)
 854 #define SWF14_TEXT_PFIT_EN      (1<<30)
 855 #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
 856 #define SWF14_POPUP_EN          (1<<28)
 857 #define SWF14_DISPLAY_HOLDOFF   (1<<27)
 858 #define SWF14_DISP_DETECT_EN    (1<<26)
 859 #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
 860 #define SWF14_DRIVER_STATUS     (1<<24)
 861 #define SWF14_OS_TYPE_WIN9X     (1<<23)
 862 #define SWF14_OS_TYPE_WINNT     (1<<22)
 863 /* 21:19 rsvd */
 864 #define SWF14_PM_TYPE_MASK      0x00070000
 865 #define   SWF14_PM_ACPI_VIDEO   (0x4 << 16)
 866 #define   SWF14_PM_ACPI         (0x3 << 16)
 867 #define   SWF14_PM_APM_12       (0x2 << 16)
 868 #define   SWF14_PM_APM_11       (0x1 << 16)
 869 #define SWF14_HK_REQUEST_MASK   0x0000ffff /* see GR18 6:3 for event type */
 870           /* if GR18 indicates a display switch */
 871 #define   SWF14_DS_PIPEB_LFP2_EN (1<<15)
 872 #define   SWF14_DS_PIPEB_EFP2_EN (1<<14)
 873 #define   SWF14_DS_PIPEB_TV2_EN  (1<<13)
 874 #define   SWF14_DS_PIPEB_CRT2_EN (1<<12)
 875 #define   SWF14_DS_PIPEB_LFP_EN  (1<<11)
 876 #define   SWF14_DS_PIPEB_EFP_EN  (1<<10)
 877 #define   SWF14_DS_PIPEB_TV_EN   (1<<9)
 878 #define   SWF14_DS_PIPEB_CRT_EN  (1<<8)
 879 #define   SWF14_DS_PIPEA_LFP2_EN (1<<7)
 880 #define   SWF14_DS_PIPEA_EFP2_EN (1<<6)
 881 #define   SWF14_DS_PIPEA_TV2_EN  (1<<5)
 882 #define   SWF14_DS_PIPEA_CRT2_EN (1<<4)
 883 #define   SWF14_DS_PIPEA_LFP_EN  (1<<3)
 884 #define   SWF14_DS_PIPEA_EFP_EN  (1<<2)
 885 #define   SWF14_DS_PIPEA_TV_EN   (1<<1)
 886 #define   SWF14_DS_PIPEA_CRT_EN  (1<<0)
 887           /* if GR18 indicates a panel fitting request */
 888 #define   SWF14_PFIT_EN         (1<<0) /* 0 means disable */
 889           /* if GR18 indicates an APM change request */
 890 #define   SWF14_APM_HIBERNATE   0x4
 891 #define   SWF14_APM_SUSPEND     0x3
 892 #define   SWF14_APM_STANDBY     0x1
 893 #define   SWF14_APM_RESTORE     0x0
 894
 895 /* Block 52 contains MIPI configuration block
 896  * 6 * bdb_mipi_config, followed by 6 pps data block
 897  * block below
 898  */
 899 #define MAX_MIPI_CONFIGURATIONS 6
 900
 901 struct bdb_mipi_config {
 902         struct mipi_config config[MAX_MIPI_CONFIGURATIONS];
 903         struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS];
 904 } __packed;
 905
 906 /* Block 53 contains MIPI sequences as needed by the panel
 907  * for enabling it. This block can be variable in size and
 908  * can be maximum of 6 blocks
 909  */
 910 struct bdb_mipi_sequence {
 911         u8 version;
 912         u8 data[0];
 913 } __packed;
 914
 915 enum mipi_gpio_pin_index {
 916         MIPI_GPIO_UNDEFINED = 0,
 917         MIPI_GPIO_PANEL_ENABLE,
 918         MIPI_GPIO_BL_ENABLE,
 919         MIPI_GPIO_PWM_ENABLE,
 920         MIPI_GPIO_RESET_N,
 921         MIPI_GPIO_PWR_DOWN_R,
 922         MIPI_GPIO_STDBY_RST_N,
 923         MIPI_GPIO_MAX
 924 };
 925
 926 #endif /* _INTEL_VBT_DEFS_H_ */