drivers/gpu/drm/i915/intel_guc_submission.h

   1 /*
   2  * Copyright © 2014-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #ifndef _INTEL_GUC_SUBMISSION_H_
  26 #define _INTEL_GUC_SUBMISSION_H_
  27
  28 #include <linux/spinlock.h>
  29
  30 #include "i915_gem.h"
  31
  32 struct drm_i915_private;
  33
  34 /*
  35  * This structure primarily describes the GEM object shared with the GuC.
  36  * The specs sometimes refer to this object as a "GuC context", but we use
  37  * the term "client" to avoid confusion with hardware contexts. This
  38  * GEM object is held for the entire lifetime of our interaction with
  39  * the GuC, being allocated before the GuC is loaded with its firmware.
  40  * Because there's no way to update the address used by the GuC after
  41  * initialisation, the shared object must stay pinned into the GGTT as
  42  * long as the GuC is in use. We also keep the first page (only) mapped
  43  * into kernel address space, as it includes shared data that must be
  44  * updated on every request submission.
  45  *
  46  * The single GEM object described here is actually made up of several
  47  * separate areas, as far as the GuC is concerned. The first page (kept
  48  * kmap'd) includes the "process descriptor" which holds sequence data for
  49  * the doorbell, and one cacheline which actually *is* the doorbell; a
  50  * write to this will "ring the doorbell" (i.e. send an interrupt to the
  51  * GuC). The subsequent  pages of the client object constitute the work
  52  * queue (a circular array of work items), again described in the process
  53  * descriptor. Work queue pages are mapped momentarily as required.
  54  */
  55 struct intel_guc_client {
  56         struct i915_vma *vma;
  57         void *vaddr;
  58         struct i915_gem_context *owner;
  59         struct intel_guc *guc;
  60
  61         /* bitmap of (host) engine ids */
  62         u32 engines;
  63         u32 priority;
  64         u32 stage_id;
  65         u32 proc_desc_offset;
  66
  67         u16 doorbell_id;
  68         unsigned long doorbell_offset;
  69
  70         /* Protects GuC client's WQ access */
  71         spinlock_t wq_lock;
  72         /* Per-engine counts of GuC submissions */
  73         u64 submissions[I915_NUM_ENGINES];
  74 };
  75
  76 int intel_guc_submission_init(struct intel_guc *guc);
  77 int intel_guc_submission_enable(struct intel_guc *guc);
  78 void intel_guc_submission_disable(struct intel_guc *guc);
  79 void intel_guc_submission_fini(struct intel_guc *guc);
  80 int intel_guc_preempt_work_create(struct intel_guc *guc);
  81 void intel_guc_preempt_work_destroy(struct intel_guc *guc);
  82
  83 #endif