3 * Copyright (C) 2013 Texas Instruments Incorporated
5 * Hwmod common for AM335x and AM43x
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/types.h>
19 #include <linux/platform_data/hsmmc-omap.h>
20 #include "omap_hwmod.h"
25 #include "omap_hwmod_33xx_43xx_common_data.h"
29 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
30 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
31 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
32 #define PRCM_FLAGS(oh, flag) ((oh).prcm.omap4.flags = (flag))
36 * instance(s): l3_main, l3_s, l3_instr
38 static struct omap_hwmod_class am33xx_l3_hwmod_class
= {
42 struct omap_hwmod am33xx_l3_main_hwmod
= {
44 .class = &am33xx_l3_hwmod_class
,
45 .clkdm_name
= "l3_clkdm",
46 .flags
= HWMOD_INIT_NO_IDLE
,
47 .main_clk
= "l3_gclk",
50 .modulemode
= MODULEMODE_SWCTRL
,
56 struct omap_hwmod am33xx_l3_s_hwmod
= {
58 .class = &am33xx_l3_hwmod_class
,
59 .clkdm_name
= "l3s_clkdm",
63 struct omap_hwmod am33xx_l3_instr_hwmod
= {
65 .class = &am33xx_l3_hwmod_class
,
66 .clkdm_name
= "l3_clkdm",
67 .flags
= HWMOD_INIT_NO_IDLE
,
68 .main_clk
= "l3_gclk",
71 .modulemode
= MODULEMODE_SWCTRL
,
78 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
80 struct omap_hwmod_class am33xx_l4_hwmod_class
= {
85 struct omap_hwmod am33xx_l4_ls_hwmod
= {
87 .class = &am33xx_l4_hwmod_class
,
88 .clkdm_name
= "l4ls_clkdm",
89 .flags
= HWMOD_INIT_NO_IDLE
,
90 .main_clk
= "l4ls_gclk",
93 .modulemode
= MODULEMODE_SWCTRL
,
99 struct omap_hwmod am33xx_l4_wkup_hwmod
= {
101 .class = &am33xx_l4_hwmod_class
,
102 .clkdm_name
= "l4_wkup_clkdm",
103 .flags
= HWMOD_INIT_NO_IDLE
,
106 .modulemode
= MODULEMODE_SWCTRL
,
114 static struct omap_hwmod_class am33xx_mpu_hwmod_class
= {
118 struct omap_hwmod am33xx_mpu_hwmod
= {
120 .class = &am33xx_mpu_hwmod_class
,
121 .clkdm_name
= "mpu_clkdm",
122 .flags
= HWMOD_INIT_NO_IDLE
,
123 .main_clk
= "dpll_mpu_m2_ck",
126 .modulemode
= MODULEMODE_SWCTRL
,
133 * Wakeup controller sub-system under wakeup domain
135 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class
= {
141 * Programmable Real-Time Unit and Industrial Communication Subsystem
143 static struct omap_hwmod_class am33xx_pruss_hwmod_class
= {
147 static struct omap_hwmod_rst_info am33xx_pruss_resets
[] = {
148 { .name
= "pruss", .rst_shift
= 1 },
152 /* Pseudo hwmod for reset control purpose only */
153 struct omap_hwmod am33xx_pruss_hwmod
= {
155 .class = &am33xx_pruss_hwmod_class
,
156 .clkdm_name
= "pruss_ocp_clkdm",
157 .main_clk
= "pruss_ocp_gclk",
160 .modulemode
= MODULEMODE_SWCTRL
,
163 .rst_lines
= am33xx_pruss_resets
,
164 .rst_lines_cnt
= ARRAY_SIZE(am33xx_pruss_resets
),
168 /* Pseudo hwmod for reset control purpose only */
169 static struct omap_hwmod_class am33xx_gfx_hwmod_class
= {
173 static struct omap_hwmod_rst_info am33xx_gfx_resets
[] = {
174 { .name
= "gfx", .rst_shift
= 0, .st_shift
= 0},
177 struct omap_hwmod am33xx_gfx_hwmod
= {
179 .class = &am33xx_gfx_hwmod_class
,
180 .clkdm_name
= "gfx_l3_clkdm",
181 .main_clk
= "gfx_fck_div_ck",
184 .modulemode
= MODULEMODE_SWCTRL
,
187 .rst_lines
= am33xx_gfx_resets
,
188 .rst_lines_cnt
= ARRAY_SIZE(am33xx_gfx_resets
),
193 * power and reset manager (whole prcm infrastructure)
195 static struct omap_hwmod_class am33xx_prcm_hwmod_class
= {
200 struct omap_hwmod am33xx_prcm_hwmod
= {
202 .class = &am33xx_prcm_hwmod_class
,
203 .clkdm_name
= "l4_wkup_clkdm",
210 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc
= {
214 struct omap_hwmod_class am33xx_emif_hwmod_class
= {
216 .sysc
= &am33xx_emif_sysc
,
222 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc
= {
226 .sysc_flags
= SYSS_HAS_RESET_STATUS
,
229 static struct omap_hwmod_class am33xx_aes0_hwmod_class
= {
231 .sysc
= &am33xx_aes0_sysc
,
234 struct omap_hwmod am33xx_aes0_hwmod
= {
236 .class = &am33xx_aes0_hwmod_class
,
237 .clkdm_name
= "l3_clkdm",
238 .main_clk
= "aes0_fck",
241 .modulemode
= MODULEMODE_SWCTRL
,
246 /* sha0 HIB2 (the 'P' (public) device) */
247 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc
= {
251 .sysc_flags
= SYSS_HAS_RESET_STATUS
,
254 static struct omap_hwmod_class am33xx_sha0_hwmod_class
= {
256 .sysc
= &am33xx_sha0_sysc
,
259 struct omap_hwmod am33xx_sha0_hwmod
= {
261 .class = &am33xx_sha0_hwmod_class
,
262 .clkdm_name
= "l3_clkdm",
263 .main_clk
= "l3_gclk",
266 .modulemode
= MODULEMODE_SWCTRL
,
272 static struct omap_hwmod_class_sysconfig am33xx_rng_sysc
= {
275 .sysc_flags
= SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
,
276 .idlemodes
= SIDLE_FORCE
| SIDLE_NO
,
277 .sysc_fields
= &omap_hwmod_sysc_type1
,
280 static struct omap_hwmod_class am33xx_rng_hwmod_class
= {
282 .sysc
= &am33xx_rng_sysc
,
285 struct omap_hwmod am33xx_rng_hwmod
= {
287 .class = &am33xx_rng_hwmod_class
,
288 .clkdm_name
= "l4ls_clkdm",
289 .flags
= HWMOD_SWSUP_SIDLE
,
290 .main_clk
= "rng_fck",
293 .modulemode
= MODULEMODE_SWCTRL
,
299 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class
= {
303 struct omap_hwmod am33xx_ocmcram_hwmod
= {
305 .class = &am33xx_ocmcram_hwmod_class
,
306 .clkdm_name
= "l3_clkdm",
307 .flags
= HWMOD_INIT_NO_IDLE
,
308 .main_clk
= "l3_gclk",
311 .modulemode
= MODULEMODE_SWCTRL
,
316 /* 'smartreflex' class */
317 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class
= {
318 .name
= "smartreflex",
322 struct omap_hwmod am33xx_smartreflex0_hwmod
= {
323 .name
= "smartreflex0",
324 .class = &am33xx_smartreflex_hwmod_class
,
325 .clkdm_name
= "l4_wkup_clkdm",
326 .main_clk
= "smartreflex0_fck",
329 .modulemode
= MODULEMODE_SWCTRL
,
335 struct omap_hwmod am33xx_smartreflex1_hwmod
= {
336 .name
= "smartreflex1",
337 .class = &am33xx_smartreflex_hwmod_class
,
338 .clkdm_name
= "l4_wkup_clkdm",
339 .main_clk
= "smartreflex1_fck",
342 .modulemode
= MODULEMODE_SWCTRL
,
348 * 'control' module class
350 struct omap_hwmod_class am33xx_control_hwmod_class
= {
356 * cpsw/cpgmac sub system
358 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc
= {
362 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_MIDLEMODE
|
363 SYSS_HAS_RESET_STATUS
),
364 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| MSTANDBY_FORCE
|
366 .sysc_fields
= &omap_hwmod_sysc_type3
,
369 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class
= {
371 .sysc
= &am33xx_cpgmac_sysc
,
374 struct omap_hwmod am33xx_cpgmac0_hwmod
= {
376 .class = &am33xx_cpgmac0_hwmod_class
,
377 .clkdm_name
= "cpsw_125mhz_clkdm",
378 .flags
= (HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
),
379 .main_clk
= "cpsw_125mhz_gclk",
383 .modulemode
= MODULEMODE_SWCTRL
,
391 static struct omap_hwmod_class am33xx_mdio_hwmod_class
= {
392 .name
= "davinci_mdio",
395 struct omap_hwmod am33xx_mdio_hwmod
= {
396 .name
= "davinci_mdio",
397 .class = &am33xx_mdio_hwmod_class
,
398 .clkdm_name
= "cpsw_125mhz_clkdm",
399 .main_clk
= "cpsw_125mhz_gclk",
405 static struct omap_hwmod_class am33xx_dcan_hwmod_class
= {
410 struct omap_hwmod am33xx_dcan0_hwmod
= {
412 .class = &am33xx_dcan_hwmod_class
,
413 .clkdm_name
= "l4ls_clkdm",
414 .main_clk
= "dcan0_fck",
417 .modulemode
= MODULEMODE_SWCTRL
,
423 struct omap_hwmod am33xx_dcan1_hwmod
= {
425 .class = &am33xx_dcan_hwmod_class
,
426 .clkdm_name
= "l4ls_clkdm",
427 .main_clk
= "dcan1_fck",
430 .modulemode
= MODULEMODE_SWCTRL
,
436 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc
= {
440 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
441 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
|
442 SYSS_HAS_RESET_STATUS
),
443 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
444 .sysc_fields
= &omap_hwmod_sysc_type1
,
447 static struct omap_hwmod_class am33xx_elm_hwmod_class
= {
449 .sysc
= &am33xx_elm_sysc
,
452 struct omap_hwmod am33xx_elm_hwmod
= {
454 .class = &am33xx_elm_hwmod_class
,
455 .clkdm_name
= "l4ls_clkdm",
456 .main_clk
= "l4ls_gclk",
459 .modulemode
= MODULEMODE_SWCTRL
,
465 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc
= {
468 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_MIDLEMODE
),
469 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
470 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
471 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
472 .sysc_fields
= &omap_hwmod_sysc_type2
,
475 struct omap_hwmod_class am33xx_epwmss_hwmod_class
= {
477 .sysc
= &am33xx_epwmss_sysc
,
481 struct omap_hwmod am33xx_epwmss0_hwmod
= {
483 .class = &am33xx_epwmss_hwmod_class
,
484 .clkdm_name
= "l4ls_clkdm",
485 .main_clk
= "l4ls_gclk",
488 .modulemode
= MODULEMODE_SWCTRL
,
494 struct omap_hwmod am33xx_epwmss1_hwmod
= {
496 .class = &am33xx_epwmss_hwmod_class
,
497 .clkdm_name
= "l4ls_clkdm",
498 .main_clk
= "l4ls_gclk",
501 .modulemode
= MODULEMODE_SWCTRL
,
507 struct omap_hwmod am33xx_epwmss2_hwmod
= {
509 .class = &am33xx_epwmss_hwmod_class
,
510 .clkdm_name
= "l4ls_clkdm",
511 .main_clk
= "l4ls_gclk",
514 .modulemode
= MODULEMODE_SWCTRL
,
520 * 'gpio' class: for gpio 0,1,2,3
522 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc
= {
526 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
527 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
528 SYSS_HAS_RESET_STATUS
),
529 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
531 .sysc_fields
= &omap_hwmod_sysc_type1
,
534 struct omap_hwmod_class am33xx_gpio_hwmod_class
= {
536 .sysc
= &am33xx_gpio_sysc
,
541 static struct omap_hwmod_opt_clk gpio1_opt_clks
[] = {
542 { .role
= "dbclk", .clk
= "gpio1_dbclk" },
545 struct omap_hwmod am33xx_gpio1_hwmod
= {
547 .class = &am33xx_gpio_hwmod_class
,
548 .clkdm_name
= "l4ls_clkdm",
549 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
550 .main_clk
= "l4ls_gclk",
553 .modulemode
= MODULEMODE_SWCTRL
,
556 .opt_clks
= gpio1_opt_clks
,
557 .opt_clks_cnt
= ARRAY_SIZE(gpio1_opt_clks
),
561 static struct omap_hwmod_opt_clk gpio2_opt_clks
[] = {
562 { .role
= "dbclk", .clk
= "gpio2_dbclk" },
565 struct omap_hwmod am33xx_gpio2_hwmod
= {
567 .class = &am33xx_gpio_hwmod_class
,
568 .clkdm_name
= "l4ls_clkdm",
569 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
570 .main_clk
= "l4ls_gclk",
573 .modulemode
= MODULEMODE_SWCTRL
,
576 .opt_clks
= gpio2_opt_clks
,
577 .opt_clks_cnt
= ARRAY_SIZE(gpio2_opt_clks
),
581 static struct omap_hwmod_opt_clk gpio3_opt_clks
[] = {
582 { .role
= "dbclk", .clk
= "gpio3_dbclk" },
585 struct omap_hwmod am33xx_gpio3_hwmod
= {
587 .class = &am33xx_gpio_hwmod_class
,
588 .clkdm_name
= "l4ls_clkdm",
589 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
590 .main_clk
= "l4ls_gclk",
593 .modulemode
= MODULEMODE_SWCTRL
,
596 .opt_clks
= gpio3_opt_clks
,
597 .opt_clks_cnt
= ARRAY_SIZE(gpio3_opt_clks
),
601 static struct omap_hwmod_class_sysconfig gpmc_sysc
= {
605 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
606 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
607 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
608 .sysc_fields
= &omap_hwmod_sysc_type1
,
611 static struct omap_hwmod_class am33xx_gpmc_hwmod_class
= {
616 struct omap_hwmod am33xx_gpmc_hwmod
= {
618 .class = &am33xx_gpmc_hwmod_class
,
619 .clkdm_name
= "l3s_clkdm",
620 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
621 .flags
= DEBUG_OMAP_GPMC_HWMOD_FLAGS
,
622 .main_clk
= "l3s_gclk",
625 .modulemode
= MODULEMODE_SWCTRL
,
631 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc
= {
635 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
636 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
637 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
638 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
640 .sysc_fields
= &omap_hwmod_sysc_type1
,
643 static struct omap_hwmod_class i2c_class
= {
645 .sysc
= &am33xx_i2c_sysc
,
646 .rev
= OMAP_I2C_IP_VERSION_2
,
647 .reset
= &omap_i2c_reset
,
651 struct omap_hwmod am33xx_i2c1_hwmod
= {
654 .clkdm_name
= "l4_wkup_clkdm",
655 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
656 .main_clk
= "dpll_per_m2_div4_wkupdm_ck",
659 .modulemode
= MODULEMODE_SWCTRL
,
665 struct omap_hwmod am33xx_i2c2_hwmod
= {
668 .clkdm_name
= "l4ls_clkdm",
669 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
670 .main_clk
= "dpll_per_m2_div4_ck",
673 .modulemode
= MODULEMODE_SWCTRL
,
679 struct omap_hwmod am33xx_i2c3_hwmod
= {
682 .clkdm_name
= "l4ls_clkdm",
683 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
684 .main_clk
= "dpll_per_m2_div4_ck",
687 .modulemode
= MODULEMODE_SWCTRL
,
694 * mailbox module allowing communication between the on-chip processors using a
695 * queued mailbox-interrupt mechanism.
697 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc
= {
700 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
702 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
703 .sysc_fields
= &omap_hwmod_sysc_type2
,
706 static struct omap_hwmod_class am33xx_mailbox_hwmod_class
= {
708 .sysc
= &am33xx_mailbox_sysc
,
711 struct omap_hwmod am33xx_mailbox_hwmod
= {
713 .class = &am33xx_mailbox_hwmod_class
,
714 .clkdm_name
= "l4ls_clkdm",
715 .main_clk
= "l4ls_gclk",
718 .modulemode
= MODULEMODE_SWCTRL
,
726 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc
= {
729 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
730 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
731 .sysc_fields
= &omap_hwmod_sysc_type3
,
734 static struct omap_hwmod_class am33xx_mcasp_hwmod_class
= {
736 .sysc
= &am33xx_mcasp_sysc
,
740 struct omap_hwmod am33xx_mcasp0_hwmod
= {
742 .class = &am33xx_mcasp_hwmod_class
,
743 .clkdm_name
= "l3s_clkdm",
744 .main_clk
= "mcasp0_fck",
747 .modulemode
= MODULEMODE_SWCTRL
,
753 struct omap_hwmod am33xx_mcasp1_hwmod
= {
755 .class = &am33xx_mcasp_hwmod_class
,
756 .clkdm_name
= "l3s_clkdm",
757 .main_clk
= "mcasp1_fck",
760 .modulemode
= MODULEMODE_SWCTRL
,
766 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc
= {
770 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
771 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
772 SYSC_HAS_AUTOIDLE
| SYSS_HAS_RESET_STATUS
),
773 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
774 .sysc_fields
= &omap_hwmod_sysc_type1
,
777 static struct omap_hwmod_class am33xx_mmc_hwmod_class
= {
779 .sysc
= &am33xx_mmc_sysc
,
783 static struct omap_hsmmc_dev_attr am33xx_mmc0_dev_attr
= {
784 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
787 struct omap_hwmod am33xx_mmc0_hwmod
= {
789 .class = &am33xx_mmc_hwmod_class
,
790 .clkdm_name
= "l4ls_clkdm",
791 .main_clk
= "mmc_clk",
794 .modulemode
= MODULEMODE_SWCTRL
,
797 .dev_attr
= &am33xx_mmc0_dev_attr
,
801 static struct omap_hsmmc_dev_attr am33xx_mmc1_dev_attr
= {
802 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
805 struct omap_hwmod am33xx_mmc1_hwmod
= {
807 .class = &am33xx_mmc_hwmod_class
,
808 .clkdm_name
= "l4ls_clkdm",
809 .main_clk
= "mmc_clk",
812 .modulemode
= MODULEMODE_SWCTRL
,
815 .dev_attr
= &am33xx_mmc1_dev_attr
,
819 static struct omap_hsmmc_dev_attr am33xx_mmc2_dev_attr
= {
820 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
822 struct omap_hwmod am33xx_mmc2_hwmod
= {
824 .class = &am33xx_mmc_hwmod_class
,
825 .clkdm_name
= "l3s_clkdm",
826 .main_clk
= "mmc_clk",
829 .modulemode
= MODULEMODE_SWCTRL
,
832 .dev_attr
= &am33xx_mmc2_dev_attr
,
839 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc
= {
842 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
843 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
|
844 SIDLE_SMART
| SIDLE_SMART_WKUP
),
845 .sysc_fields
= &omap_hwmod_sysc_type3
,
848 static struct omap_hwmod_class am33xx_rtc_hwmod_class
= {
850 .sysc
= &am33xx_rtc_sysc
,
851 .unlock
= &omap_hwmod_rtc_unlock
,
852 .lock
= &omap_hwmod_rtc_lock
,
855 struct omap_hwmod am33xx_rtc_hwmod
= {
857 .class = &am33xx_rtc_hwmod_class
,
858 .clkdm_name
= "l4_rtc_clkdm",
859 .main_clk
= "clk_32768_ck",
862 .modulemode
= MODULEMODE_SWCTRL
,
868 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc
= {
872 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
873 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
|
874 SYSS_HAS_RESET_STATUS
),
875 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
876 .sysc_fields
= &omap_hwmod_sysc_type1
,
879 struct omap_hwmod_class am33xx_spi_hwmod_class
= {
881 .sysc
= &am33xx_mcspi_sysc
,
885 struct omap_hwmod am33xx_spi0_hwmod
= {
887 .class = &am33xx_spi_hwmod_class
,
888 .clkdm_name
= "l4ls_clkdm",
889 .main_clk
= "dpll_per_m2_div4_ck",
892 .modulemode
= MODULEMODE_SWCTRL
,
898 struct omap_hwmod am33xx_spi1_hwmod
= {
900 .class = &am33xx_spi_hwmod_class
,
901 .clkdm_name
= "l4ls_clkdm",
902 .main_clk
= "dpll_per_m2_div4_ck",
905 .modulemode
= MODULEMODE_SWCTRL
,
912 * spinlock provides hardware assistance for synchronizing the
913 * processes running on multiple processors
916 static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc
= {
920 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
921 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
922 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
923 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
924 .sysc_fields
= &omap_hwmod_sysc_type1
,
927 static struct omap_hwmod_class am33xx_spinlock_hwmod_class
= {
929 .sysc
= &am33xx_spinlock_sysc
,
932 struct omap_hwmod am33xx_spinlock_hwmod
= {
934 .class = &am33xx_spinlock_hwmod_class
,
935 .clkdm_name
= "l4ls_clkdm",
936 .main_clk
= "l4ls_gclk",
939 .modulemode
= MODULEMODE_SWCTRL
,
944 /* 'timer 2-7' class */
945 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc
= {
949 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
950 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
952 .sysc_fields
= &omap_hwmod_sysc_type2
,
955 struct omap_hwmod_class am33xx_timer_hwmod_class
= {
957 .sysc
= &am33xx_timer_sysc
,
961 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc
= {
965 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
966 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
|
967 SYSS_HAS_RESET_STATUS
),
968 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
969 .sysc_fields
= &omap_hwmod_sysc_type1
,
972 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class
= {
974 .sysc
= &am33xx_timer1ms_sysc
,
977 struct omap_hwmod am33xx_timer1_hwmod
= {
979 .class = &am33xx_timer1ms_hwmod_class
,
980 .clkdm_name
= "l4_wkup_clkdm",
981 .main_clk
= "timer1_fck",
984 .modulemode
= MODULEMODE_SWCTRL
,
989 struct omap_hwmod am33xx_timer2_hwmod
= {
991 .class = &am33xx_timer_hwmod_class
,
992 .clkdm_name
= "l4ls_clkdm",
993 .main_clk
= "timer2_fck",
996 .modulemode
= MODULEMODE_SWCTRL
,
1001 struct omap_hwmod am33xx_timer3_hwmod
= {
1003 .class = &am33xx_timer_hwmod_class
,
1004 .clkdm_name
= "l4ls_clkdm",
1005 .main_clk
= "timer3_fck",
1008 .modulemode
= MODULEMODE_SWCTRL
,
1013 struct omap_hwmod am33xx_timer4_hwmod
= {
1015 .class = &am33xx_timer_hwmod_class
,
1016 .clkdm_name
= "l4ls_clkdm",
1017 .main_clk
= "timer4_fck",
1020 .modulemode
= MODULEMODE_SWCTRL
,
1025 struct omap_hwmod am33xx_timer5_hwmod
= {
1027 .class = &am33xx_timer_hwmod_class
,
1028 .clkdm_name
= "l4ls_clkdm",
1029 .main_clk
= "timer5_fck",
1032 .modulemode
= MODULEMODE_SWCTRL
,
1037 struct omap_hwmod am33xx_timer6_hwmod
= {
1039 .class = &am33xx_timer_hwmod_class
,
1040 .clkdm_name
= "l4ls_clkdm",
1041 .main_clk
= "timer6_fck",
1044 .modulemode
= MODULEMODE_SWCTRL
,
1049 struct omap_hwmod am33xx_timer7_hwmod
= {
1051 .class = &am33xx_timer_hwmod_class
,
1052 .clkdm_name
= "l4ls_clkdm",
1053 .main_clk
= "timer7_fck",
1056 .modulemode
= MODULEMODE_SWCTRL
,
1062 static struct omap_hwmod_class am33xx_tpcc_hwmod_class
= {
1066 struct omap_hwmod am33xx_tpcc_hwmod
= {
1068 .class = &am33xx_tpcc_hwmod_class
,
1069 .clkdm_name
= "l3_clkdm",
1070 .main_clk
= "l3_gclk",
1073 .modulemode
= MODULEMODE_SWCTRL
,
1078 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc
= {
1081 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1082 SYSC_HAS_MIDLEMODE
),
1083 .idlemodes
= (SIDLE_FORCE
| SIDLE_SMART
| MSTANDBY_FORCE
),
1084 .sysc_fields
= &omap_hwmod_sysc_type2
,
1088 static struct omap_hwmod_class am33xx_tptc_hwmod_class
= {
1090 .sysc
= &am33xx_tptc_sysc
,
1094 struct omap_hwmod am33xx_tptc0_hwmod
= {
1096 .class = &am33xx_tptc_hwmod_class
,
1097 .clkdm_name
= "l3_clkdm",
1098 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
,
1099 .main_clk
= "l3_gclk",
1102 .modulemode
= MODULEMODE_SWCTRL
,
1108 struct omap_hwmod am33xx_tptc1_hwmod
= {
1110 .class = &am33xx_tptc_hwmod_class
,
1111 .clkdm_name
= "l3_clkdm",
1112 .flags
= (HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
),
1113 .main_clk
= "l3_gclk",
1116 .modulemode
= MODULEMODE_SWCTRL
,
1122 struct omap_hwmod am33xx_tptc2_hwmod
= {
1124 .class = &am33xx_tptc_hwmod_class
,
1125 .clkdm_name
= "l3_clkdm",
1126 .flags
= (HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
),
1127 .main_clk
= "l3_gclk",
1130 .modulemode
= MODULEMODE_SWCTRL
,
1136 static struct omap_hwmod_class_sysconfig uart_sysc
= {
1140 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_ENAWAKEUP
|
1141 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
1142 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1144 .sysc_fields
= &omap_hwmod_sysc_type1
,
1147 static struct omap_hwmod_class uart_class
= {
1152 struct omap_hwmod am33xx_uart1_hwmod
= {
1154 .class = &uart_class
,
1155 .clkdm_name
= "l4_wkup_clkdm",
1156 .flags
= DEBUG_AM33XXUART1_FLAGS
| HWMOD_SWSUP_SIDLE_ACT
,
1157 .main_clk
= "dpll_per_m2_div4_wkupdm_ck",
1160 .modulemode
= MODULEMODE_SWCTRL
,
1165 struct omap_hwmod am33xx_uart2_hwmod
= {
1167 .class = &uart_class
,
1168 .clkdm_name
= "l4ls_clkdm",
1169 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
1170 .main_clk
= "dpll_per_m2_div4_ck",
1173 .modulemode
= MODULEMODE_SWCTRL
,
1179 struct omap_hwmod am33xx_uart3_hwmod
= {
1181 .class = &uart_class
,
1182 .clkdm_name
= "l4ls_clkdm",
1183 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
1184 .main_clk
= "dpll_per_m2_div4_ck",
1187 .modulemode
= MODULEMODE_SWCTRL
,
1192 struct omap_hwmod am33xx_uart4_hwmod
= {
1194 .class = &uart_class
,
1195 .clkdm_name
= "l4ls_clkdm",
1196 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
1197 .main_clk
= "dpll_per_m2_div4_ck",
1200 .modulemode
= MODULEMODE_SWCTRL
,
1205 struct omap_hwmod am33xx_uart5_hwmod
= {
1207 .class = &uart_class
,
1208 .clkdm_name
= "l4ls_clkdm",
1209 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
1210 .main_clk
= "dpll_per_m2_div4_ck",
1213 .modulemode
= MODULEMODE_SWCTRL
,
1218 struct omap_hwmod am33xx_uart6_hwmod
= {
1220 .class = &uart_class
,
1221 .clkdm_name
= "l4ls_clkdm",
1222 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
1223 .main_clk
= "dpll_per_m2_div4_ck",
1226 .modulemode
= MODULEMODE_SWCTRL
,
1231 /* 'wd_timer' class */
1232 static struct omap_hwmod_class_sysconfig wdt_sysc
= {
1236 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_SIDLEMODE
|
1237 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1238 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1240 .sysc_fields
= &omap_hwmod_sysc_type1
,
1243 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class
= {
1246 .pre_shutdown
= &omap2_wd_timer_disable
,
1250 * XXX: device.c file uses hardcoded name for watchdog timer
1251 * driver "wd_timer2, so we are also using same name as of now...
1253 struct omap_hwmod am33xx_wd_timer1_hwmod
= {
1254 .name
= "wd_timer2",
1255 .class = &am33xx_wd_timer_hwmod_class
,
1256 .clkdm_name
= "l4_wkup_clkdm",
1257 .flags
= HWMOD_SWSUP_SIDLE
,
1258 .main_clk
= "wdt1_fck",
1261 .modulemode
= MODULEMODE_SWCTRL
,
1266 static void omap_hwmod_am33xx_clkctrl(void)
1268 CLKCTRL(am33xx_uart2_hwmod
, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET
);
1269 CLKCTRL(am33xx_uart3_hwmod
, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET
);
1270 CLKCTRL(am33xx_uart4_hwmod
, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET
);
1271 CLKCTRL(am33xx_uart5_hwmod
, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET
);
1272 CLKCTRL(am33xx_uart6_hwmod
, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET
);
1273 CLKCTRL(am33xx_dcan0_hwmod
, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET
);
1274 CLKCTRL(am33xx_dcan1_hwmod
, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET
);
1275 CLKCTRL(am33xx_elm_hwmod
, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET
);
1276 CLKCTRL(am33xx_epwmss0_hwmod
, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET
);
1277 CLKCTRL(am33xx_epwmss1_hwmod
, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET
);
1278 CLKCTRL(am33xx_epwmss2_hwmod
, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET
);
1279 CLKCTRL(am33xx_gpio1_hwmod
, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET
);
1280 CLKCTRL(am33xx_gpio2_hwmod
, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET
);
1281 CLKCTRL(am33xx_gpio3_hwmod
, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET
);
1282 CLKCTRL(am33xx_i2c2_hwmod
, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET
);
1283 CLKCTRL(am33xx_i2c3_hwmod
, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET
);
1284 CLKCTRL(am33xx_mailbox_hwmod
, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET
);
1285 CLKCTRL(am33xx_mcasp0_hwmod
, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET
);
1286 CLKCTRL(am33xx_mcasp1_hwmod
, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET
);
1287 CLKCTRL(am33xx_mmc0_hwmod
, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET
);
1288 CLKCTRL(am33xx_mmc1_hwmod
, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET
);
1289 CLKCTRL(am33xx_spi0_hwmod
, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET
);
1290 CLKCTRL(am33xx_spi1_hwmod
, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET
);
1291 CLKCTRL(am33xx_spinlock_hwmod
, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET
);
1292 CLKCTRL(am33xx_timer2_hwmod
, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET
);
1293 CLKCTRL(am33xx_timer3_hwmod
, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET
);
1294 CLKCTRL(am33xx_timer4_hwmod
, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET
);
1295 CLKCTRL(am33xx_timer5_hwmod
, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET
);
1296 CLKCTRL(am33xx_timer6_hwmod
, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET
);
1297 CLKCTRL(am33xx_timer7_hwmod
, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET
);
1298 CLKCTRL(am33xx_smartreflex0_hwmod
,
1299 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET
);
1300 CLKCTRL(am33xx_smartreflex1_hwmod
,
1301 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET
);
1302 CLKCTRL(am33xx_uart1_hwmod
, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET
);
1303 CLKCTRL(am33xx_timer1_hwmod
, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET
);
1304 CLKCTRL(am33xx_i2c1_hwmod
, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET
);
1305 CLKCTRL(am33xx_wd_timer1_hwmod
, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET
);
1306 CLKCTRL(am33xx_rtc_hwmod
, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET
);
1307 PRCM_FLAGS(am33xx_rtc_hwmod
, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET
);
1308 CLKCTRL(am33xx_mmc2_hwmod
, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET
);
1309 CLKCTRL(am33xx_gpmc_hwmod
, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET
);
1310 CLKCTRL(am33xx_l4_ls_hwmod
, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET
);
1311 CLKCTRL(am33xx_l4_wkup_hwmod
, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET
);
1312 CLKCTRL(am33xx_l3_main_hwmod
, AM33XX_CM_PER_L3_CLKCTRL_OFFSET
);
1313 CLKCTRL(am33xx_tpcc_hwmod
, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET
);
1314 CLKCTRL(am33xx_tptc0_hwmod
, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET
);
1315 CLKCTRL(am33xx_tptc1_hwmod
, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET
);
1316 CLKCTRL(am33xx_tptc2_hwmod
, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET
);
1317 CLKCTRL(am33xx_gfx_hwmod
, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET
);
1318 CLKCTRL(am33xx_cpgmac0_hwmod
, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET
);
1319 CLKCTRL(am33xx_pruss_hwmod
, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET
);
1320 CLKCTRL(am33xx_mpu_hwmod
, AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET
);
1321 CLKCTRL(am33xx_l3_instr_hwmod
, AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET
);
1322 CLKCTRL(am33xx_ocmcram_hwmod
, AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET
);
1323 CLKCTRL(am33xx_sha0_hwmod
, AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET
);
1324 CLKCTRL(am33xx_aes0_hwmod
, AM33XX_CM_PER_AES0_CLKCTRL_OFFSET
);
1325 CLKCTRL(am33xx_rng_hwmod
, AM33XX_CM_PER_RNG_CLKCTRL_OFFSET
);
1328 static void omap_hwmod_am33xx_rst(void)
1330 RSTCTRL(am33xx_pruss_hwmod
, AM33XX_RM_PER_RSTCTRL_OFFSET
);
1331 RSTCTRL(am33xx_gfx_hwmod
, AM33XX_RM_GFX_RSTCTRL_OFFSET
);
1332 RSTST(am33xx_gfx_hwmod
, AM33XX_RM_GFX_RSTST_OFFSET
);
1335 void omap_hwmod_am33xx_reg(void)
1337 omap_hwmod_am33xx_clkctrl();
1338 omap_hwmod_am33xx_rst();
1341 static void omap_hwmod_am43xx_clkctrl(void)
1343 CLKCTRL(am33xx_uart2_hwmod
, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET
);
1344 CLKCTRL(am33xx_uart3_hwmod
, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET
);
1345 CLKCTRL(am33xx_uart4_hwmod
, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET
);
1346 CLKCTRL(am33xx_uart5_hwmod
, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET
);
1347 CLKCTRL(am33xx_uart6_hwmod
, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET
);
1348 CLKCTRL(am33xx_dcan0_hwmod
, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET
);
1349 CLKCTRL(am33xx_dcan1_hwmod
, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET
);
1350 CLKCTRL(am33xx_elm_hwmod
, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET
);
1351 CLKCTRL(am33xx_epwmss0_hwmod
, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET
);
1352 CLKCTRL(am33xx_epwmss1_hwmod
, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET
);
1353 CLKCTRL(am33xx_epwmss2_hwmod
, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET
);
1354 CLKCTRL(am33xx_gpio1_hwmod
, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET
);
1355 CLKCTRL(am33xx_gpio2_hwmod
, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET
);
1356 CLKCTRL(am33xx_gpio3_hwmod
, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET
);
1357 CLKCTRL(am33xx_i2c2_hwmod
, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET
);
1358 CLKCTRL(am33xx_i2c3_hwmod
, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET
);
1359 CLKCTRL(am33xx_mailbox_hwmod
, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET
);
1360 CLKCTRL(am33xx_mcasp0_hwmod
, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET
);
1361 CLKCTRL(am33xx_mcasp1_hwmod
, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET
);
1362 CLKCTRL(am33xx_mmc0_hwmod
, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET
);
1363 CLKCTRL(am33xx_mmc1_hwmod
, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET
);
1364 CLKCTRL(am33xx_spi0_hwmod
, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET
);
1365 CLKCTRL(am33xx_spi1_hwmod
, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET
);
1366 CLKCTRL(am33xx_spinlock_hwmod
, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET
);
1367 CLKCTRL(am33xx_timer2_hwmod
, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET
);
1368 CLKCTRL(am33xx_timer3_hwmod
, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET
);
1369 CLKCTRL(am33xx_timer4_hwmod
, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET
);
1370 CLKCTRL(am33xx_timer5_hwmod
, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET
);
1371 CLKCTRL(am33xx_timer6_hwmod
, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET
);
1372 CLKCTRL(am33xx_timer7_hwmod
, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET
);
1373 CLKCTRL(am33xx_smartreflex0_hwmod
,
1374 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET
);
1375 CLKCTRL(am33xx_smartreflex1_hwmod
,
1376 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET
);
1377 CLKCTRL(am33xx_uart1_hwmod
, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET
);
1378 CLKCTRL(am33xx_timer1_hwmod
, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET
);
1379 CLKCTRL(am33xx_i2c1_hwmod
, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET
);
1380 CLKCTRL(am33xx_wd_timer1_hwmod
, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET
);
1381 CLKCTRL(am33xx_rtc_hwmod
, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET
);
1382 CLKCTRL(am33xx_mmc2_hwmod
, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET
);
1383 CLKCTRL(am33xx_gpmc_hwmod
, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET
);
1384 CLKCTRL(am33xx_l4_ls_hwmod
, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET
);
1385 CLKCTRL(am33xx_l4_wkup_hwmod
, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET
);
1386 CLKCTRL(am33xx_l3_main_hwmod
, AM43XX_CM_PER_L3_CLKCTRL_OFFSET
);
1387 CLKCTRL(am33xx_tpcc_hwmod
, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET
);
1388 CLKCTRL(am33xx_tptc0_hwmod
, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET
);
1389 CLKCTRL(am33xx_tptc1_hwmod
, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET
);
1390 CLKCTRL(am33xx_tptc2_hwmod
, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET
);
1391 CLKCTRL(am33xx_gfx_hwmod
, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET
);
1392 CLKCTRL(am33xx_cpgmac0_hwmod
, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET
);
1393 CLKCTRL(am33xx_pruss_hwmod
, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET
);
1394 CLKCTRL(am33xx_mpu_hwmod
, AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET
);
1395 CLKCTRL(am33xx_l3_instr_hwmod
, AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET
);
1396 CLKCTRL(am33xx_ocmcram_hwmod
, AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET
);
1397 CLKCTRL(am33xx_sha0_hwmod
, AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET
);
1398 CLKCTRL(am33xx_aes0_hwmod
, AM43XX_CM_PER_AES0_CLKCTRL_OFFSET
);
1399 CLKCTRL(am33xx_rng_hwmod
, AM43XX_CM_PER_RNG_CLKCTRL_OFFSET
);
1402 static void omap_hwmod_am43xx_rst(void)
1404 RSTCTRL(am33xx_pruss_hwmod
, AM43XX_RM_PER_RSTCTRL_OFFSET
);
1405 RSTCTRL(am33xx_gfx_hwmod
, AM43XX_RM_GFX_RSTCTRL_OFFSET
);
1406 RSTST(am33xx_pruss_hwmod
, AM43XX_RM_PER_RSTST_OFFSET
);
1407 RSTST(am33xx_gfx_hwmod
, AM43XX_RM_GFX_RSTST_OFFSET
);
1410 void omap_hwmod_am43xx_reg(void)
1412 omap_hwmod_am43xx_clkctrl();
1413 omap_hwmod_am43xx_rst();