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media: coda: streamline framebuffer size calculation a bit
[linux-2.6/btrfs-unstable.git] / drivers / media / platform / coda / coda-bit.c
blobbf8d8489f8274966def974f1c073c28b6e9d26ba
1 /*
2 * Coda multi-standard codec IP - BIT processor functions
3 *
4 * Copyright (C) 2012 Vista Silicon S.L.
5 * Javier Martin, <javier.martin@vista-silicon.com>
6 * Xavier Duret
7 * Copyright (C) 2012-2014 Philipp Zabel, Pengutronix
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/irqreturn.h>
17 #include <linux/kernel.h>
18 #include <linux/log2.h>
19 #include <linux/platform_device.h>
20 #include <linux/reset.h>
21 #include <linux/slab.h>
22 #include <linux/videodev2.h>
23
24 #include <media/v4l2-common.h>
25 #include <media/v4l2-ctrls.h>
26 #include <media/v4l2-fh.h>
27 #include <media/v4l2-mem2mem.h>
28 #include <media/videobuf2-v4l2.h>
29 #include <media/videobuf2-dma-contig.h>
30 #include <media/videobuf2-vmalloc.h>
31
32 #include "coda.h"
33 #include "imx-vdoa.h"
34 #define CREATE_TRACE_POINTS
35 #include "trace.h"
36
37 #define CODA_PARA_BUF_SIZE (10 * 1024)
38 #define CODA7_PS_BUF_SIZE 0x28000
39 #define CODA9_PS_SAVE_SIZE (512 * 1024)
40
41 #define CODA_DEFAULT_GAMMA 4096
42 #define CODA9_DEFAULT_GAMMA 24576 /* 0.75 * 32768 */
43
44 static void coda_free_bitstream_buffer(struct coda_ctx *ctx);
45
46 static inline int coda_is_initialized(struct coda_dev *dev)
47 {
48 return coda_read(dev, CODA_REG_BIT_CUR_PC) != 0;
49 }
50
51 static inline unsigned long coda_isbusy(struct coda_dev *dev)
52 {
53 return coda_read(dev, CODA_REG_BIT_BUSY);
54 }
55
56 static int coda_wait_timeout(struct coda_dev *dev)
57 {
58 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
59
60 while (coda_isbusy(dev)) {
61 if (time_after(jiffies, timeout))
62 return -ETIMEDOUT;
63 }
64 return 0;
65 }
66
67 static void coda_command_async(struct coda_ctx *ctx, int cmd)
68 {
69 struct coda_dev *dev = ctx->dev;
70
71 if (dev->devtype->product == CODA_HX4 ||
72 dev->devtype->product == CODA_7541 ||
73 dev->devtype->product == CODA_960) {
74 /* Restore context related registers to CODA */
75 coda_write(dev, ctx->bit_stream_param,
76 CODA_REG_BIT_BIT_STREAM_PARAM);
77 coda_write(dev, ctx->frm_dis_flg,
78 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
79 coda_write(dev, ctx->frame_mem_ctrl,
80 CODA_REG_BIT_FRAME_MEM_CTRL);
81 coda_write(dev, ctx->workbuf.paddr, CODA_REG_BIT_WORK_BUF_ADDR);
82 }
83
84 if (dev->devtype->product == CODA_960) {
85 coda_write(dev, 1, CODA9_GDI_WPROT_ERR_CLR);
86 coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
87 }
88
89 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
90
91 coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
92 coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
93 coda_write(dev, ctx->params.codec_mode_aux, CODA7_REG_BIT_RUN_AUX_STD);
94
95 trace_coda_bit_run(ctx, cmd);
96
97 coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
98 }
99
100 static int coda_command_sync(struct coda_ctx *ctx, int cmd)
101 {
102 struct coda_dev *dev = ctx->dev;
103 int ret;
104
105 coda_command_async(ctx, cmd);
106 ret = coda_wait_timeout(dev);
107 trace_coda_bit_done(ctx);
108
109 return ret;
110 }
111
112 int coda_hw_reset(struct coda_ctx *ctx)
113 {
114 struct coda_dev *dev = ctx->dev;
115 unsigned long timeout;
116 unsigned int idx;
117 int ret;
118
119 if (!dev->rstc)
120 return -ENOENT;
121
122 idx = coda_read(dev, CODA_REG_BIT_RUN_INDEX);
123
124 if (dev->devtype->product == CODA_960) {
125 timeout = jiffies + msecs_to_jiffies(100);
126 coda_write(dev, 0x11, CODA9_GDI_BUS_CTRL);
127 while (coda_read(dev, CODA9_GDI_BUS_STATUS) != 0x77) {
128 if (time_after(jiffies, timeout))
129 return -ETIME;
130 cpu_relax();
131 }
132 }
133
134 ret = reset_control_reset(dev->rstc);
135 if (ret < 0)
136 return ret;
137
138 if (dev->devtype->product == CODA_960)
139 coda_write(dev, 0x00, CODA9_GDI_BUS_CTRL);
140 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
141 coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
142 ret = coda_wait_timeout(dev);
143 coda_write(dev, idx, CODA_REG_BIT_RUN_INDEX);
144
145 return ret;
146 }
147
148 static void coda_kfifo_sync_from_device(struct coda_ctx *ctx)
149 {
150 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
151 struct coda_dev *dev = ctx->dev;
152 u32 rd_ptr;
153
154 rd_ptr = coda_read(dev, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
155 kfifo->out = (kfifo->in & ~kfifo->mask) |
156 (rd_ptr - ctx->bitstream.paddr);
157 if (kfifo->out > kfifo->in)
158 kfifo->out -= kfifo->mask + 1;
159 }
160
161 static void coda_kfifo_sync_to_device_full(struct coda_ctx *ctx)
162 {
163 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
164 struct coda_dev *dev = ctx->dev;
165 u32 rd_ptr, wr_ptr;
166
167 rd_ptr = ctx->bitstream.paddr + (kfifo->out & kfifo->mask);
168 coda_write(dev, rd_ptr, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
169 wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
170 coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
171 }
172
173 static void coda_kfifo_sync_to_device_write(struct coda_ctx *ctx)
174 {
175 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
176 struct coda_dev *dev = ctx->dev;
177 u32 wr_ptr;
178
179 wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
180 coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
181 }
182
183 static int coda_bitstream_pad(struct coda_ctx *ctx, u32 size)
184 {
185 unsigned char *buf;
186 u32 n;
187
188 if (size < 6)
189 size = 6;
190
191 buf = kmalloc(size, GFP_KERNEL);
192 if (!buf)
193 return -ENOMEM;
194
195 coda_h264_filler_nal(size, buf);
196 n = kfifo_in(&ctx->bitstream_fifo, buf, size);
197 kfree(buf);
198
199 return (n < size) ? -ENOSPC : 0;
200 }
201
202 static int coda_bitstream_queue(struct coda_ctx *ctx,
203 struct vb2_v4l2_buffer *src_buf)
204 {
205 u32 src_size = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
206 u32 n;
207
208 n = kfifo_in(&ctx->bitstream_fifo,
209 vb2_plane_vaddr(&src_buf->vb2_buf, 0), src_size);
210 if (n < src_size)
211 return -ENOSPC;
212
213 src_buf->sequence = ctx->qsequence++;
214
215 return 0;
216 }
217
218 static bool coda_bitstream_try_queue(struct coda_ctx *ctx,
219 struct vb2_v4l2_buffer *src_buf)
220 {
221 unsigned long payload = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
222 int ret;
223
224 if (coda_get_bitstream_payload(ctx) + payload + 512 >=
225 ctx->bitstream.size)
226 return false;
227
228 if (vb2_plane_vaddr(&src_buf->vb2_buf, 0) == NULL) {
229 v4l2_err(&ctx->dev->v4l2_dev, "trying to queue empty buffer\n");
230 return true;
231 }
232
233 /* Add zero padding before the first H.264 buffer, if it is too small */
234 if (ctx->qsequence == 0 && payload < 512 &&
235 ctx->codec->src_fourcc == V4L2_PIX_FMT_H264)
236 coda_bitstream_pad(ctx, 512 - payload);
237
238 ret = coda_bitstream_queue(ctx, src_buf);
239 if (ret < 0) {
240 v4l2_err(&ctx->dev->v4l2_dev, "bitstream buffer overflow\n");
241 return false;
242 }
243 /* Sync read pointer to device */
244 if (ctx == v4l2_m2m_get_curr_priv(ctx->dev->m2m_dev))
245 coda_kfifo_sync_to_device_write(ctx);
246
247 ctx->hold = false;
248
249 return true;
250 }
251
252 void coda_fill_bitstream(struct coda_ctx *ctx, struct list_head *buffer_list)
253 {
254 struct vb2_v4l2_buffer *src_buf;
255 struct coda_buffer_meta *meta;
256 unsigned long flags;
257 u32 start;
258
259 if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG)
260 return;
261
262 while (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) > 0) {
263 /*
264 * Only queue two JPEGs into the bitstream buffer to keep
265 * latency low. We need at least one complete buffer and the
266 * header of another buffer (for prescan) in the bitstream.
267 */
268 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
269 ctx->num_metas > 1)
270 break;
271
272 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
273
274 /* Drop frames that do not start/end with a SOI/EOI markers */
275 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
276 !coda_jpeg_check_buffer(ctx, &src_buf->vb2_buf)) {
277 v4l2_err(&ctx->dev->v4l2_dev,
278 "dropping invalid JPEG frame %d\n",
279 ctx->qsequence);
280 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
281 if (buffer_list) {
282 struct v4l2_m2m_buffer *m2m_buf;
283
284 m2m_buf = container_of(src_buf,
285 struct v4l2_m2m_buffer,
286 vb);
287 list_add_tail(&m2m_buf->list, buffer_list);
288 } else {
289 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR);
290 }
291 continue;
292 }
293
294 /* Dump empty buffers */
295 if (!vb2_get_plane_payload(&src_buf->vb2_buf, 0)) {
296 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
297 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
298 continue;
299 }
300
301 /* Buffer start position */
302 start = ctx->bitstream_fifo.kfifo.in &
303 ctx->bitstream_fifo.kfifo.mask;
304
305 if (coda_bitstream_try_queue(ctx, src_buf)) {
306 /*
307 * Source buffer is queued in the bitstream ringbuffer;
308 * queue the timestamp and mark source buffer as done
309 */
310 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
311
312 meta = kmalloc(sizeof(*meta), GFP_KERNEL);
313 if (meta) {
314 meta->sequence = src_buf->sequence;
315 meta->timecode = src_buf->timecode;
316 meta->timestamp = src_buf->vb2_buf.timestamp;
317 meta->start = start;
318 meta->end = ctx->bitstream_fifo.kfifo.in &
319 ctx->bitstream_fifo.kfifo.mask;
320 spin_lock_irqsave(&ctx->buffer_meta_lock,
321 flags);
322 list_add_tail(&meta->list,
323 &ctx->buffer_meta_list);
324 ctx->num_metas++;
325 spin_unlock_irqrestore(&ctx->buffer_meta_lock,
326 flags);
327
328 trace_coda_bit_queue(ctx, src_buf, meta);
329 }
330
331 if (buffer_list) {
332 struct v4l2_m2m_buffer *m2m_buf;
333
334 m2m_buf = container_of(src_buf,
335 struct v4l2_m2m_buffer,
336 vb);
337 list_add_tail(&m2m_buf->list, buffer_list);
338 } else {
339 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
340 }
341 } else {
342 break;
343 }
344 }
345 }
346
347 void coda_bit_stream_end_flag(struct coda_ctx *ctx)
348 {
349 struct coda_dev *dev = ctx->dev;
350
351 ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
352
353 /* If this context is currently running, update the hardware flag */
354 if ((dev->devtype->product == CODA_960) &&
355 coda_isbusy(dev) &&
356 (ctx->idx == coda_read(dev, CODA_REG_BIT_RUN_INDEX))) {
357 coda_write(dev, ctx->bit_stream_param,
358 CODA_REG_BIT_BIT_STREAM_PARAM);
359 }
360 }
361
362 static void coda_parabuf_write(struct coda_ctx *ctx, int index, u32 value)
363 {
364 struct coda_dev *dev = ctx->dev;
365 u32 *p = ctx->parabuf.vaddr;
366
367 if (dev->devtype->product == CODA_DX6)
368 p[index] = value;
369 else
370 p[index ^ 1] = value;
371 }
372
373 static inline int coda_alloc_context_buf(struct coda_ctx *ctx,
374 struct coda_aux_buf *buf, size_t size,
375 const char *name)
376 {
377 return coda_alloc_aux_buf(ctx->dev, buf, size, name, ctx->debugfs_entry);
378 }
379
380
381 static void coda_free_framebuffers(struct coda_ctx *ctx)
382 {
383 int i;
384
385 for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++)
386 coda_free_aux_buf(ctx->dev, &ctx->internal_frames[i]);
387 }
388
389 static int coda_alloc_framebuffers(struct coda_ctx *ctx,
390 struct coda_q_data *q_data, u32 fourcc)
391 {
392 struct coda_dev *dev = ctx->dev;
393 unsigned int ysize, ycbcr_size;
394 int ret;
395 int i;
396
397 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 ||
398 ctx->codec->dst_fourcc == V4L2_PIX_FMT_H264 ||
399 ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4 ||
400 ctx->codec->dst_fourcc == V4L2_PIX_FMT_MPEG4)
401 ysize = round_up(q_data->width, 16) *
402 round_up(q_data->height, 16);
403 else
404 ysize = round_up(q_data->width, 8) * q_data->height;
405
406 if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
407 ycbcr_size = round_up(ysize, 4096) + ysize / 2;
408 else
409 ycbcr_size = ysize + ysize / 2;
410
411 /* Allocate frame buffers */
412 for (i = 0; i < ctx->num_internal_frames; i++) {
413 size_t size = ycbcr_size;
414 char *name;
415
416 /* Add space for mvcol buffers */
417 if (dev->devtype->product != CODA_DX6 &&
418 (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 ||
419 (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4 && i == 0)))
420 size += ysize / 4;
421 name = kasprintf(GFP_KERNEL, "fb%d", i);
422 if (!name) {
423 coda_free_framebuffers(ctx);
424 return -ENOMEM;
425 }
426 ret = coda_alloc_context_buf(ctx, &ctx->internal_frames[i],
427 size, name);
428 kfree(name);
429 if (ret < 0) {
430 coda_free_framebuffers(ctx);
431 return ret;
432 }
433 }
434
435 /* Register frame buffers in the parameter buffer */
436 for (i = 0; i < ctx->num_internal_frames; i++) {
437 u32 y, cb, cr, mvcol;
438
439 /* Start addresses of Y, Cb, Cr planes */
440 y = ctx->internal_frames[i].paddr;
441 cb = y + ysize;
442 cr = y + ysize + ysize/4;
443 mvcol = y + ysize + ysize/4 + ysize/4;
444 if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP) {
445 cb = round_up(cb, 4096);
446 mvcol = cb + ysize/2;
447 cr = 0;
448 /* Packed 20-bit MSB of base addresses */
449 /* YYYYYCCC, CCyyyyyc, cccc.... */
450 y = (y & 0xfffff000) | cb >> 20;
451 cb = (cb & 0x000ff000) << 12;
452 }
453 coda_parabuf_write(ctx, i * 3 + 0, y);
454 coda_parabuf_write(ctx, i * 3 + 1, cb);
455 coda_parabuf_write(ctx, i * 3 + 2, cr);
456
457 if (dev->devtype->product == CODA_DX6)
458 continue;
459
460 /* mvcol buffer for h.264 and mpeg4 */
461 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264)
462 coda_parabuf_write(ctx, 96 + i, mvcol);
463 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4 && i == 0)
464 coda_parabuf_write(ctx, 97, mvcol);
465 }
466
467 return 0;
468 }
469
470 static void coda_free_context_buffers(struct coda_ctx *ctx)
471 {
472 struct coda_dev *dev = ctx->dev;
473
474 coda_free_aux_buf(dev, &ctx->slicebuf);
475 coda_free_aux_buf(dev, &ctx->psbuf);
476 if (dev->devtype->product != CODA_DX6)
477 coda_free_aux_buf(dev, &ctx->workbuf);
478 coda_free_aux_buf(dev, &ctx->parabuf);
479 }
480
481 static int coda_alloc_context_buffers(struct coda_ctx *ctx,
482 struct coda_q_data *q_data)
483 {
484 struct coda_dev *dev = ctx->dev;
485 size_t size;
486 int ret;
487
488 if (!ctx->parabuf.vaddr) {
489 ret = coda_alloc_context_buf(ctx, &ctx->parabuf,
490 CODA_PARA_BUF_SIZE, "parabuf");
491 if (ret < 0)
492 return ret;
493 }
494
495 if (dev->devtype->product == CODA_DX6)
496 return 0;
497
498 if (!ctx->slicebuf.vaddr && q_data->fourcc == V4L2_PIX_FMT_H264) {
499 /* worst case slice size */
500 size = (DIV_ROUND_UP(q_data->width, 16) *
501 DIV_ROUND_UP(q_data->height, 16)) * 3200 / 8 + 512;
502 ret = coda_alloc_context_buf(ctx, &ctx->slicebuf, size,
503 "slicebuf");
504 if (ret < 0)
505 goto err;
506 }
507
508 if (!ctx->psbuf.vaddr && (dev->devtype->product == CODA_HX4 ||
509 dev->devtype->product == CODA_7541)) {
510 ret = coda_alloc_context_buf(ctx, &ctx->psbuf,
511 CODA7_PS_BUF_SIZE, "psbuf");
512 if (ret < 0)
513 goto err;
514 }
515
516 if (!ctx->workbuf.vaddr) {
517 size = dev->devtype->workbuf_size;
518 if (dev->devtype->product == CODA_960 &&
519 q_data->fourcc == V4L2_PIX_FMT_H264)
520 size += CODA9_PS_SAVE_SIZE;
521 ret = coda_alloc_context_buf(ctx, &ctx->workbuf, size,
522 "workbuf");
523 if (ret < 0)
524 goto err;
525 }
526
527 return 0;
528
529 err:
530 coda_free_context_buffers(ctx);
531 return ret;
532 }
533
534 static int coda_encode_header(struct coda_ctx *ctx, struct vb2_v4l2_buffer *buf,
535 int header_code, u8 *header, int *size)
536 {
537 struct vb2_buffer *vb = &buf->vb2_buf;
538 struct coda_dev *dev = ctx->dev;
539 size_t bufsize;
540 int ret;
541 int i;
542
543 if (dev->devtype->product == CODA_960)
544 memset(vb2_plane_vaddr(vb, 0), 0, 64);
545
546 coda_write(dev, vb2_dma_contig_plane_dma_addr(vb, 0),
547 CODA_CMD_ENC_HEADER_BB_START);
548 bufsize = vb2_plane_size(vb, 0);
549 if (dev->devtype->product == CODA_960)
550 bufsize /= 1024;
551 coda_write(dev, bufsize, CODA_CMD_ENC_HEADER_BB_SIZE);
552 coda_write(dev, header_code, CODA_CMD_ENC_HEADER_CODE);
553 ret = coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER);
554 if (ret < 0) {
555 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
556 return ret;
557 }
558
559 if (dev->devtype->product == CODA_960) {
560 for (i = 63; i > 0; i--)
561 if (((char *)vb2_plane_vaddr(vb, 0))[i] != 0)
562 break;
563 *size = i + 1;
564 } else {
565 *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) -
566 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
567 }
568 memcpy(header, vb2_plane_vaddr(vb, 0), *size);
569
570 return 0;
571 }
572
573 static phys_addr_t coda_iram_alloc(struct coda_iram_info *iram, size_t size)
574 {
575 phys_addr_t ret;
576
577 size = round_up(size, 1024);
578 if (size > iram->remaining)
579 return 0;
580 iram->remaining -= size;
581
582 ret = iram->next_paddr;
583 iram->next_paddr += size;
584
585 return ret;
586 }
587
588 static void coda_setup_iram(struct coda_ctx *ctx)
589 {
590 struct coda_iram_info *iram_info = &ctx->iram_info;
591 struct coda_dev *dev = ctx->dev;
592 int w64, w128;
593 int mb_width;
594 int dbk_bits;
595 int bit_bits;
596 int ip_bits;
597 int me_bits;
598
599 memset(iram_info, 0, sizeof(*iram_info));
600 iram_info->next_paddr = dev->iram.paddr;
601 iram_info->remaining = dev->iram.size;
602
603 if (!dev->iram.vaddr)
604 return;
605
606 switch (dev->devtype->product) {
607 case CODA_HX4:
608 dbk_bits = CODA7_USE_HOST_DBK_ENABLE;
609 bit_bits = CODA7_USE_HOST_BIT_ENABLE;
610 ip_bits = CODA7_USE_HOST_IP_ENABLE;
611 me_bits = CODA7_USE_HOST_ME_ENABLE;
612 break;
613 case CODA_7541:
614 dbk_bits = CODA7_USE_HOST_DBK_ENABLE | CODA7_USE_DBK_ENABLE;
615 bit_bits = CODA7_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
616 ip_bits = CODA7_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
617 me_bits = CODA7_USE_HOST_ME_ENABLE | CODA7_USE_ME_ENABLE;
618 break;
619 case CODA_960:
620 dbk_bits = CODA9_USE_HOST_DBK_ENABLE | CODA9_USE_DBK_ENABLE;
621 bit_bits = CODA9_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
622 ip_bits = CODA9_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
623 me_bits = 0;
624 break;
625 default: /* CODA_DX6 */
626 return;
627 }
628
629 if (ctx->inst_type == CODA_INST_ENCODER) {
630 struct coda_q_data *q_data_src;
631
632 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
633 mb_width = DIV_ROUND_UP(q_data_src->width, 16);
634 w128 = mb_width * 128;
635 w64 = mb_width * 64;
636
637 /* Prioritize in case IRAM is too small for everything */
638 if (dev->devtype->product == CODA_HX4 ||
639 dev->devtype->product == CODA_7541) {
640 iram_info->search_ram_size = round_up(mb_width * 16 *
641 36 + 2048, 1024);
642 iram_info->search_ram_paddr = coda_iram_alloc(iram_info,
643 iram_info->search_ram_size);
644 if (!iram_info->search_ram_paddr) {
645 pr_err("IRAM is smaller than the search ram size\n");
646 goto out;
647 }
648 iram_info->axi_sram_use |= me_bits;
649 }
650
651 /* Only H.264BP and H.263P3 are considered */
652 iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w64);
653 iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w64);
654 if (!iram_info->buf_dbk_c_use)
655 goto out;
656 iram_info->axi_sram_use |= dbk_bits;
657
658 iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
659 if (!iram_info->buf_bit_use)
660 goto out;
661 iram_info->axi_sram_use |= bit_bits;
662
663 iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
664 if (!iram_info->buf_ip_ac_dc_use)
665 goto out;
666 iram_info->axi_sram_use |= ip_bits;
667
668 /* OVL and BTP disabled for encoder */
669 } else if (ctx->inst_type == CODA_INST_DECODER) {
670 struct coda_q_data *q_data_dst;
671
672 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
673 mb_width = DIV_ROUND_UP(q_data_dst->width, 16);
674 w128 = mb_width * 128;
675
676 iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w128);
677 iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w128);
678 if (!iram_info->buf_dbk_c_use)
679 goto out;
680 iram_info->axi_sram_use |= dbk_bits;
681
682 iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
683 if (!iram_info->buf_bit_use)
684 goto out;
685 iram_info->axi_sram_use |= bit_bits;
686
687 iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
688 if (!iram_info->buf_ip_ac_dc_use)
689 goto out;
690 iram_info->axi_sram_use |= ip_bits;
691
692 /* OVL and BTP unused as there is no VC1 support yet */
693 }
694
695 out:
696 if (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE))
697 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
698 "IRAM smaller than needed\n");
699
700 if (dev->devtype->product == CODA_HX4 ||
701 dev->devtype->product == CODA_7541) {
702 /* TODO - Enabling these causes picture errors on CODA7541 */
703 if (ctx->inst_type == CODA_INST_DECODER) {
704 /* fw 1.4.50 */
705 iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
706 CODA7_USE_IP_ENABLE);
707 } else {
708 /* fw 13.4.29 */
709 iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
710 CODA7_USE_HOST_DBK_ENABLE |
711 CODA7_USE_IP_ENABLE |
712 CODA7_USE_DBK_ENABLE);
713 }
714 }
715 }
716
717 static u32 coda_supported_firmwares[] = {
718 CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
719 CODA_FIRMWARE_VERNUM(CODA_HX4, 1, 4, 50),
720 CODA_FIRMWARE_VERNUM(CODA_7541, 1, 4, 50),
721 CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 5),
722 CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 9),
723 CODA_FIRMWARE_VERNUM(CODA_960, 2, 3, 10),
724 CODA_FIRMWARE_VERNUM(CODA_960, 3, 1, 1),
725 };
726
727 static bool coda_firmware_supported(u32 vernum)
728 {
729 int i;
730
731 for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
732 if (vernum == coda_supported_firmwares[i])
733 return true;
734 return false;
735 }
736
737 int coda_check_firmware(struct coda_dev *dev)
738 {
739 u16 product, major, minor, release;
740 u32 data;
741 int ret;
742
743 ret = clk_prepare_enable(dev->clk_per);
744 if (ret)
745 goto err_clk_per;
746
747 ret = clk_prepare_enable(dev->clk_ahb);
748 if (ret)
749 goto err_clk_ahb;
750
751 coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
752 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
753 coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
754 coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
755 coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
756 if (coda_wait_timeout(dev)) {
757 v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
758 ret = -EIO;
759 goto err_run_cmd;
760 }
761
762 if (dev->devtype->product == CODA_960) {
763 data = coda_read(dev, CODA9_CMD_FIRMWARE_CODE_REV);
764 v4l2_info(&dev->v4l2_dev, "Firmware code revision: %d\n",
765 data);
766 }
767
768 /* Check we are compatible with the loaded firmware */
769 data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
770 product = CODA_FIRMWARE_PRODUCT(data);
771 major = CODA_FIRMWARE_MAJOR(data);
772 minor = CODA_FIRMWARE_MINOR(data);
773 release = CODA_FIRMWARE_RELEASE(data);
774
775 clk_disable_unprepare(dev->clk_per);
776 clk_disable_unprepare(dev->clk_ahb);
777
778 if (product != dev->devtype->product) {
779 v4l2_err(&dev->v4l2_dev,
780 "Wrong firmware. Hw: %s, Fw: %s, Version: %u.%u.%u\n",
781 coda_product_name(dev->devtype->product),
782 coda_product_name(product), major, minor, release);
783 return -EINVAL;
784 }
785
786 v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
787 coda_product_name(product));
788
789 if (coda_firmware_supported(data)) {
790 v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
791 major, minor, release);
792 } else {
793 v4l2_warn(&dev->v4l2_dev,
794 "Unsupported firmware version: %u.%u.%u\n",
795 major, minor, release);
796 }
797
798 return 0;
799
800 err_run_cmd:
801 clk_disable_unprepare(dev->clk_ahb);
802 err_clk_ahb:
803 clk_disable_unprepare(dev->clk_per);
804 err_clk_per:
805 return ret;
806 }
807
808 static void coda9_set_frame_cache(struct coda_ctx *ctx, u32 fourcc)
809 {
810 u32 cache_size, cache_config;
811
812 if (ctx->tiled_map_type == GDI_LINEAR_FRAME_MAP) {
813 /* Luma 2x0 page, 2x6 cache, chroma 2x0 page, 2x4 cache size */
814 cache_size = 0x20262024;
815 cache_config = 2 << CODA9_CACHE_PAGEMERGE_OFFSET;
816 } else {
817 /* Luma 0x2 page, 4x4 cache, chroma 0x2 page, 4x3 cache size */
818 cache_size = 0x02440243;
819 cache_config = 1 << CODA9_CACHE_PAGEMERGE_OFFSET;
820 }
821 coda_write(ctx->dev, cache_size, CODA9_CMD_SET_FRAME_CACHE_SIZE);
822 if (fourcc == V4L2_PIX_FMT_NV12 || fourcc == V4L2_PIX_FMT_YUYV) {
823 cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
824 16 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |
825 0 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;
826 } else {
827 cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
828 8 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |
829 8 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;
830 }
831 coda_write(ctx->dev, cache_config, CODA9_CMD_SET_FRAME_CACHE_CONFIG);
832 }
833
834 /*
835 * Encoder context operations
836 */
837
838 static int coda_encoder_reqbufs(struct coda_ctx *ctx,
839 struct v4l2_requestbuffers *rb)
840 {
841 struct coda_q_data *q_data_src;
842 int ret;
843
844 if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
845 return 0;
846
847 if (rb->count) {
848 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
849 ret = coda_alloc_context_buffers(ctx, q_data_src);
850 if (ret < 0)
851 return ret;
852 } else {
853 coda_free_context_buffers(ctx);
854 }
855
856 return 0;
857 }
858
859 static int coda_start_encoding(struct coda_ctx *ctx)
860 {
861 struct coda_dev *dev = ctx->dev;
862 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
863 struct coda_q_data *q_data_src, *q_data_dst;
864 u32 bitstream_buf, bitstream_size;
865 struct vb2_v4l2_buffer *buf;
866 int gamma, ret, value;
867 u32 dst_fourcc;
868 int num_fb;
869 u32 stride;
870
871 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
872 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
873 dst_fourcc = q_data_dst->fourcc;
874
875 buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
876 bitstream_buf = vb2_dma_contig_plane_dma_addr(&buf->vb2_buf, 0);
877 bitstream_size = q_data_dst->sizeimage;
878
879 if (!coda_is_initialized(dev)) {
880 v4l2_err(v4l2_dev, "coda is not initialized.\n");
881 return -EFAULT;
882 }
883
884 if (dst_fourcc == V4L2_PIX_FMT_JPEG) {
885 if (!ctx->params.jpeg_qmat_tab[0])
886 ctx->params.jpeg_qmat_tab[0] = kmalloc(64, GFP_KERNEL);
887 if (!ctx->params.jpeg_qmat_tab[1])
888 ctx->params.jpeg_qmat_tab[1] = kmalloc(64, GFP_KERNEL);
889 coda_set_jpeg_compression_quality(ctx, ctx->params.jpeg_quality);
890 }
891
892 mutex_lock(&dev->coda_mutex);
893
894 coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
895 coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
896 coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
897 switch (dev->devtype->product) {
898 case CODA_DX6:
899 coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
900 CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
901 break;
902 case CODA_960:
903 coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
904 /* fallthrough */
905 case CODA_HX4:
906 case CODA_7541:
907 coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
908 CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
909 break;
910 }
911
912 ctx->frame_mem_ctrl &= ~(CODA_FRAME_CHROMA_INTERLEAVE | (0x3 << 9) |
913 CODA9_FRAME_TILED2LINEAR);
914 if (q_data_src->fourcc == V4L2_PIX_FMT_NV12)
915 ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
916 if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
917 ctx->frame_mem_ctrl |= (0x3 << 9) | CODA9_FRAME_TILED2LINEAR;
918 coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
919
920 if (dev->devtype->product == CODA_DX6) {
921 /* Configure the coda */
922 coda_write(dev, dev->iram.paddr,
923 CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
924 }
925
926 /* Could set rotation here if needed */
927 value = 0;
928 switch (dev->devtype->product) {
929 case CODA_DX6:
930 value = (q_data_src->width & CODADX6_PICWIDTH_MASK)
931 << CODADX6_PICWIDTH_OFFSET;
932 value |= (q_data_src->height & CODADX6_PICHEIGHT_MASK)
933 << CODA_PICHEIGHT_OFFSET;
934 break;
935 case CODA_HX4:
936 case CODA_7541:
937 if (dst_fourcc == V4L2_PIX_FMT_H264) {
938 value = (round_up(q_data_src->width, 16) &
939 CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
940 value |= (round_up(q_data_src->height, 16) &
941 CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
942 break;
943 }
944 /* fallthrough */
945 case CODA_960:
946 value = (q_data_src->width & CODA7_PICWIDTH_MASK)
947 << CODA7_PICWIDTH_OFFSET;
948 value |= (q_data_src->height & CODA7_PICHEIGHT_MASK)
949 << CODA_PICHEIGHT_OFFSET;
950 }
951 coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
952 if (dst_fourcc == V4L2_PIX_FMT_JPEG)
953 ctx->params.framerate = 0;
954 coda_write(dev, ctx->params.framerate,
955 CODA_CMD_ENC_SEQ_SRC_F_RATE);
956
957 ctx->params.codec_mode = ctx->codec->mode;
958 switch (dst_fourcc) {
959 case V4L2_PIX_FMT_MPEG4:
960 if (dev->devtype->product == CODA_960)
961 coda_write(dev, CODA9_STD_MPEG4,
962 CODA_CMD_ENC_SEQ_COD_STD);
963 else
964 coda_write(dev, CODA_STD_MPEG4,
965 CODA_CMD_ENC_SEQ_COD_STD);
966 coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
967 break;
968 case V4L2_PIX_FMT_H264:
969 if (dev->devtype->product == CODA_960)
970 coda_write(dev, CODA9_STD_H264,
971 CODA_CMD_ENC_SEQ_COD_STD);
972 else
973 coda_write(dev, CODA_STD_H264,
974 CODA_CMD_ENC_SEQ_COD_STD);
975 if (ctx->params.h264_deblk_enabled) {
976 value = ((ctx->params.h264_deblk_alpha &
977 CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK) <<
978 CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET) |
979 ((ctx->params.h264_deblk_beta &
980 CODA_264PARAM_DEBLKFILTEROFFSETBETA_MASK) <<
981 CODA_264PARAM_DEBLKFILTEROFFSETBETA_OFFSET);
982 } else {
983 value = 1 << CODA_264PARAM_DISABLEDEBLK_OFFSET;
984 }
985 coda_write(dev, value, CODA_CMD_ENC_SEQ_264_PARA);
986 break;
987 case V4L2_PIX_FMT_JPEG:
988 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_PARA);
989 coda_write(dev, ctx->params.jpeg_restart_interval,
990 CODA_CMD_ENC_SEQ_JPG_RST_INTERVAL);
991 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_EN);
992 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_SIZE);
993 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_OFFSET);
994
995 coda_jpeg_write_tables(ctx);
996 break;
997 default:
998 v4l2_err(v4l2_dev,
999 "dst format (0x%08x) invalid.\n", dst_fourcc);
1000 ret = -EINVAL;
1001 goto out;
1002 }
1003
1004 /*
1005 * slice mode and GOP size registers are used for thumb size/offset
1006 * in JPEG mode
1007 */
1008 if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
1009 switch (ctx->params.slice_mode) {
1010 case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
1011 value = 0;
1012 break;
1013 case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
1014 value = (ctx->params.slice_max_mb &
1015 CODA_SLICING_SIZE_MASK)
1016 << CODA_SLICING_SIZE_OFFSET;
1017 value |= (1 & CODA_SLICING_UNIT_MASK)
1018 << CODA_SLICING_UNIT_OFFSET;
1019 value |= 1 & CODA_SLICING_MODE_MASK;
1020 break;
1021 case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
1022 value = (ctx->params.slice_max_bits &
1023 CODA_SLICING_SIZE_MASK)
1024 << CODA_SLICING_SIZE_OFFSET;
1025 value |= (0 & CODA_SLICING_UNIT_MASK)
1026 << CODA_SLICING_UNIT_OFFSET;
1027 value |= 1 & CODA_SLICING_MODE_MASK;
1028 break;
1029 }
1030 coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
1031 value = ctx->params.gop_size;
1032 coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
1033 }
1034
1035 if (ctx->params.bitrate) {
1036 /* Rate control enabled */
1037 value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK)
1038 << CODA_RATECONTROL_BITRATE_OFFSET;
1039 value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
1040 value |= (ctx->params.vbv_delay &
1041 CODA_RATECONTROL_INITIALDELAY_MASK)
1042 << CODA_RATECONTROL_INITIALDELAY_OFFSET;
1043 if (dev->devtype->product == CODA_960)
1044 value |= BIT(31); /* disable autoskip */
1045 } else {
1046 value = 0;
1047 }
1048 coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
1049
1050 coda_write(dev, ctx->params.vbv_size, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
1051 coda_write(dev, ctx->params.intra_refresh,
1052 CODA_CMD_ENC_SEQ_INTRA_REFRESH);
1053
1054 coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
1055 coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
1056
1057
1058 value = 0;
1059 if (dev->devtype->product == CODA_960)
1060 gamma = CODA9_DEFAULT_GAMMA;
1061 else
1062 gamma = CODA_DEFAULT_GAMMA;
1063 if (gamma > 0) {
1064 coda_write(dev, (gamma & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET,
1065 CODA_CMD_ENC_SEQ_RC_GAMMA);
1066 }
1067
1068 if (ctx->params.h264_min_qp || ctx->params.h264_max_qp) {
1069 coda_write(dev,
1070 ctx->params.h264_min_qp << CODA_QPMIN_OFFSET |
1071 ctx->params.h264_max_qp << CODA_QPMAX_OFFSET,
1072 CODA_CMD_ENC_SEQ_RC_QP_MIN_MAX);
1073 }
1074 if (dev->devtype->product == CODA_960) {
1075 if (ctx->params.h264_max_qp)
1076 value |= 1 << CODA9_OPTION_RCQPMAX_OFFSET;
1077 if (CODA_DEFAULT_GAMMA > 0)
1078 value |= 1 << CODA9_OPTION_GAMMA_OFFSET;
1079 } else {
1080 if (CODA_DEFAULT_GAMMA > 0) {
1081 if (dev->devtype->product == CODA_DX6)
1082 value |= 1 << CODADX6_OPTION_GAMMA_OFFSET;
1083 else
1084 value |= 1 << CODA7_OPTION_GAMMA_OFFSET;
1085 }
1086 if (ctx->params.h264_min_qp)
1087 value |= 1 << CODA7_OPTION_RCQPMIN_OFFSET;
1088 if (ctx->params.h264_max_qp)
1089 value |= 1 << CODA7_OPTION_RCQPMAX_OFFSET;
1090 }
1091 coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
1092
1093 coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_INTERVAL_MODE);
1094
1095 coda_setup_iram(ctx);
1096
1097 if (dst_fourcc == V4L2_PIX_FMT_H264) {
1098 switch (dev->devtype->product) {
1099 case CODA_DX6:
1100 value = FMO_SLICE_SAVE_BUF_SIZE << 7;
1101 coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
1102 break;
1103 case CODA_HX4:
1104 case CODA_7541:
1105 coda_write(dev, ctx->iram_info.search_ram_paddr,
1106 CODA7_CMD_ENC_SEQ_SEARCH_BASE);
1107 coda_write(dev, ctx->iram_info.search_ram_size,
1108 CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
1109 break;
1110 case CODA_960:
1111 coda_write(dev, 0, CODA9_CMD_ENC_SEQ_ME_OPTION);
1112 coda_write(dev, 0, CODA9_CMD_ENC_SEQ_INTRA_WEIGHT);
1113 }
1114 }
1115
1116 ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
1117 if (ret < 0) {
1118 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
1119 goto out;
1120 }
1121
1122 if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0) {
1123 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT failed\n");
1124 ret = -EFAULT;
1125 goto out;
1126 }
1127 ctx->initialized = 1;
1128
1129 if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
1130 if (dev->devtype->product == CODA_960)
1131 ctx->num_internal_frames = 4;
1132 else
1133 ctx->num_internal_frames = 2;
1134 ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
1135 if (ret < 0) {
1136 v4l2_err(v4l2_dev, "failed to allocate framebuffers\n");
1137 goto out;
1138 }
1139 num_fb = 2;
1140 stride = q_data_src->bytesperline;
1141 } else {
1142 ctx->num_internal_frames = 0;
1143 num_fb = 0;
1144 stride = 0;
1145 }
1146 coda_write(dev, num_fb, CODA_CMD_SET_FRAME_BUF_NUM);
1147 coda_write(dev, stride, CODA_CMD_SET_FRAME_BUF_STRIDE);
1148
1149 if (dev->devtype->product == CODA_HX4 ||
1150 dev->devtype->product == CODA_7541) {
1151 coda_write(dev, q_data_src->bytesperline,
1152 CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
1153 }
1154 if (dev->devtype->product != CODA_DX6) {
1155 coda_write(dev, ctx->iram_info.buf_bit_use,
1156 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
1157 coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
1158 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
1159 coda_write(dev, ctx->iram_info.buf_dbk_y_use,
1160 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
1161 coda_write(dev, ctx->iram_info.buf_dbk_c_use,
1162 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
1163 coda_write(dev, ctx->iram_info.buf_ovl_use,
1164 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
1165 if (dev->devtype->product == CODA_960) {
1166 coda_write(dev, ctx->iram_info.buf_btp_use,
1167 CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
1168
1169 coda9_set_frame_cache(ctx, q_data_src->fourcc);
1170
1171 /* FIXME */
1172 coda_write(dev, ctx->internal_frames[2].paddr,
1173 CODA9_CMD_SET_FRAME_SUBSAMP_A);
1174 coda_write(dev, ctx->internal_frames[3].paddr,
1175 CODA9_CMD_SET_FRAME_SUBSAMP_B);
1176 }
1177 }
1178
1179 ret = coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF);
1180 if (ret < 0) {
1181 v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1182 goto out;
1183 }
1184
1185 /* Save stream headers */
1186 buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1187 switch (dst_fourcc) {
1188 case V4L2_PIX_FMT_H264:
1189 /*
1190 * Get SPS in the first frame and copy it to an
1191 * intermediate buffer.
1192 */
1193 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_SPS,
1194 &ctx->vpu_header[0][0],
1195 &ctx->vpu_header_size[0]);
1196 if (ret < 0)
1197 goto out;
1198
1199 /*
1200 * Get PPS in the first frame and copy it to an
1201 * intermediate buffer.
1202 */
1203 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_PPS,
1204 &ctx->vpu_header[1][0],
1205 &ctx->vpu_header_size[1]);
1206 if (ret < 0)
1207 goto out;
1208
1209 /*
1210 * Length of H.264 headers is variable and thus it might not be
1211 * aligned for the coda to append the encoded frame. In that is
1212 * the case a filler NAL must be added to header 2.
1213 */
1214 ctx->vpu_header_size[2] = coda_h264_padding(
1215 (ctx->vpu_header_size[0] +
1216 ctx->vpu_header_size[1]),
1217 ctx->vpu_header[2]);
1218 break;
1219 case V4L2_PIX_FMT_MPEG4:
1220 /*
1221 * Get VOS in the first frame and copy it to an
1222 * intermediate buffer
1223 */
1224 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOS,
1225 &ctx->vpu_header[0][0],
1226 &ctx->vpu_header_size[0]);
1227 if (ret < 0)
1228 goto out;
1229
1230 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VIS,
1231 &ctx->vpu_header[1][0],
1232 &ctx->vpu_header_size[1]);
1233 if (ret < 0)
1234 goto out;
1235
1236 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOL,
1237 &ctx->vpu_header[2][0],
1238 &ctx->vpu_header_size[2]);
1239 if (ret < 0)
1240 goto out;
1241 break;
1242 default:
1243 /* No more formats need to save headers at the moment */
1244 break;
1245 }
1246
1247 out:
1248 mutex_unlock(&dev->coda_mutex);
1249 return ret;
1250 }
1251
1252 static int coda_prepare_encode(struct coda_ctx *ctx)
1253 {
1254 struct coda_q_data *q_data_src, *q_data_dst;
1255 struct vb2_v4l2_buffer *src_buf, *dst_buf;
1256 struct coda_dev *dev = ctx->dev;
1257 int force_ipicture;
1258 int quant_param = 0;
1259 u32 pic_stream_buffer_addr, pic_stream_buffer_size;
1260 u32 rot_mode = 0;
1261 u32 dst_fourcc;
1262 u32 reg;
1263
1264 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
1265 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1266 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1267 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1268 dst_fourcc = q_data_dst->fourcc;
1269
1270 src_buf->sequence = ctx->osequence;
1271 dst_buf->sequence = ctx->osequence;
1272 ctx->osequence++;
1273
1274 force_ipicture = ctx->params.force_ipicture;
1275 if (force_ipicture)
1276 ctx->params.force_ipicture = false;
1277 else if (ctx->params.gop_size != 0 &&
1278 (src_buf->sequence % ctx->params.gop_size) == 0)
1279 force_ipicture = 1;
1280
1281 /*
1282 * Workaround coda firmware BUG that only marks the first
1283 * frame as IDR. This is a problem for some decoders that can't
1284 * recover when a frame is lost.
1285 */
1286 if (!force_ipicture) {
1287 src_buf->flags |= V4L2_BUF_FLAG_PFRAME;
1288 src_buf->flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1289 } else {
1290 src_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
1291 src_buf->flags &= ~V4L2_BUF_FLAG_PFRAME;
1292 }
1293
1294 if (dev->devtype->product == CODA_960)
1295 coda_set_gdi_regs(ctx);
1296
1297 /*
1298 * Copy headers in front of the first frame and forced I frames for
1299 * H.264 only. In MPEG4 they are already copied by the CODA.
1300 */
1301 if (src_buf->sequence == 0 || force_ipicture) {
1302 pic_stream_buffer_addr =
1303 vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0) +
1304 ctx->vpu_header_size[0] +
1305 ctx->vpu_header_size[1] +
1306 ctx->vpu_header_size[2];
1307 pic_stream_buffer_size = q_data_dst->sizeimage -
1308 ctx->vpu_header_size[0] -
1309 ctx->vpu_header_size[1] -
1310 ctx->vpu_header_size[2];
1311 memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0),
1312 &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
1313 memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0)
1314 + ctx->vpu_header_size[0], &ctx->vpu_header[1][0],
1315 ctx->vpu_header_size[1]);
1316 memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0)
1317 + ctx->vpu_header_size[0] + ctx->vpu_header_size[1],
1318 &ctx->vpu_header[2][0], ctx->vpu_header_size[2]);
1319 } else {
1320 pic_stream_buffer_addr =
1321 vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
1322 pic_stream_buffer_size = q_data_dst->sizeimage;
1323 }
1324
1325 if (force_ipicture) {
1326 switch (dst_fourcc) {
1327 case V4L2_PIX_FMT_H264:
1328 quant_param = ctx->params.h264_intra_qp;
1329 break;
1330 case V4L2_PIX_FMT_MPEG4:
1331 quant_param = ctx->params.mpeg4_intra_qp;
1332 break;
1333 case V4L2_PIX_FMT_JPEG:
1334 quant_param = 30;
1335 break;
1336 default:
1337 v4l2_warn(&ctx->dev->v4l2_dev,
1338 "cannot set intra qp, fmt not supported\n");
1339 break;
1340 }
1341 } else {
1342 switch (dst_fourcc) {
1343 case V4L2_PIX_FMT_H264:
1344 quant_param = ctx->params.h264_inter_qp;
1345 break;
1346 case V4L2_PIX_FMT_MPEG4:
1347 quant_param = ctx->params.mpeg4_inter_qp;
1348 break;
1349 default:
1350 v4l2_warn(&ctx->dev->v4l2_dev,
1351 "cannot set inter qp, fmt not supported\n");
1352 break;
1353 }
1354 }
1355
1356 /* submit */
1357 if (ctx->params.rot_mode)
1358 rot_mode = CODA_ROT_MIR_ENABLE | ctx->params.rot_mode;
1359 coda_write(dev, rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
1360 coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
1361
1362 if (dev->devtype->product == CODA_960) {
1363 coda_write(dev, 4/*FIXME: 0*/, CODA9_CMD_ENC_PIC_SRC_INDEX);
1364 coda_write(dev, q_data_src->bytesperline,
1365 CODA9_CMD_ENC_PIC_SRC_STRIDE);
1366 coda_write(dev, 0, CODA9_CMD_ENC_PIC_SUB_FRAME_SYNC);
1367
1368 reg = CODA9_CMD_ENC_PIC_SRC_ADDR_Y;
1369 } else {
1370 reg = CODA_CMD_ENC_PIC_SRC_ADDR_Y;
1371 }
1372 coda_write_base(ctx, q_data_src, src_buf, reg);
1373
1374 coda_write(dev, force_ipicture << 1 & 0x2,
1375 CODA_CMD_ENC_PIC_OPTION);
1376
1377 coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
1378 coda_write(dev, pic_stream_buffer_size / 1024,
1379 CODA_CMD_ENC_PIC_BB_SIZE);
1380
1381 if (!ctx->streamon_out) {
1382 /* After streamoff on the output side, set stream end flag */
1383 ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
1384 coda_write(dev, ctx->bit_stream_param,
1385 CODA_REG_BIT_BIT_STREAM_PARAM);
1386 }
1387
1388 if (dev->devtype->product != CODA_DX6)
1389 coda_write(dev, ctx->iram_info.axi_sram_use,
1390 CODA7_REG_BIT_AXI_SRAM_USE);
1391
1392 trace_coda_enc_pic_run(ctx, src_buf);
1393
1394 coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
1395
1396 return 0;
1397 }
1398
1399 static void coda_finish_encode(struct coda_ctx *ctx)
1400 {
1401 struct vb2_v4l2_buffer *src_buf, *dst_buf;
1402 struct coda_dev *dev = ctx->dev;
1403 u32 wr_ptr, start_ptr;
1404
1405 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1406 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1407
1408 trace_coda_enc_pic_done(ctx, dst_buf);
1409
1410 /* Get results from the coda */
1411 start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
1412 wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
1413
1414 /* Calculate bytesused field */
1415 if (dst_buf->sequence == 0 ||
1416 src_buf->flags & V4L2_BUF_FLAG_KEYFRAME) {
1417 vb2_set_plane_payload(&dst_buf->vb2_buf, 0, wr_ptr - start_ptr +
1418 ctx->vpu_header_size[0] +
1419 ctx->vpu_header_size[1] +
1420 ctx->vpu_header_size[2]);
1421 } else {
1422 vb2_set_plane_payload(&dst_buf->vb2_buf, 0, wr_ptr - start_ptr);
1423 }
1424
1425 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
1426 wr_ptr - start_ptr);
1427
1428 coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
1429 coda_read(dev, CODA_RET_ENC_PIC_FLAG);
1430
1431 if (coda_read(dev, CODA_RET_ENC_PIC_TYPE) == 0) {
1432 dst_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
1433 dst_buf->flags &= ~V4L2_BUF_FLAG_PFRAME;
1434 } else {
1435 dst_buf->flags |= V4L2_BUF_FLAG_PFRAME;
1436 dst_buf->flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1437 }
1438
1439 dst_buf->vb2_buf.timestamp = src_buf->vb2_buf.timestamp;
1440 dst_buf->field = src_buf->field;
1441 dst_buf->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
1442 dst_buf->flags |=
1443 src_buf->flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
1444 dst_buf->timecode = src_buf->timecode;
1445
1446 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
1447
1448 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1449 coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_DONE);
1450
1451 ctx->gopcounter--;
1452 if (ctx->gopcounter < 0)
1453 ctx->gopcounter = ctx->params.gop_size - 1;
1454
1455 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1456 "job finished: encoding frame (%d) (%s)\n",
1457 dst_buf->sequence,
1458 (dst_buf->flags & V4L2_BUF_FLAG_KEYFRAME) ?
1459 "KEYFRAME" : "PFRAME");
1460 }
1461
1462 static void coda_seq_end_work(struct work_struct *work)
1463 {
1464 struct coda_ctx *ctx = container_of(work, struct coda_ctx, seq_end_work);
1465 struct coda_dev *dev = ctx->dev;
1466
1467 mutex_lock(&ctx->buffer_mutex);
1468 mutex_lock(&dev->coda_mutex);
1469
1470 if (ctx->initialized == 0)
1471 goto out;
1472
1473 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1474 "%d: %s: sent command 'SEQ_END' to coda\n", ctx->idx,
1475 __func__);
1476 if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
1477 v4l2_err(&dev->v4l2_dev,
1478 "CODA_COMMAND_SEQ_END failed\n");
1479 }
1480
1481 /*
1482 * FIXME: Sometimes h.264 encoding fails with 8-byte sequences missing
1483 * from the output stream after the h.264 decoder has run. Resetting the
1484 * hardware after the decoder has finished seems to help.
1485 */
1486 if (dev->devtype->product == CODA_960)
1487 coda_hw_reset(ctx);
1488
1489 kfifo_init(&ctx->bitstream_fifo,
1490 ctx->bitstream.vaddr, ctx->bitstream.size);
1491
1492 coda_free_framebuffers(ctx);
1493
1494 ctx->initialized = 0;
1495
1496 out:
1497 mutex_unlock(&dev->coda_mutex);
1498 mutex_unlock(&ctx->buffer_mutex);
1499 }
1500
1501 static void coda_bit_release(struct coda_ctx *ctx)
1502 {
1503 mutex_lock(&ctx->buffer_mutex);
1504 coda_free_framebuffers(ctx);
1505 coda_free_context_buffers(ctx);
1506 coda_free_bitstream_buffer(ctx);
1507 mutex_unlock(&ctx->buffer_mutex);
1508 }
1509
1510 const struct coda_context_ops coda_bit_encode_ops = {
1511 .queue_init = coda_encoder_queue_init,
1512 .reqbufs = coda_encoder_reqbufs,
1513 .start_streaming = coda_start_encoding,
1514 .prepare_run = coda_prepare_encode,
1515 .finish_run = coda_finish_encode,
1516 .seq_end_work = coda_seq_end_work,
1517 .release = coda_bit_release,
1518 };
1519
1520 /*
1521 * Decoder context operations
1522 */
1523
1524 static int coda_alloc_bitstream_buffer(struct coda_ctx *ctx,
1525 struct coda_q_data *q_data)
1526 {
1527 if (ctx->bitstream.vaddr)
1528 return 0;
1529
1530 ctx->bitstream.size = roundup_pow_of_two(q_data->sizeimage * 2);
1531 ctx->bitstream.vaddr = dma_alloc_wc(&ctx->dev->plat_dev->dev,
1532 ctx->bitstream.size,
1533 &ctx->bitstream.paddr, GFP_KERNEL);
1534 if (!ctx->bitstream.vaddr) {
1535 v4l2_err(&ctx->dev->v4l2_dev,
1536 "failed to allocate bitstream ringbuffer");
1537 return -ENOMEM;
1538 }
1539 kfifo_init(&ctx->bitstream_fifo,
1540 ctx->bitstream.vaddr, ctx->bitstream.size);
1541
1542 return 0;
1543 }
1544
1545 static void coda_free_bitstream_buffer(struct coda_ctx *ctx)
1546 {
1547 if (ctx->bitstream.vaddr == NULL)
1548 return;
1549
1550 dma_free_wc(&ctx->dev->plat_dev->dev, ctx->bitstream.size,
1551 ctx->bitstream.vaddr, ctx->bitstream.paddr);
1552 ctx->bitstream.vaddr = NULL;
1553 kfifo_init(&ctx->bitstream_fifo, NULL, 0);
1554 }
1555
1556 static int coda_decoder_reqbufs(struct coda_ctx *ctx,
1557 struct v4l2_requestbuffers *rb)
1558 {
1559 struct coda_q_data *q_data_src;
1560 int ret;
1561
1562 if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
1563 return 0;
1564
1565 if (rb->count) {
1566 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1567 ret = coda_alloc_context_buffers(ctx, q_data_src);
1568 if (ret < 0)
1569 return ret;
1570 ret = coda_alloc_bitstream_buffer(ctx, q_data_src);
1571 if (ret < 0) {
1572 coda_free_context_buffers(ctx);
1573 return ret;
1574 }
1575 } else {
1576 coda_free_bitstream_buffer(ctx);
1577 coda_free_context_buffers(ctx);
1578 }
1579
1580 return 0;
1581 }
1582
1583 static bool coda_reorder_enable(struct coda_ctx *ctx)
1584 {
1585 struct coda_dev *dev = ctx->dev;
1586 int profile;
1587
1588 if (dev->devtype->product != CODA_HX4 &&
1589 dev->devtype->product != CODA_7541 &&
1590 dev->devtype->product != CODA_960)
1591 return false;
1592
1593 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG)
1594 return false;
1595
1596 if (ctx->codec->src_fourcc != V4L2_PIX_FMT_H264)
1597 return true;
1598
1599 profile = coda_h264_profile(ctx->params.h264_profile_idc);
1600 if (profile < 0)
1601 v4l2_warn(&dev->v4l2_dev, "Unknown H264 Profile: %u\n",
1602 ctx->params.h264_profile_idc);
1603
1604 /* Baseline profile does not support reordering */
1605 return profile > V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE;
1606 }
1607
1608 static int __coda_start_decoding(struct coda_ctx *ctx)
1609 {
1610 struct coda_q_data *q_data_src, *q_data_dst;
1611 u32 bitstream_buf, bitstream_size;
1612 struct coda_dev *dev = ctx->dev;
1613 int width, height;
1614 u32 src_fourcc, dst_fourcc;
1615 u32 val;
1616 int ret;
1617
1618 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1619 "Video Data Order Adapter: %s\n",
1620 ctx->use_vdoa ? "Enabled" : "Disabled");
1621
1622 /* Start decoding */
1623 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1624 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1625 bitstream_buf = ctx->bitstream.paddr;
1626 bitstream_size = ctx->bitstream.size;
1627 src_fourcc = q_data_src->fourcc;
1628 dst_fourcc = q_data_dst->fourcc;
1629
1630 coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
1631
1632 /* Update coda bitstream read and write pointers from kfifo */
1633 coda_kfifo_sync_to_device_full(ctx);
1634
1635 ctx->frame_mem_ctrl &= ~(CODA_FRAME_CHROMA_INTERLEAVE | (0x3 << 9) |
1636 CODA9_FRAME_TILED2LINEAR);
1637 if (dst_fourcc == V4L2_PIX_FMT_NV12 || dst_fourcc == V4L2_PIX_FMT_YUYV)
1638 ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
1639 if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
1640 ctx->frame_mem_ctrl |= (0x3 << 9) |
1641 ((ctx->use_vdoa) ? 0 : CODA9_FRAME_TILED2LINEAR);
1642 coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
1643
1644 ctx->display_idx = -1;
1645 ctx->frm_dis_flg = 0;
1646 coda_write(dev, 0, CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1647
1648 coda_write(dev, bitstream_buf, CODA_CMD_DEC_SEQ_BB_START);
1649 coda_write(dev, bitstream_size / 1024, CODA_CMD_DEC_SEQ_BB_SIZE);
1650 val = 0;
1651 if (coda_reorder_enable(ctx))
1652 val |= CODA_REORDER_ENABLE;
1653 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG)
1654 val |= CODA_NO_INT_ENABLE;
1655 coda_write(dev, val, CODA_CMD_DEC_SEQ_OPTION);
1656
1657 ctx->params.codec_mode = ctx->codec->mode;
1658 if (dev->devtype->product == CODA_960 &&
1659 src_fourcc == V4L2_PIX_FMT_MPEG4)
1660 ctx->params.codec_mode_aux = CODA_MP4_AUX_MPEG4;
1661 else
1662 ctx->params.codec_mode_aux = 0;
1663 if (src_fourcc == V4L2_PIX_FMT_MPEG4) {
1664 coda_write(dev, CODA_MP4_CLASS_MPEG4,
1665 CODA_CMD_DEC_SEQ_MP4_ASP_CLASS);
1666 }
1667 if (src_fourcc == V4L2_PIX_FMT_H264) {
1668 if (dev->devtype->product == CODA_HX4 ||
1669 dev->devtype->product == CODA_7541) {
1670 coda_write(dev, ctx->psbuf.paddr,
1671 CODA_CMD_DEC_SEQ_PS_BB_START);
1672 coda_write(dev, (CODA7_PS_BUF_SIZE / 1024),
1673 CODA_CMD_DEC_SEQ_PS_BB_SIZE);
1674 }
1675 if (dev->devtype->product == CODA_960) {
1676 coda_write(dev, 0, CODA_CMD_DEC_SEQ_X264_MV_EN);
1677 coda_write(dev, 512, CODA_CMD_DEC_SEQ_SPP_CHUNK_SIZE);
1678 }
1679 }
1680 if (src_fourcc == V4L2_PIX_FMT_JPEG)
1681 coda_write(dev, 0, CODA_CMD_DEC_SEQ_JPG_THUMB_EN);
1682 if (dev->devtype->product != CODA_960)
1683 coda_write(dev, 0, CODA_CMD_DEC_SEQ_SRC_SIZE);
1684
1685 ctx->bit_stream_param = CODA_BIT_DEC_SEQ_INIT_ESCAPE;
1686 ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
1687 ctx->bit_stream_param = 0;
1688 if (ret) {
1689 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
1690 return ret;
1691 }
1692 ctx->initialized = 1;
1693
1694 /* Update kfifo out pointer from coda bitstream read pointer */
1695 coda_kfifo_sync_from_device(ctx);
1696
1697 if (coda_read(dev, CODA_RET_DEC_SEQ_SUCCESS) == 0) {
1698 v4l2_err(&dev->v4l2_dev,
1699 "CODA_COMMAND_SEQ_INIT failed, error code = %d\n",
1700 coda_read(dev, CODA_RET_DEC_SEQ_ERR_REASON));
1701 return -EAGAIN;
1702 }
1703
1704 val = coda_read(dev, CODA_RET_DEC_SEQ_SRC_SIZE);
1705 if (dev->devtype->product == CODA_DX6) {
1706 width = (val >> CODADX6_PICWIDTH_OFFSET) & CODADX6_PICWIDTH_MASK;
1707 height = val & CODADX6_PICHEIGHT_MASK;
1708 } else {
1709 width = (val >> CODA7_PICWIDTH_OFFSET) & CODA7_PICWIDTH_MASK;
1710 height = val & CODA7_PICHEIGHT_MASK;
1711 }
1712
1713 if (width > q_data_dst->bytesperline || height > q_data_dst->height) {
1714 v4l2_err(&dev->v4l2_dev, "stream is %dx%d, not %dx%d\n",
1715 width, height, q_data_dst->bytesperline,
1716 q_data_dst->height);
1717 return -EINVAL;
1718 }
1719
1720 width = round_up(width, 16);
1721 height = round_up(height, 16);
1722
1723 v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "%s instance %d now: %dx%d\n",
1724 __func__, ctx->idx, width, height);
1725
1726 ctx->num_internal_frames = coda_read(dev, CODA_RET_DEC_SEQ_FRAME_NEED);
1727 /*
1728 * If the VDOA is used, the decoder needs one additional frame,
1729 * because the frames are freed when the next frame is decoded.
1730 * Otherwise there are visible errors in the decoded frames (green
1731 * regions in displayed frames) and a broken order of frames (earlier
1732 * frames are sporadically displayed after later frames).
1733 */
1734 if (ctx->use_vdoa)
1735 ctx->num_internal_frames += 1;
1736 if (ctx->num_internal_frames > CODA_MAX_FRAMEBUFFERS) {
1737 v4l2_err(&dev->v4l2_dev,
1738 "not enough framebuffers to decode (%d < %d)\n",
1739 CODA_MAX_FRAMEBUFFERS, ctx->num_internal_frames);
1740 return -EINVAL;
1741 }
1742
1743 if (src_fourcc == V4L2_PIX_FMT_H264) {
1744 u32 left_right;
1745 u32 top_bottom;
1746
1747 left_right = coda_read(dev, CODA_RET_DEC_SEQ_CROP_LEFT_RIGHT);
1748 top_bottom = coda_read(dev, CODA_RET_DEC_SEQ_CROP_TOP_BOTTOM);
1749
1750 q_data_dst->rect.left = (left_right >> 10) & 0x3ff;
1751 q_data_dst->rect.top = (top_bottom >> 10) & 0x3ff;
1752 q_data_dst->rect.width = width - q_data_dst->rect.left -
1753 (left_right & 0x3ff);
1754 q_data_dst->rect.height = height - q_data_dst->rect.top -
1755 (top_bottom & 0x3ff);
1756 }
1757
1758 ret = coda_alloc_framebuffers(ctx, q_data_dst, src_fourcc);
1759 if (ret < 0) {
1760 v4l2_err(&dev->v4l2_dev, "failed to allocate framebuffers\n");
1761 return ret;
1762 }
1763
1764 /* Tell the decoder how many frame buffers we allocated. */
1765 coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
1766 coda_write(dev, width, CODA_CMD_SET_FRAME_BUF_STRIDE);
1767
1768 if (dev->devtype->product != CODA_DX6) {
1769 /* Set secondary AXI IRAM */
1770 coda_setup_iram(ctx);
1771
1772 coda_write(dev, ctx->iram_info.buf_bit_use,
1773 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
1774 coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
1775 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
1776 coda_write(dev, ctx->iram_info.buf_dbk_y_use,
1777 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
1778 coda_write(dev, ctx->iram_info.buf_dbk_c_use,
1779 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
1780 coda_write(dev, ctx->iram_info.buf_ovl_use,
1781 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
1782 if (dev->devtype->product == CODA_960) {
1783 coda_write(dev, ctx->iram_info.buf_btp_use,
1784 CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
1785
1786 coda_write(dev, -1, CODA9_CMD_SET_FRAME_DELAY);
1787 coda9_set_frame_cache(ctx, dst_fourcc);
1788 }
1789 }
1790
1791 if (src_fourcc == V4L2_PIX_FMT_H264) {
1792 coda_write(dev, ctx->slicebuf.paddr,
1793 CODA_CMD_SET_FRAME_SLICE_BB_START);
1794 coda_write(dev, ctx->slicebuf.size / 1024,
1795 CODA_CMD_SET_FRAME_SLICE_BB_SIZE);
1796 }
1797
1798 if (dev->devtype->product == CODA_HX4 ||
1799 dev->devtype->product == CODA_7541) {
1800 int max_mb_x = 1920 / 16;
1801 int max_mb_y = 1088 / 16;
1802 int max_mb_num = max_mb_x * max_mb_y;
1803
1804 coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
1805 CODA7_CMD_SET_FRAME_MAX_DEC_SIZE);
1806 } else if (dev->devtype->product == CODA_960) {
1807 int max_mb_x = 1920 / 16;
1808 int max_mb_y = 1088 / 16;
1809 int max_mb_num = max_mb_x * max_mb_y;
1810
1811 coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
1812 CODA9_CMD_SET_FRAME_MAX_DEC_SIZE);
1813 }
1814
1815 if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
1816 v4l2_err(&ctx->dev->v4l2_dev,
1817 "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1818 return -ETIMEDOUT;
1819 }
1820
1821 return 0;
1822 }
1823
1824 static int coda_start_decoding(struct coda_ctx *ctx)
1825 {
1826 struct coda_dev *dev = ctx->dev;
1827 int ret;
1828
1829 mutex_lock(&dev->coda_mutex);
1830 ret = __coda_start_decoding(ctx);
1831 mutex_unlock(&dev->coda_mutex);
1832
1833 return ret;
1834 }
1835
1836 static int coda_prepare_decode(struct coda_ctx *ctx)
1837 {
1838 struct vb2_v4l2_buffer *dst_buf;
1839 struct coda_dev *dev = ctx->dev;
1840 struct coda_q_data *q_data_dst;
1841 struct coda_buffer_meta *meta;
1842 unsigned long flags;
1843 u32 rot_mode = 0;
1844 u32 reg_addr, reg_stride;
1845
1846 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1847 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1848
1849 /* Try to copy source buffer contents into the bitstream ringbuffer */
1850 mutex_lock(&ctx->bitstream_mutex);
1851 coda_fill_bitstream(ctx, NULL);
1852 mutex_unlock(&ctx->bitstream_mutex);
1853
1854 if (coda_get_bitstream_payload(ctx) < 512 &&
1855 (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))) {
1856 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1857 "bitstream payload: %d, skipping\n",
1858 coda_get_bitstream_payload(ctx));
1859 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
1860 return -EAGAIN;
1861 }
1862
1863 /* Run coda_start_decoding (again) if not yet initialized */
1864 if (!ctx->initialized) {
1865 int ret = __coda_start_decoding(ctx);
1866
1867 if (ret < 0) {
1868 v4l2_err(&dev->v4l2_dev, "failed to start decoding\n");
1869 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
1870 return -EAGAIN;
1871 } else {
1872 ctx->initialized = 1;
1873 }
1874 }
1875
1876 if (dev->devtype->product == CODA_960)
1877 coda_set_gdi_regs(ctx);
1878
1879 if (ctx->use_vdoa &&
1880 ctx->display_idx >= 0 &&
1881 ctx->display_idx < ctx->num_internal_frames) {
1882 vdoa_device_run(ctx->vdoa,
1883 vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0),
1884 ctx->internal_frames[ctx->display_idx].paddr);
1885 } else {
1886 if (dev->devtype->product == CODA_960) {
1887 /*
1888 * The CODA960 seems to have an internal list of
1889 * buffers with 64 entries that includes the
1890 * registered frame buffers as well as the rotator
1891 * buffer output.
1892 *
1893 * ROT_INDEX needs to be < 0x40, but >
1894 * ctx->num_internal_frames.
1895 */
1896 coda_write(dev,
1897 CODA_MAX_FRAMEBUFFERS + dst_buf->vb2_buf.index,
1898 CODA9_CMD_DEC_PIC_ROT_INDEX);
1899
1900 reg_addr = CODA9_CMD_DEC_PIC_ROT_ADDR_Y;
1901 reg_stride = CODA9_CMD_DEC_PIC_ROT_STRIDE;
1902 } else {
1903 reg_addr = CODA_CMD_DEC_PIC_ROT_ADDR_Y;
1904 reg_stride = CODA_CMD_DEC_PIC_ROT_STRIDE;
1905 }
1906 coda_write_base(ctx, q_data_dst, dst_buf, reg_addr);
1907 coda_write(dev, q_data_dst->bytesperline, reg_stride);
1908
1909 rot_mode = CODA_ROT_MIR_ENABLE | ctx->params.rot_mode;
1910 }
1911
1912 coda_write(dev, rot_mode, CODA_CMD_DEC_PIC_ROT_MODE);
1913
1914 switch (dev->devtype->product) {
1915 case CODA_DX6:
1916 /* TBD */
1917 case CODA_HX4:
1918 case CODA_7541:
1919 coda_write(dev, CODA_PRE_SCAN_EN, CODA_CMD_DEC_PIC_OPTION);
1920 break;
1921 case CODA_960:
1922 /* 'hardcode to use interrupt disable mode'? */
1923 coda_write(dev, (1 << 10), CODA_CMD_DEC_PIC_OPTION);
1924 break;
1925 }
1926
1927 coda_write(dev, 0, CODA_CMD_DEC_PIC_SKIP_NUM);
1928
1929 coda_write(dev, 0, CODA_CMD_DEC_PIC_BB_START);
1930 coda_write(dev, 0, CODA_CMD_DEC_PIC_START_BYTE);
1931
1932 if (dev->devtype->product != CODA_DX6)
1933 coda_write(dev, ctx->iram_info.axi_sram_use,
1934 CODA7_REG_BIT_AXI_SRAM_USE);
1935
1936 spin_lock_irqsave(&ctx->buffer_meta_lock, flags);
1937 meta = list_first_entry_or_null(&ctx->buffer_meta_list,
1938 struct coda_buffer_meta, list);
1939
1940 if (meta && ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG) {
1941
1942 /* If this is the last buffer in the bitstream, add padding */
1943 if (meta->end == (ctx->bitstream_fifo.kfifo.in &
1944 ctx->bitstream_fifo.kfifo.mask)) {
1945 static unsigned char buf[512];
1946 unsigned int pad;
1947
1948 /* Pad to multiple of 256 and then add 256 more */
1949 pad = ((0 - meta->end) & 0xff) + 256;
1950
1951 memset(buf, 0xff, sizeof(buf));
1952
1953 kfifo_in(&ctx->bitstream_fifo, buf, pad);
1954 }
1955 }
1956 spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
1957
1958 coda_kfifo_sync_to_device_full(ctx);
1959
1960 /* Clear decode success flag */
1961 coda_write(dev, 0, CODA_RET_DEC_PIC_SUCCESS);
1962
1963 trace_coda_dec_pic_run(ctx, meta);
1964
1965 coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
1966
1967 return 0;
1968 }
1969
1970 static void coda_finish_decode(struct coda_ctx *ctx)
1971 {
1972 struct coda_dev *dev = ctx->dev;
1973 struct coda_q_data *q_data_src;
1974 struct coda_q_data *q_data_dst;
1975 struct vb2_v4l2_buffer *dst_buf;
1976 struct coda_buffer_meta *meta;
1977 unsigned long payload;
1978 unsigned long flags;
1979 int width, height;
1980 int decoded_idx;
1981 int display_idx;
1982 u32 src_fourcc;
1983 int success;
1984 u32 err_mb;
1985 int err_vdoa = 0;
1986 u32 val;
1987
1988 /* Update kfifo out pointer from coda bitstream read pointer */
1989 coda_kfifo_sync_from_device(ctx);
1990
1991 /*
1992 * in stream-end mode, the read pointer can overshoot the write pointer
1993 * by up to 512 bytes
1994 */
1995 if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG) {
1996 if (coda_get_bitstream_payload(ctx) >= ctx->bitstream.size - 512)
1997 kfifo_init(&ctx->bitstream_fifo,
1998 ctx->bitstream.vaddr, ctx->bitstream.size);
1999 }
2000
2001 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
2002 src_fourcc = q_data_src->fourcc;
2003
2004 val = coda_read(dev, CODA_RET_DEC_PIC_SUCCESS);
2005 if (val != 1)
2006 pr_err("DEC_PIC_SUCCESS = %d\n", val);
2007
2008 success = val & 0x1;
2009 if (!success)
2010 v4l2_err(&dev->v4l2_dev, "decode failed\n");
2011
2012 if (src_fourcc == V4L2_PIX_FMT_H264) {
2013 if (val & (1 << 3))
2014 v4l2_err(&dev->v4l2_dev,
2015 "insufficient PS buffer space (%d bytes)\n",
2016 ctx->psbuf.size);
2017 if (val & (1 << 2))
2018 v4l2_err(&dev->v4l2_dev,
2019 "insufficient slice buffer space (%d bytes)\n",
2020 ctx->slicebuf.size);
2021 }
2022
2023 val = coda_read(dev, CODA_RET_DEC_PIC_SIZE);
2024 width = (val >> 16) & 0xffff;
2025 height = val & 0xffff;
2026
2027 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
2028
2029 /* frame crop information */
2030 if (src_fourcc == V4L2_PIX_FMT_H264) {
2031 u32 left_right;
2032 u32 top_bottom;
2033
2034 left_right = coda_read(dev, CODA_RET_DEC_PIC_CROP_LEFT_RIGHT);
2035 top_bottom = coda_read(dev, CODA_RET_DEC_PIC_CROP_TOP_BOTTOM);
2036
2037 if (left_right == 0xffffffff && top_bottom == 0xffffffff) {
2038 /* Keep current crop information */
2039 } else {
2040 struct v4l2_rect *rect = &q_data_dst->rect;
2041
2042 rect->left = left_right >> 16 & 0xffff;
2043 rect->top = top_bottom >> 16 & 0xffff;
2044 rect->width = width - rect->left -
2045 (left_right & 0xffff);
2046 rect->height = height - rect->top -
2047 (top_bottom & 0xffff);
2048 }
2049 } else {
2050 /* no cropping */
2051 }
2052
2053 err_mb = coda_read(dev, CODA_RET_DEC_PIC_ERR_MB);
2054 if (err_mb > 0)
2055 v4l2_err(&dev->v4l2_dev,
2056 "errors in %d macroblocks\n", err_mb);
2057
2058 if (dev->devtype->product == CODA_HX4 ||
2059 dev->devtype->product == CODA_7541) {
2060 val = coda_read(dev, CODA_RET_DEC_PIC_OPTION);
2061 if (val == 0) {
2062 /* not enough bitstream data */
2063 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
2064 "prescan failed: %d\n", val);
2065 ctx->hold = true;
2066 return;
2067 }
2068 }
2069
2070 /* Wait until the VDOA finished writing the previous display frame */
2071 if (ctx->use_vdoa &&
2072 ctx->display_idx >= 0 &&
2073 ctx->display_idx < ctx->num_internal_frames) {
2074 err_vdoa = vdoa_wait_for_completion(ctx->vdoa);
2075 }
2076
2077 ctx->frm_dis_flg = coda_read(dev,
2078 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
2079
2080 /* The previous display frame was copied out and can be overwritten */
2081 if (ctx->display_idx >= 0 &&
2082 ctx->display_idx < ctx->num_internal_frames) {
2083 ctx->frm_dis_flg &= ~(1 << ctx->display_idx);
2084 coda_write(dev, ctx->frm_dis_flg,
2085 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
2086 }
2087
2088 /*
2089 * The index of the last decoded frame, not necessarily in
2090 * display order, and the index of the next display frame.
2091 * The latter could have been decoded in a previous run.
2092 */
2093 decoded_idx = coda_read(dev, CODA_RET_DEC_PIC_CUR_IDX);
2094 display_idx = coda_read(dev, CODA_RET_DEC_PIC_FRAME_IDX);
2095
2096 if (decoded_idx == -1) {
2097 /* no frame was decoded, but we might have a display frame */
2098 if (display_idx >= 0 && display_idx < ctx->num_internal_frames)
2099 ctx->sequence_offset++;
2100 else if (ctx->display_idx < 0)
2101 ctx->hold = true;
2102 } else if (decoded_idx == -2) {
2103 /* no frame was decoded, we still return remaining buffers */
2104 } else if (decoded_idx < 0 || decoded_idx >= ctx->num_internal_frames) {
2105 v4l2_err(&dev->v4l2_dev,
2106 "decoded frame index out of range: %d\n", decoded_idx);
2107 } else {
2108 val = coda_read(dev, CODA_RET_DEC_PIC_FRAME_NUM) - 1;
2109 val -= ctx->sequence_offset;
2110 spin_lock_irqsave(&ctx->buffer_meta_lock, flags);
2111 if (!list_empty(&ctx->buffer_meta_list)) {
2112 meta = list_first_entry(&ctx->buffer_meta_list,
2113 struct coda_buffer_meta, list);
2114 list_del(&meta->list);
2115 ctx->num_metas--;
2116 spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
2117 /*
2118 * Clamp counters to 16 bits for comparison, as the HW
2119 * counter rolls over at this point for h.264. This
2120 * may be different for other formats, but using 16 bits
2121 * should be enough to detect most errors and saves us
2122 * from doing different things based on the format.
2123 */
2124 if ((val & 0xffff) != (meta->sequence & 0xffff)) {
2125 v4l2_err(&dev->v4l2_dev,
2126 "sequence number mismatch (%d(%d) != %d)\n",
2127 val, ctx->sequence_offset,
2128 meta->sequence);
2129 }
2130 ctx->frame_metas[decoded_idx] = *meta;
2131 kfree(meta);
2132 } else {
2133 spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
2134 v4l2_err(&dev->v4l2_dev, "empty timestamp list!\n");
2135 memset(&ctx->frame_metas[decoded_idx], 0,
2136 sizeof(struct coda_buffer_meta));
2137 ctx->frame_metas[decoded_idx].sequence = val;
2138 ctx->sequence_offset++;
2139 }
2140
2141 trace_coda_dec_pic_done(ctx, &ctx->frame_metas[decoded_idx]);
2142
2143 val = coda_read(dev, CODA_RET_DEC_PIC_TYPE) & 0x7;
2144 if (val == 0)
2145 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_KEYFRAME;
2146 else if (val == 1)
2147 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_PFRAME;
2148 else
2149 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_BFRAME;
2150
2151 ctx->frame_errors[decoded_idx] = err_mb;
2152 }
2153
2154 if (display_idx == -1) {
2155 /*
2156 * no more frames to be decoded, but there could still
2157 * be rotator output to dequeue
2158 */
2159 ctx->hold = true;
2160 } else if (display_idx == -3) {
2161 /* possibly prescan failure */
2162 } else if (display_idx < 0 || display_idx >= ctx->num_internal_frames) {
2163 v4l2_err(&dev->v4l2_dev,
2164 "presentation frame index out of range: %d\n",
2165 display_idx);
2166 }
2167
2168 /* If a frame was copied out, return it */
2169 if (ctx->display_idx >= 0 &&
2170 ctx->display_idx < ctx->num_internal_frames) {
2171 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
2172 dst_buf->sequence = ctx->osequence++;
2173
2174 dst_buf->field = V4L2_FIELD_NONE;
2175 dst_buf->flags &= ~(V4L2_BUF_FLAG_KEYFRAME |
2176 V4L2_BUF_FLAG_PFRAME |
2177 V4L2_BUF_FLAG_BFRAME);
2178 dst_buf->flags |= ctx->frame_types[ctx->display_idx];
2179 meta = &ctx->frame_metas[ctx->display_idx];
2180 dst_buf->timecode = meta->timecode;
2181 dst_buf->vb2_buf.timestamp = meta->timestamp;
2182
2183 trace_coda_dec_rot_done(ctx, dst_buf, meta);
2184
2185 switch (q_data_dst->fourcc) {
2186 case V4L2_PIX_FMT_YUYV:
2187 payload = width * height * 2;
2188 break;
2189 case V4L2_PIX_FMT_YUV420:
2190 case V4L2_PIX_FMT_YVU420:
2191 case V4L2_PIX_FMT_NV12:
2192 default:
2193 payload = width * height * 3 / 2;
2194 break;
2195 case V4L2_PIX_FMT_YUV422P:
2196 payload = width * height * 2;
2197 break;
2198 }
2199 vb2_set_plane_payload(&dst_buf->vb2_buf, 0, payload);
2200
2201 if (ctx->frame_errors[ctx->display_idx] || err_vdoa)
2202 coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_ERROR);
2203 else
2204 coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_DONE);
2205
2206 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
2207 "job finished: decoding frame (%d) (%s)\n",
2208 dst_buf->sequence,
2209 (dst_buf->flags & V4L2_BUF_FLAG_KEYFRAME) ?
2210 "KEYFRAME" : "PFRAME");
2211 } else {
2212 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
2213 "job finished: no frame decoded\n");
2214 }
2215
2216 /* The rotator will copy the current display frame next time */
2217 ctx->display_idx = display_idx;
2218 }
2219
2220 static void coda_decode_timeout(struct coda_ctx *ctx)
2221 {
2222 struct vb2_v4l2_buffer *dst_buf;
2223
2224 /*
2225 * For now this only handles the case where we would deadlock with
2226 * userspace, i.e. userspace issued DEC_CMD_STOP and waits for EOS,
2227 * but after a failed decode run we would hold the context and wait for
2228 * userspace to queue more buffers.
2229 */
2230 if (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))
2231 return;
2232
2233 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
2234 dst_buf->sequence = ctx->qsequence - 1;
2235
2236 coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_ERROR);
2237 }
2238
2239 const struct coda_context_ops coda_bit_decode_ops = {
2240 .queue_init = coda_decoder_queue_init,
2241 .reqbufs = coda_decoder_reqbufs,
2242 .start_streaming = coda_start_decoding,
2243 .prepare_run = coda_prepare_decode,
2244 .finish_run = coda_finish_decode,
2245 .run_timeout = coda_decode_timeout,
2246 .seq_end_work = coda_seq_end_work,
2247 .release = coda_bit_release,
2248 };
2249
2250 irqreturn_t coda_irq_handler(int irq, void *data)
2251 {
2252 struct coda_dev *dev = data;
2253 struct coda_ctx *ctx;
2254
2255 /* read status register to attend the IRQ */
2256 coda_read(dev, CODA_REG_BIT_INT_STATUS);
2257 coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
2258 CODA_REG_BIT_INT_CLEAR);
2259
2260 ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
2261 if (ctx == NULL) {
2262 v4l2_err(&dev->v4l2_dev,
2263 "Instance released before the end of transaction\n");
2264 mutex_unlock(&dev->coda_mutex);
2265 return IRQ_HANDLED;
2266 }
2267
2268 trace_coda_bit_done(ctx);
2269
2270 if (ctx->aborting) {
2271 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
2272 "task has been aborted\n");
2273 }
2274
2275 if (coda_isbusy(ctx->dev)) {
2276 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
2277 "coda is still busy!!!!\n");
2278 return IRQ_NONE;
2279 }
2280
2281 complete(&ctx->completion);
2282
2283 return IRQ_HANDLED;
2284 }
(deprecated) Btrfs devel tree