?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
target: Remove core_tpg_release_virtual_lun0 function
[linux-2.6/btrfs-unstable.git] / drivers / media / dvb-frontends / stv0367.c
blob59b6e661acc085bd99e6c11ff8dc8f58c88de35f
1 /*
2 * stv0367.c
3 *
4 * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
5 *
6 * Copyright (C) ST Microelectronics.
7 * Copyright (C) 2010,2011 NetUP Inc.
8 * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 *
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/string.h>
29 #include <linux/slab.h>
30 #include <linux/i2c.h>
31
32 #include "stv0367.h"
33 #include "stv0367_regs.h"
34 #include "stv0367_priv.h"
35
36 /* Max transfer size done by I2C transfer functions */
37 #define MAX_XFER_SIZE 64
38
39 static int stvdebug;
40 module_param_named(debug, stvdebug, int, 0644);
41
42 static int i2cdebug;
43 module_param_named(i2c_debug, i2cdebug, int, 0644);
44
45 #define dprintk(args...) \
46 do { \
47 if (stvdebug) \
48 printk(KERN_DEBUG args); \
49 } while (0)
50 /* DVB-C */
51
52 struct stv0367cab_state {
53 enum stv0367_cab_signal_type state;
54 u32 mclk;
55 u32 adc_clk;
56 s32 search_range;
57 s32 derot_offset;
58 /* results */
59 int locked; /* channel found */
60 u32 freq_khz; /* found frequency (in kHz) */
61 u32 symbol_rate; /* found symbol rate (in Bds) */
62 enum stv0367cab_mod modulation; /* modulation */
63 fe_spectral_inversion_t spect_inv; /* Spectrum Inversion */
64 };
65
66 struct stv0367ter_state {
67 /* DVB-T */
68 enum stv0367_ter_signal_type state;
69 enum stv0367_ter_if_iq_mode if_iq_mode;
70 enum stv0367_ter_mode mode;/* mode 2K or 8K */
71 fe_guard_interval_t guard;
72 enum stv0367_ter_hierarchy hierarchy;
73 u32 frequency;
74 fe_spectral_inversion_t sense; /* current search spectrum */
75 u8 force; /* force mode/guard */
76 u8 bw; /* channel width 6, 7 or 8 in MHz */
77 u8 pBW; /* channel width used during previous lock */
78 u32 pBER;
79 u32 pPER;
80 u32 ucblocks;
81 s8 echo_pos; /* echo position */
82 u8 first_lock;
83 u8 unlock_counter;
84 u32 agc_val;
85 };
86
87 struct stv0367_state {
88 struct dvb_frontend fe;
89 struct i2c_adapter *i2c;
90 /* config settings */
91 const struct stv0367_config *config;
92 u8 chip_id;
93 /* DVB-C */
94 struct stv0367cab_state *cab_state;
95 /* DVB-T */
96 struct stv0367ter_state *ter_state;
97 };
98
99 struct st_register {
100 u16 addr;
101 u8 value;
102 };
103
104 /* values for STV4100 XTAL=30M int clk=53.125M*/
105 static struct st_register def0367ter[STV0367TER_NBREGS] = {
106 {R367TER_ID, 0x60},
107 {R367TER_I2CRPT, 0xa0},
108 /* {R367TER_I2CRPT, 0x22},*/
109 {R367TER_TOPCTRL, 0x00},/* for xc5000; was 0x02 */
110 {R367TER_IOCFG0, 0x40},
111 {R367TER_DAC0R, 0x00},
112 {R367TER_IOCFG1, 0x00},
113 {R367TER_DAC1R, 0x00},
114 {R367TER_IOCFG2, 0x62},
115 {R367TER_SDFR, 0x00},
116 {R367TER_STATUS, 0xf8},
117 {R367TER_AUX_CLK, 0x0a},
118 {R367TER_FREESYS1, 0x00},
119 {R367TER_FREESYS2, 0x00},
120 {R367TER_FREESYS3, 0x00},
121 {R367TER_GPIO_CFG, 0x55},
122 {R367TER_GPIO_CMD, 0x00},
123 {R367TER_AGC2MAX, 0xff},
124 {R367TER_AGC2MIN, 0x00},
125 {R367TER_AGC1MAX, 0xff},
126 {R367TER_AGC1MIN, 0x00},
127 {R367TER_AGCR, 0xbc},
128 {R367TER_AGC2TH, 0x00},
129 {R367TER_AGC12C, 0x00},
130 {R367TER_AGCCTRL1, 0x85},
131 {R367TER_AGCCTRL2, 0x1f},
132 {R367TER_AGC1VAL1, 0x00},
133 {R367TER_AGC1VAL2, 0x00},
134 {R367TER_AGC2VAL1, 0x6f},
135 {R367TER_AGC2VAL2, 0x05},
136 {R367TER_AGC2PGA, 0x00},
137 {R367TER_OVF_RATE1, 0x00},
138 {R367TER_OVF_RATE2, 0x00},
139 {R367TER_GAIN_SRC1, 0xaa},/* for xc5000; was 0x2b */
140 {R367TER_GAIN_SRC2, 0xd6},/* for xc5000; was 0x04 */
141 {R367TER_INC_DEROT1, 0x55},
142 {R367TER_INC_DEROT2, 0x55},
143 {R367TER_PPM_CPAMP_DIR, 0x2c},
144 {R367TER_PPM_CPAMP_INV, 0x00},
145 {R367TER_FREESTFE_1, 0x00},
146 {R367TER_FREESTFE_2, 0x1c},
147 {R367TER_DCOFFSET, 0x00},
148 {R367TER_EN_PROCESS, 0x05},
149 {R367TER_SDI_SMOOTHER, 0x80},
150 {R367TER_FE_LOOP_OPEN, 0x1c},
151 {R367TER_FREQOFF1, 0x00},
152 {R367TER_FREQOFF2, 0x00},
153 {R367TER_FREQOFF3, 0x00},
154 {R367TER_TIMOFF1, 0x00},
155 {R367TER_TIMOFF2, 0x00},
156 {R367TER_EPQ, 0x02},
157 {R367TER_EPQAUTO, 0x01},
158 {R367TER_SYR_UPDATE, 0xf5},
159 {R367TER_CHPFREE, 0x00},
160 {R367TER_PPM_STATE_MAC, 0x23},
161 {R367TER_INR_THRESHOLD, 0xff},
162 {R367TER_EPQ_TPS_ID_CELL, 0xf9},
163 {R367TER_EPQ_CFG, 0x00},
164 {R367TER_EPQ_STATUS, 0x01},
165 {R367TER_AUTORELOCK, 0x81},
166 {R367TER_BER_THR_VMSB, 0x00},
167 {R367TER_BER_THR_MSB, 0x00},
168 {R367TER_BER_THR_LSB, 0x00},
169 {R367TER_CCD, 0x83},
170 {R367TER_SPECTR_CFG, 0x00},
171 {R367TER_CHC_DUMMY, 0x18},
172 {R367TER_INC_CTL, 0x88},
173 {R367TER_INCTHRES_COR1, 0xb4},
174 {R367TER_INCTHRES_COR2, 0x96},
175 {R367TER_INCTHRES_DET1, 0x0e},
176 {R367TER_INCTHRES_DET2, 0x11},
177 {R367TER_IIR_CELLNB, 0x8d},
178 {R367TER_IIRCX_COEFF1_MSB, 0x00},
179 {R367TER_IIRCX_COEFF1_LSB, 0x00},
180 {R367TER_IIRCX_COEFF2_MSB, 0x09},
181 {R367TER_IIRCX_COEFF2_LSB, 0x18},
182 {R367TER_IIRCX_COEFF3_MSB, 0x14},
183 {R367TER_IIRCX_COEFF3_LSB, 0x9c},
184 {R367TER_IIRCX_COEFF4_MSB, 0x00},
185 {R367TER_IIRCX_COEFF4_LSB, 0x00},
186 {R367TER_IIRCX_COEFF5_MSB, 0x36},
187 {R367TER_IIRCX_COEFF5_LSB, 0x42},
188 {R367TER_FEPATH_CFG, 0x00},
189 {R367TER_PMC1_FUNC, 0x65},
190 {R367TER_PMC1_FOR, 0x00},
191 {R367TER_PMC2_FUNC, 0x00},
192 {R367TER_STATUS_ERR_DA, 0xe0},
193 {R367TER_DIG_AGC_R, 0xfe},
194 {R367TER_COMAGC_TARMSB, 0x0b},
195 {R367TER_COM_AGC_TAR_ENMODE, 0x41},
196 {R367TER_COM_AGC_CFG, 0x3e},
197 {R367TER_COM_AGC_GAIN1, 0x39},
198 {R367TER_AUT_AGC_TARGETMSB, 0x0b},
199 {R367TER_LOCK_DET_MSB, 0x01},
200 {R367TER_AGCTAR_LOCK_LSBS, 0x40},
201 {R367TER_AUT_GAIN_EN, 0xf4},
202 {R367TER_AUT_CFG, 0xf0},
203 {R367TER_LOCKN, 0x23},
204 {R367TER_INT_X_3, 0x00},
205 {R367TER_INT_X_2, 0x03},
206 {R367TER_INT_X_1, 0x8d},
207 {R367TER_INT_X_0, 0xa0},
208 {R367TER_MIN_ERRX_MSB, 0x00},
209 {R367TER_COR_CTL, 0x23},
210 {R367TER_COR_STAT, 0xf6},
211 {R367TER_COR_INTEN, 0x00},
212 {R367TER_COR_INTSTAT, 0x3f},
213 {R367TER_COR_MODEGUARD, 0x03},
214 {R367TER_AGC_CTL, 0x08},
215 {R367TER_AGC_MANUAL1, 0x00},
216 {R367TER_AGC_MANUAL2, 0x00},
217 {R367TER_AGC_TARG, 0x16},
218 {R367TER_AGC_GAIN1, 0x53},
219 {R367TER_AGC_GAIN2, 0x1d},
220 {R367TER_RESERVED_1, 0x00},
221 {R367TER_RESERVED_2, 0x00},
222 {R367TER_RESERVED_3, 0x00},
223 {R367TER_CAS_CTL, 0x44},
224 {R367TER_CAS_FREQ, 0xb3},
225 {R367TER_CAS_DAGCGAIN, 0x12},
226 {R367TER_SYR_CTL, 0x04},
227 {R367TER_SYR_STAT, 0x10},
228 {R367TER_SYR_NCO1, 0x00},
229 {R367TER_SYR_NCO2, 0x00},
230 {R367TER_SYR_OFFSET1, 0x00},
231 {R367TER_SYR_OFFSET2, 0x00},
232 {R367TER_FFT_CTL, 0x00},
233 {R367TER_SCR_CTL, 0x70},
234 {R367TER_PPM_CTL1, 0xf8},
235 {R367TER_TRL_CTL, 0x14},/* for xc5000; was 0xac */
236 {R367TER_TRL_NOMRATE1, 0xae},/* for xc5000; was 0x1e */
237 {R367TER_TRL_NOMRATE2, 0x56},/* for xc5000; was 0x58 */
238 {R367TER_TRL_TIME1, 0x1d},
239 {R367TER_TRL_TIME2, 0xfc},
240 {R367TER_CRL_CTL, 0x24},
241 {R367TER_CRL_FREQ1, 0xad},
242 {R367TER_CRL_FREQ2, 0x9d},
243 {R367TER_CRL_FREQ3, 0xff},
244 {R367TER_CHC_CTL, 0x01},
245 {R367TER_CHC_SNR, 0xf0},
246 {R367TER_BDI_CTL, 0x00},
247 {R367TER_DMP_CTL, 0x00},
248 {R367TER_TPS_RCVD1, 0x30},
249 {R367TER_TPS_RCVD2, 0x02},
250 {R367TER_TPS_RCVD3, 0x01},
251 {R367TER_TPS_RCVD4, 0x00},
252 {R367TER_TPS_ID_CELL1, 0x00},
253 {R367TER_TPS_ID_CELL2, 0x00},
254 {R367TER_TPS_RCVD5_SET1, 0x02},
255 {R367TER_TPS_SET2, 0x02},
256 {R367TER_TPS_SET3, 0x01},
257 {R367TER_TPS_CTL, 0x00},
258 {R367TER_CTL_FFTOSNUM, 0x34},
259 {R367TER_TESTSELECT, 0x09},
260 {R367TER_MSC_REV, 0x0a},
261 {R367TER_PIR_CTL, 0x00},
262 {R367TER_SNR_CARRIER1, 0xa1},
263 {R367TER_SNR_CARRIER2, 0x9a},
264 {R367TER_PPM_CPAMP, 0x2c},
265 {R367TER_TSM_AP0, 0x00},
266 {R367TER_TSM_AP1, 0x00},
267 {R367TER_TSM_AP2 , 0x00},
268 {R367TER_TSM_AP3, 0x00},
269 {R367TER_TSM_AP4, 0x00},
270 {R367TER_TSM_AP5, 0x00},
271 {R367TER_TSM_AP6, 0x00},
272 {R367TER_TSM_AP7, 0x00},
273 {R367TER_TSTRES, 0x00},
274 {R367TER_ANACTRL, 0x0D},/* PLL stoped, restart at init!!! */
275 {R367TER_TSTBUS, 0x00},
276 {R367TER_TSTRATE, 0x00},
277 {R367TER_CONSTMODE, 0x01},
278 {R367TER_CONSTCARR1, 0x00},
279 {R367TER_CONSTCARR2, 0x00},
280 {R367TER_ICONSTEL, 0x0a},
281 {R367TER_QCONSTEL, 0x15},
282 {R367TER_TSTBISTRES0, 0x00},
283 {R367TER_TSTBISTRES1, 0x00},
284 {R367TER_TSTBISTRES2, 0x28},
285 {R367TER_TSTBISTRES3, 0x00},
286 {R367TER_RF_AGC1, 0xff},
287 {R367TER_RF_AGC2, 0x83},
288 {R367TER_ANADIGCTRL, 0x19},
289 {R367TER_PLLMDIV, 0x01},/* for xc5000; was 0x0c */
290 {R367TER_PLLNDIV, 0x06},/* for xc5000; was 0x55 */
291 {R367TER_PLLSETUP, 0x18},
292 {R367TER_DUAL_AD12, 0x0C},/* for xc5000 AGC voltage 1.6V */
293 {R367TER_TSTBIST, 0x00},
294 {R367TER_PAD_COMP_CTRL, 0x00},
295 {R367TER_PAD_COMP_WR, 0x00},
296 {R367TER_PAD_COMP_RD, 0xe0},
297 {R367TER_SYR_TARGET_FFTADJT_MSB, 0x00},
298 {R367TER_SYR_TARGET_FFTADJT_LSB, 0x00},
299 {R367TER_SYR_TARGET_CHCADJT_MSB, 0x00},
300 {R367TER_SYR_TARGET_CHCADJT_LSB, 0x00},
301 {R367TER_SYR_FLAG, 0x00},
302 {R367TER_CRL_TARGET1, 0x00},
303 {R367TER_CRL_TARGET2, 0x00},
304 {R367TER_CRL_TARGET3, 0x00},
305 {R367TER_CRL_TARGET4, 0x00},
306 {R367TER_CRL_FLAG, 0x00},
307 {R367TER_TRL_TARGET1, 0x00},
308 {R367TER_TRL_TARGET2, 0x00},
309 {R367TER_TRL_CHC, 0x00},
310 {R367TER_CHC_SNR_TARG, 0x00},
311 {R367TER_TOP_TRACK, 0x00},
312 {R367TER_TRACKER_FREE1, 0x00},
313 {R367TER_ERROR_CRL1, 0x00},
314 {R367TER_ERROR_CRL2, 0x00},
315 {R367TER_ERROR_CRL3, 0x00},
316 {R367TER_ERROR_CRL4, 0x00},
317 {R367TER_DEC_NCO1, 0x2c},
318 {R367TER_DEC_NCO2, 0x0f},
319 {R367TER_DEC_NCO3, 0x20},
320 {R367TER_SNR, 0xf1},
321 {R367TER_SYR_FFTADJ1, 0x00},
322 {R367TER_SYR_FFTADJ2, 0x00},
323 {R367TER_SYR_CHCADJ1, 0x00},
324 {R367TER_SYR_CHCADJ2, 0x00},
325 {R367TER_SYR_OFF, 0x00},
326 {R367TER_PPM_OFFSET1, 0x00},
327 {R367TER_PPM_OFFSET2, 0x03},
328 {R367TER_TRACKER_FREE2, 0x00},
329 {R367TER_DEBG_LT10, 0x00},
330 {R367TER_DEBG_LT11, 0x00},
331 {R367TER_DEBG_LT12, 0x00},
332 {R367TER_DEBG_LT13, 0x00},
333 {R367TER_DEBG_LT14, 0x00},
334 {R367TER_DEBG_LT15, 0x00},
335 {R367TER_DEBG_LT16, 0x00},
336 {R367TER_DEBG_LT17, 0x00},
337 {R367TER_DEBG_LT18, 0x00},
338 {R367TER_DEBG_LT19, 0x00},
339 {R367TER_DEBG_LT1A, 0x00},
340 {R367TER_DEBG_LT1B, 0x00},
341 {R367TER_DEBG_LT1C, 0x00},
342 {R367TER_DEBG_LT1D, 0x00},
343 {R367TER_DEBG_LT1E, 0x00},
344 {R367TER_DEBG_LT1F, 0x00},
345 {R367TER_RCCFGH, 0x00},
346 {R367TER_RCCFGM, 0x00},
347 {R367TER_RCCFGL, 0x00},
348 {R367TER_RCINSDELH, 0x00},
349 {R367TER_RCINSDELM, 0x00},
350 {R367TER_RCINSDELL, 0x00},
351 {R367TER_RCSTATUS, 0x00},
352 {R367TER_RCSPEED, 0x6f},
353 {R367TER_RCDEBUGM, 0xe7},
354 {R367TER_RCDEBUGL, 0x9b},
355 {R367TER_RCOBSCFG, 0x00},
356 {R367TER_RCOBSM, 0x00},
357 {R367TER_RCOBSL, 0x00},
358 {R367TER_RCFECSPY, 0x00},
359 {R367TER_RCFSPYCFG, 0x00},
360 {R367TER_RCFSPYDATA, 0x00},
361 {R367TER_RCFSPYOUT, 0x00},
362 {R367TER_RCFSTATUS, 0x00},
363 {R367TER_RCFGOODPACK, 0x00},
364 {R367TER_RCFPACKCNT, 0x00},
365 {R367TER_RCFSPYMISC, 0x00},
366 {R367TER_RCFBERCPT4, 0x00},
367 {R367TER_RCFBERCPT3, 0x00},
368 {R367TER_RCFBERCPT2, 0x00},
369 {R367TER_RCFBERCPT1, 0x00},
370 {R367TER_RCFBERCPT0, 0x00},
371 {R367TER_RCFBERERR2, 0x00},
372 {R367TER_RCFBERERR1, 0x00},
373 {R367TER_RCFBERERR0, 0x00},
374 {R367TER_RCFSTATESM, 0x00},
375 {R367TER_RCFSTATESL, 0x00},
376 {R367TER_RCFSPYBER, 0x00},
377 {R367TER_RCFSPYDISTM, 0x00},
378 {R367TER_RCFSPYDISTL, 0x00},
379 {R367TER_RCFSPYOBS7, 0x00},
380 {R367TER_RCFSPYOBS6, 0x00},
381 {R367TER_RCFSPYOBS5, 0x00},
382 {R367TER_RCFSPYOBS4, 0x00},
383 {R367TER_RCFSPYOBS3, 0x00},
384 {R367TER_RCFSPYOBS2, 0x00},
385 {R367TER_RCFSPYOBS1, 0x00},
386 {R367TER_RCFSPYOBS0, 0x00},
387 {R367TER_TSGENERAL, 0x00},
388 {R367TER_RC1SPEED, 0x6f},
389 {R367TER_TSGSTATUS, 0x18},
390 {R367TER_FECM, 0x01},
391 {R367TER_VTH12, 0xff},
392 {R367TER_VTH23, 0xa1},
393 {R367TER_VTH34, 0x64},
394 {R367TER_VTH56, 0x40},
395 {R367TER_VTH67, 0x00},
396 {R367TER_VTH78, 0x2c},
397 {R367TER_VITCURPUN, 0x12},
398 {R367TER_VERROR, 0x01},
399 {R367TER_PRVIT, 0x3f},
400 {R367TER_VAVSRVIT, 0x00},
401 {R367TER_VSTATUSVIT, 0xbd},
402 {R367TER_VTHINUSE, 0xa1},
403 {R367TER_KDIV12, 0x20},
404 {R367TER_KDIV23, 0x40},
405 {R367TER_KDIV34, 0x20},
406 {R367TER_KDIV56, 0x30},
407 {R367TER_KDIV67, 0x00},
408 {R367TER_KDIV78, 0x30},
409 {R367TER_SIGPOWER, 0x54},
410 {R367TER_DEMAPVIT, 0x40},
411 {R367TER_VITSCALE, 0x00},
412 {R367TER_FFEC1PRG, 0x00},
413 {R367TER_FVITCURPUN, 0x12},
414 {R367TER_FVERROR, 0x01},
415 {R367TER_FVSTATUSVIT, 0xbd},
416 {R367TER_DEBUG_LT1, 0x00},
417 {R367TER_DEBUG_LT2, 0x00},
418 {R367TER_DEBUG_LT3, 0x00},
419 {R367TER_TSTSFMET, 0x00},
420 {R367TER_SELOUT, 0x00},
421 {R367TER_TSYNC, 0x00},
422 {R367TER_TSTERR, 0x00},
423 {R367TER_TSFSYNC, 0x00},
424 {R367TER_TSTSFERR, 0x00},
425 {R367TER_TSTTSSF1, 0x01},
426 {R367TER_TSTTSSF2, 0x1f},
427 {R367TER_TSTTSSF3, 0x00},
428 {R367TER_TSTTS1, 0x00},
429 {R367TER_TSTTS2, 0x1f},
430 {R367TER_TSTTS3, 0x01},
431 {R367TER_TSTTS4, 0x00},
432 {R367TER_TSTTSRC, 0x00},
433 {R367TER_TSTTSRS, 0x00},
434 {R367TER_TSSTATEM, 0xb0},
435 {R367TER_TSSTATEL, 0x40},
436 {R367TER_TSCFGH, 0xC0},
437 {R367TER_TSCFGM, 0xc0},/* for xc5000; was 0x00 */
438 {R367TER_TSCFGL, 0x20},
439 {R367TER_TSSYNC, 0x00},
440 {R367TER_TSINSDELH, 0x00},
441 {R367TER_TSINSDELM, 0x00},
442 {R367TER_TSINSDELL, 0x00},
443 {R367TER_TSDIVN, 0x03},
444 {R367TER_TSDIVPM, 0x00},
445 {R367TER_TSDIVPL, 0x00},
446 {R367TER_TSDIVQM, 0x00},
447 {R367TER_TSDIVQL, 0x00},
448 {R367TER_TSDILSTKM, 0x00},
449 {R367TER_TSDILSTKL, 0x00},
450 {R367TER_TSSPEED, 0x40},/* for xc5000; was 0x6f */
451 {R367TER_TSSTATUS, 0x81},
452 {R367TER_TSSTATUS2, 0x6a},
453 {R367TER_TSBITRATEM, 0x0f},
454 {R367TER_TSBITRATEL, 0xc6},
455 {R367TER_TSPACKLENM, 0x00},
456 {R367TER_TSPACKLENL, 0xfc},
457 {R367TER_TSBLOCLENM, 0x0a},
458 {R367TER_TSBLOCLENL, 0x80},
459 {R367TER_TSDLYH, 0x90},
460 {R367TER_TSDLYM, 0x68},
461 {R367TER_TSDLYL, 0x01},
462 {R367TER_TSNPDAV, 0x00},
463 {R367TER_TSBUFSTATH, 0x00},
464 {R367TER_TSBUFSTATM, 0x00},
465 {R367TER_TSBUFSTATL, 0x00},
466 {R367TER_TSDEBUGM, 0xcf},
467 {R367TER_TSDEBUGL, 0x1e},
468 {R367TER_TSDLYSETH, 0x00},
469 {R367TER_TSDLYSETM, 0x68},
470 {R367TER_TSDLYSETL, 0x00},
471 {R367TER_TSOBSCFG, 0x00},
472 {R367TER_TSOBSM, 0x47},
473 {R367TER_TSOBSL, 0x1f},
474 {R367TER_ERRCTRL1, 0x95},
475 {R367TER_ERRCNT1H, 0x80},
476 {R367TER_ERRCNT1M, 0x00},
477 {R367TER_ERRCNT1L, 0x00},
478 {R367TER_ERRCTRL2, 0x95},
479 {R367TER_ERRCNT2H, 0x00},
480 {R367TER_ERRCNT2M, 0x00},
481 {R367TER_ERRCNT2L, 0x00},
482 {R367TER_FECSPY, 0x88},
483 {R367TER_FSPYCFG, 0x2c},
484 {R367TER_FSPYDATA, 0x3a},
485 {R367TER_FSPYOUT, 0x06},
486 {R367TER_FSTATUS, 0x61},
487 {R367TER_FGOODPACK, 0xff},
488 {R367TER_FPACKCNT, 0xff},
489 {R367TER_FSPYMISC, 0x66},
490 {R367TER_FBERCPT4, 0x00},
491 {R367TER_FBERCPT3, 0x00},
492 {R367TER_FBERCPT2, 0x36},
493 {R367TER_FBERCPT1, 0x36},
494 {R367TER_FBERCPT0, 0x14},
495 {R367TER_FBERERR2, 0x00},
496 {R367TER_FBERERR1, 0x03},
497 {R367TER_FBERERR0, 0x28},
498 {R367TER_FSTATESM, 0x00},
499 {R367TER_FSTATESL, 0x02},
500 {R367TER_FSPYBER, 0x00},
501 {R367TER_FSPYDISTM, 0x01},
502 {R367TER_FSPYDISTL, 0x9f},
503 {R367TER_FSPYOBS7, 0xc9},
504 {R367TER_FSPYOBS6, 0x99},
505 {R367TER_FSPYOBS5, 0x08},
506 {R367TER_FSPYOBS4, 0xec},
507 {R367TER_FSPYOBS3, 0x01},
508 {R367TER_FSPYOBS2, 0x0f},
509 {R367TER_FSPYOBS1, 0xf5},
510 {R367TER_FSPYOBS0, 0x08},
511 {R367TER_SFDEMAP, 0x40},
512 {R367TER_SFERROR, 0x00},
513 {R367TER_SFAVSR, 0x30},
514 {R367TER_SFECSTATUS, 0xcc},
515 {R367TER_SFKDIV12, 0x20},
516 {R367TER_SFKDIV23, 0x40},
517 {R367TER_SFKDIV34, 0x20},
518 {R367TER_SFKDIV56, 0x20},
519 {R367TER_SFKDIV67, 0x00},
520 {R367TER_SFKDIV78, 0x20},
521 {R367TER_SFDILSTKM, 0x00},
522 {R367TER_SFDILSTKL, 0x00},
523 {R367TER_SFSTATUS, 0xb5},
524 {R367TER_SFDLYH, 0x90},
525 {R367TER_SFDLYM, 0x60},
526 {R367TER_SFDLYL, 0x01},
527 {R367TER_SFDLYSETH, 0xc0},
528 {R367TER_SFDLYSETM, 0x60},
529 {R367TER_SFDLYSETL, 0x00},
530 {R367TER_SFOBSCFG, 0x00},
531 {R367TER_SFOBSM, 0x47},
532 {R367TER_SFOBSL, 0x05},
533 {R367TER_SFECINFO, 0x40},
534 {R367TER_SFERRCTRL, 0x74},
535 {R367TER_SFERRCNTH, 0x80},
536 {R367TER_SFERRCNTM , 0x00},
537 {R367TER_SFERRCNTL, 0x00},
538 {R367TER_SYMBRATEM, 0x2f},
539 {R367TER_SYMBRATEL, 0x50},
540 {R367TER_SYMBSTATUS, 0x7f},
541 {R367TER_SYMBCFG, 0x00},
542 {R367TER_SYMBFIFOM, 0xf4},
543 {R367TER_SYMBFIFOL, 0x0d},
544 {R367TER_SYMBOFFSM, 0xf0},
545 {R367TER_SYMBOFFSL, 0x2d},
546 {R367TER_DEBUG_LT4, 0x00},
547 {R367TER_DEBUG_LT5, 0x00},
548 {R367TER_DEBUG_LT6, 0x00},
549 {R367TER_DEBUG_LT7, 0x00},
550 {R367TER_DEBUG_LT8, 0x00},
551 {R367TER_DEBUG_LT9, 0x00},
552 };
553
554 #define RF_LOOKUP_TABLE_SIZE 31
555 #define RF_LOOKUP_TABLE2_SIZE 16
556 /* RF Level (for RF AGC->AGC1) Lookup Table, depends on the board and tuner.*/
557 s32 stv0367cab_RF_LookUp1[RF_LOOKUP_TABLE_SIZE][RF_LOOKUP_TABLE_SIZE] = {
558 {/*AGC1*/
559 48, 50, 51, 53, 54, 56, 57, 58, 60, 61, 62, 63,
560 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
561 76, 77, 78, 80, 83, 85, 88,
562 }, {/*RF(dbm)*/
563 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
564 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 46, 47,
565 49, 50, 52, 53, 54, 55, 56,
566 }
567 };
568 /* RF Level (for IF AGC->AGC2) Lookup Table, depends on the board and tuner.*/
569 s32 stv0367cab_RF_LookUp2[RF_LOOKUP_TABLE2_SIZE][RF_LOOKUP_TABLE2_SIZE] = {
570 {/*AGC2*/
571 28, 29, 31, 32, 34, 35, 36, 37,
572 38, 39, 40, 41, 42, 43, 44, 45,
573 }, {/*RF(dbm)*/
574 57, 58, 59, 60, 61, 62, 63, 64,
575 65, 66, 67, 68, 69, 70, 71, 72,
576 }
577 };
578
579 static struct st_register def0367cab[STV0367CAB_NBREGS] = {
580 {R367CAB_ID, 0x60},
581 {R367CAB_I2CRPT, 0xa0},
582 /*{R367CAB_I2CRPT, 0x22},*/
583 {R367CAB_TOPCTRL, 0x10},
584 {R367CAB_IOCFG0, 0x80},
585 {R367CAB_DAC0R, 0x00},
586 {R367CAB_IOCFG1, 0x00},
587 {R367CAB_DAC1R, 0x00},
588 {R367CAB_IOCFG2, 0x00},
589 {R367CAB_SDFR, 0x00},
590 {R367CAB_AUX_CLK, 0x00},
591 {R367CAB_FREESYS1, 0x00},
592 {R367CAB_FREESYS2, 0x00},
593 {R367CAB_FREESYS3, 0x00},
594 {R367CAB_GPIO_CFG, 0x55},
595 {R367CAB_GPIO_CMD, 0x01},
596 {R367CAB_TSTRES, 0x00},
597 {R367CAB_ANACTRL, 0x0d},/* was 0x00 need to check - I.M.L.*/
598 {R367CAB_TSTBUS, 0x00},
599 {R367CAB_RF_AGC1, 0xea},
600 {R367CAB_RF_AGC2, 0x82},
601 {R367CAB_ANADIGCTRL, 0x0b},
602 {R367CAB_PLLMDIV, 0x01},
603 {R367CAB_PLLNDIV, 0x08},
604 {R367CAB_PLLSETUP, 0x18},
605 {R367CAB_DUAL_AD12, 0x0C}, /* for xc5000 AGC voltage 1.6V */
606 {R367CAB_TSTBIST, 0x00},
607 {R367CAB_CTRL_1, 0x00},
608 {R367CAB_CTRL_2, 0x03},
609 {R367CAB_IT_STATUS1, 0x2b},
610 {R367CAB_IT_STATUS2, 0x08},
611 {R367CAB_IT_EN1, 0x00},
612 {R367CAB_IT_EN2, 0x00},
613 {R367CAB_CTRL_STATUS, 0x04},
614 {R367CAB_TEST_CTL, 0x00},
615 {R367CAB_AGC_CTL, 0x73},
616 {R367CAB_AGC_IF_CFG, 0x50},
617 {R367CAB_AGC_RF_CFG, 0x00},
618 {R367CAB_AGC_PWM_CFG, 0x03},
619 {R367CAB_AGC_PWR_REF_L, 0x5a},
620 {R367CAB_AGC_PWR_REF_H, 0x00},
621 {R367CAB_AGC_RF_TH_L, 0xff},
622 {R367CAB_AGC_RF_TH_H, 0x07},
623 {R367CAB_AGC_IF_LTH_L, 0x00},
624 {R367CAB_AGC_IF_LTH_H, 0x08},
625 {R367CAB_AGC_IF_HTH_L, 0xff},
626 {R367CAB_AGC_IF_HTH_H, 0x07},
627 {R367CAB_AGC_PWR_RD_L, 0xa0},
628 {R367CAB_AGC_PWR_RD_M, 0xe9},
629 {R367CAB_AGC_PWR_RD_H, 0x03},
630 {R367CAB_AGC_PWM_IFCMD_L, 0xe4},
631 {R367CAB_AGC_PWM_IFCMD_H, 0x00},
632 {R367CAB_AGC_PWM_RFCMD_L, 0xff},
633 {R367CAB_AGC_PWM_RFCMD_H, 0x07},
634 {R367CAB_IQDEM_CFG, 0x01},
635 {R367CAB_MIX_NCO_LL, 0x22},
636 {R367CAB_MIX_NCO_HL, 0x96},
637 {R367CAB_MIX_NCO_HH, 0x55},
638 {R367CAB_SRC_NCO_LL, 0xff},
639 {R367CAB_SRC_NCO_LH, 0x0c},
640 {R367CAB_SRC_NCO_HL, 0xf5},
641 {R367CAB_SRC_NCO_HH, 0x20},
642 {R367CAB_IQDEM_GAIN_SRC_L, 0x06},
643 {R367CAB_IQDEM_GAIN_SRC_H, 0x01},
644 {R367CAB_IQDEM_DCRM_CFG_LL, 0xfe},
645 {R367CAB_IQDEM_DCRM_CFG_LH, 0xff},
646 {R367CAB_IQDEM_DCRM_CFG_HL, 0x0f},
647 {R367CAB_IQDEM_DCRM_CFG_HH, 0x00},
648 {R367CAB_IQDEM_ADJ_COEFF0, 0x34},
649 {R367CAB_IQDEM_ADJ_COEFF1, 0xae},
650 {R367CAB_IQDEM_ADJ_COEFF2, 0x46},
651 {R367CAB_IQDEM_ADJ_COEFF3, 0x77},
652 {R367CAB_IQDEM_ADJ_COEFF4, 0x96},
653 {R367CAB_IQDEM_ADJ_COEFF5, 0x69},
654 {R367CAB_IQDEM_ADJ_COEFF6, 0xc7},
655 {R367CAB_IQDEM_ADJ_COEFF7, 0x01},
656 {R367CAB_IQDEM_ADJ_EN, 0x04},
657 {R367CAB_IQDEM_ADJ_AGC_REF, 0x94},
658 {R367CAB_ALLPASSFILT1, 0xc9},
659 {R367CAB_ALLPASSFILT2, 0x2d},
660 {R367CAB_ALLPASSFILT3, 0xa3},
661 {R367CAB_ALLPASSFILT4, 0xfb},
662 {R367CAB_ALLPASSFILT5, 0xf6},
663 {R367CAB_ALLPASSFILT6, 0x45},
664 {R367CAB_ALLPASSFILT7, 0x6f},
665 {R367CAB_ALLPASSFILT8, 0x7e},
666 {R367CAB_ALLPASSFILT9, 0x05},
667 {R367CAB_ALLPASSFILT10, 0x0a},
668 {R367CAB_ALLPASSFILT11, 0x51},
669 {R367CAB_TRL_AGC_CFG, 0x20},
670 {R367CAB_TRL_LPF_CFG, 0x28},
671 {R367CAB_TRL_LPF_ACQ_GAIN, 0x44},
672 {R367CAB_TRL_LPF_TRK_GAIN, 0x22},
673 {R367CAB_TRL_LPF_OUT_GAIN, 0x03},
674 {R367CAB_TRL_LOCKDET_LTH, 0x04},
675 {R367CAB_TRL_LOCKDET_HTH, 0x11},
676 {R367CAB_TRL_LOCKDET_TRGVAL, 0x20},
677 {R367CAB_IQ_QAM, 0x01},
678 {R367CAB_FSM_STATE, 0xa0},
679 {R367CAB_FSM_CTL, 0x08},
680 {R367CAB_FSM_STS, 0x0c},
681 {R367CAB_FSM_SNR0_HTH, 0x00},
682 {R367CAB_FSM_SNR1_HTH, 0x00},
683 {R367CAB_FSM_SNR2_HTH, 0x23},/* 0x00 */
684 {R367CAB_FSM_SNR0_LTH, 0x00},
685 {R367CAB_FSM_SNR1_LTH, 0x00},
686 {R367CAB_FSM_EQA1_HTH, 0x00},
687 {R367CAB_FSM_TEMPO, 0x32},
688 {R367CAB_FSM_CONFIG, 0x03},
689 {R367CAB_EQU_I_TESTTAP_L, 0x11},
690 {R367CAB_EQU_I_TESTTAP_M, 0x00},
691 {R367CAB_EQU_I_TESTTAP_H, 0x00},
692 {R367CAB_EQU_TESTAP_CFG, 0x00},
693 {R367CAB_EQU_Q_TESTTAP_L, 0xff},
694 {R367CAB_EQU_Q_TESTTAP_M, 0x00},
695 {R367CAB_EQU_Q_TESTTAP_H, 0x00},
696 {R367CAB_EQU_TAP_CTRL, 0x00},
697 {R367CAB_EQU_CTR_CRL_CONTROL_L, 0x11},
698 {R367CAB_EQU_CTR_CRL_CONTROL_H, 0x05},
699 {R367CAB_EQU_CTR_HIPOW_L, 0x00},
700 {R367CAB_EQU_CTR_HIPOW_H, 0x00},
701 {R367CAB_EQU_I_EQU_LO, 0xef},
702 {R367CAB_EQU_I_EQU_HI, 0x00},
703 {R367CAB_EQU_Q_EQU_LO, 0xee},
704 {R367CAB_EQU_Q_EQU_HI, 0x00},
705 {R367CAB_EQU_MAPPER, 0xc5},
706 {R367CAB_EQU_SWEEP_RATE, 0x80},
707 {R367CAB_EQU_SNR_LO, 0x64},
708 {R367CAB_EQU_SNR_HI, 0x03},
709 {R367CAB_EQU_GAMMA_LO, 0x00},
710 {R367CAB_EQU_GAMMA_HI, 0x00},
711 {R367CAB_EQU_ERR_GAIN, 0x36},
712 {R367CAB_EQU_RADIUS, 0xaa},
713 {R367CAB_EQU_FFE_MAINTAP, 0x00},
714 {R367CAB_EQU_FFE_LEAKAGE, 0x63},
715 {R367CAB_EQU_FFE_MAINTAP_POS, 0xdf},
716 {R367CAB_EQU_GAIN_WIDE, 0x88},
717 {R367CAB_EQU_GAIN_NARROW, 0x41},
718 {R367CAB_EQU_CTR_LPF_GAIN, 0xd1},
719 {R367CAB_EQU_CRL_LPF_GAIN, 0xa7},
720 {R367CAB_EQU_GLOBAL_GAIN, 0x06},
721 {R367CAB_EQU_CRL_LD_SEN, 0x85},
722 {R367CAB_EQU_CRL_LD_VAL, 0xe2},
723 {R367CAB_EQU_CRL_TFR, 0x20},
724 {R367CAB_EQU_CRL_BISTH_LO, 0x00},
725 {R367CAB_EQU_CRL_BISTH_HI, 0x00},
726 {R367CAB_EQU_SWEEP_RANGE_LO, 0x00},
727 {R367CAB_EQU_SWEEP_RANGE_HI, 0x00},
728 {R367CAB_EQU_CRL_LIMITER, 0x40},
729 {R367CAB_EQU_MODULUS_MAP, 0x90},
730 {R367CAB_EQU_PNT_GAIN, 0xa7},
731 {R367CAB_FEC_AC_CTR_0, 0x16},
732 {R367CAB_FEC_AC_CTR_1, 0x0b},
733 {R367CAB_FEC_AC_CTR_2, 0x88},
734 {R367CAB_FEC_AC_CTR_3, 0x02},
735 {R367CAB_FEC_STATUS, 0x12},
736 {R367CAB_RS_COUNTER_0, 0x7d},
737 {R367CAB_RS_COUNTER_1, 0xd0},
738 {R367CAB_RS_COUNTER_2, 0x19},
739 {R367CAB_RS_COUNTER_3, 0x0b},
740 {R367CAB_RS_COUNTER_4, 0xa3},
741 {R367CAB_RS_COUNTER_5, 0x00},
742 {R367CAB_BERT_0, 0x01},
743 {R367CAB_BERT_1, 0x25},
744 {R367CAB_BERT_2, 0x41},
745 {R367CAB_BERT_3, 0x39},
746 {R367CAB_OUTFORMAT_0, 0xc2},
747 {R367CAB_OUTFORMAT_1, 0x22},
748 {R367CAB_SMOOTHER_2, 0x28},
749 {R367CAB_TSMF_CTRL_0, 0x01},
750 {R367CAB_TSMF_CTRL_1, 0xc6},
751 {R367CAB_TSMF_CTRL_3, 0x43},
752 {R367CAB_TS_ON_ID_0, 0x00},
753 {R367CAB_TS_ON_ID_1, 0x00},
754 {R367CAB_TS_ON_ID_2, 0x00},
755 {R367CAB_TS_ON_ID_3, 0x00},
756 {R367CAB_RE_STATUS_0, 0x00},
757 {R367CAB_RE_STATUS_1, 0x00},
758 {R367CAB_RE_STATUS_2, 0x00},
759 {R367CAB_RE_STATUS_3, 0x00},
760 {R367CAB_TS_STATUS_0, 0x00},
761 {R367CAB_TS_STATUS_1, 0x00},
762 {R367CAB_TS_STATUS_2, 0xa0},
763 {R367CAB_TS_STATUS_3, 0x00},
764 {R367CAB_T_O_ID_0, 0x00},
765 {R367CAB_T_O_ID_1, 0x00},
766 {R367CAB_T_O_ID_2, 0x00},
767 {R367CAB_T_O_ID_3, 0x00},
768 };
769
770 static
771 int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len)
772 {
773 u8 buf[MAX_XFER_SIZE];
774 struct i2c_msg msg = {
775 .addr = state->config->demod_address,
776 .flags = 0,
777 .buf = buf,
778 .len = len + 2
779 };
780 int ret;
781
782 if (2 + len > sizeof(buf)) {
783 printk(KERN_WARNING
784 "%s: i2c wr reg=%04x: len=%d is too big!\n",
785 KBUILD_MODNAME, reg, len);
786 return -EINVAL;
787 }
788
789
790 buf[0] = MSB(reg);
791 buf[1] = LSB(reg);
792 memcpy(buf + 2, data, len);
793
794 if (i2cdebug)
795 printk(KERN_DEBUG "%s: %02x: %02x\n", __func__, reg, buf[2]);
796
797 ret = i2c_transfer(state->i2c, &msg, 1);
798 if (ret != 1)
799 printk(KERN_ERR "%s: i2c write error!\n", __func__);
800
801 return (ret != 1) ? -EREMOTEIO : 0;
802 }
803
804 static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data)
805 {
806 return stv0367_writeregs(state, reg, &data, 1);
807 }
808
809 static u8 stv0367_readreg(struct stv0367_state *state, u16 reg)
810 {
811 u8 b0[] = { 0, 0 };
812 u8 b1[] = { 0 };
813 struct i2c_msg msg[] = {
814 {
815 .addr = state->config->demod_address,
816 .flags = 0,
817 .buf = b0,
818 .len = 2
819 }, {
820 .addr = state->config->demod_address,
821 .flags = I2C_M_RD,
822 .buf = b1,
823 .len = 1
824 }
825 };
826 int ret;
827
828 b0[0] = MSB(reg);
829 b0[1] = LSB(reg);
830
831 ret = i2c_transfer(state->i2c, msg, 2);
832 if (ret != 2)
833 printk(KERN_ERR "%s: i2c read error\n", __func__);
834
835 if (i2cdebug)
836 printk(KERN_DEBUG "%s: %02x: %02x\n", __func__, reg, b1[0]);
837
838 return b1[0];
839 }
840
841 static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
842 {
843 u8 position = 0, i = 0;
844
845 (*mask) = label & 0xff;
846
847 while ((position == 0) && (i < 8)) {
848 position = ((*mask) >> i) & 0x01;
849 i++;
850 }
851
852 (*pos) = (i - 1);
853 }
854
855 static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val)
856 {
857 u8 reg, mask, pos;
858
859 reg = stv0367_readreg(state, (label >> 16) & 0xffff);
860 extract_mask_pos(label, &mask, &pos);
861
862 val = mask & (val << pos);
863
864 reg = (reg & (~mask)) | val;
865 stv0367_writereg(state, (label >> 16) & 0xffff, reg);
866
867 }
868
869 static void stv0367_setbits(u8 *reg, u32 label, u8 val)
870 {
871 u8 mask, pos;
872
873 extract_mask_pos(label, &mask, &pos);
874
875 val = mask & (val << pos);
876
877 (*reg) = ((*reg) & (~mask)) | val;
878 }
879
880 static u8 stv0367_readbits(struct stv0367_state *state, u32 label)
881 {
882 u8 val = 0xff;
883 u8 mask, pos;
884
885 extract_mask_pos(label, &mask, &pos);
886
887 val = stv0367_readreg(state, label >> 16);
888 val = (val & mask) >> pos;
889
890 return val;
891 }
892
893 #if 0 /* Currently, unused */
894 static u8 stv0367_getbits(u8 reg, u32 label)
895 {
896 u8 mask, pos;
897
898 extract_mask_pos(label, &mask, &pos);
899
900 return (reg & mask) >> pos;
901 }
902 #endif
903 static int stv0367ter_gate_ctrl(struct dvb_frontend *fe, int enable)
904 {
905 struct stv0367_state *state = fe->demodulator_priv;
906 u8 tmp = stv0367_readreg(state, R367TER_I2CRPT);
907
908 dprintk("%s:\n", __func__);
909
910 if (enable) {
911 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 0);
912 stv0367_setbits(&tmp, F367TER_I2CT_ON, 1);
913 } else {
914 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 1);
915 stv0367_setbits(&tmp, F367TER_I2CT_ON, 0);
916 }
917
918 stv0367_writereg(state, R367TER_I2CRPT, tmp);
919
920 return 0;
921 }
922
923 static u32 stv0367_get_tuner_freq(struct dvb_frontend *fe)
924 {
925 struct dvb_frontend_ops *frontend_ops = &fe->ops;
926 struct dvb_tuner_ops *tuner_ops = &frontend_ops->tuner_ops;
927 u32 freq = 0;
928 int err = 0;
929
930 dprintk("%s:\n", __func__);
931
932 if (tuner_ops->get_frequency) {
933 err = tuner_ops->get_frequency(fe, &freq);
934 if (err < 0) {
935 printk(KERN_ERR "%s: Invalid parameter\n", __func__);
936 return err;
937 }
938
939 dprintk("%s: frequency=%d\n", __func__, freq);
940
941 } else
942 return -1;
943
944 return freq;
945 }
946
947 static u16 CellsCoeffs_8MHz_367cofdm[3][6][5] = {
948 {
949 {0x10EF, 0xE205, 0x10EF, 0xCE49, 0x6DA7}, /* CELL 1 COEFFS 27M*/
950 {0x2151, 0xc557, 0x2151, 0xc705, 0x6f93}, /* CELL 2 COEFFS */
951 {0x2503, 0xc000, 0x2503, 0xc375, 0x7194}, /* CELL 3 COEFFS */
952 {0x20E9, 0xca94, 0x20e9, 0xc153, 0x7194}, /* CELL 4 COEFFS */
953 {0x06EF, 0xF852, 0x06EF, 0xC057, 0x7207}, /* CELL 5 COEFFS */
954 {0x0000, 0x0ECC, 0x0ECC, 0x0000, 0x3647} /* CELL 6 COEFFS */
955 }, {
956 {0x10A0, 0xE2AF, 0x10A1, 0xCE76, 0x6D6D}, /* CELL 1 COEFFS 25M*/
957 {0x20DC, 0xC676, 0x20D9, 0xC80A, 0x6F29},
958 {0x2532, 0xC000, 0x251D, 0xC391, 0x706F},
959 {0x1F7A, 0xCD2B, 0x2032, 0xC15E, 0x711F},
960 {0x0698, 0xFA5E, 0x0568, 0xC059, 0x7193},
961 {0x0000, 0x0918, 0x149C, 0x0000, 0x3642} /* CELL 6 COEFFS */
962 }, {
963 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
964 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
965 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
966 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
967 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
968 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
969 }
970 };
971
972 static u16 CellsCoeffs_7MHz_367cofdm[3][6][5] = {
973 {
974 {0x12CA, 0xDDAF, 0x12CA, 0xCCEB, 0x6FB1}, /* CELL 1 COEFFS 27M*/
975 {0x2329, 0xC000, 0x2329, 0xC6B0, 0x725F}, /* CELL 2 COEFFS */
976 {0x2394, 0xC000, 0x2394, 0xC2C7, 0x7410}, /* CELL 3 COEFFS */
977 {0x251C, 0xC000, 0x251C, 0xC103, 0x74D9}, /* CELL 4 COEFFS */
978 {0x0804, 0xF546, 0x0804, 0xC040, 0x7544}, /* CELL 5 COEFFS */
979 {0x0000, 0x0CD9, 0x0CD9, 0x0000, 0x370A} /* CELL 6 COEFFS */
980 }, {
981 {0x1285, 0xDE47, 0x1285, 0xCD17, 0x6F76}, /*25M*/
982 {0x234C, 0xC000, 0x2348, 0xC6DA, 0x7206},
983 {0x23B4, 0xC000, 0x23AC, 0xC2DB, 0x73B3},
984 {0x253D, 0xC000, 0x25B6, 0xC10B, 0x747F},
985 {0x0721, 0xF79C, 0x065F, 0xC041, 0x74EB},
986 {0x0000, 0x08FA, 0x1162, 0x0000, 0x36FF}
987 }, {
988 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
989 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
990 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
991 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
992 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
993 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
994 }
995 };
996
997 static u16 CellsCoeffs_6MHz_367cofdm[3][6][5] = {
998 {
999 {0x1699, 0xD5B8, 0x1699, 0xCBC3, 0x713B}, /* CELL 1 COEFFS 27M*/
1000 {0x2245, 0xC000, 0x2245, 0xC568, 0x74D5}, /* CELL 2 COEFFS */
1001 {0x227F, 0xC000, 0x227F, 0xC1FC, 0x76C6}, /* CELL 3 COEFFS */
1002 {0x235E, 0xC000, 0x235E, 0xC0A7, 0x778A}, /* CELL 4 COEFFS */
1003 {0x0ECB, 0xEA0B, 0x0ECB, 0xC027, 0x77DD}, /* CELL 5 COEFFS */
1004 {0x0000, 0x0B68, 0x0B68, 0x0000, 0xC89A}, /* CELL 6 COEFFS */
1005 }, {
1006 {0x1655, 0xD64E, 0x1658, 0xCBEF, 0x70FE}, /*25M*/
1007 {0x225E, 0xC000, 0x2256, 0xC589, 0x7489},
1008 {0x2293, 0xC000, 0x2295, 0xC209, 0x767E},
1009 {0x2377, 0xC000, 0x23AA, 0xC0AB, 0x7746},
1010 {0x0DC7, 0xEBC8, 0x0D07, 0xC027, 0x7799},
1011 {0x0000, 0x0888, 0x0E9C, 0x0000, 0x3757}
1012
1013 }, {
1014 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
1015 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1016 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1017 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1018 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1019 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
1020 }
1021 };
1022
1023 static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz)
1024 {
1025 u32 mclk_Hz = 0; /* master clock frequency (Hz) */
1026 u32 m, n, p;
1027
1028 dprintk("%s:\n", __func__);
1029
1030 if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) {
1031 n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV);
1032 if (n == 0)
1033 n = n + 1;
1034
1035 m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV);
1036 if (m == 0)
1037 m = m + 1;
1038
1039 p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV);
1040 if (p > 5)
1041 p = 5;
1042
1043 mclk_Hz = ((ExtClk_Hz / 2) * n) / (m * (1 << p));
1044
1045 dprintk("N=%d M=%d P=%d mclk_Hz=%d ExtClk_Hz=%d\n",
1046 n, m, p, mclk_Hz, ExtClk_Hz);
1047 } else
1048 mclk_Hz = ExtClk_Hz;
1049
1050 dprintk("%s: mclk_Hz=%d\n", __func__, mclk_Hz);
1051
1052 return mclk_Hz;
1053 }
1054
1055 static int stv0367ter_filt_coeff_init(struct stv0367_state *state,
1056 u16 CellsCoeffs[3][6][5], u32 DemodXtal)
1057 {
1058 int i, j, k, freq;
1059
1060 dprintk("%s:\n", __func__);
1061
1062 freq = stv0367ter_get_mclk(state, DemodXtal);
1063
1064 if (freq == 53125000)
1065 k = 1; /* equivalent to Xtal 25M on 362*/
1066 else if (freq == 54000000)
1067 k = 0; /* equivalent to Xtal 27M on 362*/
1068 else if (freq == 52500000)
1069 k = 2; /* equivalent to Xtal 30M on 362*/
1070 else
1071 return 0;
1072
1073 for (i = 1; i <= 6; i++) {
1074 stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1);
1075
1076 for (j = 1; j <= 5; j++) {
1077 stv0367_writereg(state,
1078 (R367TER_IIRCX_COEFF1_MSB + 2 * (j - 1)),
1079 MSB(CellsCoeffs[k][i-1][j-1]));
1080 stv0367_writereg(state,
1081 (R367TER_IIRCX_COEFF1_LSB + 2 * (j - 1)),
1082 LSB(CellsCoeffs[k][i-1][j-1]));
1083 }
1084 }
1085
1086 return 1;
1087
1088 }
1089
1090 static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state)
1091 {
1092 dprintk("%s:\n", __func__);
1093
1094 stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00);
1095
1096 /* Lock detect 1 */
1097 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00);
1098 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
1099 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
1100
1101 /* Lock detect 2 */
1102 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01);
1103 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
1104 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
1105
1106 /* Lock detect 3 */
1107 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02);
1108 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
1109 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
1110
1111 /* Lock detect 4 */
1112 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03);
1113 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
1114 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
1115
1116 }
1117
1118 static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth,
1119 u32 DemodXtalValue)
1120 {
1121 dprintk("%s:\n", __func__);
1122
1123 stv0367_writebits(state, F367TER_NRST_IIR, 0);
1124
1125 switch (Bandwidth) {
1126 case 6:
1127 if (!stv0367ter_filt_coeff_init(state,
1128 CellsCoeffs_6MHz_367cofdm,
1129 DemodXtalValue))
1130 return 0;
1131 break;
1132 case 7:
1133 if (!stv0367ter_filt_coeff_init(state,
1134 CellsCoeffs_7MHz_367cofdm,
1135 DemodXtalValue))
1136 return 0;
1137 break;
1138 case 8:
1139 if (!stv0367ter_filt_coeff_init(state,
1140 CellsCoeffs_8MHz_367cofdm,
1141 DemodXtalValue))
1142 return 0;
1143 break;
1144 default:
1145 return 0;
1146 }
1147
1148 stv0367_writebits(state, F367TER_NRST_IIR, 1);
1149
1150 return 1;
1151 }
1152
1153 static void stv0367ter_agc_iir_rst(struct stv0367_state *state)
1154 {
1155
1156 u8 com_n;
1157
1158 dprintk("%s:\n", __func__);
1159
1160 com_n = stv0367_readbits(state, F367TER_COM_N);
1161
1162 stv0367_writebits(state, F367TER_COM_N, 0x07);
1163
1164 stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00);
1165 stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00);
1166
1167 stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01);
1168 stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01);
1169
1170 stv0367_writebits(state, F367TER_COM_N, com_n);
1171
1172 }
1173
1174 static int stv0367ter_duration(s32 mode, int tempo1, int tempo2, int tempo3)
1175 {
1176 int local_tempo = 0;
1177 switch (mode) {
1178 case 0:
1179 local_tempo = tempo1;
1180 break;
1181 case 1:
1182 local_tempo = tempo2;
1183 break ;
1184
1185 case 2:
1186 local_tempo = tempo3;
1187 break;
1188
1189 default:
1190 break;
1191 }
1192 /* msleep(local_tempo); */
1193 return local_tempo;
1194 }
1195
1196 static enum
1197 stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state)
1198 {
1199 int wd = 100;
1200 unsigned short int SYR_var;
1201 s32 SYRStatus;
1202
1203 dprintk("%s:\n", __func__);
1204
1205 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
1206
1207 while ((!SYR_var) && (wd > 0)) {
1208 usleep_range(2000, 3000);
1209 wd -= 2;
1210 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
1211 }
1212
1213 if (!SYR_var)
1214 SYRStatus = FE_TER_NOSYMBOL;
1215 else
1216 SYRStatus = FE_TER_SYMBOLOK;
1217
1218 dprintk("stv0367ter_check_syr SYRStatus %s\n",
1219 SYR_var == 0 ? "No Symbol" : "OK");
1220
1221 return SYRStatus;
1222 }
1223
1224 static enum
1225 stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state,
1226 s32 FFTmode)
1227 {
1228
1229 s32 CPAMPvalue = 0, CPAMPStatus, CPAMPMin;
1230 int wd = 0;
1231
1232 dprintk("%s:\n", __func__);
1233
1234 switch (FFTmode) {
1235 case 0: /*2k mode*/
1236 CPAMPMin = 20;
1237 wd = 10;
1238 break;
1239 case 1: /*8k mode*/
1240 CPAMPMin = 80;
1241 wd = 55;
1242 break;
1243 case 2: /*4k mode*/
1244 CPAMPMin = 40;
1245 wd = 30;
1246 break;
1247 default:
1248 CPAMPMin = 0xffff; /*drives to NOCPAMP */
1249 break;
1250 }
1251
1252 dprintk("%s: CPAMPMin=%d wd=%d\n", __func__, CPAMPMin, wd);
1253
1254 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
1255 while ((CPAMPvalue < CPAMPMin) && (wd > 0)) {
1256 usleep_range(1000, 2000);
1257 wd -= 1;
1258 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
1259 /*dprintk("CPAMPvalue= %d at wd=%d\n",CPAMPvalue,wd); */
1260 }
1261 dprintk("******last CPAMPvalue= %d at wd=%d\n", CPAMPvalue, wd);
1262 if (CPAMPvalue < CPAMPMin) {
1263 CPAMPStatus = FE_TER_NOCPAMP;
1264 printk(KERN_ERR "CPAMP failed\n");
1265 } else {
1266 printk(KERN_ERR "CPAMP OK !\n");
1267 CPAMPStatus = FE_TER_CPAMPOK;
1268 }
1269
1270 return CPAMPStatus;
1271 }
1272
1273 static enum stv0367_ter_signal_type
1274 stv0367ter_lock_algo(struct stv0367_state *state)
1275 {
1276 enum stv0367_ter_signal_type ret_flag;
1277 short int wd, tempo;
1278 u8 try, u_var1 = 0, u_var2 = 0, u_var3 = 0, u_var4 = 0, mode, guard;
1279 u8 tmp, tmp2;
1280
1281 dprintk("%s:\n", __func__);
1282
1283 if (state == NULL)
1284 return FE_TER_SWNOK;
1285
1286 try = 0;
1287 do {
1288 ret_flag = FE_TER_LOCKOK;
1289
1290 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1291
1292 if (state->config->if_iq_mode != 0)
1293 stv0367_writebits(state, F367TER_COM_N, 0x07);
1294
1295 stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */
1296 stv0367_writebits(state, F367TER_MODE, 0);
1297 stv0367_writebits(state, F367TER_SYR_TR_DIS, 0);
1298 usleep_range(5000, 10000);
1299
1300 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1301
1302
1303 if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL)
1304 return FE_TER_NOSYMBOL;
1305 else { /*
1306 if chip locked on wrong mode first try,
1307 it must lock correctly second try */
1308 mode = stv0367_readbits(state, F367TER_SYR_MODE);
1309 if (stv0367ter_check_cpamp(state, mode) ==
1310 FE_TER_NOCPAMP) {
1311 if (try == 0)
1312 ret_flag = FE_TER_NOCPAMP;
1313
1314 }
1315 }
1316
1317 try++;
1318 } while ((try < 10) && (ret_flag != FE_TER_LOCKOK));
1319
1320 tmp = stv0367_readreg(state, R367TER_SYR_STAT);
1321 tmp2 = stv0367_readreg(state, R367TER_STATUS);
1322 dprintk("state=%p\n", state);
1323 dprintk("LOCK OK! mode=%d SYR_STAT=0x%x R367TER_STATUS=0x%x\n",
1324 mode, tmp, tmp2);
1325
1326 tmp = stv0367_readreg(state, R367TER_PRVIT);
1327 tmp2 = stv0367_readreg(state, R367TER_I2CRPT);
1328 dprintk("PRVIT=0x%x I2CRPT=0x%x\n", tmp, tmp2);
1329
1330 tmp = stv0367_readreg(state, R367TER_GAIN_SRC1);
1331 dprintk("GAIN_SRC1=0x%x\n", tmp);
1332
1333 if ((mode != 0) && (mode != 1) && (mode != 2))
1334 return FE_TER_SWNOK;
1335
1336 /*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */
1337
1338 /*suppress EPQ auto for SYR_GARD 1/16 or 1/32
1339 and set channel predictor in automatic */
1340 #if 0
1341 switch (guard) {
1342
1343 case 0:
1344 case 1:
1345 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
1346 stv0367_writereg(state, R367TER_CHC_CTL, 0x01);
1347 break;
1348 case 2:
1349 case 3:
1350 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
1351 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
1352 break;
1353
1354 default:
1355 return FE_TER_SWNOK;
1356 }
1357 #endif
1358
1359 /*reset fec an reedsolo FOR 367 only*/
1360 stv0367_writebits(state, F367TER_RST_SFEC, 1);
1361 stv0367_writebits(state, F367TER_RST_REEDSOLO, 1);
1362 usleep_range(1000, 2000);
1363 stv0367_writebits(state, F367TER_RST_SFEC, 0);
1364 stv0367_writebits(state, F367TER_RST_REEDSOLO, 0);
1365
1366 u_var1 = stv0367_readbits(state, F367TER_LK);
1367 u_var2 = stv0367_readbits(state, F367TER_PRF);
1368 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
1369 /* u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */
1370
1371 wd = stv0367ter_duration(mode, 125, 500, 250);
1372 tempo = stv0367ter_duration(mode, 4, 16, 8);
1373
1374 /*while ( ((!u_var1)||(!u_var2)||(!u_var3)||(!u_var4)) && (wd>=0)) */
1375 while (((!u_var1) || (!u_var2) || (!u_var3)) && (wd >= 0)) {
1376 usleep_range(1000 * tempo, 1000 * (tempo + 1));
1377 wd -= tempo;
1378 u_var1 = stv0367_readbits(state, F367TER_LK);
1379 u_var2 = stv0367_readbits(state, F367TER_PRF);
1380 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
1381 /*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */
1382 }
1383
1384 if (!u_var1)
1385 return FE_TER_NOLOCK;
1386
1387
1388 if (!u_var2)
1389 return FE_TER_NOPRFOUND;
1390
1391 if (!u_var3)
1392 return FE_TER_NOTPS;
1393
1394 guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1395 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
1396 switch (guard) {
1397 case 0:
1398 case 1:
1399 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
1400 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/
1401 stv0367_writebits(state, F367TER_SYR_FILTER, 0);
1402 break;
1403 case 2:
1404 case 3:
1405 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
1406 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/
1407 stv0367_writebits(state, F367TER_SYR_FILTER, 1);
1408 break;
1409
1410 default:
1411 return FE_TER_SWNOK;
1412 }
1413
1414 /* apply Sfec workaround if 8K 64QAM CR!=1/2*/
1415 if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) &&
1416 (mode == 1) &&
1417 (stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) {
1418 stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0);
1419 stv0367_writereg(state, R367TER_SFDLYSETM, 0x60);
1420 stv0367_writereg(state, R367TER_SFDLYSETL, 0x0);
1421 } else
1422 stv0367_writereg(state, R367TER_SFDLYSETH, 0x0);
1423
1424 wd = stv0367ter_duration(mode, 125, 500, 250);
1425 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
1426
1427 while ((!u_var4) && (wd >= 0)) {
1428 usleep_range(1000 * tempo, 1000 * (tempo + 1));
1429 wd -= tempo;
1430 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
1431 }
1432
1433 if (!u_var4)
1434 return FE_TER_NOLOCK;
1435
1436 /* for 367 leave COM_N at 0x7 for IQ_mode*/
1437 /*if(ter_state->if_iq_mode!=FE_TER_NORMAL_IF_TUNER) {
1438 tempo=0;
1439 while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) &&
1440 (stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) {
1441 ChipWaitOrAbort(state,1);
1442 tempo+=1;
1443 }
1444
1445 stv0367_writebits(state,F367TER_COM_N,0x17);
1446 } */
1447
1448 stv0367_writebits(state, F367TER_SYR_TR_DIS, 1);
1449
1450 dprintk("FE_TER_LOCKOK !!!\n");
1451
1452 return FE_TER_LOCKOK;
1453
1454 }
1455
1456 static void stv0367ter_set_ts_mode(struct stv0367_state *state,
1457 enum stv0367_ts_mode PathTS)
1458 {
1459
1460 dprintk("%s:\n", __func__);
1461
1462 if (state == NULL)
1463 return;
1464
1465 stv0367_writebits(state, F367TER_TS_DIS, 0);
1466 switch (PathTS) {
1467 default:
1468 /*for removing warning :default we can assume in parallel mode*/
1469 case STV0367_PARALLEL_PUNCT_CLOCK:
1470 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0);
1471 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0);
1472 break;
1473 case STV0367_SERIAL_PUNCT_CLOCK:
1474 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1);
1475 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1);
1476 break;
1477 }
1478 }
1479
1480 static void stv0367ter_set_clk_pol(struct stv0367_state *state,
1481 enum stv0367_clk_pol clock)
1482 {
1483
1484 dprintk("%s:\n", __func__);
1485
1486 if (state == NULL)
1487 return;
1488
1489 switch (clock) {
1490 case STV0367_RISINGEDGE_CLOCK:
1491 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1);
1492 break;
1493 case STV0367_FALLINGEDGE_CLOCK:
1494 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
1495 break;
1496 /*case FE_TER_CLOCK_POLARITY_DEFAULT:*/
1497 default:
1498 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
1499 break;
1500 }
1501 }
1502
1503 #if 0
1504 static void stv0367ter_core_sw(struct stv0367_state *state)
1505 {
1506
1507 dprintk("%s:\n", __func__);
1508
1509 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1510 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1511 msleep(350);
1512 }
1513 #endif
1514 static int stv0367ter_standby(struct dvb_frontend *fe, u8 standby_on)
1515 {
1516 struct stv0367_state *state = fe->demodulator_priv;
1517
1518 dprintk("%s:\n", __func__);
1519
1520 if (standby_on) {
1521 stv0367_writebits(state, F367TER_STDBY, 1);
1522 stv0367_writebits(state, F367TER_STDBY_FEC, 1);
1523 stv0367_writebits(state, F367TER_STDBY_CORE, 1);
1524 } else {
1525 stv0367_writebits(state, F367TER_STDBY, 0);
1526 stv0367_writebits(state, F367TER_STDBY_FEC, 0);
1527 stv0367_writebits(state, F367TER_STDBY_CORE, 0);
1528 }
1529
1530 return 0;
1531 }
1532
1533 static int stv0367ter_sleep(struct dvb_frontend *fe)
1534 {
1535 return stv0367ter_standby(fe, 1);
1536 }
1537
1538 static int stv0367ter_init(struct dvb_frontend *fe)
1539 {
1540 struct stv0367_state *state = fe->demodulator_priv;
1541 struct stv0367ter_state *ter_state = state->ter_state;
1542 int i;
1543
1544 dprintk("%s:\n", __func__);
1545
1546 ter_state->pBER = 0;
1547
1548 for (i = 0; i < STV0367TER_NBREGS; i++)
1549 stv0367_writereg(state, def0367ter[i].addr,
1550 def0367ter[i].value);
1551
1552 switch (state->config->xtal) {
1553 /*set internal freq to 53.125MHz */
1554 case 25000000:
1555 stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
1556 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
1557 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1558 break;
1559 default:
1560 case 27000000:
1561 dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n");
1562 stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
1563 stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
1564 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1565 break;
1566 case 30000000:
1567 stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
1568 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
1569 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1570 break;
1571 }
1572
1573 stv0367_writereg(state, R367TER_I2CRPT, 0xa0);
1574 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
1575
1576 /*Set TS1 and TS2 to serial or parallel mode */
1577 stv0367ter_set_ts_mode(state, state->config->ts_mode);
1578 stv0367ter_set_clk_pol(state, state->config->clk_pol);
1579
1580 state->chip_id = stv0367_readreg(state, R367TER_ID);
1581 ter_state->first_lock = 0;
1582 ter_state->unlock_counter = 2;
1583
1584 return 0;
1585 }
1586
1587 static int stv0367ter_algo(struct dvb_frontend *fe)
1588 {
1589 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1590 struct stv0367_state *state = fe->demodulator_priv;
1591 struct stv0367ter_state *ter_state = state->ter_state;
1592 int offset = 0, tempo = 0;
1593 u8 u_var;
1594 u8 /*constell,*/ counter;
1595 s8 step;
1596 s32 timing_offset = 0;
1597 u32 trl_nomrate = 0, InternalFreq = 0, temp = 0;
1598
1599 dprintk("%s:\n", __func__);
1600
1601 ter_state->frequency = p->frequency;
1602 ter_state->force = FE_TER_FORCENONE
1603 + stv0367_readbits(state, F367TER_FORCE) * 2;
1604 ter_state->if_iq_mode = state->config->if_iq_mode;
1605 switch (state->config->if_iq_mode) {
1606 case FE_TER_NORMAL_IF_TUNER: /* Normal IF mode */
1607 dprintk("ALGO: FE_TER_NORMAL_IF_TUNER selected\n");
1608 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1609 stv0367_writebits(state, F367TER_LONGPATH_IF, 0);
1610 stv0367_writebits(state, F367TER_DEMUX_SWAP, 0);
1611 break;
1612 case FE_TER_LONGPATH_IF_TUNER: /* Long IF mode */
1613 dprintk("ALGO: FE_TER_LONGPATH_IF_TUNER selected\n");
1614 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1615 stv0367_writebits(state, F367TER_LONGPATH_IF, 1);
1616 stv0367_writebits(state, F367TER_DEMUX_SWAP, 1);
1617 break;
1618 case FE_TER_IQ_TUNER: /* IQ mode */
1619 dprintk("ALGO: FE_TER_IQ_TUNER selected\n");
1620 stv0367_writebits(state, F367TER_TUNER_BB, 1);
1621 stv0367_writebits(state, F367TER_PPM_INVSEL, 0);
1622 break;
1623 default:
1624 printk(KERN_ERR "ALGO: wrong TUNER type selected\n");
1625 return -EINVAL;
1626 }
1627
1628 usleep_range(5000, 7000);
1629
1630 switch (p->inversion) {
1631 case INVERSION_AUTO:
1632 default:
1633 dprintk("%s: inversion AUTO\n", __func__);
1634 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1635 stv0367_writebits(state, F367TER_IQ_INVERT,
1636 ter_state->sense);
1637 else
1638 stv0367_writebits(state, F367TER_INV_SPECTR,
1639 ter_state->sense);
1640
1641 break;
1642 case INVERSION_ON:
1643 case INVERSION_OFF:
1644 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1645 stv0367_writebits(state, F367TER_IQ_INVERT,
1646 p->inversion);
1647 else
1648 stv0367_writebits(state, F367TER_INV_SPECTR,
1649 p->inversion);
1650
1651 break;
1652 }
1653
1654 if ((ter_state->if_iq_mode != FE_TER_NORMAL_IF_TUNER) &&
1655 (ter_state->pBW != ter_state->bw)) {
1656 stv0367ter_agc_iir_lock_detect_set(state);
1657
1658 /*set fine agc target to 180 for LPIF or IQ mode*/
1659 /* set Q_AGCTarget */
1660 stv0367_writebits(state, F367TER_SEL_IQNTAR, 1);
1661 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1662 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1663
1664 /* set Q_AGCTarget */
1665 stv0367_writebits(state, F367TER_SEL_IQNTAR, 0);
1666 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1667 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1668
1669 if (!stv0367_iir_filt_init(state, ter_state->bw,
1670 state->config->xtal))
1671 return -EINVAL;
1672 /*set IIR filter once for 6,7 or 8MHz BW*/
1673 ter_state->pBW = ter_state->bw;
1674
1675 stv0367ter_agc_iir_rst(state);
1676 }
1677
1678 if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1679 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01);
1680 else
1681 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00);
1682
1683 InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000;
1684 temp = (int)
1685 ((((ter_state->bw * 64 * (1 << 15) * 100)
1686 / (InternalFreq)) * 10) / 7);
1687
1688 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2);
1689 temp = temp / 2;
1690 stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256);
1691 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256);
1692
1693 temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 +
1694 stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 +
1695 stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB);
1696 temp = (int)(((1 << 17) * ter_state->bw * 1000) / (7 * (InternalFreq)));
1697 stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256);
1698 stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256);
1699 temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 +
1700 stv0367_readbits(state, F367TER_GAIN_SRC_LO);
1701
1702 temp = (int)
1703 ((InternalFreq - state->config->if_khz) * (1 << 16)
1704 / (InternalFreq));
1705
1706 dprintk("DEROT temp=0x%x\n", temp);
1707 stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256);
1708 stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256);
1709
1710 ter_state->echo_pos = 0;
1711 ter_state->ucblocks = 0; /* liplianin */
1712 ter_state->pBER = 0; /* liplianin */
1713 stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos);
1714
1715 if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK)
1716 return 0;
1717
1718 ter_state->state = FE_TER_LOCKOK;
1719
1720 ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE);
1721 ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1722
1723 ter_state->first_lock = 1; /* we know sense now :) */
1724
1725 ter_state->agc_val =
1726 (stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) +
1727 (stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) +
1728 stv0367_readbits(state, F367TER_AGC2_VAL_LO) +
1729 (stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8);
1730
1731 /* Carrier offset calculation */
1732 stv0367_writebits(state, F367TER_FREEZE, 1);
1733 offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ;
1734 offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8);
1735 offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO));
1736 stv0367_writebits(state, F367TER_FREEZE, 0);
1737 if (offset > 8388607)
1738 offset -= 16777216;
1739
1740 offset = offset * 2 / 16384;
1741
1742 if (ter_state->mode == FE_TER_MODE_2K)
1743 offset = (offset * 4464) / 1000;/*** 1 FFT BIN=4.464khz***/
1744 else if (ter_state->mode == FE_TER_MODE_4K)
1745 offset = (offset * 223) / 100;/*** 1 FFT BIN=2.23khz***/
1746 else if (ter_state->mode == FE_TER_MODE_8K)
1747 offset = (offset * 111) / 100;/*** 1 FFT BIN=1.1khz***/
1748
1749 if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) {
1750 if ((stv0367_readbits(state, F367TER_INV_SPECTR) ==
1751 (stv0367_readbits(state,
1752 F367TER_STATUS_INV_SPECRUM) == 1)))
1753 offset = offset * -1;
1754 }
1755
1756 if (ter_state->bw == 6)
1757 offset = (offset * 6) / 8;
1758 else if (ter_state->bw == 7)
1759 offset = (offset * 7) / 8;
1760
1761 ter_state->frequency += offset;
1762
1763 tempo = 10; /* exit even if timing_offset stays null */
1764 while ((timing_offset == 0) && (tempo > 0)) {
1765 usleep_range(10000, 20000); /*was 20ms */
1766 /* fine tuning of timing offset if required */
1767 timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO)
1768 + 256 * stv0367_readbits(state,
1769 F367TER_TRL_TOFFSET_HI);
1770 if (timing_offset >= 32768)
1771 timing_offset -= 65536;
1772 trl_nomrate = (512 * stv0367_readbits(state,
1773 F367TER_TRL_NOMRATE_HI)
1774 + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2
1775 + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB));
1776
1777 timing_offset = ((signed)(1000000 / trl_nomrate) *
1778 timing_offset) / 2048;
1779 tempo--;
1780 }
1781
1782 if (timing_offset <= 0) {
1783 timing_offset = (timing_offset - 11) / 22;
1784 step = -1;
1785 } else {
1786 timing_offset = (timing_offset + 11) / 22;
1787 step = 1;
1788 }
1789
1790 for (counter = 0; counter < abs(timing_offset); counter++) {
1791 trl_nomrate += step;
1792 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB,
1793 trl_nomrate % 2);
1794 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO,
1795 trl_nomrate / 2);
1796 usleep_range(1000, 2000);
1797 }
1798
1799 usleep_range(5000, 6000);
1800 /* unlocks could happen in case of trl centring big step,
1801 then a core off/on restarts demod */
1802 u_var = stv0367_readbits(state, F367TER_LK);
1803
1804 if (!u_var) {
1805 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1806 msleep(20);
1807 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1808 }
1809
1810 return 0;
1811 }
1812
1813 static int stv0367ter_set_frontend(struct dvb_frontend *fe)
1814 {
1815 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1816 struct stv0367_state *state = fe->demodulator_priv;
1817 struct stv0367ter_state *ter_state = state->ter_state;
1818
1819 /*u8 trials[2]; */
1820 s8 num_trials, index;
1821 u8 SenseTrials[] = { INVERSION_ON, INVERSION_OFF };
1822
1823 stv0367ter_init(fe);
1824
1825 if (fe->ops.tuner_ops.set_params) {
1826 if (fe->ops.i2c_gate_ctrl)
1827 fe->ops.i2c_gate_ctrl(fe, 1);
1828 fe->ops.tuner_ops.set_params(fe);
1829 if (fe->ops.i2c_gate_ctrl)
1830 fe->ops.i2c_gate_ctrl(fe, 0);
1831 }
1832
1833 switch (p->transmission_mode) {
1834 default:
1835 case TRANSMISSION_MODE_AUTO:
1836 case TRANSMISSION_MODE_2K:
1837 ter_state->mode = FE_TER_MODE_2K;
1838 break;
1839 /* case TRANSMISSION_MODE_4K:
1840 pLook.mode = FE_TER_MODE_4K;
1841 break;*/
1842 case TRANSMISSION_MODE_8K:
1843 ter_state->mode = FE_TER_MODE_8K;
1844 break;
1845 }
1846
1847 switch (p->guard_interval) {
1848 default:
1849 case GUARD_INTERVAL_1_32:
1850 case GUARD_INTERVAL_1_16:
1851 case GUARD_INTERVAL_1_8:
1852 case GUARD_INTERVAL_1_4:
1853 ter_state->guard = p->guard_interval;
1854 break;
1855 case GUARD_INTERVAL_AUTO:
1856 ter_state->guard = GUARD_INTERVAL_1_32;
1857 break;
1858 }
1859
1860 switch (p->bandwidth_hz) {
1861 case 6000000:
1862 ter_state->bw = FE_TER_CHAN_BW_6M;
1863 break;
1864 case 7000000:
1865 ter_state->bw = FE_TER_CHAN_BW_7M;
1866 break;
1867 case 8000000:
1868 default:
1869 ter_state->bw = FE_TER_CHAN_BW_8M;
1870 }
1871
1872 ter_state->hierarchy = FE_TER_HIER_NONE;
1873
1874 switch (p->inversion) {
1875 case INVERSION_OFF:
1876 case INVERSION_ON:
1877 num_trials = 1;
1878 break;
1879 default:
1880 num_trials = 2;
1881 if (ter_state->first_lock)
1882 num_trials = 1;
1883 break;
1884 }
1885
1886 ter_state->state = FE_TER_NOLOCK;
1887 index = 0;
1888
1889 while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) {
1890 if (!ter_state->first_lock) {
1891 if (p->inversion == INVERSION_AUTO)
1892 ter_state->sense = SenseTrials[index];
1893
1894 }
1895 stv0367ter_algo(fe);
1896
1897 if ((ter_state->state == FE_TER_LOCKOK) &&
1898 (p->inversion == INVERSION_AUTO) &&
1899 (index == 1)) {
1900 /* invert spectrum sense */
1901 SenseTrials[index] = SenseTrials[0];
1902 SenseTrials[(index + 1) % 2] = (SenseTrials[1] + 1) % 2;
1903 }
1904
1905 index++;
1906 }
1907
1908 return 0;
1909 }
1910
1911 static int stv0367ter_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1912 {
1913 struct stv0367_state *state = fe->demodulator_priv;
1914 struct stv0367ter_state *ter_state = state->ter_state;
1915 u32 errs = 0;
1916
1917 /*wait for counting completion*/
1918 if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) {
1919 errs =
1920 ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1921 * (1 << 16))
1922 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1923 * (1 << 8))
1924 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1925 ter_state->ucblocks = errs;
1926 }
1927
1928 (*ucblocks) = ter_state->ucblocks;
1929
1930 return 0;
1931 }
1932
1933 static int stv0367ter_get_frontend(struct dvb_frontend *fe)
1934 {
1935 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1936 struct stv0367_state *state = fe->demodulator_priv;
1937 struct stv0367ter_state *ter_state = state->ter_state;
1938
1939 int error = 0;
1940 enum stv0367_ter_mode mode;
1941 int constell = 0,/* snr = 0,*/ Data = 0;
1942
1943 p->frequency = stv0367_get_tuner_freq(fe);
1944 if ((int)p->frequency < 0)
1945 p->frequency = -p->frequency;
1946
1947 constell = stv0367_readbits(state, F367TER_TPS_CONST);
1948 if (constell == 0)
1949 p->modulation = QPSK;
1950 else if (constell == 1)
1951 p->modulation = QAM_16;
1952 else
1953 p->modulation = QAM_64;
1954
1955 p->inversion = stv0367_readbits(state, F367TER_INV_SPECTR);
1956
1957 /* Get the Hierarchical mode */
1958 Data = stv0367_readbits(state, F367TER_TPS_HIERMODE);
1959
1960 switch (Data) {
1961 case 0:
1962 p->hierarchy = HIERARCHY_NONE;
1963 break;
1964 case 1:
1965 p->hierarchy = HIERARCHY_1;
1966 break;
1967 case 2:
1968 p->hierarchy = HIERARCHY_2;
1969 break;
1970 case 3:
1971 p->hierarchy = HIERARCHY_4;
1972 break;
1973 default:
1974 p->hierarchy = HIERARCHY_AUTO;
1975 break; /* error */
1976 }
1977
1978 /* Get the FEC Rate */
1979 if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1980 Data = stv0367_readbits(state, F367TER_TPS_LPCODE);
1981 else
1982 Data = stv0367_readbits(state, F367TER_TPS_HPCODE);
1983
1984 switch (Data) {
1985 case 0:
1986 p->code_rate_HP = FEC_1_2;
1987 break;
1988 case 1:
1989 p->code_rate_HP = FEC_2_3;
1990 break;
1991 case 2:
1992 p->code_rate_HP = FEC_3_4;
1993 break;
1994 case 3:
1995 p->code_rate_HP = FEC_5_6;
1996 break;
1997 case 4:
1998 p->code_rate_HP = FEC_7_8;
1999 break;
2000 default:
2001 p->code_rate_HP = FEC_AUTO;
2002 break; /* error */
2003 }
2004
2005 mode = stv0367_readbits(state, F367TER_SYR_MODE);
2006
2007 switch (mode) {
2008 case FE_TER_MODE_2K:
2009 p->transmission_mode = TRANSMISSION_MODE_2K;
2010 break;
2011 /* case FE_TER_MODE_4K:
2012 p->transmission_mode = TRANSMISSION_MODE_4K;
2013 break;*/
2014 case FE_TER_MODE_8K:
2015 p->transmission_mode = TRANSMISSION_MODE_8K;
2016 break;
2017 default:
2018 p->transmission_mode = TRANSMISSION_MODE_AUTO;
2019 }
2020
2021 p->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD);
2022
2023 return error;
2024 }
2025
2026 static int stv0367ter_read_snr(struct dvb_frontend *fe, u16 *snr)
2027 {
2028 struct stv0367_state *state = fe->demodulator_priv;
2029 u32 snru32 = 0;
2030 int cpt = 0;
2031 u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG);
2032
2033 while (cpt < 10) {
2034 usleep_range(2000, 3000);
2035 if (cut == 0x50) /*cut 1.0 cut 1.1*/
2036 snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4;
2037 else /*cu2.0*/
2038 snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR);
2039
2040 cpt++;
2041 }
2042
2043 snru32 /= 10;/*average on 10 values*/
2044
2045 *snr = snru32 / 1000;
2046
2047 return 0;
2048 }
2049
2050 #if 0
2051 static int stv0367ter_status(struct dvb_frontend *fe)
2052 {
2053
2054 struct stv0367_state *state = fe->demodulator_priv;
2055 struct stv0367ter_state *ter_state = state->ter_state;
2056 int locked = FALSE;
2057
2058 locked = (stv0367_readbits(state, F367TER_LK));
2059 if (!locked)
2060 ter_state->unlock_counter += 1;
2061 else
2062 ter_state->unlock_counter = 0;
2063
2064 if (ter_state->unlock_counter > 2) {
2065 if (!stv0367_readbits(state, F367TER_TPS_LOCK) ||
2066 (!stv0367_readbits(state, F367TER_LK))) {
2067 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
2068 usleep_range(2000, 3000);
2069 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
2070 msleep(350);
2071 locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) &&
2072 (stv0367_readbits(state, F367TER_LK));
2073 }
2074
2075 }
2076
2077 return locked;
2078 }
2079 #endif
2080 static int stv0367ter_read_status(struct dvb_frontend *fe, fe_status_t *status)
2081 {
2082 struct stv0367_state *state = fe->demodulator_priv;
2083
2084 dprintk("%s:\n", __func__);
2085
2086 *status = 0;
2087
2088 if (stv0367_readbits(state, F367TER_LK)) {
2089 *status |= FE_HAS_LOCK;
2090 dprintk("%s: stv0367 has locked\n", __func__);
2091 }
2092
2093 return 0;
2094 }
2095
2096 static int stv0367ter_read_ber(struct dvb_frontend *fe, u32 *ber)
2097 {
2098 struct stv0367_state *state = fe->demodulator_priv;
2099 struct stv0367ter_state *ter_state = state->ter_state;
2100 u32 Errors = 0, tber = 0, temporary = 0;
2101 int abc = 0, def = 0;
2102
2103
2104 /*wait for counting completion*/
2105 if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0)
2106 Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT)
2107 * (1 << 16))
2108 + ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI)
2109 * (1 << 8))
2110 + ((u32)stv0367_readbits(state,
2111 F367TER_SFEC_ERR_CNT_LO));
2112 /*measurement not completed, load previous value*/
2113 else {
2114 tber = ter_state->pBER;
2115 return 0;
2116 }
2117
2118 abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE);
2119 def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT);
2120
2121 if (Errors == 0) {
2122 tber = 0;
2123 } else if (abc == 0x7) {
2124 if (Errors <= 4) {
2125 temporary = (Errors * 1000000000) / (8 * (1 << 14));
2126 temporary = temporary;
2127 } else if (Errors <= 42) {
2128 temporary = (Errors * 100000000) / (8 * (1 << 14));
2129 temporary = temporary * 10;
2130 } else if (Errors <= 429) {
2131 temporary = (Errors * 10000000) / (8 * (1 << 14));
2132 temporary = temporary * 100;
2133 } else if (Errors <= 4294) {
2134 temporary = (Errors * 1000000) / (8 * (1 << 14));
2135 temporary = temporary * 1000;
2136 } else if (Errors <= 42949) {
2137 temporary = (Errors * 100000) / (8 * (1 << 14));
2138 temporary = temporary * 10000;
2139 } else if (Errors <= 429496) {
2140 temporary = (Errors * 10000) / (8 * (1 << 14));
2141 temporary = temporary * 100000;
2142 } else { /*if (Errors<4294967) 2^22 max error*/
2143 temporary = (Errors * 1000) / (8 * (1 << 14));
2144 temporary = temporary * 100000; /* still to *10 */
2145 }
2146
2147 /* Byte error*/
2148 if (def == 2)
2149 /*tber=Errors/(8*(1 <<14));*/
2150 tber = temporary;
2151 else if (def == 3)
2152 /*tber=Errors/(8*(1 <<16));*/
2153 tber = temporary / 4;
2154 else if (def == 4)
2155 /*tber=Errors/(8*(1 <<18));*/
2156 tber = temporary / 16;
2157 else if (def == 5)
2158 /*tber=Errors/(8*(1 <<20));*/
2159 tber = temporary / 64;
2160 else if (def == 6)
2161 /*tber=Errors/(8*(1 <<22));*/
2162 tber = temporary / 256;
2163 else
2164 /* should not pass here*/
2165 tber = 0;
2166
2167 if ((Errors < 4294967) && (Errors > 429496))
2168 tber *= 10;
2169
2170 }
2171
2172 /* save actual value */
2173 ter_state->pBER = tber;
2174
2175 (*ber) = tber;
2176
2177 return 0;
2178 }
2179 #if 0
2180 static u32 stv0367ter_get_per(struct stv0367_state *state)
2181 {
2182 struct stv0367ter_state *ter_state = state->ter_state;
2183 u32 Errors = 0, Per = 0, temporary = 0;
2184 int abc = 0, def = 0, cpt = 0;
2185
2186 while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) &&
2187 (cpt < 400)) || ((Errors == 0) && (cpt < 400))) {
2188 usleep_range(1000, 2000);
2189 Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
2190 * (1 << 16))
2191 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
2192 * (1 << 8))
2193 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
2194 cpt++;
2195 }
2196 abc = stv0367_readbits(state, F367TER_ERR_SRC1);
2197 def = stv0367_readbits(state, F367TER_NUM_EVT1);
2198
2199 if (Errors == 0)
2200 Per = 0;
2201 else if (abc == 0x9) {
2202 if (Errors <= 4) {
2203 temporary = (Errors * 1000000000) / (8 * (1 << 8));
2204 temporary = temporary;
2205 } else if (Errors <= 42) {
2206 temporary = (Errors * 100000000) / (8 * (1 << 8));
2207 temporary = temporary * 10;
2208 } else if (Errors <= 429) {
2209 temporary = (Errors * 10000000) / (8 * (1 << 8));
2210 temporary = temporary * 100;
2211 } else if (Errors <= 4294) {
2212 temporary = (Errors * 1000000) / (8 * (1 << 8));
2213 temporary = temporary * 1000;
2214 } else if (Errors <= 42949) {
2215 temporary = (Errors * 100000) / (8 * (1 << 8));
2216 temporary = temporary * 10000;
2217 } else { /*if(Errors<=429496) 2^16 errors max*/
2218 temporary = (Errors * 10000) / (8 * (1 << 8));
2219 temporary = temporary * 100000;
2220 }
2221
2222 /* pkt error*/
2223 if (def == 2)
2224 /*Per=Errors/(1 << 8);*/
2225 Per = temporary;
2226 else if (def == 3)
2227 /*Per=Errors/(1 << 10);*/
2228 Per = temporary / 4;
2229 else if (def == 4)
2230 /*Per=Errors/(1 << 12);*/
2231 Per = temporary / 16;
2232 else if (def == 5)
2233 /*Per=Errors/(1 << 14);*/
2234 Per = temporary / 64;
2235 else if (def == 6)
2236 /*Per=Errors/(1 << 16);*/
2237 Per = temporary / 256;
2238 else
2239 Per = 0;
2240
2241 }
2242 /* save actual value */
2243 ter_state->pPER = Per;
2244
2245 return Per;
2246 }
2247 #endif
2248 static int stv0367_get_tune_settings(struct dvb_frontend *fe,
2249 struct dvb_frontend_tune_settings
2250 *fe_tune_settings)
2251 {
2252 fe_tune_settings->min_delay_ms = 1000;
2253 fe_tune_settings->step_size = 0;
2254 fe_tune_settings->max_drift = 0;
2255
2256 return 0;
2257 }
2258
2259 static void stv0367_release(struct dvb_frontend *fe)
2260 {
2261 struct stv0367_state *state = fe->demodulator_priv;
2262
2263 kfree(state->ter_state);
2264 kfree(state->cab_state);
2265 kfree(state);
2266 }
2267
2268 static struct dvb_frontend_ops stv0367ter_ops = {
2269 .delsys = { SYS_DVBT },
2270 .info = {
2271 .name = "ST STV0367 DVB-T",
2272 .frequency_min = 47000000,
2273 .frequency_max = 862000000,
2274 .frequency_stepsize = 15625,
2275 .frequency_tolerance = 0,
2276 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
2277 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
2278 FE_CAN_FEC_AUTO |
2279 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2280 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
2281 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
2282 FE_CAN_INVERSION_AUTO |
2283 FE_CAN_MUTE_TS
2284 },
2285 .release = stv0367_release,
2286 .init = stv0367ter_init,
2287 .sleep = stv0367ter_sleep,
2288 .i2c_gate_ctrl = stv0367ter_gate_ctrl,
2289 .set_frontend = stv0367ter_set_frontend,
2290 .get_frontend = stv0367ter_get_frontend,
2291 .get_tune_settings = stv0367_get_tune_settings,
2292 .read_status = stv0367ter_read_status,
2293 .read_ber = stv0367ter_read_ber,/* too slow */
2294 /* .read_signal_strength = stv0367_read_signal_strength,*/
2295 .read_snr = stv0367ter_read_snr,
2296 .read_ucblocks = stv0367ter_read_ucblocks,
2297 };
2298
2299 struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
2300 struct i2c_adapter *i2c)
2301 {
2302 struct stv0367_state *state = NULL;
2303 struct stv0367ter_state *ter_state = NULL;
2304
2305 /* allocate memory for the internal state */
2306 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
2307 if (state == NULL)
2308 goto error;
2309 ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
2310 if (ter_state == NULL)
2311 goto error;
2312
2313 /* setup the state */
2314 state->i2c = i2c;
2315 state->config = config;
2316 state->ter_state = ter_state;
2317 state->fe.ops = stv0367ter_ops;
2318 state->fe.demodulator_priv = state;
2319 state->chip_id = stv0367_readreg(state, 0xf000);
2320
2321 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
2322
2323 /* check if the demod is there */
2324 if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
2325 goto error;
2326
2327 return &state->fe;
2328
2329 error:
2330 kfree(ter_state);
2331 kfree(state);
2332 return NULL;
2333 }
2334 EXPORT_SYMBOL(stv0367ter_attach);
2335
2336 static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable)
2337 {
2338 struct stv0367_state *state = fe->demodulator_priv;
2339
2340 dprintk("%s:\n", __func__);
2341
2342 stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0);
2343
2344 return 0;
2345 }
2346
2347 static u32 stv0367cab_get_mclk(struct dvb_frontend *fe, u32 ExtClk_Hz)
2348 {
2349 struct stv0367_state *state = fe->demodulator_priv;
2350 u32 mclk_Hz = 0;/* master clock frequency (Hz) */
2351 u32 M, N, P;
2352
2353
2354 if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) {
2355 N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV);
2356 if (N == 0)
2357 N = N + 1;
2358
2359 M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV);
2360 if (M == 0)
2361 M = M + 1;
2362
2363 P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV);
2364
2365 if (P > 5)
2366 P = 5;
2367
2368 mclk_Hz = ((ExtClk_Hz / 2) * N) / (M * (1 << P));
2369 dprintk("stv0367cab_get_mclk BYPASS_PLLXN mclk_Hz=%d\n",
2370 mclk_Hz);
2371 } else
2372 mclk_Hz = ExtClk_Hz;
2373
2374 dprintk("stv0367cab_get_mclk final mclk_Hz=%d\n", mclk_Hz);
2375
2376 return mclk_Hz;
2377 }
2378
2379 static u32 stv0367cab_get_adc_freq(struct dvb_frontend *fe, u32 ExtClk_Hz)
2380 {
2381 u32 ADCClk_Hz = ExtClk_Hz;
2382
2383 ADCClk_Hz = stv0367cab_get_mclk(fe, ExtClk_Hz);
2384
2385 return ADCClk_Hz;
2386 }
2387
2388 static enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state,
2389 u32 SymbolRate,
2390 enum stv0367cab_mod QAMSize)
2391 {
2392 /* Set QAM size */
2393 stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize);
2394
2395 /* Set Registers settings specific to the QAM size */
2396 switch (QAMSize) {
2397 case FE_CAB_MOD_QAM4:
2398 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2399 break;
2400 case FE_CAB_MOD_QAM16:
2401 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64);
2402 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2403 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
2404 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2405 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2406 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
2407 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2408 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a);
2409 break;
2410 case FE_CAB_MOD_QAM32:
2411 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2412 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e);
2413 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
2414 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2415 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7);
2416 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d);
2417 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
2418 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2419 break;
2420 case FE_CAB_MOD_QAM64:
2421 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82);
2422 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
2423 if (SymbolRate > 45000000) {
2424 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
2425 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2426 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5);
2427 } else if (SymbolRate > 25000000) {
2428 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2429 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2430 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
2431 } else {
2432 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2433 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
2434 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2435 }
2436 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
2437 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2438 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99);
2439 break;
2440 case FE_CAB_MOD_QAM128:
2441 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2442 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76);
2443 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
2444 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1);
2445 if (SymbolRate > 45000000)
2446 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2447 else if (SymbolRate > 25000000)
2448 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
2449 else
2450 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97);
2451
2452 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e);
2453 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
2454 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2455 break;
2456 case FE_CAB_MOD_QAM256:
2457 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94);
2458 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
2459 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2460 if (SymbolRate > 45000000)
2461 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2462 else if (SymbolRate > 25000000)
2463 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2464 else
2465 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
2466
2467 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2468 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85);
2469 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2470 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2471 break;
2472 case FE_CAB_MOD_QAM512:
2473 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2474 break;
2475 case FE_CAB_MOD_QAM1024:
2476 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2477 break;
2478 default:
2479 break;
2480 }
2481
2482 return QAMSize;
2483 }
2484
2485 static u32 stv0367cab_set_derot_freq(struct stv0367_state *state,
2486 u32 adc_hz, s32 derot_hz)
2487 {
2488 u32 sampled_if = 0;
2489 u32 adc_khz;
2490
2491 adc_khz = adc_hz / 1000;
2492
2493 dprintk("%s: adc_hz=%d derot_hz=%d\n", __func__, adc_hz, derot_hz);
2494
2495 if (adc_khz != 0) {
2496 if (derot_hz < 1000000)
2497 derot_hz = adc_hz / 4; /* ZIF operation */
2498 if (derot_hz > adc_hz)
2499 derot_hz = derot_hz - adc_hz;
2500 sampled_if = (u32)derot_hz / 1000;
2501 sampled_if *= 32768;
2502 sampled_if /= adc_khz;
2503 sampled_if *= 256;
2504 }
2505
2506 if (sampled_if > 8388607)
2507 sampled_if = 8388607;
2508
2509 dprintk("%s: sampled_if=0x%x\n", __func__, sampled_if);
2510
2511 stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if);
2512 stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8));
2513 stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16));
2514
2515 return derot_hz;
2516 }
2517
2518 static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz)
2519 {
2520 u32 sampled_if;
2521
2522 sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) +
2523 (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) +
2524 (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16);
2525
2526 sampled_if /= 256;
2527 sampled_if *= (adc_hz / 1000);
2528 sampled_if += 1;
2529 sampled_if /= 32768;
2530
2531 return sampled_if;
2532 }
2533
2534 static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz,
2535 u32 mclk_hz, u32 SymbolRate,
2536 enum stv0367cab_mod QAMSize)
2537 {
2538 u32 QamSizeCorr = 0;
2539 u32 u32_tmp = 0, u32_tmp1 = 0;
2540 u32 adp_khz;
2541
2542 dprintk("%s:\n", __func__);
2543
2544 /* Set Correction factor of SRC gain */
2545 switch (QAMSize) {
2546 case FE_CAB_MOD_QAM4:
2547 QamSizeCorr = 1110;
2548 break;
2549 case FE_CAB_MOD_QAM16:
2550 QamSizeCorr = 1032;
2551 break;
2552 case FE_CAB_MOD_QAM32:
2553 QamSizeCorr = 954;
2554 break;
2555 case FE_CAB_MOD_QAM64:
2556 QamSizeCorr = 983;
2557 break;
2558 case FE_CAB_MOD_QAM128:
2559 QamSizeCorr = 957;
2560 break;
2561 case FE_CAB_MOD_QAM256:
2562 QamSizeCorr = 948;
2563 break;
2564 case FE_CAB_MOD_QAM512:
2565 QamSizeCorr = 0;
2566 break;
2567 case FE_CAB_MOD_QAM1024:
2568 QamSizeCorr = 944;
2569 break;
2570 default:
2571 break;
2572 }
2573
2574 /* Transfer ratio calculation */
2575 if (adc_hz != 0) {
2576 u32_tmp = 256 * SymbolRate;
2577 u32_tmp = u32_tmp / adc_hz;
2578 }
2579 stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp);
2580
2581 /* Symbol rate and SRC gain calculation */
2582 adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2583 if (adp_khz != 0) {
2584 u32_tmp = SymbolRate;
2585 u32_tmp1 = SymbolRate;
2586
2587 if (u32_tmp < 2097152) { /* 2097152 = 2^21 */
2588 /* Symbol rate calculation */
2589 u32_tmp *= 2048; /* 2048 = 2^11 */
2590 u32_tmp = u32_tmp / adp_khz;
2591 u32_tmp = u32_tmp * 16384; /* 16384 = 2^14 */
2592 u32_tmp /= 125 ; /* 125 = 1000/2^3 */
2593 u32_tmp = u32_tmp * 8; /* 8 = 2^3 */
2594
2595 /* SRC Gain Calculation */
2596 u32_tmp1 *= 2048; /* *2*2^10 */
2597 u32_tmp1 /= 439; /* *2/878 */
2598 u32_tmp1 *= 256; /* *2^8 */
2599 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2600 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2601 u32_tmp1 = u32_tmp1 / 10000000;
2602
2603 } else if (u32_tmp < 4194304) { /* 4194304 = 2**22 */
2604 /* Symbol rate calculation */
2605 u32_tmp *= 1024 ; /* 1024 = 2**10 */
2606 u32_tmp = u32_tmp / adp_khz;
2607 u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2608 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2609 u32_tmp = u32_tmp * 16; /* 16 = 2**4 */
2610
2611 /* SRC Gain Calculation */
2612 u32_tmp1 *= 1024; /* *2*2^9 */
2613 u32_tmp1 /= 439; /* *2/878 */
2614 u32_tmp1 *= 256; /* *2^8 */
2615 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz)*/
2616 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2617 u32_tmp1 = u32_tmp1 / 5000000;
2618 } else if (u32_tmp < 8388607) { /* 8388607 = 2**23 */
2619 /* Symbol rate calculation */
2620 u32_tmp *= 512 ; /* 512 = 2**9 */
2621 u32_tmp = u32_tmp / adp_khz;
2622 u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2623 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2624 u32_tmp = u32_tmp * 32; /* 32 = 2**5 */
2625
2626 /* SRC Gain Calculation */
2627 u32_tmp1 *= 512; /* *2*2^8 */
2628 u32_tmp1 /= 439; /* *2/878 */
2629 u32_tmp1 *= 256; /* *2^8 */
2630 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2631 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2632 u32_tmp1 = u32_tmp1 / 2500000;
2633 } else {
2634 /* Symbol rate calculation */
2635 u32_tmp *= 256 ; /* 256 = 2**8 */
2636 u32_tmp = u32_tmp / adp_khz;
2637 u32_tmp = u32_tmp * 16384; /* 16384 = 2**13 */
2638 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2639 u32_tmp = u32_tmp * 64; /* 64 = 2**6 */
2640
2641 /* SRC Gain Calculation */
2642 u32_tmp1 *= 256; /* 2*2^7 */
2643 u32_tmp1 /= 439; /* *2/878 */
2644 u32_tmp1 *= 256; /* *2^8 */
2645 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2646 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2647 u32_tmp1 = u32_tmp1 / 1250000;
2648 }
2649 }
2650 #if 0
2651 /* Filters' coefficients are calculated and written
2652 into registers only if the filters are enabled */
2653 if (stv0367_readbits(state, F367CAB_ADJ_EN)) {
2654 stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz,
2655 SymbolRate);
2656 /* AllPass filter must be enabled
2657 when the adjacents filter is used */
2658 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1);
2659 stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate);
2660 } else
2661 /* AllPass filter must be disabled
2662 when the adjacents filter is not used */
2663 #endif
2664 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2665
2666 stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp);
2667 stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8));
2668 stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16));
2669 stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24));
2670
2671 stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff);
2672 stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff);
2673
2674 return SymbolRate ;
2675 }
2676
2677 static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz)
2678 {
2679 u32 regsym;
2680 u32 adp_khz;
2681
2682 regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) +
2683 (stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) +
2684 (stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) +
2685 (stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24);
2686
2687 adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2688
2689 if (regsym < 134217728) { /* 134217728L = 2**27*/
2690 regsym = regsym * 32; /* 32 = 2**5 */
2691 regsym = regsym / 32768; /* 32768L = 2**15 */
2692 regsym = adp_khz * regsym; /* AdpClk in kHz */
2693 regsym = regsym / 128; /* 128 = 2**7 */
2694 regsym *= 125 ; /* 125 = 1000/2**3 */
2695 regsym /= 2048 ; /* 2048 = 2**11 */
2696 } else if (regsym < 268435456) { /* 268435456L = 2**28 */
2697 regsym = regsym * 16; /* 16 = 2**4 */
2698 regsym = regsym / 32768; /* 32768L = 2**15 */
2699 regsym = adp_khz * regsym; /* AdpClk in kHz */
2700 regsym = regsym / 128; /* 128 = 2**7 */
2701 regsym *= 125 ; /* 125 = 1000/2**3*/
2702 regsym /= 1024 ; /* 256 = 2**10*/
2703 } else if (regsym < 536870912) { /* 536870912L = 2**29*/
2704 regsym = regsym * 8; /* 8 = 2**3 */
2705 regsym = regsym / 32768; /* 32768L = 2**15 */
2706 regsym = adp_khz * regsym; /* AdpClk in kHz */
2707 regsym = regsym / 128; /* 128 = 2**7 */
2708 regsym *= 125 ; /* 125 = 1000/2**3 */
2709 regsym /= 512 ; /* 128 = 2**9 */
2710 } else {
2711 regsym = regsym * 4; /* 4 = 2**2 */
2712 regsym = regsym / 32768; /* 32768L = 2**15 */
2713 regsym = adp_khz * regsym; /* AdpClk in kHz */
2714 regsym = regsym / 128; /* 128 = 2**7 */
2715 regsym *= 125 ; /* 125 = 1000/2**3 */
2716 regsym /= 256 ; /* 64 = 2**8 */
2717 }
2718
2719 return regsym;
2720 }
2721
2722 static int stv0367cab_read_status(struct dvb_frontend *fe, fe_status_t *status)
2723 {
2724 struct stv0367_state *state = fe->demodulator_priv;
2725
2726 dprintk("%s:\n", __func__);
2727
2728 *status = 0;
2729
2730 if (stv0367_readbits(state, F367CAB_QAMFEC_LOCK)) {
2731 *status |= FE_HAS_LOCK;
2732 dprintk("%s: stv0367 has locked\n", __func__);
2733 }
2734
2735 return 0;
2736 }
2737
2738 static int stv0367cab_standby(struct dvb_frontend *fe, u8 standby_on)
2739 {
2740 struct stv0367_state *state = fe->demodulator_priv;
2741
2742 dprintk("%s:\n", __func__);
2743
2744 if (standby_on) {
2745 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03);
2746 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01);
2747 stv0367_writebits(state, F367CAB_STDBY, 1);
2748 stv0367_writebits(state, F367CAB_STDBY_CORE, 1);
2749 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0);
2750 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0);
2751 stv0367_writebits(state, F367CAB_POFFQ, 1);
2752 stv0367_writebits(state, F367CAB_POFFI, 1);
2753 } else {
2754 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00);
2755 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00);
2756 stv0367_writebits(state, F367CAB_STDBY, 0);
2757 stv0367_writebits(state, F367CAB_STDBY_CORE, 0);
2758 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1);
2759 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1);
2760 stv0367_writebits(state, F367CAB_POFFQ, 0);
2761 stv0367_writebits(state, F367CAB_POFFI, 0);
2762 }
2763
2764 return 0;
2765 }
2766
2767 static int stv0367cab_sleep(struct dvb_frontend *fe)
2768 {
2769 return stv0367cab_standby(fe, 1);
2770 }
2771
2772 static int stv0367cab_init(struct dvb_frontend *fe)
2773 {
2774 struct stv0367_state *state = fe->demodulator_priv;
2775 struct stv0367cab_state *cab_state = state->cab_state;
2776 int i;
2777
2778 dprintk("%s:\n", __func__);
2779
2780 for (i = 0; i < STV0367CAB_NBREGS; i++)
2781 stv0367_writereg(state, def0367cab[i].addr,
2782 def0367cab[i].value);
2783
2784 switch (state->config->ts_mode) {
2785 case STV0367_DVBCI_CLOCK:
2786 dprintk("Setting TSMode = STV0367_DVBCI_CLOCK\n");
2787 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03);
2788 break;
2789 case STV0367_SERIAL_PUNCT_CLOCK:
2790 case STV0367_SERIAL_CONT_CLOCK:
2791 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01);
2792 break;
2793 case STV0367_PARALLEL_PUNCT_CLOCK:
2794 case STV0367_OUTPUTMODE_DEFAULT:
2795 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00);
2796 break;
2797 }
2798
2799 switch (state->config->clk_pol) {
2800 case STV0367_RISINGEDGE_CLOCK:
2801 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00);
2802 break;
2803 case STV0367_FALLINGEDGE_CLOCK:
2804 case STV0367_CLOCKPOLARITY_DEFAULT:
2805 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01);
2806 break;
2807 }
2808
2809 stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00);
2810
2811 stv0367_writebits(state, F367CAB_CT_NBST, 0x01);
2812
2813 stv0367_writebits(state, F367CAB_TS_SWAP, 0x01);
2814
2815 stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00);
2816
2817 stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */
2818
2819 cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal);
2820 cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal);
2821
2822 return 0;
2823 }
2824 static
2825 enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
2826 struct dtv_frontend_properties *p)
2827 {
2828 struct stv0367cab_state *cab_state = state->cab_state;
2829 enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC;
2830 u32 QAMFEC_Lock, QAM_Lock, u32_tmp,
2831 LockTime, TRLTimeOut, AGCTimeOut, CRLSymbols,
2832 CRLTimeOut, EQLTimeOut, DemodTimeOut, FECTimeOut;
2833 u8 TrackAGCAccum;
2834 s32 tmp;
2835
2836 dprintk("%s:\n", __func__);
2837
2838 /* Timeouts calculation */
2839 /* A max lock time of 25 ms is allowed for delayed AGC */
2840 AGCTimeOut = 25;
2841 /* 100000 symbols needed by the TRL as a maximum value */
2842 TRLTimeOut = 100000000 / p->symbol_rate;
2843 /* CRLSymbols is the needed number of symbols to achieve a lock
2844 within [-4%, +4%] of the symbol rate.
2845 CRL timeout is calculated
2846 for a lock within [-search_range, +search_range].
2847 EQL timeout can be changed depending on
2848 the micro-reflections we want to handle.
2849 A characterization must be performed
2850 with these echoes to get new timeout values.
2851 */
2852 switch (p->modulation) {
2853 case QAM_16:
2854 CRLSymbols = 150000;
2855 EQLTimeOut = 100;
2856 break;
2857 case QAM_32:
2858 CRLSymbols = 250000;
2859 EQLTimeOut = 100;
2860 break;
2861 case QAM_64:
2862 CRLSymbols = 200000;
2863 EQLTimeOut = 100;
2864 break;
2865 case QAM_128:
2866 CRLSymbols = 250000;
2867 EQLTimeOut = 100;
2868 break;
2869 case QAM_256:
2870 CRLSymbols = 250000;
2871 EQLTimeOut = 100;
2872 break;
2873 default:
2874 CRLSymbols = 200000;
2875 EQLTimeOut = 100;
2876 break;
2877 }
2878 #if 0
2879 if (pIntParams->search_range < 0) {
2880 CRLTimeOut = (25 * CRLSymbols *
2881 (-pIntParams->search_range / 1000)) /
2882 (pIntParams->symbol_rate / 1000);
2883 } else
2884 #endif
2885 CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) /
2886 (p->symbol_rate / 1000);
2887
2888 CRLTimeOut = (1000 * CRLTimeOut) / p->symbol_rate;
2889 /* Timeouts below 50ms are coerced */
2890 if (CRLTimeOut < 50)
2891 CRLTimeOut = 50;
2892 /* A maximum of 100 TS packets is needed to get FEC lock even in case
2893 the spectrum inversion needs to be changed.
2894 This is equal to 20 ms in case of the lowest symbol rate of 0.87Msps
2895 */
2896 FECTimeOut = 20;
2897 DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut;
2898
2899 dprintk("%s: DemodTimeOut=%d\n", __func__, DemodTimeOut);
2900
2901 /* Reset the TRL to ensure nothing starts until the
2902 AGC is stable which ensures a better lock time
2903 */
2904 stv0367_writereg(state, R367CAB_CTRL_1, 0x04);
2905 /* Set AGC accumulation time to minimum and lock threshold to maximum
2906 in order to speed up the AGC lock */
2907 TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL);
2908 stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0);
2909 /* Modulus Mapper is disabled */
2910 stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0);
2911 /* Disable the sweep function */
2912 stv0367_writebits(state, F367CAB_SWEEP_EN, 0);
2913 /* The sweep function is never used, Sweep rate must be set to 0 */
2914 /* Set the derotator frequency in Hz */
2915 stv0367cab_set_derot_freq(state, cab_state->adc_clk,
2916 (1000 * (s32)state->config->if_khz + cab_state->derot_offset));
2917 /* Disable the Allpass Filter when the symbol rate is out of range */
2918 if ((p->symbol_rate > 10800000) | (p->symbol_rate < 1800000)) {
2919 stv0367_writebits(state, F367CAB_ADJ_EN, 0);
2920 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2921 }
2922 #if 0
2923 /* Check if the tuner is locked */
2924 tuner_lock = stv0367cab_tuner_get_status(fe);
2925 if (tuner_lock == 0)
2926 return FE_367CAB_NOTUNER;
2927 #endif
2928 /* Release the TRL to start demodulator acquisition */
2929 /* Wait for QAM lock */
2930 LockTime = 0;
2931 stv0367_writereg(state, R367CAB_CTRL_1, 0x00);
2932 do {
2933 QAM_Lock = stv0367_readbits(state, F367CAB_FSM_STATUS);
2934 if ((LockTime >= (DemodTimeOut - EQLTimeOut)) &&
2935 (QAM_Lock == 0x04))
2936 /*
2937 * We don't wait longer, the frequency/phase offset
2938 * must be too big
2939 */
2940 LockTime = DemodTimeOut;
2941 else if ((LockTime >= (AGCTimeOut + TRLTimeOut)) &&
2942 (QAM_Lock == 0x02))
2943 /*
2944 * We don't wait longer, either there is no signal or
2945 * it is not the right symbol rate or it is an analog
2946 * carrier
2947 */
2948 {
2949 LockTime = DemodTimeOut;
2950 u32_tmp = stv0367_readbits(state,
2951 F367CAB_AGC_PWR_WORD_LO) +
2952 (stv0367_readbits(state,
2953 F367CAB_AGC_PWR_WORD_ME) << 8) +
2954 (stv0367_readbits(state,
2955 F367CAB_AGC_PWR_WORD_HI) << 16);
2956 if (u32_tmp >= 131072)
2957 u32_tmp = 262144 - u32_tmp;
2958 u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state,
2959 F367CAB_AGC_IF_BWSEL)));
2960
2961 if (u32_tmp < stv0367_readbits(state,
2962 F367CAB_AGC_PWRREF_LO) +
2963 256 * stv0367_readbits(state,
2964 F367CAB_AGC_PWRREF_HI) - 10)
2965 QAM_Lock = 0x0f;
2966 } else {
2967 usleep_range(10000, 20000);
2968 LockTime += 10;
2969 }
2970 dprintk("QAM_Lock=0x%x LockTime=%d\n", QAM_Lock, LockTime);
2971 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2972
2973 dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2974
2975 } while (((QAM_Lock != 0x0c) && (QAM_Lock != 0x0b)) &&
2976 (LockTime < DemodTimeOut));
2977
2978 dprintk("QAM_Lock=0x%x\n", QAM_Lock);
2979
2980 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2981 dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2982 tmp = stv0367_readreg(state, R367CAB_IT_STATUS2);
2983 dprintk("R367CAB_IT_STATUS2=0x%x\n", tmp);
2984
2985 tmp = stv0367cab_get_derot_freq(state, cab_state->adc_clk);
2986 dprintk("stv0367cab_get_derot_freq=0x%x\n", tmp);
2987
2988 if ((QAM_Lock == 0x0c) || (QAM_Lock == 0x0b)) {
2989 /* Wait for FEC lock */
2990 LockTime = 0;
2991 do {
2992 usleep_range(5000, 7000);
2993 LockTime += 5;
2994 QAMFEC_Lock = stv0367_readbits(state,
2995 F367CAB_QAMFEC_LOCK);
2996 } while (!QAMFEC_Lock && (LockTime < FECTimeOut));
2997 } else
2998 QAMFEC_Lock = 0;
2999
3000 if (QAMFEC_Lock) {
3001 signalType = FE_CAB_DATAOK;
3002 cab_state->modulation = p->modulation;
3003 cab_state->spect_inv = stv0367_readbits(state,
3004 F367CAB_QUAD_INV);
3005 #if 0
3006 /* not clear for me */
3007 if (state->config->if_khz != 0) {
3008 if (state->config->if_khz > cab_state->adc_clk / 1000) {
3009 cab_state->freq_khz =
3010 FE_Cab_TunerGetFrequency(pIntParams->hTuner)
3011 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3012 - cab_state->adc_clk / 1000 + state->config->if_khz;
3013 } else {
3014 cab_state->freq_khz =
3015 FE_Cab_TunerGetFrequency(pIntParams->hTuner)
3016 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3017 + state->config->if_khz;
3018 }
3019 } else {
3020 cab_state->freq_khz =
3021 FE_Cab_TunerGetFrequency(pIntParams->hTuner) +
3022 stv0367cab_get_derot_freq(state,
3023 cab_state->adc_clk) -
3024 cab_state->adc_clk / 4000;
3025 }
3026 #endif
3027 cab_state->symbol_rate = stv0367cab_GetSymbolRate(state,
3028 cab_state->mclk);
3029 cab_state->locked = 1;
3030
3031 /* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/
3032 } else {
3033 switch (QAM_Lock) {
3034 case 1:
3035 signalType = FE_CAB_NOAGC;
3036 break;
3037 case 2:
3038 signalType = FE_CAB_NOTIMING;
3039 break;
3040 case 3:
3041 signalType = FE_CAB_TIMINGOK;
3042 break;
3043 case 4:
3044 signalType = FE_CAB_NOCARRIER;
3045 break;
3046 case 5:
3047 signalType = FE_CAB_CARRIEROK;
3048 break;
3049 case 7:
3050 signalType = FE_CAB_NOBLIND;
3051 break;
3052 case 8:
3053 signalType = FE_CAB_BLINDOK;
3054 break;
3055 case 10:
3056 signalType = FE_CAB_NODEMOD;
3057 break;
3058 case 11:
3059 signalType = FE_CAB_DEMODOK;
3060 break;
3061 case 12:
3062 signalType = FE_CAB_DEMODOK;
3063 break;
3064 case 13:
3065 signalType = FE_CAB_NODEMOD;
3066 break;
3067 case 14:
3068 signalType = FE_CAB_NOBLIND;
3069 break;
3070 case 15:
3071 signalType = FE_CAB_NOSIGNAL;
3072 break;
3073 default:
3074 break;
3075 }
3076
3077 }
3078
3079 /* Set the AGC control values to tracking values */
3080 stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum);
3081 return signalType;
3082 }
3083
3084 static int stv0367cab_set_frontend(struct dvb_frontend *fe)
3085 {
3086 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3087 struct stv0367_state *state = fe->demodulator_priv;
3088 struct stv0367cab_state *cab_state = state->cab_state;
3089 enum stv0367cab_mod QAMSize = 0;
3090
3091 dprintk("%s: freq = %d, srate = %d\n", __func__,
3092 p->frequency, p->symbol_rate);
3093
3094 cab_state->derot_offset = 0;
3095
3096 switch (p->modulation) {
3097 case QAM_16:
3098 QAMSize = FE_CAB_MOD_QAM16;
3099 break;
3100 case QAM_32:
3101 QAMSize = FE_CAB_MOD_QAM32;
3102 break;
3103 case QAM_64:
3104 QAMSize = FE_CAB_MOD_QAM64;
3105 break;
3106 case QAM_128:
3107 QAMSize = FE_CAB_MOD_QAM128;
3108 break;
3109 case QAM_256:
3110 QAMSize = FE_CAB_MOD_QAM256;
3111 break;
3112 default:
3113 break;
3114 }
3115
3116 stv0367cab_init(fe);
3117
3118 /* Tuner Frequency Setting */
3119 if (fe->ops.tuner_ops.set_params) {
3120 if (fe->ops.i2c_gate_ctrl)
3121 fe->ops.i2c_gate_ctrl(fe, 1);
3122 fe->ops.tuner_ops.set_params(fe);
3123 if (fe->ops.i2c_gate_ctrl)
3124 fe->ops.i2c_gate_ctrl(fe, 0);
3125 }
3126
3127 stv0367cab_SetQamSize(
3128 state,
3129 p->symbol_rate,
3130 QAMSize);
3131
3132 stv0367cab_set_srate(state,
3133 cab_state->adc_clk,
3134 cab_state->mclk,
3135 p->symbol_rate,
3136 QAMSize);
3137 /* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */
3138 cab_state->state = stv0367cab_algo(state, p);
3139 return 0;
3140 }
3141
3142 static int stv0367cab_get_frontend(struct dvb_frontend *fe)
3143 {
3144 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3145 struct stv0367_state *state = fe->demodulator_priv;
3146 struct stv0367cab_state *cab_state = state->cab_state;
3147
3148 enum stv0367cab_mod QAMSize;
3149
3150 dprintk("%s:\n", __func__);
3151
3152 p->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk);
3153
3154 QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
3155 switch (QAMSize) {
3156 case FE_CAB_MOD_QAM16:
3157 p->modulation = QAM_16;
3158 break;
3159 case FE_CAB_MOD_QAM32:
3160 p->modulation = QAM_32;
3161 break;
3162 case FE_CAB_MOD_QAM64:
3163 p->modulation = QAM_64;
3164 break;
3165 case FE_CAB_MOD_QAM128:
3166 p->modulation = QAM_128;
3167 break;
3168 case QAM_256:
3169 p->modulation = QAM_256;
3170 break;
3171 default:
3172 break;
3173 }
3174
3175 p->frequency = stv0367_get_tuner_freq(fe);
3176
3177 dprintk("%s: tuner frequency = %d\n", __func__, p->frequency);
3178
3179 if (state->config->if_khz == 0) {
3180 p->frequency +=
3181 (stv0367cab_get_derot_freq(state, cab_state->adc_clk) -
3182 cab_state->adc_clk / 4000);
3183 return 0;
3184 }
3185
3186 if (state->config->if_khz > cab_state->adc_clk / 1000)
3187 p->frequency += (state->config->if_khz
3188 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3189 - cab_state->adc_clk / 1000);
3190 else
3191 p->frequency += (state->config->if_khz
3192 - stv0367cab_get_derot_freq(state, cab_state->adc_clk));
3193
3194 return 0;
3195 }
3196
3197 #if 0
3198 void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize,
3199 u32 symbol_rate, FE_367qam_Monitor *Monitor_results)
3200 {
3201 stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results);
3202 stv0367cab_GetPacketsCount(state, Monitor_results);
3203
3204 return;
3205 }
3206
3207 static int stv0367cab_read_ber(struct dvb_frontend *fe, u32 *ber)
3208 {
3209 struct stv0367_state *state = fe->demodulator_priv;
3210
3211 return 0;
3212 }
3213 #endif
3214 static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state)
3215 {
3216 s32 rfLevel = 0;
3217 s32 RfAgcPwm = 0, IfAgcPwm = 0;
3218 u8 i;
3219
3220 stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0);
3221
3222 RfAgcPwm =
3223 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) +
3224 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2);
3225 RfAgcPwm = 100 * RfAgcPwm / 1023;
3226
3227 IfAgcPwm =
3228 stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) +
3229 (stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8);
3230 if (IfAgcPwm >= 2048)
3231 IfAgcPwm -= 2048;
3232 else
3233 IfAgcPwm += 2048;
3234
3235 IfAgcPwm = 100 * IfAgcPwm / 4095;
3236
3237 /* For DTT75467 on NIM */
3238 if (RfAgcPwm < 90 && IfAgcPwm < 28) {
3239 for (i = 0; i < RF_LOOKUP_TABLE_SIZE; i++) {
3240 if (RfAgcPwm <= stv0367cab_RF_LookUp1[0][i]) {
3241 rfLevel = (-1) * stv0367cab_RF_LookUp1[1][i];
3242 break;
3243 }
3244 }
3245 if (i == RF_LOOKUP_TABLE_SIZE)
3246 rfLevel = -56;
3247 } else { /*if IF AGC>10*/
3248 for (i = 0; i < RF_LOOKUP_TABLE2_SIZE; i++) {
3249 if (IfAgcPwm <= stv0367cab_RF_LookUp2[0][i]) {
3250 rfLevel = (-1) * stv0367cab_RF_LookUp2[1][i];
3251 break;
3252 }
3253 }
3254 if (i == RF_LOOKUP_TABLE2_SIZE)
3255 rfLevel = -72;
3256 }
3257 return rfLevel;
3258 }
3259
3260 static int stv0367cab_read_strength(struct dvb_frontend *fe, u16 *strength)
3261 {
3262 struct stv0367_state *state = fe->demodulator_priv;
3263
3264 s32 signal = stv0367cab_get_rf_lvl(state);
3265
3266 dprintk("%s: signal=%d dBm\n", __func__, signal);
3267
3268 if (signal <= -72)
3269 *strength = 65535;
3270 else
3271 *strength = (22 + signal) * (-1311);
3272
3273 dprintk("%s: strength=%d\n", __func__, (*strength));
3274
3275 return 0;
3276 }
3277
3278 static int stv0367cab_read_snr(struct dvb_frontend *fe, u16 *snr)
3279 {
3280 struct stv0367_state *state = fe->demodulator_priv;
3281 u32 noisepercentage;
3282 enum stv0367cab_mod QAMSize;
3283 u32 regval = 0, temp = 0;
3284 int power, i;
3285
3286 QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
3287 switch (QAMSize) {
3288 case FE_CAB_MOD_QAM4:
3289 power = 21904;
3290 break;
3291 case FE_CAB_MOD_QAM16:
3292 power = 20480;
3293 break;
3294 case FE_CAB_MOD_QAM32:
3295 power = 23040;
3296 break;
3297 case FE_CAB_MOD_QAM64:
3298 power = 21504;
3299 break;
3300 case FE_CAB_MOD_QAM128:
3301 power = 23616;
3302 break;
3303 case FE_CAB_MOD_QAM256:
3304 power = 21760;
3305 break;
3306 case FE_CAB_MOD_QAM512:
3307 power = 1;
3308 break;
3309 case FE_CAB_MOD_QAM1024:
3310 power = 21280;
3311 break;
3312 default:
3313 power = 1;
3314 break;
3315 }
3316
3317 for (i = 0; i < 10; i++) {
3318 regval += (stv0367_readbits(state, F367CAB_SNR_LO)
3319 + 256 * stv0367_readbits(state, F367CAB_SNR_HI));
3320 }
3321
3322 regval /= 10; /*for average over 10 times in for loop above*/
3323 if (regval != 0) {
3324 temp = power
3325 * (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER)));
3326 temp /= regval;
3327 }
3328
3329 /* table values, not needed to calculate logarithms */
3330 if (temp >= 5012)
3331 noisepercentage = 100;
3332 else if (temp >= 3981)
3333 noisepercentage = 93;
3334 else if (temp >= 3162)
3335 noisepercentage = 86;
3336 else if (temp >= 2512)
3337 noisepercentage = 79;
3338 else if (temp >= 1995)
3339 noisepercentage = 72;
3340 else if (temp >= 1585)
3341 noisepercentage = 65;
3342 else if (temp >= 1259)
3343 noisepercentage = 58;
3344 else if (temp >= 1000)
3345 noisepercentage = 50;
3346 else if (temp >= 794)
3347 noisepercentage = 43;
3348 else if (temp >= 501)
3349 noisepercentage = 36;
3350 else if (temp >= 316)
3351 noisepercentage = 29;
3352 else if (temp >= 200)
3353 noisepercentage = 22;
3354 else if (temp >= 158)
3355 noisepercentage = 14;
3356 else if (temp >= 126)
3357 noisepercentage = 7;
3358 else
3359 noisepercentage = 0;
3360
3361 dprintk("%s: noisepercentage=%d\n", __func__, noisepercentage);
3362
3363 *snr = (noisepercentage * 65535) / 100;
3364
3365 return 0;
3366 }
3367
3368 static int stv0367cab_read_ucblcks(struct dvb_frontend *fe, u32 *ucblocks)
3369 {
3370 struct stv0367_state *state = fe->demodulator_priv;
3371 int corrected, tscount;
3372
3373 *ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8)
3374 | stv0367_readreg(state, R367CAB_RS_COUNTER_4);
3375 corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8)
3376 | stv0367_readreg(state, R367CAB_RS_COUNTER_2);
3377 tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8)
3378 | stv0367_readreg(state, R367CAB_RS_COUNTER_1);
3379
3380 dprintk("%s: uncorrected blocks=%d corrected blocks=%d tscount=%d\n",
3381 __func__, *ucblocks, corrected, tscount);
3382
3383 return 0;
3384 };
3385
3386 static struct dvb_frontend_ops stv0367cab_ops = {
3387 .delsys = { SYS_DVBC_ANNEX_A },
3388 .info = {
3389 .name = "ST STV0367 DVB-C",
3390 .frequency_min = 47000000,
3391 .frequency_max = 862000000,
3392 .frequency_stepsize = 62500,
3393 .symbol_rate_min = 870000,
3394 .symbol_rate_max = 11700000,
3395 .caps = 0x400 |/* FE_CAN_QAM_4 */
3396 FE_CAN_QAM_16 | FE_CAN_QAM_32 |
3397 FE_CAN_QAM_64 | FE_CAN_QAM_128 |
3398 FE_CAN_QAM_256 | FE_CAN_FEC_AUTO
3399 },
3400 .release = stv0367_release,
3401 .init = stv0367cab_init,
3402 .sleep = stv0367cab_sleep,
3403 .i2c_gate_ctrl = stv0367cab_gate_ctrl,
3404 .set_frontend = stv0367cab_set_frontend,
3405 .get_frontend = stv0367cab_get_frontend,
3406 .read_status = stv0367cab_read_status,
3407 /* .read_ber = stv0367cab_read_ber, */
3408 .read_signal_strength = stv0367cab_read_strength,
3409 .read_snr = stv0367cab_read_snr,
3410 .read_ucblocks = stv0367cab_read_ucblcks,
3411 .get_tune_settings = stv0367_get_tune_settings,
3412 };
3413
3414 struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
3415 struct i2c_adapter *i2c)
3416 {
3417 struct stv0367_state *state = NULL;
3418 struct stv0367cab_state *cab_state = NULL;
3419
3420 /* allocate memory for the internal state */
3421 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
3422 if (state == NULL)
3423 goto error;
3424 cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
3425 if (cab_state == NULL)
3426 goto error;
3427
3428 /* setup the state */
3429 state->i2c = i2c;
3430 state->config = config;
3431 cab_state->search_range = 280000;
3432 state->cab_state = cab_state;
3433 state->fe.ops = stv0367cab_ops;
3434 state->fe.demodulator_priv = state;
3435 state->chip_id = stv0367_readreg(state, 0xf000);
3436
3437 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
3438
3439 /* check if the demod is there */
3440 if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
3441 goto error;
3442
3443 return &state->fe;
3444
3445 error:
3446 kfree(cab_state);
3447 kfree(state);
3448 return NULL;
3449 }
3450 EXPORT_SYMBOL(stv0367cab_attach);
3451
3452 MODULE_PARM_DESC(debug, "Set debug");
3453 MODULE_PARM_DESC(i2c_debug, "Set i2c debug");
3454
3455 MODULE_AUTHOR("Igor M. Liplianin");
3456 MODULE_DESCRIPTION("ST STV0367 DVB-C/T demodulator driver");
3457 MODULE_LICENSE("GPL");
(deprecated) Btrfs devel tree