2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
33 #include <linux/irq.h>
34 #include <linux/completion.h>
36 #include <linux/of_device.h>
37 #include <linux/of_mtd.h>
39 #include <asm/mach/flash.h>
40 #include <linux/platform_data/mtd-mxc_nand.h>
42 #define DRIVER_NAME "mxc_nand"
44 /* Addresses for NFC registers */
45 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
46 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
47 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
48 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
49 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
50 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
51 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
52 #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
53 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
54 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
55 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
56 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
57 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
58 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
59 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
60 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
61 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
62 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
63 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
64 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
65 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
66 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
68 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
69 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
70 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
71 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
72 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
73 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
74 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
75 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
76 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
77 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
79 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
82 * Operation modes for the NFC. Valid for v1, v2 and v3
85 #define NFC_CMD (1 << 0)
86 #define NFC_ADDR (1 << 1)
87 #define NFC_INPUT (1 << 2)
88 #define NFC_OUTPUT (1 << 3)
89 #define NFC_ID (1 << 4)
90 #define NFC_STATUS (1 << 5)
92 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
93 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
95 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
96 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
97 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
99 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
101 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
103 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
104 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
105 #define NFC_V3_WRPROT_LOCK (1 << 1)
106 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
107 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
109 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
111 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
112 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
113 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
114 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
115 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
116 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
117 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
118 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
119 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
120 #define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift)
121 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
122 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
123 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
124 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
126 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
127 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
128 #define NFC_V3_CONFIG3_FW8 (1 << 3)
129 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
130 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
131 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
132 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
134 #define NFC_V3_IPC (host->regs_ip + 0x2C)
135 #define NFC_V3_IPC_CREQ (1 << 0)
136 #define NFC_V3_IPC_INT (1 << 31)
138 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
140 struct mxc_nand_host
;
142 struct mxc_nand_devtype_data
{
143 void (*preset
)(struct mtd_info
*);
144 void (*send_cmd
)(struct mxc_nand_host
*, uint16_t, int);
145 void (*send_addr
)(struct mxc_nand_host
*, uint16_t, int);
146 void (*send_page
)(struct mtd_info
*, unsigned int);
147 void (*send_read_id
)(struct mxc_nand_host
*);
148 uint16_t (*get_dev_status
)(struct mxc_nand_host
*);
149 int (*check_int
)(struct mxc_nand_host
*);
150 void (*irq_control
)(struct mxc_nand_host
*, int);
151 u32 (*get_ecc_status
)(struct mxc_nand_host
*);
152 struct nand_ecclayout
*ecclayout_512
, *ecclayout_2k
, *ecclayout_4k
;
153 void (*select_chip
)(struct mtd_info
*mtd
, int chip
);
154 int (*correct_data
)(struct mtd_info
*mtd
, u_char
*dat
,
155 u_char
*read_ecc
, u_char
*calc_ecc
);
158 * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
159 * (CONFIG1:INT_MSK is set). To handle this the driver uses
160 * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
162 int irqpending_quirk
;
166 size_t spare0_offset
;
175 struct mxc_nand_host
{
177 struct nand_chip nand
;
180 void __iomem
*spare0
;
181 void __iomem
*main_area0
;
185 void __iomem
*regs_axi
;
186 void __iomem
*regs_ip
;
194 struct completion op_completion
;
197 unsigned int buf_start
;
199 const struct mxc_nand_devtype_data
*devtype_data
;
200 struct mxc_nand_platform_data pdata
;
203 /* OOB placement block for use with hardware ecc generation */
204 static struct nand_ecclayout nandv1_hw_eccoob_smallpage
= {
206 .eccpos
= {6, 7, 8, 9, 10},
207 .oobfree
= {{0, 5}, {12, 4}, }
210 static struct nand_ecclayout nandv1_hw_eccoob_largepage
= {
212 .eccpos
= {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
213 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
214 .oobfree
= {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
217 /* OOB description for 512 byte pages with 16 byte OOB */
218 static struct nand_ecclayout nandv2_hw_eccoob_smallpage
= {
221 7, 8, 9, 10, 11, 12, 13, 14, 15
224 {.offset
= 0, .length
= 5}
228 /* OOB description for 2048 byte pages with 64 byte OOB */
229 static struct nand_ecclayout nandv2_hw_eccoob_largepage
= {
232 7, 8, 9, 10, 11, 12, 13, 14, 15,
233 23, 24, 25, 26, 27, 28, 29, 30, 31,
234 39, 40, 41, 42, 43, 44, 45, 46, 47,
235 55, 56, 57, 58, 59, 60, 61, 62, 63
238 {.offset
= 2, .length
= 4},
239 {.offset
= 16, .length
= 7},
240 {.offset
= 32, .length
= 7},
241 {.offset
= 48, .length
= 7}
245 /* OOB description for 4096 byte pages with 128 byte OOB */
246 static struct nand_ecclayout nandv2_hw_eccoob_4k
= {
249 7, 8, 9, 10, 11, 12, 13, 14, 15,
250 23, 24, 25, 26, 27, 28, 29, 30, 31,
251 39, 40, 41, 42, 43, 44, 45, 46, 47,
252 55, 56, 57, 58, 59, 60, 61, 62, 63,
253 71, 72, 73, 74, 75, 76, 77, 78, 79,
254 87, 88, 89, 90, 91, 92, 93, 94, 95,
255 103, 104, 105, 106, 107, 108, 109, 110, 111,
256 119, 120, 121, 122, 123, 124, 125, 126, 127,
259 {.offset
= 2, .length
= 4},
260 {.offset
= 16, .length
= 7},
261 {.offset
= 32, .length
= 7},
262 {.offset
= 48, .length
= 7},
263 {.offset
= 64, .length
= 7},
264 {.offset
= 80, .length
= 7},
265 {.offset
= 96, .length
= 7},
266 {.offset
= 112, .length
= 7},
270 static const char * const part_probes
[] = {
271 "cmdlinepart", "RedBoot", "ofpart", NULL
};
273 static void memcpy32_fromio(void *trg
, const void __iomem
*src
, size_t size
)
277 const __iomem u32
*s
= src
;
279 for (i
= 0; i
< (size
>> 2); i
++)
280 *t
++ = __raw_readl(s
++);
283 static void memcpy32_toio(void __iomem
*trg
, const void *src
, int size
)
286 u32 __iomem
*t
= trg
;
289 for (i
= 0; i
< (size
>> 2); i
++)
290 __raw_writel(*s
++, t
++);
293 static int check_int_v3(struct mxc_nand_host
*host
)
297 tmp
= readl(NFC_V3_IPC
);
298 if (!(tmp
& NFC_V3_IPC_INT
))
301 tmp
&= ~NFC_V3_IPC_INT
;
302 writel(tmp
, NFC_V3_IPC
);
307 static int check_int_v1_v2(struct mxc_nand_host
*host
)
311 tmp
= readw(NFC_V1_V2_CONFIG2
);
312 if (!(tmp
& NFC_V1_V2_CONFIG2_INT
))
315 if (!host
->devtype_data
->irqpending_quirk
)
316 writew(tmp
& ~NFC_V1_V2_CONFIG2_INT
, NFC_V1_V2_CONFIG2
);
321 static void irq_control_v1_v2(struct mxc_nand_host
*host
, int activate
)
325 tmp
= readw(NFC_V1_V2_CONFIG1
);
328 tmp
&= ~NFC_V1_V2_CONFIG1_INT_MSK
;
330 tmp
|= NFC_V1_V2_CONFIG1_INT_MSK
;
332 writew(tmp
, NFC_V1_V2_CONFIG1
);
335 static void irq_control_v3(struct mxc_nand_host
*host
, int activate
)
339 tmp
= readl(NFC_V3_CONFIG2
);
342 tmp
&= ~NFC_V3_CONFIG2_INT_MSK
;
344 tmp
|= NFC_V3_CONFIG2_INT_MSK
;
346 writel(tmp
, NFC_V3_CONFIG2
);
349 static void irq_control(struct mxc_nand_host
*host
, int activate
)
351 if (host
->devtype_data
->irqpending_quirk
) {
353 enable_irq(host
->irq
);
355 disable_irq_nosync(host
->irq
);
357 host
->devtype_data
->irq_control(host
, activate
);
361 static u32
get_ecc_status_v1(struct mxc_nand_host
*host
)
363 return readw(NFC_V1_V2_ECC_STATUS_RESULT
);
366 static u32
get_ecc_status_v2(struct mxc_nand_host
*host
)
368 return readl(NFC_V1_V2_ECC_STATUS_RESULT
);
371 static u32
get_ecc_status_v3(struct mxc_nand_host
*host
)
373 return readl(NFC_V3_ECC_STATUS_RESULT
);
376 static irqreturn_t
mxc_nfc_irq(int irq
, void *dev_id
)
378 struct mxc_nand_host
*host
= dev_id
;
380 if (!host
->devtype_data
->check_int(host
))
383 irq_control(host
, 0);
385 complete(&host
->op_completion
);
390 /* This function polls the NANDFC to wait for the basic operation to
391 * complete by checking the INT bit of config2 register.
393 static void wait_op_done(struct mxc_nand_host
*host
, int useirq
)
395 int max_retries
= 8000;
398 if (!host
->devtype_data
->check_int(host
)) {
399 reinit_completion(&host
->op_completion
);
400 irq_control(host
, 1);
401 wait_for_completion(&host
->op_completion
);
404 while (max_retries
-- > 0) {
405 if (host
->devtype_data
->check_int(host
))
411 pr_debug("%s: INT not set\n", __func__
);
415 static void send_cmd_v3(struct mxc_nand_host
*host
, uint16_t cmd
, int useirq
)
418 writel(cmd
, NFC_V3_FLASH_CMD
);
420 /* send out command */
421 writel(NFC_CMD
, NFC_V3_LAUNCH
);
423 /* Wait for operation to complete */
424 wait_op_done(host
, useirq
);
427 /* This function issues the specified command to the NAND device and
428 * waits for completion. */
429 static void send_cmd_v1_v2(struct mxc_nand_host
*host
, uint16_t cmd
, int useirq
)
431 pr_debug("send_cmd(host, 0x%x, %d)\n", cmd
, useirq
);
433 writew(cmd
, NFC_V1_V2_FLASH_CMD
);
434 writew(NFC_CMD
, NFC_V1_V2_CONFIG2
);
436 if (host
->devtype_data
->irqpending_quirk
&& (cmd
== NAND_CMD_RESET
)) {
437 int max_retries
= 100;
438 /* Reset completion is indicated by NFC_CONFIG2 */
440 while (max_retries
-- > 0) {
441 if (readw(NFC_V1_V2_CONFIG2
) == 0) {
447 pr_debug("%s: RESET failed\n", __func__
);
449 /* Wait for operation to complete */
450 wait_op_done(host
, useirq
);
454 static void send_addr_v3(struct mxc_nand_host
*host
, uint16_t addr
, int islast
)
457 writel(addr
, NFC_V3_FLASH_ADDR0
);
459 /* send out address */
460 writel(NFC_ADDR
, NFC_V3_LAUNCH
);
462 wait_op_done(host
, 0);
465 /* This function sends an address (or partial address) to the
466 * NAND device. The address is used to select the source/destination for
468 static void send_addr_v1_v2(struct mxc_nand_host
*host
, uint16_t addr
, int islast
)
470 pr_debug("send_addr(host, 0x%x %d)\n", addr
, islast
);
472 writew(addr
, NFC_V1_V2_FLASH_ADDR
);
473 writew(NFC_ADDR
, NFC_V1_V2_CONFIG2
);
475 /* Wait for operation to complete */
476 wait_op_done(host
, islast
);
479 static void send_page_v3(struct mtd_info
*mtd
, unsigned int ops
)
481 struct nand_chip
*nand_chip
= mtd
->priv
;
482 struct mxc_nand_host
*host
= nand_chip
->priv
;
485 tmp
= readl(NFC_V3_CONFIG1
);
487 writel(tmp
, NFC_V3_CONFIG1
);
489 /* transfer data from NFC ram to nand */
490 writel(ops
, NFC_V3_LAUNCH
);
492 wait_op_done(host
, false);
495 static void send_page_v2(struct mtd_info
*mtd
, unsigned int ops
)
497 struct nand_chip
*nand_chip
= mtd
->priv
;
498 struct mxc_nand_host
*host
= nand_chip
->priv
;
500 /* NANDFC buffer 0 is used for page read/write */
501 writew(host
->active_cs
<< 4, NFC_V1_V2_BUF_ADDR
);
503 writew(ops
, NFC_V1_V2_CONFIG2
);
505 /* Wait for operation to complete */
506 wait_op_done(host
, true);
509 static void send_page_v1(struct mtd_info
*mtd
, unsigned int ops
)
511 struct nand_chip
*nand_chip
= mtd
->priv
;
512 struct mxc_nand_host
*host
= nand_chip
->priv
;
515 if (mtd
->writesize
> 512)
520 for (i
= 0; i
< bufs
; i
++) {
522 /* NANDFC buffer 0 is used for page read/write */
523 writew((host
->active_cs
<< 4) | i
, NFC_V1_V2_BUF_ADDR
);
525 writew(ops
, NFC_V1_V2_CONFIG2
);
527 /* Wait for operation to complete */
528 wait_op_done(host
, true);
532 static void send_read_id_v3(struct mxc_nand_host
*host
)
534 struct nand_chip
*this = &host
->nand
;
536 /* Read ID into main buffer */
537 writel(NFC_ID
, NFC_V3_LAUNCH
);
539 wait_op_done(host
, true);
541 memcpy32_fromio(host
->data_buf
, host
->main_area0
, 16);
543 if (this->options
& NAND_BUSWIDTH_16
) {
544 /* compress the ID info */
545 host
->data_buf
[1] = host
->data_buf
[2];
546 host
->data_buf
[2] = host
->data_buf
[4];
547 host
->data_buf
[3] = host
->data_buf
[6];
548 host
->data_buf
[4] = host
->data_buf
[8];
549 host
->data_buf
[5] = host
->data_buf
[10];
553 /* Request the NANDFC to perform a read of the NAND device ID. */
554 static void send_read_id_v1_v2(struct mxc_nand_host
*host
)
556 struct nand_chip
*this = &host
->nand
;
558 /* NANDFC buffer 0 is used for device ID output */
559 writew(host
->active_cs
<< 4, NFC_V1_V2_BUF_ADDR
);
561 writew(NFC_ID
, NFC_V1_V2_CONFIG2
);
563 /* Wait for operation to complete */
564 wait_op_done(host
, true);
566 memcpy32_fromio(host
->data_buf
, host
->main_area0
, 16);
568 if (this->options
& NAND_BUSWIDTH_16
) {
569 /* compress the ID info */
570 host
->data_buf
[1] = host
->data_buf
[2];
571 host
->data_buf
[2] = host
->data_buf
[4];
572 host
->data_buf
[3] = host
->data_buf
[6];
573 host
->data_buf
[4] = host
->data_buf
[8];
574 host
->data_buf
[5] = host
->data_buf
[10];
578 static uint16_t get_dev_status_v3(struct mxc_nand_host
*host
)
580 writew(NFC_STATUS
, NFC_V3_LAUNCH
);
581 wait_op_done(host
, true);
583 return readl(NFC_V3_CONFIG1
) >> 16;
586 /* This function requests the NANDFC to perform a read of the
587 * NAND device status and returns the current status. */
588 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host
*host
)
590 void __iomem
*main_buf
= host
->main_area0
;
594 writew(host
->active_cs
<< 4, NFC_V1_V2_BUF_ADDR
);
597 * The device status is stored in main_area0. To
598 * prevent corruption of the buffer save the value
599 * and restore it afterwards.
601 store
= readl(main_buf
);
603 writew(NFC_STATUS
, NFC_V1_V2_CONFIG2
);
604 wait_op_done(host
, true);
606 ret
= readw(main_buf
);
608 writel(store
, main_buf
);
613 /* This functions is used by upper layer to checks if device is ready */
614 static int mxc_nand_dev_ready(struct mtd_info
*mtd
)
617 * NFC handles R/B internally. Therefore, this function
618 * always returns status as ready.
623 static void mxc_nand_enable_hwecc(struct mtd_info
*mtd
, int mode
)
626 * If HW ECC is enabled, we turn it on during init. There is
627 * no need to enable again here.
631 static int mxc_nand_correct_data_v1(struct mtd_info
*mtd
, u_char
*dat
,
632 u_char
*read_ecc
, u_char
*calc_ecc
)
634 struct nand_chip
*nand_chip
= mtd
->priv
;
635 struct mxc_nand_host
*host
= nand_chip
->priv
;
638 * 1-Bit errors are automatically corrected in HW. No need for
639 * additional correction. 2-Bit errors cannot be corrected by
640 * HW ECC, so we need to return failure
642 uint16_t ecc_status
= get_ecc_status_v1(host
);
644 if (((ecc_status
& 0x3) == 2) || ((ecc_status
>> 2) == 2)) {
645 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
652 static int mxc_nand_correct_data_v2_v3(struct mtd_info
*mtd
, u_char
*dat
,
653 u_char
*read_ecc
, u_char
*calc_ecc
)
655 struct nand_chip
*nand_chip
= mtd
->priv
;
656 struct mxc_nand_host
*host
= nand_chip
->priv
;
660 u8 ecc_bit_mask
, err_limit
;
662 ecc_bit_mask
= (host
->eccsize
== 4) ? 0x7 : 0xf;
663 err_limit
= (host
->eccsize
== 4) ? 0x4 : 0x8;
665 no_subpages
= mtd
->writesize
>> 9;
667 ecc_stat
= host
->devtype_data
->get_ecc_status(host
);
670 err
= ecc_stat
& ecc_bit_mask
;
671 if (err
> err_limit
) {
672 printk(KERN_WARNING
"UnCorrectable RS-ECC Error\n");
678 } while (--no_subpages
);
680 mtd
->ecc_stats
.corrected
+= ret
;
681 pr_debug("%d Symbol Correctable RS-ECC Error\n", ret
);
686 static int mxc_nand_calculate_ecc(struct mtd_info
*mtd
, const u_char
*dat
,
692 static u_char
mxc_nand_read_byte(struct mtd_info
*mtd
)
694 struct nand_chip
*nand_chip
= mtd
->priv
;
695 struct mxc_nand_host
*host
= nand_chip
->priv
;
698 /* Check for status request */
699 if (host
->status_request
)
700 return host
->devtype_data
->get_dev_status(host
) & 0xFF;
702 ret
= *(uint8_t *)(host
->data_buf
+ host
->buf_start
);
708 static uint16_t mxc_nand_read_word(struct mtd_info
*mtd
)
710 struct nand_chip
*nand_chip
= mtd
->priv
;
711 struct mxc_nand_host
*host
= nand_chip
->priv
;
714 ret
= *(uint16_t *)(host
->data_buf
+ host
->buf_start
);
715 host
->buf_start
+= 2;
720 /* Write data of length len to buffer buf. The data to be
721 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
722 * Operation by the NFC, the data is written to NAND Flash */
723 static void mxc_nand_write_buf(struct mtd_info
*mtd
,
724 const u_char
*buf
, int len
)
726 struct nand_chip
*nand_chip
= mtd
->priv
;
727 struct mxc_nand_host
*host
= nand_chip
->priv
;
728 u16 col
= host
->buf_start
;
729 int n
= mtd
->oobsize
+ mtd
->writesize
- col
;
733 memcpy(host
->data_buf
+ col
, buf
, n
);
735 host
->buf_start
+= n
;
738 /* Read the data buffer from the NAND Flash. To read the data from NAND
739 * Flash first the data output cycle is initiated by the NFC, which copies
740 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
742 static void mxc_nand_read_buf(struct mtd_info
*mtd
, u_char
*buf
, int len
)
744 struct nand_chip
*nand_chip
= mtd
->priv
;
745 struct mxc_nand_host
*host
= nand_chip
->priv
;
746 u16 col
= host
->buf_start
;
747 int n
= mtd
->oobsize
+ mtd
->writesize
- col
;
751 memcpy(buf
, host
->data_buf
+ col
, n
);
753 host
->buf_start
+= n
;
756 /* This function is used by upper layer for select and
757 * deselect of the NAND chip */
758 static void mxc_nand_select_chip_v1_v3(struct mtd_info
*mtd
, int chip
)
760 struct nand_chip
*nand_chip
= mtd
->priv
;
761 struct mxc_nand_host
*host
= nand_chip
->priv
;
764 /* Disable the NFC clock */
766 clk_disable_unprepare(host
->clk
);
772 if (!host
->clk_act
) {
773 /* Enable the NFC clock */
774 clk_prepare_enable(host
->clk
);
779 static void mxc_nand_select_chip_v2(struct mtd_info
*mtd
, int chip
)
781 struct nand_chip
*nand_chip
= mtd
->priv
;
782 struct mxc_nand_host
*host
= nand_chip
->priv
;
785 /* Disable the NFC clock */
787 clk_disable_unprepare(host
->clk
);
793 if (!host
->clk_act
) {
794 /* Enable the NFC clock */
795 clk_prepare_enable(host
->clk
);
799 host
->active_cs
= chip
;
800 writew(host
->active_cs
<< 4, NFC_V1_V2_BUF_ADDR
);
804 * Function to transfer data to/from spare area.
806 static void copy_spare(struct mtd_info
*mtd
, bool bfrom
)
808 struct nand_chip
*this = mtd
->priv
;
809 struct mxc_nand_host
*host
= this->priv
;
811 u16 n
= mtd
->writesize
>> 9;
812 u8
*d
= host
->data_buf
+ mtd
->writesize
;
813 u8 __iomem
*s
= host
->spare0
;
814 u16 t
= host
->devtype_data
->spare_len
;
816 j
= (mtd
->oobsize
/ n
>> 1) << 1;
819 for (i
= 0; i
< n
- 1; i
++)
820 memcpy32_fromio(d
+ i
* j
, s
+ i
* t
, j
);
822 /* the last section */
823 memcpy32_fromio(d
+ i
* j
, s
+ i
* t
, mtd
->oobsize
- i
* j
);
825 for (i
= 0; i
< n
- 1; i
++)
826 memcpy32_toio(&s
[i
* t
], &d
[i
* j
], j
);
828 /* the last section */
829 memcpy32_toio(&s
[i
* t
], &d
[i
* j
], mtd
->oobsize
- i
* j
);
833 static void mxc_do_addr_cycle(struct mtd_info
*mtd
, int column
, int page_addr
)
835 struct nand_chip
*nand_chip
= mtd
->priv
;
836 struct mxc_nand_host
*host
= nand_chip
->priv
;
838 /* Write out column address, if necessary */
841 * MXC NANDFC can only perform full page+spare or
842 * spare-only read/write. When the upper layers
843 * perform a read/write buf operation, the saved column
844 * address is used to index into the full page.
846 host
->devtype_data
->send_addr(host
, 0, page_addr
== -1);
847 if (mtd
->writesize
> 512)
848 /* another col addr cycle for 2k page */
849 host
->devtype_data
->send_addr(host
, 0, false);
852 /* Write out page address, if necessary */
853 if (page_addr
!= -1) {
854 /* paddr_0 - p_addr_7 */
855 host
->devtype_data
->send_addr(host
, (page_addr
& 0xff), false);
857 if (mtd
->writesize
> 512) {
858 if (mtd
->size
>= 0x10000000) {
859 /* paddr_8 - paddr_15 */
860 host
->devtype_data
->send_addr(host
,
861 (page_addr
>> 8) & 0xff,
863 host
->devtype_data
->send_addr(host
,
864 (page_addr
>> 16) & 0xff,
867 /* paddr_8 - paddr_15 */
868 host
->devtype_data
->send_addr(host
,
869 (page_addr
>> 8) & 0xff, true);
871 /* One more address cycle for higher density devices */
872 if (mtd
->size
>= 0x4000000) {
873 /* paddr_8 - paddr_15 */
874 host
->devtype_data
->send_addr(host
,
875 (page_addr
>> 8) & 0xff,
877 host
->devtype_data
->send_addr(host
,
878 (page_addr
>> 16) & 0xff,
881 /* paddr_8 - paddr_15 */
882 host
->devtype_data
->send_addr(host
,
883 (page_addr
>> 8) & 0xff, true);
889 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
890 * on how much oob the nand chip has. For 8bit ecc we need at least
891 * 26 bytes of oob data per 512 byte block.
893 static int get_eccsize(struct mtd_info
*mtd
)
895 int oobbytes_per_512
= 0;
897 oobbytes_per_512
= mtd
->oobsize
* 512 / mtd
->writesize
;
899 if (oobbytes_per_512
< 26)
905 static void preset_v1(struct mtd_info
*mtd
)
907 struct nand_chip
*nand_chip
= mtd
->priv
;
908 struct mxc_nand_host
*host
= nand_chip
->priv
;
909 uint16_t config1
= 0;
911 if (nand_chip
->ecc
.mode
== NAND_ECC_HW
)
912 config1
|= NFC_V1_V2_CONFIG1_ECC_EN
;
914 if (!host
->devtype_data
->irqpending_quirk
)
915 config1
|= NFC_V1_V2_CONFIG1_INT_MSK
;
919 writew(config1
, NFC_V1_V2_CONFIG1
);
920 /* preset operation */
922 /* Unlock the internal RAM Buffer */
923 writew(0x2, NFC_V1_V2_CONFIG
);
925 /* Blocks to be unlocked */
926 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR
);
927 writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR
);
929 /* Unlock Block Command for given address range */
930 writew(0x4, NFC_V1_V2_WRPROT
);
933 static void preset_v2(struct mtd_info
*mtd
)
935 struct nand_chip
*nand_chip
= mtd
->priv
;
936 struct mxc_nand_host
*host
= nand_chip
->priv
;
937 uint16_t config1
= 0;
939 if (nand_chip
->ecc
.mode
== NAND_ECC_HW
)
940 config1
|= NFC_V1_V2_CONFIG1_ECC_EN
;
942 config1
|= NFC_V2_CONFIG1_FP_INT
;
944 if (!host
->devtype_data
->irqpending_quirk
)
945 config1
|= NFC_V1_V2_CONFIG1_INT_MSK
;
947 if (mtd
->writesize
) {
948 uint16_t pages_per_block
= mtd
->erasesize
/ mtd
->writesize
;
950 host
->eccsize
= get_eccsize(mtd
);
951 if (host
->eccsize
== 4)
952 config1
|= NFC_V2_CONFIG1_ECC_MODE_4
;
954 config1
|= NFC_V2_CONFIG1_PPB(ffs(pages_per_block
) - 6);
959 writew(config1
, NFC_V1_V2_CONFIG1
);
960 /* preset operation */
962 /* Unlock the internal RAM Buffer */
963 writew(0x2, NFC_V1_V2_CONFIG
);
965 /* Blocks to be unlocked */
966 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0
);
967 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1
);
968 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2
);
969 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3
);
970 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0
);
971 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1
);
972 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2
);
973 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3
);
975 /* Unlock Block Command for given address range */
976 writew(0x4, NFC_V1_V2_WRPROT
);
979 static void preset_v3(struct mtd_info
*mtd
)
981 struct nand_chip
*chip
= mtd
->priv
;
982 struct mxc_nand_host
*host
= chip
->priv
;
983 uint32_t config2
, config3
;
986 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1
);
987 writel(NFC_V3_IPC_CREQ
, NFC_V3_IPC
);
989 /* Unlock the internal RAM Buffer */
990 writel(NFC_V3_WRPROT_BLS_UNLOCK
| NFC_V3_WRPROT_UNLOCK
,
993 /* Blocks to be unlocked */
994 for (i
= 0; i
< NAND_MAX_CHIPS
; i
++)
995 writel(0x0 | (0xffff << 16),
996 NFC_V3_WRPROT_UNLOCK_BLK_ADD0
+ (i
<< 2));
998 writel(0, NFC_V3_IPC
);
1000 config2
= NFC_V3_CONFIG2_ONE_CYCLE
|
1001 NFC_V3_CONFIG2_2CMD_PHASES
|
1002 NFC_V3_CONFIG2_SPAS(mtd
->oobsize
>> 1) |
1003 NFC_V3_CONFIG2_ST_CMD(0x70) |
1004 NFC_V3_CONFIG2_INT_MSK
|
1005 NFC_V3_CONFIG2_NUM_ADDR_PHASE0
;
1007 if (chip
->ecc
.mode
== NAND_ECC_HW
)
1008 config2
|= NFC_V3_CONFIG2_ECC_EN
;
1010 addr_phases
= fls(chip
->pagemask
) >> 3;
1012 if (mtd
->writesize
== 2048) {
1013 config2
|= NFC_V3_CONFIG2_PS_2048
;
1014 config2
|= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases
);
1015 } else if (mtd
->writesize
== 4096) {
1016 config2
|= NFC_V3_CONFIG2_PS_4096
;
1017 config2
|= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases
);
1019 config2
|= NFC_V3_CONFIG2_PS_512
;
1020 config2
|= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases
- 1);
1023 if (mtd
->writesize
) {
1024 config2
|= NFC_V3_CONFIG2_PPB(
1025 ffs(mtd
->erasesize
/ mtd
->writesize
) - 6,
1026 host
->devtype_data
->ppb_shift
);
1027 host
->eccsize
= get_eccsize(mtd
);
1028 if (host
->eccsize
== 8)
1029 config2
|= NFC_V3_CONFIG2_ECC_MODE_8
;
1032 writel(config2
, NFC_V3_CONFIG2
);
1034 config3
= NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1035 NFC_V3_CONFIG3_NO_SDMA
|
1036 NFC_V3_CONFIG3_RBB_MODE
|
1037 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1038 NFC_V3_CONFIG3_ADD_OP(0);
1040 if (!(chip
->options
& NAND_BUSWIDTH_16
))
1041 config3
|= NFC_V3_CONFIG3_FW8
;
1043 writel(config3
, NFC_V3_CONFIG3
);
1045 writel(0, NFC_V3_DELAY_LINE
);
1048 /* Used by the upper layer to write command to NAND Flash for
1049 * different operations to be carried out on NAND Flash */
1050 static void mxc_nand_command(struct mtd_info
*mtd
, unsigned command
,
1051 int column
, int page_addr
)
1053 struct nand_chip
*nand_chip
= mtd
->priv
;
1054 struct mxc_nand_host
*host
= nand_chip
->priv
;
1056 pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1057 command
, column
, page_addr
);
1059 /* Reset command state information */
1060 host
->status_request
= false;
1062 /* Command pre-processing step */
1064 case NAND_CMD_RESET
:
1065 host
->devtype_data
->preset(mtd
);
1066 host
->devtype_data
->send_cmd(host
, command
, false);
1069 case NAND_CMD_STATUS
:
1070 host
->buf_start
= 0;
1071 host
->status_request
= true;
1073 host
->devtype_data
->send_cmd(host
, command
, true);
1074 mxc_do_addr_cycle(mtd
, column
, page_addr
);
1077 case NAND_CMD_READ0
:
1078 case NAND_CMD_READOOB
:
1079 if (command
== NAND_CMD_READ0
)
1080 host
->buf_start
= column
;
1082 host
->buf_start
= column
+ mtd
->writesize
;
1084 command
= NAND_CMD_READ0
; /* only READ0 is valid */
1086 host
->devtype_data
->send_cmd(host
, command
, false);
1087 mxc_do_addr_cycle(mtd
, column
, page_addr
);
1089 if (mtd
->writesize
> 512)
1090 host
->devtype_data
->send_cmd(host
,
1091 NAND_CMD_READSTART
, true);
1093 host
->devtype_data
->send_page(mtd
, NFC_OUTPUT
);
1095 memcpy32_fromio(host
->data_buf
, host
->main_area0
,
1097 copy_spare(mtd
, true);
1100 case NAND_CMD_SEQIN
:
1101 if (column
>= mtd
->writesize
)
1102 /* call ourself to read a page */
1103 mxc_nand_command(mtd
, NAND_CMD_READ0
, 0, page_addr
);
1105 host
->buf_start
= column
;
1107 host
->devtype_data
->send_cmd(host
, command
, false);
1108 mxc_do_addr_cycle(mtd
, column
, page_addr
);
1111 case NAND_CMD_PAGEPROG
:
1112 memcpy32_toio(host
->main_area0
, host
->data_buf
, mtd
->writesize
);
1113 copy_spare(mtd
, false);
1114 host
->devtype_data
->send_page(mtd
, NFC_INPUT
);
1115 host
->devtype_data
->send_cmd(host
, command
, true);
1116 mxc_do_addr_cycle(mtd
, column
, page_addr
);
1119 case NAND_CMD_READID
:
1120 host
->devtype_data
->send_cmd(host
, command
, true);
1121 mxc_do_addr_cycle(mtd
, column
, page_addr
);
1122 host
->devtype_data
->send_read_id(host
);
1123 host
->buf_start
= column
;
1126 case NAND_CMD_ERASE1
:
1127 case NAND_CMD_ERASE2
:
1128 host
->devtype_data
->send_cmd(host
, command
, false);
1129 mxc_do_addr_cycle(mtd
, column
, page_addr
);
1136 * The generic flash bbt decriptors overlap with our ecc
1137 * hardware, so define some i.MX specific ones.
1139 static uint8_t bbt_pattern
[] = { 'B', 'b', 't', '0' };
1140 static uint8_t mirror_pattern
[] = { '1', 't', 'b', 'B' };
1142 static struct nand_bbt_descr bbt_main_descr
= {
1143 .options
= NAND_BBT_LASTBLOCK
| NAND_BBT_CREATE
| NAND_BBT_WRITE
1144 | NAND_BBT_2BIT
| NAND_BBT_VERSION
| NAND_BBT_PERCHIP
,
1149 .pattern
= bbt_pattern
,
1152 static struct nand_bbt_descr bbt_mirror_descr
= {
1153 .options
= NAND_BBT_LASTBLOCK
| NAND_BBT_CREATE
| NAND_BBT_WRITE
1154 | NAND_BBT_2BIT
| NAND_BBT_VERSION
| NAND_BBT_PERCHIP
,
1159 .pattern
= mirror_pattern
,
1162 /* v1 + irqpending_quirk: i.MX21 */
1163 static const struct mxc_nand_devtype_data imx21_nand_devtype_data
= {
1164 .preset
= preset_v1
,
1165 .send_cmd
= send_cmd_v1_v2
,
1166 .send_addr
= send_addr_v1_v2
,
1167 .send_page
= send_page_v1
,
1168 .send_read_id
= send_read_id_v1_v2
,
1169 .get_dev_status
= get_dev_status_v1_v2
,
1170 .check_int
= check_int_v1_v2
,
1171 .irq_control
= irq_control_v1_v2
,
1172 .get_ecc_status
= get_ecc_status_v1
,
1173 .ecclayout_512
= &nandv1_hw_eccoob_smallpage
,
1174 .ecclayout_2k
= &nandv1_hw_eccoob_largepage
,
1175 .ecclayout_4k
= &nandv1_hw_eccoob_smallpage
, /* XXX: needs fix */
1176 .select_chip
= mxc_nand_select_chip_v1_v3
,
1177 .correct_data
= mxc_nand_correct_data_v1
,
1178 .irqpending_quirk
= 1,
1180 .regs_offset
= 0xe00,
1181 .spare0_offset
= 0x800,
1187 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */
1188 static const struct mxc_nand_devtype_data imx27_nand_devtype_data
= {
1189 .preset
= preset_v1
,
1190 .send_cmd
= send_cmd_v1_v2
,
1191 .send_addr
= send_addr_v1_v2
,
1192 .send_page
= send_page_v1
,
1193 .send_read_id
= send_read_id_v1_v2
,
1194 .get_dev_status
= get_dev_status_v1_v2
,
1195 .check_int
= check_int_v1_v2
,
1196 .irq_control
= irq_control_v1_v2
,
1197 .get_ecc_status
= get_ecc_status_v1
,
1198 .ecclayout_512
= &nandv1_hw_eccoob_smallpage
,
1199 .ecclayout_2k
= &nandv1_hw_eccoob_largepage
,
1200 .ecclayout_4k
= &nandv1_hw_eccoob_smallpage
, /* XXX: needs fix */
1201 .select_chip
= mxc_nand_select_chip_v1_v3
,
1202 .correct_data
= mxc_nand_correct_data_v1
,
1203 .irqpending_quirk
= 0,
1205 .regs_offset
= 0xe00,
1206 .spare0_offset
= 0x800,
1213 /* v21: i.MX25, i.MX35 */
1214 static const struct mxc_nand_devtype_data imx25_nand_devtype_data
= {
1215 .preset
= preset_v2
,
1216 .send_cmd
= send_cmd_v1_v2
,
1217 .send_addr
= send_addr_v1_v2
,
1218 .send_page
= send_page_v2
,
1219 .send_read_id
= send_read_id_v1_v2
,
1220 .get_dev_status
= get_dev_status_v1_v2
,
1221 .check_int
= check_int_v1_v2
,
1222 .irq_control
= irq_control_v1_v2
,
1223 .get_ecc_status
= get_ecc_status_v2
,
1224 .ecclayout_512
= &nandv2_hw_eccoob_smallpage
,
1225 .ecclayout_2k
= &nandv2_hw_eccoob_largepage
,
1226 .ecclayout_4k
= &nandv2_hw_eccoob_4k
,
1227 .select_chip
= mxc_nand_select_chip_v2
,
1228 .correct_data
= mxc_nand_correct_data_v2_v3
,
1229 .irqpending_quirk
= 0,
1231 .regs_offset
= 0x1e00,
1232 .spare0_offset
= 0x1000,
1240 static const struct mxc_nand_devtype_data imx51_nand_devtype_data
= {
1241 .preset
= preset_v3
,
1242 .send_cmd
= send_cmd_v3
,
1243 .send_addr
= send_addr_v3
,
1244 .send_page
= send_page_v3
,
1245 .send_read_id
= send_read_id_v3
,
1246 .get_dev_status
= get_dev_status_v3
,
1247 .check_int
= check_int_v3
,
1248 .irq_control
= irq_control_v3
,
1249 .get_ecc_status
= get_ecc_status_v3
,
1250 .ecclayout_512
= &nandv2_hw_eccoob_smallpage
,
1251 .ecclayout_2k
= &nandv2_hw_eccoob_largepage
,
1252 .ecclayout_4k
= &nandv2_hw_eccoob_smallpage
, /* XXX: needs fix */
1253 .select_chip
= mxc_nand_select_chip_v1_v3
,
1254 .correct_data
= mxc_nand_correct_data_v2_v3
,
1255 .irqpending_quirk
= 0,
1258 .spare0_offset
= 0x1000,
1259 .axi_offset
= 0x1e00,
1267 static const struct mxc_nand_devtype_data imx53_nand_devtype_data
= {
1268 .preset
= preset_v3
,
1269 .send_cmd
= send_cmd_v3
,
1270 .send_addr
= send_addr_v3
,
1271 .send_page
= send_page_v3
,
1272 .send_read_id
= send_read_id_v3
,
1273 .get_dev_status
= get_dev_status_v3
,
1274 .check_int
= check_int_v3
,
1275 .irq_control
= irq_control_v3
,
1276 .get_ecc_status
= get_ecc_status_v3
,
1277 .ecclayout_512
= &nandv2_hw_eccoob_smallpage
,
1278 .ecclayout_2k
= &nandv2_hw_eccoob_largepage
,
1279 .ecclayout_4k
= &nandv2_hw_eccoob_smallpage
, /* XXX: needs fix */
1280 .select_chip
= mxc_nand_select_chip_v1_v3
,
1281 .correct_data
= mxc_nand_correct_data_v2_v3
,
1282 .irqpending_quirk
= 0,
1285 .spare0_offset
= 0x1000,
1286 .axi_offset
= 0x1e00,
1293 static inline int is_imx21_nfc(struct mxc_nand_host
*host
)
1295 return host
->devtype_data
== &imx21_nand_devtype_data
;
1298 static inline int is_imx27_nfc(struct mxc_nand_host
*host
)
1300 return host
->devtype_data
== &imx27_nand_devtype_data
;
1303 static inline int is_imx25_nfc(struct mxc_nand_host
*host
)
1305 return host
->devtype_data
== &imx25_nand_devtype_data
;
1308 static inline int is_imx51_nfc(struct mxc_nand_host
*host
)
1310 return host
->devtype_data
== &imx51_nand_devtype_data
;
1313 static inline int is_imx53_nfc(struct mxc_nand_host
*host
)
1315 return host
->devtype_data
== &imx53_nand_devtype_data
;
1318 static struct platform_device_id mxcnd_devtype
[] = {
1320 .name
= "imx21-nand",
1321 .driver_data
= (kernel_ulong_t
) &imx21_nand_devtype_data
,
1323 .name
= "imx27-nand",
1324 .driver_data
= (kernel_ulong_t
) &imx27_nand_devtype_data
,
1326 .name
= "imx25-nand",
1327 .driver_data
= (kernel_ulong_t
) &imx25_nand_devtype_data
,
1329 .name
= "imx51-nand",
1330 .driver_data
= (kernel_ulong_t
) &imx51_nand_devtype_data
,
1332 .name
= "imx53-nand",
1333 .driver_data
= (kernel_ulong_t
) &imx53_nand_devtype_data
,
1338 MODULE_DEVICE_TABLE(platform
, mxcnd_devtype
);
1340 #ifdef CONFIG_OF_MTD
1341 static const struct of_device_id mxcnd_dt_ids
[] = {
1343 .compatible
= "fsl,imx21-nand",
1344 .data
= &imx21_nand_devtype_data
,
1346 .compatible
= "fsl,imx27-nand",
1347 .data
= &imx27_nand_devtype_data
,
1349 .compatible
= "fsl,imx25-nand",
1350 .data
= &imx25_nand_devtype_data
,
1352 .compatible
= "fsl,imx51-nand",
1353 .data
= &imx51_nand_devtype_data
,
1355 .compatible
= "fsl,imx53-nand",
1356 .data
= &imx53_nand_devtype_data
,
1361 static int __init
mxcnd_probe_dt(struct mxc_nand_host
*host
)
1363 struct device_node
*np
= host
->dev
->of_node
;
1364 struct mxc_nand_platform_data
*pdata
= &host
->pdata
;
1365 const struct of_device_id
*of_id
=
1366 of_match_device(mxcnd_dt_ids
, host
->dev
);
1372 if (of_get_nand_ecc_mode(np
) >= 0)
1375 pdata
->flash_bbt
= of_get_nand_on_flash_bbt(np
);
1377 buswidth
= of_get_nand_bus_width(np
);
1381 pdata
->width
= buswidth
/ 8;
1383 host
->devtype_data
= of_id
->data
;
1388 static int __init
mxcnd_probe_dt(struct mxc_nand_host
*host
)
1394 static int mxcnd_probe(struct platform_device
*pdev
)
1396 struct nand_chip
*this;
1397 struct mtd_info
*mtd
;
1398 struct mxc_nand_host
*host
;
1399 struct resource
*res
;
1402 /* Allocate memory for MTD device structure and private data */
1403 host
= devm_kzalloc(&pdev
->dev
, sizeof(struct mxc_nand_host
) +
1404 NAND_MAX_PAGESIZE
+ NAND_MAX_OOBSIZE
, GFP_KERNEL
);
1408 host
->data_buf
= (uint8_t *)(host
+ 1);
1410 host
->dev
= &pdev
->dev
;
1411 /* structures must be linked */
1415 mtd
->owner
= THIS_MODULE
;
1416 mtd
->dev
.parent
= &pdev
->dev
;
1417 mtd
->name
= DRIVER_NAME
;
1419 /* 50 us command delay time */
1420 this->chip_delay
= 5;
1423 this->dev_ready
= mxc_nand_dev_ready
;
1424 this->cmdfunc
= mxc_nand_command
;
1425 this->read_byte
= mxc_nand_read_byte
;
1426 this->read_word
= mxc_nand_read_word
;
1427 this->write_buf
= mxc_nand_write_buf
;
1428 this->read_buf
= mxc_nand_read_buf
;
1430 host
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1431 if (IS_ERR(host
->clk
))
1432 return PTR_ERR(host
->clk
);
1434 err
= mxcnd_probe_dt(host
);
1436 struct mxc_nand_platform_data
*pdata
=
1437 dev_get_platdata(&pdev
->dev
);
1439 host
->pdata
= *pdata
;
1440 host
->devtype_data
= (struct mxc_nand_devtype_data
*)
1441 pdev
->id_entry
->driver_data
;
1449 if (host
->devtype_data
->needs_ip
) {
1450 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1451 host
->regs_ip
= devm_ioremap_resource(&pdev
->dev
, res
);
1452 if (IS_ERR(host
->regs_ip
))
1453 return PTR_ERR(host
->regs_ip
);
1455 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1457 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1460 host
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
1461 if (IS_ERR(host
->base
))
1462 return PTR_ERR(host
->base
);
1464 host
->main_area0
= host
->base
;
1466 if (host
->devtype_data
->regs_offset
)
1467 host
->regs
= host
->base
+ host
->devtype_data
->regs_offset
;
1468 host
->spare0
= host
->base
+ host
->devtype_data
->spare0_offset
;
1469 if (host
->devtype_data
->axi_offset
)
1470 host
->regs_axi
= host
->base
+ host
->devtype_data
->axi_offset
;
1472 this->ecc
.bytes
= host
->devtype_data
->eccbytes
;
1473 host
->eccsize
= host
->devtype_data
->eccsize
;
1475 this->select_chip
= host
->devtype_data
->select_chip
;
1476 this->ecc
.size
= 512;
1477 this->ecc
.layout
= host
->devtype_data
->ecclayout_512
;
1479 if (host
->pdata
.hw_ecc
) {
1480 this->ecc
.calculate
= mxc_nand_calculate_ecc
;
1481 this->ecc
.hwctl
= mxc_nand_enable_hwecc
;
1482 this->ecc
.correct
= host
->devtype_data
->correct_data
;
1483 this->ecc
.mode
= NAND_ECC_HW
;
1485 this->ecc
.mode
= NAND_ECC_SOFT
;
1488 /* NAND bus width determines access functions used by upper layer */
1489 if (host
->pdata
.width
== 2)
1490 this->options
|= NAND_BUSWIDTH_16
;
1492 if (host
->pdata
.flash_bbt
) {
1493 this->bbt_td
= &bbt_main_descr
;
1494 this->bbt_md
= &bbt_mirror_descr
;
1495 /* update flash based bbt */
1496 this->bbt_options
|= NAND_BBT_USE_FLASH
;
1499 init_completion(&host
->op_completion
);
1501 host
->irq
= platform_get_irq(pdev
, 0);
1504 * Use host->devtype_data->irq_control() here instead of irq_control()
1505 * because we must not disable_irq_nosync without having requested the
1508 host
->devtype_data
->irq_control(host
, 0);
1510 err
= devm_request_irq(&pdev
->dev
, host
->irq
, mxc_nfc_irq
,
1511 0, DRIVER_NAME
, host
);
1515 clk_prepare_enable(host
->clk
);
1519 * Now that we "own" the interrupt make sure the interrupt mask bit is
1520 * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1523 if (host
->devtype_data
->irqpending_quirk
) {
1524 disable_irq_nosync(host
->irq
);
1525 host
->devtype_data
->irq_control(host
, 1);
1528 /* first scan to find the device and get the page size */
1529 if (nand_scan_ident(mtd
, is_imx25_nfc(host
) ? 4 : 1, NULL
)) {
1534 /* Call preset again, with correct writesize this time */
1535 host
->devtype_data
->preset(mtd
);
1537 if (mtd
->writesize
== 2048)
1538 this->ecc
.layout
= host
->devtype_data
->ecclayout_2k
;
1539 else if (mtd
->writesize
== 4096)
1540 this->ecc
.layout
= host
->devtype_data
->ecclayout_4k
;
1542 if (this->ecc
.mode
== NAND_ECC_HW
) {
1543 if (is_imx21_nfc(host
) || is_imx27_nfc(host
))
1544 this->ecc
.strength
= 1;
1546 this->ecc
.strength
= (host
->eccsize
== 4) ? 4 : 8;
1549 /* second phase scan */
1550 if (nand_scan_tail(mtd
)) {
1555 /* Register the partitions */
1556 mtd_device_parse_register(mtd
, part_probes
,
1557 &(struct mtd_part_parser_data
){
1558 .of_node
= pdev
->dev
.of_node
,
1561 host
->pdata
.nr_parts
);
1563 platform_set_drvdata(pdev
, host
);
1569 clk_disable_unprepare(host
->clk
);
1574 static int mxcnd_remove(struct platform_device
*pdev
)
1576 struct mxc_nand_host
*host
= platform_get_drvdata(pdev
);
1578 nand_release(&host
->mtd
);
1583 static struct platform_driver mxcnd_driver
= {
1585 .name
= DRIVER_NAME
,
1586 .owner
= THIS_MODULE
,
1587 .of_match_table
= of_match_ptr(mxcnd_dt_ids
),
1589 .id_table
= mxcnd_devtype
,
1590 .probe
= mxcnd_probe
,
1591 .remove
= mxcnd_remove
,
1593 module_platform_driver(mxcnd_driver
);
1595 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1596 MODULE_DESCRIPTION("MXC NAND MTD driver");
1597 MODULE_LICENSE("GPL");