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drm/i915: Use DPCD value for max DP lanes.
[linux-2.6/btrfs-unstable.git] / drivers / gpu / drm / i915 / intel_dp.c
blobec28aebf5147c7b2f7ebb74dc919ac87581eb407
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "drm_crtc.h"
33 #include "drm_crtc_helper.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "drm_dp_helper.h"
38
39 #define DP_RECEIVER_CAP_SIZE 0xf
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
43 #define DP_LINK_CONFIGURATION_SIZE 9
44
45 struct intel_dp {
46 struct intel_encoder base;
47 uint32_t output_reg;
48 uint32_t DP;
49 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
50 bool has_audio;
51 int force_audio;
52 uint32_t color_range;
53 int dpms_mode;
54 uint8_t link_bw;
55 uint8_t lane_count;
56 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
57 struct i2c_adapter adapter;
58 struct i2c_algo_dp_aux_data algo;
59 bool is_pch_edp;
60 uint8_t train_set[4];
61 int panel_power_up_delay;
62 int panel_power_down_delay;
63 int panel_power_cycle_delay;
64 int backlight_on_delay;
65 int backlight_off_delay;
66 struct drm_display_mode *panel_fixed_mode; /* for eDP */
67 struct delayed_work panel_vdd_work;
68 bool want_panel_vdd;
69 };
70
71 /**
72 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
73 * @intel_dp: DP struct
74 *
75 * If a CPU or PCH DP output is attached to an eDP panel, this function
76 * will return true, and false otherwise.
77 */
78 static bool is_edp(struct intel_dp *intel_dp)
79 {
80 return intel_dp->base.type == INTEL_OUTPUT_EDP;
81 }
82
83 /**
84 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
85 * @intel_dp: DP struct
86 *
87 * Returns true if the given DP struct corresponds to a PCH DP port attached
88 * to an eDP panel, false otherwise. Helpful for determining whether we
89 * may need FDI resources for a given DP output or not.
90 */
91 static bool is_pch_edp(struct intel_dp *intel_dp)
92 {
93 return intel_dp->is_pch_edp;
94 }
95
96 /**
97 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
98 * @intel_dp: DP struct
99 *
100 * Returns true if the given DP struct corresponds to a CPU eDP port.
101 */
102 static bool is_cpu_edp(struct intel_dp *intel_dp)
103 {
104 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
105 }
106
107 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
108 {
109 return container_of(encoder, struct intel_dp, base.base);
110 }
111
112 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
113 {
114 return container_of(intel_attached_encoder(connector),
115 struct intel_dp, base);
116 }
117
118 /**
119 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
120 * @encoder: DRM encoder
121 *
122 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
123 * by intel_display.c.
124 */
125 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
126 {
127 struct intel_dp *intel_dp;
128
129 if (!encoder)
130 return false;
131
132 intel_dp = enc_to_intel_dp(encoder);
133
134 return is_pch_edp(intel_dp);
135 }
136
137 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
138 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
139 static void intel_dp_link_down(struct intel_dp *intel_dp);
140
141 void
142 intel_edp_link_config(struct intel_encoder *intel_encoder,
143 int *lane_num, int *link_bw)
144 {
145 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
146
147 *lane_num = intel_dp->lane_count;
148 if (intel_dp->link_bw == DP_LINK_BW_1_62)
149 *link_bw = 162000;
150 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
151 *link_bw = 270000;
152 }
153
154 static int
155 intel_dp_max_lane_count(struct intel_dp *intel_dp)
156 {
157 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
158 switch (max_lane_count) {
159 case 1: case 2: case 4:
160 break;
161 default:
162 max_lane_count = 4;
163 }
164 return max_lane_count;
165 }
166
167 static int
168 intel_dp_max_link_bw(struct intel_dp *intel_dp)
169 {
170 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
171
172 switch (max_link_bw) {
173 case DP_LINK_BW_1_62:
174 case DP_LINK_BW_2_7:
175 break;
176 default:
177 max_link_bw = DP_LINK_BW_1_62;
178 break;
179 }
180 return max_link_bw;
181 }
182
183 static int
184 intel_dp_link_clock(uint8_t link_bw)
185 {
186 if (link_bw == DP_LINK_BW_2_7)
187 return 270000;
188 else
189 return 162000;
190 }
191
192 /*
193 * The units on the numbers in the next two are... bizarre. Examples will
194 * make it clearer; this one parallels an example in the eDP spec.
195 *
196 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
197 *
198 * 270000 * 1 * 8 / 10 == 216000
199 *
200 * The actual data capacity of that configuration is 2.16Gbit/s, so the
201 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
202 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
203 * 119000. At 18bpp that's 2142000 kilobits per second.
204 *
205 * Thus the strange-looking division by 10 in intel_dp_link_required, to
206 * get the result in decakilobits instead of kilobits.
207 */
208
209 static int
210 intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock)
211 {
212 struct drm_crtc *crtc = intel_dp->base.base.crtc;
213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
214 int bpp = 24;
215
216 if (intel_crtc)
217 bpp = intel_crtc->bpp;
218
219 return (pixel_clock * bpp + 9) / 10;
220 }
221
222 static int
223 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
224 {
225 return (max_link_clock * max_lanes * 8) / 10;
226 }
227
228 static int
229 intel_dp_mode_valid(struct drm_connector *connector,
230 struct drm_display_mode *mode)
231 {
232 struct intel_dp *intel_dp = intel_attached_dp(connector);
233 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
234 int max_lanes = intel_dp_max_lane_count(intel_dp);
235
236 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
237 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
238 return MODE_PANEL;
239
240 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
241 return MODE_PANEL;
242 }
243
244 if (intel_dp_link_required(intel_dp, mode->clock)
245 > intel_dp_max_data_rate(max_link_clock, max_lanes))
246 return MODE_CLOCK_HIGH;
247
248 if (mode->clock < 10000)
249 return MODE_CLOCK_LOW;
250
251 return MODE_OK;
252 }
253
254 static uint32_t
255 pack_aux(uint8_t *src, int src_bytes)
256 {
257 int i;
258 uint32_t v = 0;
259
260 if (src_bytes > 4)
261 src_bytes = 4;
262 for (i = 0; i < src_bytes; i++)
263 v |= ((uint32_t) src[i]) << ((3-i) * 8);
264 return v;
265 }
266
267 static void
268 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
269 {
270 int i;
271 if (dst_bytes > 4)
272 dst_bytes = 4;
273 for (i = 0; i < dst_bytes; i++)
274 dst[i] = src >> ((3-i) * 8);
275 }
276
277 /* hrawclock is 1/4 the FSB frequency */
278 static int
279 intel_hrawclk(struct drm_device *dev)
280 {
281 struct drm_i915_private *dev_priv = dev->dev_private;
282 uint32_t clkcfg;
283
284 clkcfg = I915_READ(CLKCFG);
285 switch (clkcfg & CLKCFG_FSB_MASK) {
286 case CLKCFG_FSB_400:
287 return 100;
288 case CLKCFG_FSB_533:
289 return 133;
290 case CLKCFG_FSB_667:
291 return 166;
292 case CLKCFG_FSB_800:
293 return 200;
294 case CLKCFG_FSB_1067:
295 return 266;
296 case CLKCFG_FSB_1333:
297 return 333;
298 /* these two are just a guess; one of them might be right */
299 case CLKCFG_FSB_1600:
300 case CLKCFG_FSB_1600_ALT:
301 return 400;
302 default:
303 return 133;
304 }
305 }
306
307 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
308 {
309 struct drm_device *dev = intel_dp->base.base.dev;
310 struct drm_i915_private *dev_priv = dev->dev_private;
311
312 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
313 }
314
315 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
316 {
317 struct drm_device *dev = intel_dp->base.base.dev;
318 struct drm_i915_private *dev_priv = dev->dev_private;
319
320 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
321 }
322
323 static void
324 intel_dp_check_edp(struct intel_dp *intel_dp)
325 {
326 struct drm_device *dev = intel_dp->base.base.dev;
327 struct drm_i915_private *dev_priv = dev->dev_private;
328
329 if (!is_edp(intel_dp))
330 return;
331 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
332 WARN(1, "eDP powered off while attempting aux channel communication.\n");
333 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
334 I915_READ(PCH_PP_STATUS),
335 I915_READ(PCH_PP_CONTROL));
336 }
337 }
338
339 static int
340 intel_dp_aux_ch(struct intel_dp *intel_dp,
341 uint8_t *send, int send_bytes,
342 uint8_t *recv, int recv_size)
343 {
344 uint32_t output_reg = intel_dp->output_reg;
345 struct drm_device *dev = intel_dp->base.base.dev;
346 struct drm_i915_private *dev_priv = dev->dev_private;
347 uint32_t ch_ctl = output_reg + 0x10;
348 uint32_t ch_data = ch_ctl + 4;
349 int i;
350 int recv_bytes;
351 uint32_t status;
352 uint32_t aux_clock_divider;
353 int try, precharge;
354
355 intel_dp_check_edp(intel_dp);
356 /* The clock divider is based off the hrawclk,
357 * and would like to run at 2MHz. So, take the
358 * hrawclk value and divide by 2 and use that
359 *
360 * Note that PCH attached eDP panels should use a 125MHz input
361 * clock divider.
362 */
363 if (is_cpu_edp(intel_dp)) {
364 if (IS_GEN6(dev))
365 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
366 else
367 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
368 } else if (HAS_PCH_SPLIT(dev))
369 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
370 else
371 aux_clock_divider = intel_hrawclk(dev) / 2;
372
373 if (IS_GEN6(dev))
374 precharge = 3;
375 else
376 precharge = 5;
377
378 /* Try to wait for any previous AUX channel activity */
379 for (try = 0; try < 3; try++) {
380 status = I915_READ(ch_ctl);
381 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
382 break;
383 msleep(1);
384 }
385
386 if (try == 3) {
387 WARN(1, "dp_aux_ch not started status 0x%08x\n",
388 I915_READ(ch_ctl));
389 return -EBUSY;
390 }
391
392 /* Must try at least 3 times according to DP spec */
393 for (try = 0; try < 5; try++) {
394 /* Load the send data into the aux channel data registers */
395 for (i = 0; i < send_bytes; i += 4)
396 I915_WRITE(ch_data + i,
397 pack_aux(send + i, send_bytes - i));
398
399 /* Send the command and wait for it to complete */
400 I915_WRITE(ch_ctl,
401 DP_AUX_CH_CTL_SEND_BUSY |
402 DP_AUX_CH_CTL_TIME_OUT_400us |
403 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
404 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
405 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
406 DP_AUX_CH_CTL_DONE |
407 DP_AUX_CH_CTL_TIME_OUT_ERROR |
408 DP_AUX_CH_CTL_RECEIVE_ERROR);
409 for (;;) {
410 status = I915_READ(ch_ctl);
411 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
412 break;
413 udelay(100);
414 }
415
416 /* Clear done status and any errors */
417 I915_WRITE(ch_ctl,
418 status |
419 DP_AUX_CH_CTL_DONE |
420 DP_AUX_CH_CTL_TIME_OUT_ERROR |
421 DP_AUX_CH_CTL_RECEIVE_ERROR);
422 if (status & DP_AUX_CH_CTL_DONE)
423 break;
424 }
425
426 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
427 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
428 return -EBUSY;
429 }
430
431 /* Check for timeout or receive error.
432 * Timeouts occur when the sink is not connected
433 */
434 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
435 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
436 return -EIO;
437 }
438
439 /* Timeouts occur when the device isn't connected, so they're
440 * "normal" -- don't fill the kernel log with these */
441 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
442 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
443 return -ETIMEDOUT;
444 }
445
446 /* Unload any bytes sent back from the other side */
447 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
448 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
449 if (recv_bytes > recv_size)
450 recv_bytes = recv_size;
451
452 for (i = 0; i < recv_bytes; i += 4)
453 unpack_aux(I915_READ(ch_data + i),
454 recv + i, recv_bytes - i);
455
456 return recv_bytes;
457 }
458
459 /* Write data to the aux channel in native mode */
460 static int
461 intel_dp_aux_native_write(struct intel_dp *intel_dp,
462 uint16_t address, uint8_t *send, int send_bytes)
463 {
464 int ret;
465 uint8_t msg[20];
466 int msg_bytes;
467 uint8_t ack;
468
469 intel_dp_check_edp(intel_dp);
470 if (send_bytes > 16)
471 return -1;
472 msg[0] = AUX_NATIVE_WRITE << 4;
473 msg[1] = address >> 8;
474 msg[2] = address & 0xff;
475 msg[3] = send_bytes - 1;
476 memcpy(&msg[4], send, send_bytes);
477 msg_bytes = send_bytes + 4;
478 for (;;) {
479 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
480 if (ret < 0)
481 return ret;
482 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
483 break;
484 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
485 udelay(100);
486 else
487 return -EIO;
488 }
489 return send_bytes;
490 }
491
492 /* Write a single byte to the aux channel in native mode */
493 static int
494 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
495 uint16_t address, uint8_t byte)
496 {
497 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
498 }
499
500 /* read bytes from a native aux channel */
501 static int
502 intel_dp_aux_native_read(struct intel_dp *intel_dp,
503 uint16_t address, uint8_t *recv, int recv_bytes)
504 {
505 uint8_t msg[4];
506 int msg_bytes;
507 uint8_t reply[20];
508 int reply_bytes;
509 uint8_t ack;
510 int ret;
511
512 intel_dp_check_edp(intel_dp);
513 msg[0] = AUX_NATIVE_READ << 4;
514 msg[1] = address >> 8;
515 msg[2] = address & 0xff;
516 msg[3] = recv_bytes - 1;
517
518 msg_bytes = 4;
519 reply_bytes = recv_bytes + 1;
520
521 for (;;) {
522 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
523 reply, reply_bytes);
524 if (ret == 0)
525 return -EPROTO;
526 if (ret < 0)
527 return ret;
528 ack = reply[0];
529 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
530 memcpy(recv, reply + 1, ret - 1);
531 return ret - 1;
532 }
533 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
534 udelay(100);
535 else
536 return -EIO;
537 }
538 }
539
540 static int
541 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
542 uint8_t write_byte, uint8_t *read_byte)
543 {
544 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
545 struct intel_dp *intel_dp = container_of(adapter,
546 struct intel_dp,
547 adapter);
548 uint16_t address = algo_data->address;
549 uint8_t msg[5];
550 uint8_t reply[2];
551 unsigned retry;
552 int msg_bytes;
553 int reply_bytes;
554 int ret;
555
556 intel_dp_check_edp(intel_dp);
557 /* Set up the command byte */
558 if (mode & MODE_I2C_READ)
559 msg[0] = AUX_I2C_READ << 4;
560 else
561 msg[0] = AUX_I2C_WRITE << 4;
562
563 if (!(mode & MODE_I2C_STOP))
564 msg[0] |= AUX_I2C_MOT << 4;
565
566 msg[1] = address >> 8;
567 msg[2] = address;
568
569 switch (mode) {
570 case MODE_I2C_WRITE:
571 msg[3] = 0;
572 msg[4] = write_byte;
573 msg_bytes = 5;
574 reply_bytes = 1;
575 break;
576 case MODE_I2C_READ:
577 msg[3] = 0;
578 msg_bytes = 4;
579 reply_bytes = 2;
580 break;
581 default:
582 msg_bytes = 3;
583 reply_bytes = 1;
584 break;
585 }
586
587 for (retry = 0; retry < 5; retry++) {
588 ret = intel_dp_aux_ch(intel_dp,
589 msg, msg_bytes,
590 reply, reply_bytes);
591 if (ret < 0) {
592 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
593 return ret;
594 }
595
596 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
597 case AUX_NATIVE_REPLY_ACK:
598 /* I2C-over-AUX Reply field is only valid
599 * when paired with AUX ACK.
600 */
601 break;
602 case AUX_NATIVE_REPLY_NACK:
603 DRM_DEBUG_KMS("aux_ch native nack\n");
604 return -EREMOTEIO;
605 case AUX_NATIVE_REPLY_DEFER:
606 udelay(100);
607 continue;
608 default:
609 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
610 reply[0]);
611 return -EREMOTEIO;
612 }
613
614 switch (reply[0] & AUX_I2C_REPLY_MASK) {
615 case AUX_I2C_REPLY_ACK:
616 if (mode == MODE_I2C_READ) {
617 *read_byte = reply[1];
618 }
619 return reply_bytes - 1;
620 case AUX_I2C_REPLY_NACK:
621 DRM_DEBUG_KMS("aux_i2c nack\n");
622 return -EREMOTEIO;
623 case AUX_I2C_REPLY_DEFER:
624 DRM_DEBUG_KMS("aux_i2c defer\n");
625 udelay(100);
626 break;
627 default:
628 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
629 return -EREMOTEIO;
630 }
631 }
632
633 DRM_ERROR("too many retries, giving up\n");
634 return -EREMOTEIO;
635 }
636
637 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
638 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
639
640 static int
641 intel_dp_i2c_init(struct intel_dp *intel_dp,
642 struct intel_connector *intel_connector, const char *name)
643 {
644 int ret;
645
646 DRM_DEBUG_KMS("i2c_init %s\n", name);
647 intel_dp->algo.running = false;
648 intel_dp->algo.address = 0;
649 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
650
651 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
652 intel_dp->adapter.owner = THIS_MODULE;
653 intel_dp->adapter.class = I2C_CLASS_DDC;
654 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
655 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
656 intel_dp->adapter.algo_data = &intel_dp->algo;
657 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
658
659 ironlake_edp_panel_vdd_on(intel_dp);
660 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
661 ironlake_edp_panel_vdd_off(intel_dp, false);
662 return ret;
663 }
664
665 static bool
666 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
667 struct drm_display_mode *adjusted_mode)
668 {
669 struct drm_device *dev = encoder->dev;
670 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
671 int lane_count, clock;
672 int max_lane_count = intel_dp_max_lane_count(intel_dp);
673 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
674 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
675
676 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
677 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
678 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
679 mode, adjusted_mode);
680 /*
681 * the mode->clock is used to calculate the Data&Link M/N
682 * of the pipe. For the eDP the fixed clock should be used.
683 */
684 mode->clock = intel_dp->panel_fixed_mode->clock;
685 }
686
687 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
688 for (clock = 0; clock <= max_clock; clock++) {
689 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
690
691 if (intel_dp_link_required(intel_dp, mode->clock)
692 <= link_avail) {
693 intel_dp->link_bw = bws[clock];
694 intel_dp->lane_count = lane_count;
695 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
696 DRM_DEBUG_KMS("Display port link bw %02x lane "
697 "count %d clock %d\n",
698 intel_dp->link_bw, intel_dp->lane_count,
699 adjusted_mode->clock);
700 return true;
701 }
702 }
703 }
704
705 return false;
706 }
707
708 struct intel_dp_m_n {
709 uint32_t tu;
710 uint32_t gmch_m;
711 uint32_t gmch_n;
712 uint32_t link_m;
713 uint32_t link_n;
714 };
715
716 static void
717 intel_reduce_ratio(uint32_t *num, uint32_t *den)
718 {
719 while (*num > 0xffffff || *den > 0xffffff) {
720 *num >>= 1;
721 *den >>= 1;
722 }
723 }
724
725 static void
726 intel_dp_compute_m_n(int bpp,
727 int nlanes,
728 int pixel_clock,
729 int link_clock,
730 struct intel_dp_m_n *m_n)
731 {
732 m_n->tu = 64;
733 m_n->gmch_m = (pixel_clock * bpp) >> 3;
734 m_n->gmch_n = link_clock * nlanes;
735 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
736 m_n->link_m = pixel_clock;
737 m_n->link_n = link_clock;
738 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
739 }
740
741 void
742 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
743 struct drm_display_mode *adjusted_mode)
744 {
745 struct drm_device *dev = crtc->dev;
746 struct drm_mode_config *mode_config = &dev->mode_config;
747 struct drm_encoder *encoder;
748 struct drm_i915_private *dev_priv = dev->dev_private;
749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
750 int lane_count = 4;
751 struct intel_dp_m_n m_n;
752 int pipe = intel_crtc->pipe;
753
754 /*
755 * Find the lane count in the intel_encoder private
756 */
757 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
758 struct intel_dp *intel_dp;
759
760 if (encoder->crtc != crtc)
761 continue;
762
763 intel_dp = enc_to_intel_dp(encoder);
764 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
765 intel_dp->base.type == INTEL_OUTPUT_EDP)
766 {
767 lane_count = intel_dp->lane_count;
768 break;
769 }
770 }
771
772 /*
773 * Compute the GMCH and Link ratios. The '3' here is
774 * the number of bytes_per_pixel post-LUT, which we always
775 * set up for 8-bits of R/G/B, or 3 bytes total.
776 */
777 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
778 mode->clock, adjusted_mode->clock, &m_n);
779
780 if (HAS_PCH_SPLIT(dev)) {
781 I915_WRITE(TRANSDATA_M1(pipe),
782 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
783 m_n.gmch_m);
784 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
785 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
786 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
787 } else {
788 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
789 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
790 m_n.gmch_m);
791 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
792 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
793 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
794 }
795 }
796
797 static void ironlake_edp_pll_on(struct drm_encoder *encoder);
798 static void ironlake_edp_pll_off(struct drm_encoder *encoder);
799
800 static void
801 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
802 struct drm_display_mode *adjusted_mode)
803 {
804 struct drm_device *dev = encoder->dev;
805 struct drm_i915_private *dev_priv = dev->dev_private;
806 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
807 struct drm_crtc *crtc = intel_dp->base.base.crtc;
808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
809
810 /* Turn on the eDP PLL if needed */
811 if (is_edp(intel_dp)) {
812 if (!is_pch_edp(intel_dp))
813 ironlake_edp_pll_on(encoder);
814 else
815 ironlake_edp_pll_off(encoder);
816 }
817
818 /*
819 * There are three kinds of DP registers:
820 *
821 * IBX PCH
822 * CPU
823 * CPT PCH
824 *
825 * IBX PCH and CPU are the same for almost everything,
826 * except that the CPU DP PLL is configured in this
827 * register
828 *
829 * CPT PCH is quite different, having many bits moved
830 * to the TRANS_DP_CTL register instead. That
831 * configuration happens (oddly) in ironlake_pch_enable
832 */
833
834 /* Preserve the BIOS-computed detected bit. This is
835 * supposed to be read-only.
836 */
837 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
838 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
839
840 /* Handle DP bits in common between all three register formats */
841
842 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
843
844 switch (intel_dp->lane_count) {
845 case 1:
846 intel_dp->DP |= DP_PORT_WIDTH_1;
847 break;
848 case 2:
849 intel_dp->DP |= DP_PORT_WIDTH_2;
850 break;
851 case 4:
852 intel_dp->DP |= DP_PORT_WIDTH_4;
853 break;
854 }
855 if (intel_dp->has_audio) {
856 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
857 pipe_name(intel_crtc->pipe));
858 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
859 intel_write_eld(encoder, adjusted_mode);
860 }
861 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
862 intel_dp->link_configuration[0] = intel_dp->link_bw;
863 intel_dp->link_configuration[1] = intel_dp->lane_count;
864 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
865 /*
866 * Check for DPCD version > 1.1 and enhanced framing support
867 */
868 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
869 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
870 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
871 }
872
873 /* Split out the IBX/CPU vs CPT settings */
874
875 if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
876 intel_dp->DP |= intel_dp->color_range;
877
878 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
879 intel_dp->DP |= DP_SYNC_HS_HIGH;
880 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
881 intel_dp->DP |= DP_SYNC_VS_HIGH;
882 intel_dp->DP |= DP_LINK_TRAIN_OFF;
883
884 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
885 intel_dp->DP |= DP_ENHANCED_FRAMING;
886
887 if (intel_crtc->pipe == 1)
888 intel_dp->DP |= DP_PIPEB_SELECT;
889
890 if (is_cpu_edp(intel_dp)) {
891 /* don't miss out required setting for eDP */
892 intel_dp->DP |= DP_PLL_ENABLE;
893 if (adjusted_mode->clock < 200000)
894 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
895 else
896 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
897 }
898 } else {
899 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
900 }
901 }
902
903 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
904 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
905
906 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
907 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
908
909 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
910 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
911
912 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
913 u32 mask,
914 u32 value)
915 {
916 struct drm_device *dev = intel_dp->base.base.dev;
917 struct drm_i915_private *dev_priv = dev->dev_private;
918
919 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
920 mask, value,
921 I915_READ(PCH_PP_STATUS),
922 I915_READ(PCH_PP_CONTROL));
923
924 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
925 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
926 I915_READ(PCH_PP_STATUS),
927 I915_READ(PCH_PP_CONTROL));
928 }
929 }
930
931 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
932 {
933 DRM_DEBUG_KMS("Wait for panel power on\n");
934 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
935 }
936
937 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
938 {
939 DRM_DEBUG_KMS("Wait for panel power off time\n");
940 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
941 }
942
943 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
944 {
945 DRM_DEBUG_KMS("Wait for panel power cycle\n");
946 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
947 }
948
949
950 /* Read the current pp_control value, unlocking the register if it
951 * is locked
952 */
953
954 static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
955 {
956 u32 control = I915_READ(PCH_PP_CONTROL);
957
958 control &= ~PANEL_UNLOCK_MASK;
959 control |= PANEL_UNLOCK_REGS;
960 return control;
961 }
962
963 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
964 {
965 struct drm_device *dev = intel_dp->base.base.dev;
966 struct drm_i915_private *dev_priv = dev->dev_private;
967 u32 pp;
968
969 if (!is_edp(intel_dp))
970 return;
971 DRM_DEBUG_KMS("Turn eDP VDD on\n");
972
973 WARN(intel_dp->want_panel_vdd,
974 "eDP VDD already requested on\n");
975
976 intel_dp->want_panel_vdd = true;
977
978 if (ironlake_edp_have_panel_vdd(intel_dp)) {
979 DRM_DEBUG_KMS("eDP VDD already on\n");
980 return;
981 }
982
983 if (!ironlake_edp_have_panel_power(intel_dp))
984 ironlake_wait_panel_power_cycle(intel_dp);
985
986 pp = ironlake_get_pp_control(dev_priv);
987 pp |= EDP_FORCE_VDD;
988 I915_WRITE(PCH_PP_CONTROL, pp);
989 POSTING_READ(PCH_PP_CONTROL);
990 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
991 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
992
993 /*
994 * If the panel wasn't on, delay before accessing aux channel
995 */
996 if (!ironlake_edp_have_panel_power(intel_dp)) {
997 DRM_DEBUG_KMS("eDP was not running\n");
998 msleep(intel_dp->panel_power_up_delay);
999 }
1000 }
1001
1002 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1003 {
1004 struct drm_device *dev = intel_dp->base.base.dev;
1005 struct drm_i915_private *dev_priv = dev->dev_private;
1006 u32 pp;
1007
1008 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1009 pp = ironlake_get_pp_control(dev_priv);
1010 pp &= ~EDP_FORCE_VDD;
1011 I915_WRITE(PCH_PP_CONTROL, pp);
1012 POSTING_READ(PCH_PP_CONTROL);
1013
1014 /* Make sure sequencer is idle before allowing subsequent activity */
1015 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1016 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1017
1018 msleep(intel_dp->panel_power_down_delay);
1019 }
1020 }
1021
1022 static void ironlake_panel_vdd_work(struct work_struct *__work)
1023 {
1024 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1025 struct intel_dp, panel_vdd_work);
1026 struct drm_device *dev = intel_dp->base.base.dev;
1027
1028 mutex_lock(&dev->mode_config.mutex);
1029 ironlake_panel_vdd_off_sync(intel_dp);
1030 mutex_unlock(&dev->mode_config.mutex);
1031 }
1032
1033 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1034 {
1035 if (!is_edp(intel_dp))
1036 return;
1037
1038 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1039 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1040
1041 intel_dp->want_panel_vdd = false;
1042
1043 if (sync) {
1044 ironlake_panel_vdd_off_sync(intel_dp);
1045 } else {
1046 /*
1047 * Queue the timer to fire a long
1048 * time from now (relative to the power down delay)
1049 * to keep the panel power up across a sequence of operations
1050 */
1051 schedule_delayed_work(&intel_dp->panel_vdd_work,
1052 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1053 }
1054 }
1055
1056 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1057 {
1058 struct drm_device *dev = intel_dp->base.base.dev;
1059 struct drm_i915_private *dev_priv = dev->dev_private;
1060 u32 pp;
1061
1062 if (!is_edp(intel_dp))
1063 return;
1064
1065 DRM_DEBUG_KMS("Turn eDP power on\n");
1066
1067 if (ironlake_edp_have_panel_power(intel_dp)) {
1068 DRM_DEBUG_KMS("eDP power already on\n");
1069 return;
1070 }
1071
1072 ironlake_wait_panel_power_cycle(intel_dp);
1073
1074 pp = ironlake_get_pp_control(dev_priv);
1075 if (IS_GEN5(dev)) {
1076 /* ILK workaround: disable reset around power sequence */
1077 pp &= ~PANEL_POWER_RESET;
1078 I915_WRITE(PCH_PP_CONTROL, pp);
1079 POSTING_READ(PCH_PP_CONTROL);
1080 }
1081
1082 pp |= POWER_TARGET_ON;
1083 if (!IS_GEN5(dev))
1084 pp |= PANEL_POWER_RESET;
1085
1086 I915_WRITE(PCH_PP_CONTROL, pp);
1087 POSTING_READ(PCH_PP_CONTROL);
1088
1089 ironlake_wait_panel_on(intel_dp);
1090
1091 if (IS_GEN5(dev)) {
1092 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1093 I915_WRITE(PCH_PP_CONTROL, pp);
1094 POSTING_READ(PCH_PP_CONTROL);
1095 }
1096 }
1097
1098 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1099 {
1100 struct drm_device *dev = intel_dp->base.base.dev;
1101 struct drm_i915_private *dev_priv = dev->dev_private;
1102 u32 pp;
1103
1104 if (!is_edp(intel_dp))
1105 return;
1106
1107 DRM_DEBUG_KMS("Turn eDP power off\n");
1108
1109 WARN(intel_dp->want_panel_vdd, "Cannot turn power off while VDD is on\n");
1110
1111 pp = ironlake_get_pp_control(dev_priv);
1112 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1113 I915_WRITE(PCH_PP_CONTROL, pp);
1114 POSTING_READ(PCH_PP_CONTROL);
1115
1116 ironlake_wait_panel_off(intel_dp);
1117 }
1118
1119 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1120 {
1121 struct drm_device *dev = intel_dp->base.base.dev;
1122 struct drm_i915_private *dev_priv = dev->dev_private;
1123 u32 pp;
1124
1125 if (!is_edp(intel_dp))
1126 return;
1127
1128 DRM_DEBUG_KMS("\n");
1129 /*
1130 * If we enable the backlight right away following a panel power
1131 * on, we may see slight flicker as the panel syncs with the eDP
1132 * link. So delay a bit to make sure the image is solid before
1133 * allowing it to appear.
1134 */
1135 msleep(intel_dp->backlight_on_delay);
1136 pp = ironlake_get_pp_control(dev_priv);
1137 pp |= EDP_BLC_ENABLE;
1138 I915_WRITE(PCH_PP_CONTROL, pp);
1139 POSTING_READ(PCH_PP_CONTROL);
1140 }
1141
1142 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1143 {
1144 struct drm_device *dev = intel_dp->base.base.dev;
1145 struct drm_i915_private *dev_priv = dev->dev_private;
1146 u32 pp;
1147
1148 if (!is_edp(intel_dp))
1149 return;
1150
1151 DRM_DEBUG_KMS("\n");
1152 pp = ironlake_get_pp_control(dev_priv);
1153 pp &= ~EDP_BLC_ENABLE;
1154 I915_WRITE(PCH_PP_CONTROL, pp);
1155 POSTING_READ(PCH_PP_CONTROL);
1156 msleep(intel_dp->backlight_off_delay);
1157 }
1158
1159 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1160 {
1161 struct drm_device *dev = encoder->dev;
1162 struct drm_i915_private *dev_priv = dev->dev_private;
1163 u32 dpa_ctl;
1164
1165 DRM_DEBUG_KMS("\n");
1166 dpa_ctl = I915_READ(DP_A);
1167 dpa_ctl |= DP_PLL_ENABLE;
1168 I915_WRITE(DP_A, dpa_ctl);
1169 POSTING_READ(DP_A);
1170 udelay(200);
1171 }
1172
1173 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1174 {
1175 struct drm_device *dev = encoder->dev;
1176 struct drm_i915_private *dev_priv = dev->dev_private;
1177 u32 dpa_ctl;
1178
1179 dpa_ctl = I915_READ(DP_A);
1180 dpa_ctl &= ~DP_PLL_ENABLE;
1181 I915_WRITE(DP_A, dpa_ctl);
1182 POSTING_READ(DP_A);
1183 udelay(200);
1184 }
1185
1186 /* If the sink supports it, try to set the power state appropriately */
1187 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1188 {
1189 int ret, i;
1190
1191 /* Should have a valid DPCD by this point */
1192 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1193 return;
1194
1195 if (mode != DRM_MODE_DPMS_ON) {
1196 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1197 DP_SET_POWER_D3);
1198 if (ret != 1)
1199 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1200 } else {
1201 /*
1202 * When turning on, we need to retry for 1ms to give the sink
1203 * time to wake up.
1204 */
1205 for (i = 0; i < 3; i++) {
1206 ret = intel_dp_aux_native_write_1(intel_dp,
1207 DP_SET_POWER,
1208 DP_SET_POWER_D0);
1209 if (ret == 1)
1210 break;
1211 msleep(1);
1212 }
1213 }
1214 }
1215
1216 static void intel_dp_prepare(struct drm_encoder *encoder)
1217 {
1218 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1219
1220 ironlake_edp_backlight_off(intel_dp);
1221 ironlake_edp_panel_off(intel_dp);
1222
1223 /* Wake up the sink first */
1224 ironlake_edp_panel_vdd_on(intel_dp);
1225 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1226 intel_dp_link_down(intel_dp);
1227 ironlake_edp_panel_vdd_off(intel_dp, false);
1228
1229 /* Make sure the panel is off before trying to
1230 * change the mode
1231 */
1232 }
1233
1234 static void intel_dp_commit(struct drm_encoder *encoder)
1235 {
1236 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1237 struct drm_device *dev = encoder->dev;
1238 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1239
1240 ironlake_edp_panel_vdd_on(intel_dp);
1241 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1242 intel_dp_start_link_train(intel_dp);
1243 ironlake_edp_panel_on(intel_dp);
1244 ironlake_edp_panel_vdd_off(intel_dp, true);
1245 intel_dp_complete_link_train(intel_dp);
1246 ironlake_edp_backlight_on(intel_dp);
1247
1248 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1249
1250 if (HAS_PCH_CPT(dev))
1251 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
1252 }
1253
1254 static void
1255 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1256 {
1257 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1258 struct drm_device *dev = encoder->dev;
1259 struct drm_i915_private *dev_priv = dev->dev_private;
1260 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1261
1262 if (mode != DRM_MODE_DPMS_ON) {
1263 ironlake_edp_backlight_off(intel_dp);
1264 ironlake_edp_panel_off(intel_dp);
1265
1266 ironlake_edp_panel_vdd_on(intel_dp);
1267 intel_dp_sink_dpms(intel_dp, mode);
1268 intel_dp_link_down(intel_dp);
1269 ironlake_edp_panel_vdd_off(intel_dp, false);
1270
1271 if (is_cpu_edp(intel_dp))
1272 ironlake_edp_pll_off(encoder);
1273 } else {
1274 if (is_cpu_edp(intel_dp))
1275 ironlake_edp_pll_on(encoder);
1276
1277 ironlake_edp_panel_vdd_on(intel_dp);
1278 intel_dp_sink_dpms(intel_dp, mode);
1279 if (!(dp_reg & DP_PORT_EN)) {
1280 intel_dp_start_link_train(intel_dp);
1281 ironlake_edp_panel_on(intel_dp);
1282 ironlake_edp_panel_vdd_off(intel_dp, true);
1283 intel_dp_complete_link_train(intel_dp);
1284 } else
1285 ironlake_edp_panel_vdd_off(intel_dp, false);
1286 ironlake_edp_backlight_on(intel_dp);
1287 }
1288 intel_dp->dpms_mode = mode;
1289 }
1290
1291 /*
1292 * Native read with retry for link status and receiver capability reads for
1293 * cases where the sink may still be asleep.
1294 */
1295 static bool
1296 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1297 uint8_t *recv, int recv_bytes)
1298 {
1299 int ret, i;
1300
1301 /*
1302 * Sinks are *supposed* to come up within 1ms from an off state,
1303 * but we're also supposed to retry 3 times per the spec.
1304 */
1305 for (i = 0; i < 3; i++) {
1306 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1307 recv_bytes);
1308 if (ret == recv_bytes)
1309 return true;
1310 msleep(1);
1311 }
1312
1313 return false;
1314 }
1315
1316 /*
1317 * Fetch AUX CH registers 0x202 - 0x207 which contain
1318 * link status information
1319 */
1320 static bool
1321 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1322 {
1323 return intel_dp_aux_native_read_retry(intel_dp,
1324 DP_LANE0_1_STATUS,
1325 link_status,
1326 DP_LINK_STATUS_SIZE);
1327 }
1328
1329 static uint8_t
1330 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1331 int r)
1332 {
1333 return link_status[r - DP_LANE0_1_STATUS];
1334 }
1335
1336 static uint8_t
1337 intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1338 int lane)
1339 {
1340 int s = ((lane & 1) ?
1341 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1342 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1343 uint8_t l = adjust_request[lane>>1];
1344
1345 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1346 }
1347
1348 static uint8_t
1349 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1350 int lane)
1351 {
1352 int s = ((lane & 1) ?
1353 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1354 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1355 uint8_t l = adjust_request[lane>>1];
1356
1357 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1358 }
1359
1360
1361 #if 0
1362 static char *voltage_names[] = {
1363 "0.4V", "0.6V", "0.8V", "1.2V"
1364 };
1365 static char *pre_emph_names[] = {
1366 "0dB", "3.5dB", "6dB", "9.5dB"
1367 };
1368 static char *link_train_names[] = {
1369 "pattern 1", "pattern 2", "idle", "off"
1370 };
1371 #endif
1372
1373 /*
1374 * These are source-specific values; current Intel hardware supports
1375 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1376 */
1377 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
1378 #define I830_DP_VOLTAGE_MAX_CPT DP_TRAIN_VOLTAGE_SWING_1200
1379
1380 static uint8_t
1381 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1382 {
1383 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1384 case DP_TRAIN_VOLTAGE_SWING_400:
1385 return DP_TRAIN_PRE_EMPHASIS_6;
1386 case DP_TRAIN_VOLTAGE_SWING_600:
1387 return DP_TRAIN_PRE_EMPHASIS_6;
1388 case DP_TRAIN_VOLTAGE_SWING_800:
1389 return DP_TRAIN_PRE_EMPHASIS_3_5;
1390 case DP_TRAIN_VOLTAGE_SWING_1200:
1391 default:
1392 return DP_TRAIN_PRE_EMPHASIS_0;
1393 }
1394 }
1395
1396 static void
1397 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1398 {
1399 struct drm_device *dev = intel_dp->base.base.dev;
1400 uint8_t v = 0;
1401 uint8_t p = 0;
1402 int lane;
1403 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1404 int voltage_max;
1405
1406 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1407 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1408 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1409
1410 if (this_v > v)
1411 v = this_v;
1412 if (this_p > p)
1413 p = this_p;
1414 }
1415
1416 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1417 voltage_max = I830_DP_VOLTAGE_MAX_CPT;
1418 else
1419 voltage_max = I830_DP_VOLTAGE_MAX;
1420 if (v >= voltage_max)
1421 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1422
1423 if (p >= intel_dp_pre_emphasis_max(v))
1424 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1425
1426 for (lane = 0; lane < 4; lane++)
1427 intel_dp->train_set[lane] = v | p;
1428 }
1429
1430 static uint32_t
1431 intel_dp_signal_levels(uint8_t train_set)
1432 {
1433 uint32_t signal_levels = 0;
1434
1435 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1436 case DP_TRAIN_VOLTAGE_SWING_400:
1437 default:
1438 signal_levels |= DP_VOLTAGE_0_4;
1439 break;
1440 case DP_TRAIN_VOLTAGE_SWING_600:
1441 signal_levels |= DP_VOLTAGE_0_6;
1442 break;
1443 case DP_TRAIN_VOLTAGE_SWING_800:
1444 signal_levels |= DP_VOLTAGE_0_8;
1445 break;
1446 case DP_TRAIN_VOLTAGE_SWING_1200:
1447 signal_levels |= DP_VOLTAGE_1_2;
1448 break;
1449 }
1450 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1451 case DP_TRAIN_PRE_EMPHASIS_0:
1452 default:
1453 signal_levels |= DP_PRE_EMPHASIS_0;
1454 break;
1455 case DP_TRAIN_PRE_EMPHASIS_3_5:
1456 signal_levels |= DP_PRE_EMPHASIS_3_5;
1457 break;
1458 case DP_TRAIN_PRE_EMPHASIS_6:
1459 signal_levels |= DP_PRE_EMPHASIS_6;
1460 break;
1461 case DP_TRAIN_PRE_EMPHASIS_9_5:
1462 signal_levels |= DP_PRE_EMPHASIS_9_5;
1463 break;
1464 }
1465 return signal_levels;
1466 }
1467
1468 /* Gen6's DP voltage swing and pre-emphasis control */
1469 static uint32_t
1470 intel_gen6_edp_signal_levels(uint8_t train_set)
1471 {
1472 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1473 DP_TRAIN_PRE_EMPHASIS_MASK);
1474 switch (signal_levels) {
1475 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1476 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1477 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1478 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1479 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1480 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1481 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1482 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1483 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1484 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1485 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1486 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1487 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1488 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1489 default:
1490 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1491 "0x%x\n", signal_levels);
1492 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1493 }
1494 }
1495
1496 static uint8_t
1497 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1498 int lane)
1499 {
1500 int s = (lane & 1) * 4;
1501 uint8_t l = link_status[lane>>1];
1502
1503 return (l >> s) & 0xf;
1504 }
1505
1506 /* Check for clock recovery is done on all channels */
1507 static bool
1508 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1509 {
1510 int lane;
1511 uint8_t lane_status;
1512
1513 for (lane = 0; lane < lane_count; lane++) {
1514 lane_status = intel_get_lane_status(link_status, lane);
1515 if ((lane_status & DP_LANE_CR_DONE) == 0)
1516 return false;
1517 }
1518 return true;
1519 }
1520
1521 /* Check to see if channel eq is done on all channels */
1522 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1523 DP_LANE_CHANNEL_EQ_DONE|\
1524 DP_LANE_SYMBOL_LOCKED)
1525 static bool
1526 intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1527 {
1528 uint8_t lane_align;
1529 uint8_t lane_status;
1530 int lane;
1531
1532 lane_align = intel_dp_link_status(link_status,
1533 DP_LANE_ALIGN_STATUS_UPDATED);
1534 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1535 return false;
1536 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1537 lane_status = intel_get_lane_status(link_status, lane);
1538 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1539 return false;
1540 }
1541 return true;
1542 }
1543
1544 static bool
1545 intel_dp_set_link_train(struct intel_dp *intel_dp,
1546 uint32_t dp_reg_value,
1547 uint8_t dp_train_pat)
1548 {
1549 struct drm_device *dev = intel_dp->base.base.dev;
1550 struct drm_i915_private *dev_priv = dev->dev_private;
1551 int ret;
1552
1553 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1554 POSTING_READ(intel_dp->output_reg);
1555
1556 intel_dp_aux_native_write_1(intel_dp,
1557 DP_TRAINING_PATTERN_SET,
1558 dp_train_pat);
1559
1560 ret = intel_dp_aux_native_write(intel_dp,
1561 DP_TRAINING_LANE0_SET,
1562 intel_dp->train_set,
1563 intel_dp->lane_count);
1564 if (ret != intel_dp->lane_count)
1565 return false;
1566
1567 return true;
1568 }
1569
1570 /* Enable corresponding port and start training pattern 1 */
1571 static void
1572 intel_dp_start_link_train(struct intel_dp *intel_dp)
1573 {
1574 struct drm_device *dev = intel_dp->base.base.dev;
1575 struct drm_i915_private *dev_priv = dev->dev_private;
1576 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1577 int i;
1578 uint8_t voltage;
1579 bool clock_recovery = false;
1580 int voltage_tries, loop_tries;
1581 u32 reg;
1582 uint32_t DP = intel_dp->DP;
1583
1584 /*
1585 * On CPT we have to enable the port in training pattern 1, which
1586 * will happen below in intel_dp_set_link_train. Otherwise, enable
1587 * the port and wait for it to become active.
1588 */
1589 if (!HAS_PCH_CPT(dev)) {
1590 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1591 POSTING_READ(intel_dp->output_reg);
1592 intel_wait_for_vblank(dev, intel_crtc->pipe);
1593 }
1594
1595 /* Write the link configuration data */
1596 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1597 intel_dp->link_configuration,
1598 DP_LINK_CONFIGURATION_SIZE);
1599
1600 DP |= DP_PORT_EN;
1601 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1602 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1603 else
1604 DP &= ~DP_LINK_TRAIN_MASK;
1605 memset(intel_dp->train_set, 0, 4);
1606 voltage = 0xff;
1607 voltage_tries = 0;
1608 loop_tries = 0;
1609 clock_recovery = false;
1610 for (;;) {
1611 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1612 uint8_t link_status[DP_LINK_STATUS_SIZE];
1613 uint32_t signal_levels;
1614
1615 if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1616 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1617 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1618 } else {
1619 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1620 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
1621 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1622 }
1623
1624 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1625 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1626 else
1627 reg = DP | DP_LINK_TRAIN_PAT_1;
1628
1629 if (!intel_dp_set_link_train(intel_dp, reg,
1630 DP_TRAINING_PATTERN_1 |
1631 DP_LINK_SCRAMBLING_DISABLE))
1632 break;
1633 /* Set training pattern 1 */
1634
1635 udelay(100);
1636 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1637 DRM_ERROR("failed to get link status\n");
1638 break;
1639 }
1640
1641 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1642 DRM_DEBUG_KMS("clock recovery OK\n");
1643 clock_recovery = true;
1644 break;
1645 }
1646
1647 /* Check to see if we've tried the max voltage */
1648 for (i = 0; i < intel_dp->lane_count; i++)
1649 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1650 break;
1651 if (i == intel_dp->lane_count) {
1652 ++loop_tries;
1653 if (loop_tries == 5) {
1654 DRM_DEBUG_KMS("too many full retries, give up\n");
1655 break;
1656 }
1657 memset(intel_dp->train_set, 0, 4);
1658 voltage_tries = 0;
1659 continue;
1660 }
1661
1662 /* Check to see if we've tried the same voltage 5 times */
1663 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1664 ++voltage_tries;
1665 if (voltage_tries == 5) {
1666 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1667 break;
1668 }
1669 } else
1670 voltage_tries = 0;
1671 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1672
1673 /* Compute new intel_dp->train_set as requested by target */
1674 intel_get_adjust_train(intel_dp, link_status);
1675 }
1676
1677 intel_dp->DP = DP;
1678 }
1679
1680 static void
1681 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1682 {
1683 struct drm_device *dev = intel_dp->base.base.dev;
1684 struct drm_i915_private *dev_priv = dev->dev_private;
1685 bool channel_eq = false;
1686 int tries, cr_tries;
1687 u32 reg;
1688 uint32_t DP = intel_dp->DP;
1689
1690 /* channel equalization */
1691 tries = 0;
1692 cr_tries = 0;
1693 channel_eq = false;
1694 for (;;) {
1695 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1696 uint32_t signal_levels;
1697 uint8_t link_status[DP_LINK_STATUS_SIZE];
1698
1699 if (cr_tries > 5) {
1700 DRM_ERROR("failed to train DP, aborting\n");
1701 intel_dp_link_down(intel_dp);
1702 break;
1703 }
1704
1705 if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1706 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1707 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1708 } else {
1709 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1710 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1711 }
1712
1713 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1714 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1715 else
1716 reg = DP | DP_LINK_TRAIN_PAT_2;
1717
1718 /* channel eq pattern */
1719 if (!intel_dp_set_link_train(intel_dp, reg,
1720 DP_TRAINING_PATTERN_2 |
1721 DP_LINK_SCRAMBLING_DISABLE))
1722 break;
1723
1724 udelay(400);
1725 if (!intel_dp_get_link_status(intel_dp, link_status))
1726 break;
1727
1728 /* Make sure clock is still ok */
1729 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1730 intel_dp_start_link_train(intel_dp);
1731 cr_tries++;
1732 continue;
1733 }
1734
1735 if (intel_channel_eq_ok(intel_dp, link_status)) {
1736 channel_eq = true;
1737 break;
1738 }
1739
1740 /* Try 5 times, then try clock recovery if that fails */
1741 if (tries > 5) {
1742 intel_dp_link_down(intel_dp);
1743 intel_dp_start_link_train(intel_dp);
1744 tries = 0;
1745 cr_tries++;
1746 continue;
1747 }
1748
1749 /* Compute new intel_dp->train_set as requested by target */
1750 intel_get_adjust_train(intel_dp, link_status);
1751 ++tries;
1752 }
1753
1754 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1755 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1756 else
1757 reg = DP | DP_LINK_TRAIN_OFF;
1758
1759 I915_WRITE(intel_dp->output_reg, reg);
1760 POSTING_READ(intel_dp->output_reg);
1761 intel_dp_aux_native_write_1(intel_dp,
1762 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1763 }
1764
1765 static void
1766 intel_dp_link_down(struct intel_dp *intel_dp)
1767 {
1768 struct drm_device *dev = intel_dp->base.base.dev;
1769 struct drm_i915_private *dev_priv = dev->dev_private;
1770 uint32_t DP = intel_dp->DP;
1771
1772 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1773 return;
1774
1775 DRM_DEBUG_KMS("\n");
1776
1777 if (is_edp(intel_dp)) {
1778 DP &= ~DP_PLL_ENABLE;
1779 I915_WRITE(intel_dp->output_reg, DP);
1780 POSTING_READ(intel_dp->output_reg);
1781 udelay(100);
1782 }
1783
1784 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) {
1785 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1786 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1787 } else {
1788 DP &= ~DP_LINK_TRAIN_MASK;
1789 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1790 }
1791 POSTING_READ(intel_dp->output_reg);
1792
1793 msleep(17);
1794
1795 if (is_edp(intel_dp)) {
1796 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1797 DP |= DP_LINK_TRAIN_OFF_CPT;
1798 else
1799 DP |= DP_LINK_TRAIN_OFF;
1800 }
1801
1802 if (!HAS_PCH_CPT(dev) &&
1803 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1804 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1805
1806 /* Hardware workaround: leaving our transcoder select
1807 * set to transcoder B while it's off will prevent the
1808 * corresponding HDMI output on transcoder A.
1809 *
1810 * Combine this with another hardware workaround:
1811 * transcoder select bit can only be cleared while the
1812 * port is enabled.
1813 */
1814 DP &= ~DP_PIPEB_SELECT;
1815 I915_WRITE(intel_dp->output_reg, DP);
1816
1817 /* Changes to enable or select take place the vblank
1818 * after being written.
1819 */
1820 if (crtc == NULL) {
1821 /* We can arrive here never having been attached
1822 * to a CRTC, for instance, due to inheriting
1823 * random state from the BIOS.
1824 *
1825 * If the pipe is not running, play safe and
1826 * wait for the clocks to stabilise before
1827 * continuing.
1828 */
1829 POSTING_READ(intel_dp->output_reg);
1830 msleep(50);
1831 } else
1832 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1833 }
1834
1835 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1836 POSTING_READ(intel_dp->output_reg);
1837 msleep(intel_dp->panel_power_down_delay);
1838 }
1839
1840 static bool
1841 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1842 {
1843 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1844 sizeof(intel_dp->dpcd)) &&
1845 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1846 return true;
1847 }
1848
1849 return false;
1850 }
1851
1852 static bool
1853 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1854 {
1855 int ret;
1856
1857 ret = intel_dp_aux_native_read_retry(intel_dp,
1858 DP_DEVICE_SERVICE_IRQ_VECTOR,
1859 sink_irq_vector, 1);
1860 if (!ret)
1861 return false;
1862
1863 return true;
1864 }
1865
1866 static void
1867 intel_dp_handle_test_request(struct intel_dp *intel_dp)
1868 {
1869 /* NAK by default */
1870 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
1871 }
1872
1873 /*
1874 * According to DP spec
1875 * 5.1.2:
1876 * 1. Read DPCD
1877 * 2. Configure link according to Receiver Capabilities
1878 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1879 * 4. Check link status on receipt of hot-plug interrupt
1880 */
1881
1882 static void
1883 intel_dp_check_link_status(struct intel_dp *intel_dp)
1884 {
1885 u8 sink_irq_vector;
1886 u8 link_status[DP_LINK_STATUS_SIZE];
1887
1888 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1889 return;
1890
1891 if (!intel_dp->base.base.crtc)
1892 return;
1893
1894 /* Try to read receiver status if the link appears to be up */
1895 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1896 intel_dp_link_down(intel_dp);
1897 return;
1898 }
1899
1900 /* Now read the DPCD to see if it's actually running */
1901 if (!intel_dp_get_dpcd(intel_dp)) {
1902 intel_dp_link_down(intel_dp);
1903 return;
1904 }
1905
1906 /* Try to read the source of the interrupt */
1907 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
1908 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
1909 /* Clear interrupt source */
1910 intel_dp_aux_native_write_1(intel_dp,
1911 DP_DEVICE_SERVICE_IRQ_VECTOR,
1912 sink_irq_vector);
1913
1914 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
1915 intel_dp_handle_test_request(intel_dp);
1916 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
1917 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
1918 }
1919
1920 if (!intel_channel_eq_ok(intel_dp, link_status)) {
1921 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
1922 drm_get_encoder_name(&intel_dp->base.base));
1923 intel_dp_start_link_train(intel_dp);
1924 intel_dp_complete_link_train(intel_dp);
1925 }
1926 }
1927
1928 static enum drm_connector_status
1929 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
1930 {
1931 if (intel_dp_get_dpcd(intel_dp))
1932 return connector_status_connected;
1933 return connector_status_disconnected;
1934 }
1935
1936 static enum drm_connector_status
1937 ironlake_dp_detect(struct intel_dp *intel_dp)
1938 {
1939 enum drm_connector_status status;
1940
1941 /* Can't disconnect eDP, but you can close the lid... */
1942 if (is_edp(intel_dp)) {
1943 status = intel_panel_detect(intel_dp->base.base.dev);
1944 if (status == connector_status_unknown)
1945 status = connector_status_connected;
1946 return status;
1947 }
1948
1949 return intel_dp_detect_dpcd(intel_dp);
1950 }
1951
1952 static enum drm_connector_status
1953 g4x_dp_detect(struct intel_dp *intel_dp)
1954 {
1955 struct drm_device *dev = intel_dp->base.base.dev;
1956 struct drm_i915_private *dev_priv = dev->dev_private;
1957 uint32_t temp, bit;
1958
1959 switch (intel_dp->output_reg) {
1960 case DP_B:
1961 bit = DPB_HOTPLUG_INT_STATUS;
1962 break;
1963 case DP_C:
1964 bit = DPC_HOTPLUG_INT_STATUS;
1965 break;
1966 case DP_D:
1967 bit = DPD_HOTPLUG_INT_STATUS;
1968 break;
1969 default:
1970 return connector_status_unknown;
1971 }
1972
1973 temp = I915_READ(PORT_HOTPLUG_STAT);
1974
1975 if ((temp & bit) == 0)
1976 return connector_status_disconnected;
1977
1978 return intel_dp_detect_dpcd(intel_dp);
1979 }
1980
1981 static struct edid *
1982 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
1983 {
1984 struct intel_dp *intel_dp = intel_attached_dp(connector);
1985 struct edid *edid;
1986
1987 ironlake_edp_panel_vdd_on(intel_dp);
1988 edid = drm_get_edid(connector, adapter);
1989 ironlake_edp_panel_vdd_off(intel_dp, false);
1990 return edid;
1991 }
1992
1993 static int
1994 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
1995 {
1996 struct intel_dp *intel_dp = intel_attached_dp(connector);
1997 int ret;
1998
1999 ironlake_edp_panel_vdd_on(intel_dp);
2000 ret = intel_ddc_get_modes(connector, adapter);
2001 ironlake_edp_panel_vdd_off(intel_dp, false);
2002 return ret;
2003 }
2004
2005
2006 /**
2007 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2008 *
2009 * \return true if DP port is connected.
2010 * \return false if DP port is disconnected.
2011 */
2012 static enum drm_connector_status
2013 intel_dp_detect(struct drm_connector *connector, bool force)
2014 {
2015 struct intel_dp *intel_dp = intel_attached_dp(connector);
2016 struct drm_device *dev = intel_dp->base.base.dev;
2017 enum drm_connector_status status;
2018 struct edid *edid = NULL;
2019
2020 intel_dp->has_audio = false;
2021
2022 if (HAS_PCH_SPLIT(dev))
2023 status = ironlake_dp_detect(intel_dp);
2024 else
2025 status = g4x_dp_detect(intel_dp);
2026
2027 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2028 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2029 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2030 intel_dp->dpcd[6], intel_dp->dpcd[7]);
2031
2032 if (status != connector_status_connected)
2033 return status;
2034
2035 if (intel_dp->force_audio) {
2036 intel_dp->has_audio = intel_dp->force_audio > 0;
2037 } else {
2038 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2039 if (edid) {
2040 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2041 connector->display_info.raw_edid = NULL;
2042 kfree(edid);
2043 }
2044 }
2045
2046 return connector_status_connected;
2047 }
2048
2049 static int intel_dp_get_modes(struct drm_connector *connector)
2050 {
2051 struct intel_dp *intel_dp = intel_attached_dp(connector);
2052 struct drm_device *dev = intel_dp->base.base.dev;
2053 struct drm_i915_private *dev_priv = dev->dev_private;
2054 int ret;
2055
2056 /* We should parse the EDID data and find out if it has an audio sink
2057 */
2058
2059 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2060 if (ret) {
2061 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2062 struct drm_display_mode *newmode;
2063 list_for_each_entry(newmode, &connector->probed_modes,
2064 head) {
2065 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2066 intel_dp->panel_fixed_mode =
2067 drm_mode_duplicate(dev, newmode);
2068 break;
2069 }
2070 }
2071 }
2072 return ret;
2073 }
2074
2075 /* if eDP has no EDID, try to use fixed panel mode from VBT */
2076 if (is_edp(intel_dp)) {
2077 /* initialize panel mode from VBT if available for eDP */
2078 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2079 intel_dp->panel_fixed_mode =
2080 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2081 if (intel_dp->panel_fixed_mode) {
2082 intel_dp->panel_fixed_mode->type |=
2083 DRM_MODE_TYPE_PREFERRED;
2084 }
2085 }
2086 if (intel_dp->panel_fixed_mode) {
2087 struct drm_display_mode *mode;
2088 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2089 drm_mode_probed_add(connector, mode);
2090 return 1;
2091 }
2092 }
2093 return 0;
2094 }
2095
2096 static bool
2097 intel_dp_detect_audio(struct drm_connector *connector)
2098 {
2099 struct intel_dp *intel_dp = intel_attached_dp(connector);
2100 struct edid *edid;
2101 bool has_audio = false;
2102
2103 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2104 if (edid) {
2105 has_audio = drm_detect_monitor_audio(edid);
2106
2107 connector->display_info.raw_edid = NULL;
2108 kfree(edid);
2109 }
2110
2111 return has_audio;
2112 }
2113
2114 static int
2115 intel_dp_set_property(struct drm_connector *connector,
2116 struct drm_property *property,
2117 uint64_t val)
2118 {
2119 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2120 struct intel_dp *intel_dp = intel_attached_dp(connector);
2121 int ret;
2122
2123 ret = drm_connector_property_set_value(connector, property, val);
2124 if (ret)
2125 return ret;
2126
2127 if (property == dev_priv->force_audio_property) {
2128 int i = val;
2129 bool has_audio;
2130
2131 if (i == intel_dp->force_audio)
2132 return 0;
2133
2134 intel_dp->force_audio = i;
2135
2136 if (i == 0)
2137 has_audio = intel_dp_detect_audio(connector);
2138 else
2139 has_audio = i > 0;
2140
2141 if (has_audio == intel_dp->has_audio)
2142 return 0;
2143
2144 intel_dp->has_audio = has_audio;
2145 goto done;
2146 }
2147
2148 if (property == dev_priv->broadcast_rgb_property) {
2149 if (val == !!intel_dp->color_range)
2150 return 0;
2151
2152 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2153 goto done;
2154 }
2155
2156 return -EINVAL;
2157
2158 done:
2159 if (intel_dp->base.base.crtc) {
2160 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2161 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2162 crtc->x, crtc->y,
2163 crtc->fb);
2164 }
2165
2166 return 0;
2167 }
2168
2169 static void
2170 intel_dp_destroy(struct drm_connector *connector)
2171 {
2172 struct drm_device *dev = connector->dev;
2173
2174 if (intel_dpd_is_edp(dev))
2175 intel_panel_destroy_backlight(dev);
2176
2177 drm_sysfs_connector_remove(connector);
2178 drm_connector_cleanup(connector);
2179 kfree(connector);
2180 }
2181
2182 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2183 {
2184 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2185
2186 i2c_del_adapter(&intel_dp->adapter);
2187 drm_encoder_cleanup(encoder);
2188 if (is_edp(intel_dp)) {
2189 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2190 ironlake_panel_vdd_off_sync(intel_dp);
2191 }
2192 kfree(intel_dp);
2193 }
2194
2195 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2196 .dpms = intel_dp_dpms,
2197 .mode_fixup = intel_dp_mode_fixup,
2198 .prepare = intel_dp_prepare,
2199 .mode_set = intel_dp_mode_set,
2200 .commit = intel_dp_commit,
2201 };
2202
2203 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2204 .dpms = drm_helper_connector_dpms,
2205 .detect = intel_dp_detect,
2206 .fill_modes = drm_helper_probe_single_connector_modes,
2207 .set_property = intel_dp_set_property,
2208 .destroy = intel_dp_destroy,
2209 };
2210
2211 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2212 .get_modes = intel_dp_get_modes,
2213 .mode_valid = intel_dp_mode_valid,
2214 .best_encoder = intel_best_encoder,
2215 };
2216
2217 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2218 .destroy = intel_dp_encoder_destroy,
2219 };
2220
2221 static void
2222 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2223 {
2224 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2225
2226 intel_dp_check_link_status(intel_dp);
2227 }
2228
2229 /* Return which DP Port should be selected for Transcoder DP control */
2230 int
2231 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2232 {
2233 struct drm_device *dev = crtc->dev;
2234 struct drm_mode_config *mode_config = &dev->mode_config;
2235 struct drm_encoder *encoder;
2236
2237 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
2238 struct intel_dp *intel_dp;
2239
2240 if (encoder->crtc != crtc)
2241 continue;
2242
2243 intel_dp = enc_to_intel_dp(encoder);
2244 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2245 intel_dp->base.type == INTEL_OUTPUT_EDP)
2246 return intel_dp->output_reg;
2247 }
2248
2249 return -1;
2250 }
2251
2252 /* check the VBT to see whether the eDP is on DP-D port */
2253 bool intel_dpd_is_edp(struct drm_device *dev)
2254 {
2255 struct drm_i915_private *dev_priv = dev->dev_private;
2256 struct child_device_config *p_child;
2257 int i;
2258
2259 if (!dev_priv->child_dev_num)
2260 return false;
2261
2262 for (i = 0; i < dev_priv->child_dev_num; i++) {
2263 p_child = dev_priv->child_dev + i;
2264
2265 if (p_child->dvo_port == PORT_IDPD &&
2266 p_child->device_type == DEVICE_TYPE_eDP)
2267 return true;
2268 }
2269 return false;
2270 }
2271
2272 static void
2273 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2274 {
2275 intel_attach_force_audio_property(connector);
2276 intel_attach_broadcast_rgb_property(connector);
2277 }
2278
2279 void
2280 intel_dp_init(struct drm_device *dev, int output_reg)
2281 {
2282 struct drm_i915_private *dev_priv = dev->dev_private;
2283 struct drm_connector *connector;
2284 struct intel_dp *intel_dp;
2285 struct intel_encoder *intel_encoder;
2286 struct intel_connector *intel_connector;
2287 const char *name = NULL;
2288 int type;
2289
2290 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2291 if (!intel_dp)
2292 return;
2293
2294 intel_dp->output_reg = output_reg;
2295 intel_dp->dpms_mode = -1;
2296
2297 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2298 if (!intel_connector) {
2299 kfree(intel_dp);
2300 return;
2301 }
2302 intel_encoder = &intel_dp->base;
2303
2304 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2305 if (intel_dpd_is_edp(dev))
2306 intel_dp->is_pch_edp = true;
2307
2308 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2309 type = DRM_MODE_CONNECTOR_eDP;
2310 intel_encoder->type = INTEL_OUTPUT_EDP;
2311 } else {
2312 type = DRM_MODE_CONNECTOR_DisplayPort;
2313 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2314 }
2315
2316 connector = &intel_connector->base;
2317 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2318 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2319
2320 connector->polled = DRM_CONNECTOR_POLL_HPD;
2321
2322 if (output_reg == DP_B || output_reg == PCH_DP_B)
2323 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2324 else if (output_reg == DP_C || output_reg == PCH_DP_C)
2325 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
2326 else if (output_reg == DP_D || output_reg == PCH_DP_D)
2327 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
2328
2329 if (is_edp(intel_dp)) {
2330 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2331 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2332 ironlake_panel_vdd_work);
2333 }
2334
2335 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2336 connector->interlace_allowed = true;
2337 connector->doublescan_allowed = 0;
2338
2339 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2340 DRM_MODE_ENCODER_TMDS);
2341 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2342
2343 intel_connector_attach_encoder(intel_connector, intel_encoder);
2344 drm_sysfs_connector_add(connector);
2345
2346 /* Set up the DDC bus. */
2347 switch (output_reg) {
2348 case DP_A:
2349 name = "DPDDC-A";
2350 break;
2351 case DP_B:
2352 case PCH_DP_B:
2353 dev_priv->hotplug_supported_mask |=
2354 HDMIB_HOTPLUG_INT_STATUS;
2355 name = "DPDDC-B";
2356 break;
2357 case DP_C:
2358 case PCH_DP_C:
2359 dev_priv->hotplug_supported_mask |=
2360 HDMIC_HOTPLUG_INT_STATUS;
2361 name = "DPDDC-C";
2362 break;
2363 case DP_D:
2364 case PCH_DP_D:
2365 dev_priv->hotplug_supported_mask |=
2366 HDMID_HOTPLUG_INT_STATUS;
2367 name = "DPDDC-D";
2368 break;
2369 }
2370
2371 /* Cache some DPCD data in the eDP case */
2372 if (is_edp(intel_dp)) {
2373 bool ret;
2374 struct edp_power_seq cur, vbt;
2375 u32 pp_on, pp_off, pp_div;
2376
2377 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2378 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2379 pp_div = I915_READ(PCH_PP_DIVISOR);
2380
2381 /* Pull timing values out of registers */
2382 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2383 PANEL_POWER_UP_DELAY_SHIFT;
2384
2385 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2386 PANEL_LIGHT_ON_DELAY_SHIFT;
2387
2388 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2389 PANEL_LIGHT_OFF_DELAY_SHIFT;
2390
2391 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2392 PANEL_POWER_DOWN_DELAY_SHIFT;
2393
2394 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2395 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2396
2397 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2398 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2399
2400 vbt = dev_priv->edp.pps;
2401
2402 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2403 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2404
2405 #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2406
2407 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2408 intel_dp->backlight_on_delay = get_delay(t8);
2409 intel_dp->backlight_off_delay = get_delay(t9);
2410 intel_dp->panel_power_down_delay = get_delay(t10);
2411 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2412
2413 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2414 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2415 intel_dp->panel_power_cycle_delay);
2416
2417 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2418 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2419
2420 ironlake_edp_panel_vdd_on(intel_dp);
2421 ret = intel_dp_get_dpcd(intel_dp);
2422 ironlake_edp_panel_vdd_off(intel_dp, false);
2423
2424 if (ret) {
2425 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2426 dev_priv->no_aux_handshake =
2427 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2428 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2429 } else {
2430 /* if this fails, presume the device is a ghost */
2431 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2432 intel_dp_encoder_destroy(&intel_dp->base.base);
2433 intel_dp_destroy(&intel_connector->base);
2434 return;
2435 }
2436 }
2437
2438 intel_dp_i2c_init(intel_dp, intel_connector, name);
2439
2440 intel_encoder->hot_plug = intel_dp_hot_plug;
2441
2442 if (is_edp(intel_dp)) {
2443 dev_priv->int_edp_connector = connector;
2444 intel_panel_setup_backlight(dev);
2445 }
2446
2447 intel_dp_add_properties(intel_dp, connector);
2448
2449 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2450 * 0xd. Failure to do so will result in spurious interrupts being
2451 * generated on the port when a cable is not attached.
2452 */
2453 if (IS_G4X(dev) && !IS_GM45(dev)) {
2454 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2455 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2456 }
2457 }
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