2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/types.h>
18 #include <linux/atomic.h>
19 #include <linux/kernel.h>
20 #include <linux/kthread.h>
21 #include <linux/printk.h>
22 #include <linux/pci_ids.h>
23 #include <linux/netdevice.h>
24 #include <linux/interrupt.h>
25 #include <linux/sched.h>
26 #include <linux/mmc/sdio.h>
27 #include <linux/mmc/sdio_ids.h>
28 #include <linux/mmc/sdio_func.h>
29 #include <linux/mmc/card.h>
30 #include <linux/semaphore.h>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
33 #include <linux/bcma/bcma.h>
34 #include <linux/debugfs.h>
35 #include <linux/vmalloc.h>
36 #include <asm/unaligned.h>
38 #include <brcmu_wifi.h>
39 #include <brcmu_utils.h>
40 #include <brcm_hw_ids.h>
48 #define DCMD_RESP_TIMEOUT msecs_to_jiffies(2500)
49 #define CTL_DONE_TIMEOUT msecs_to_jiffies(2500)
53 #define BRCMF_TRAP_INFO_SIZE 80
55 #define CBUF_LEN (128)
57 /* Device console log buffer state */
58 #define CONSOLE_BUFFER_MAX 2024
61 __le32 buf
; /* Can't be pointer on (64-bit) hosts */
64 char *_buf_compat
; /* Redundant pointer for backward compat. */
69 * When there is no UART (e.g. Quickturn),
70 * the host should write a complete
71 * input line directly into cbuf and then write
72 * the length into vcons_in.
73 * This may also be used when there is a real UART
74 * (at risk of conflicting with
75 * the real UART). vcons_out is currently unused.
80 /* Output (logging) buffer
81 * Console output is written to a ring buffer log_buf at index log_idx.
82 * The host may read the output when it sees log_idx advance.
83 * Output will be lost if the output wraps around faster than the host
86 struct rte_log_le log_le
;
88 /* Console input line buffer
89 * Characters are read one at a time into cbuf
90 * until <CR> is received, then
91 * the buffer is processed as a command line.
92 * Also used for virtual UART.
99 #include <chipcommon.h>
103 #include "tracepoint.h"
105 #define TXQLEN 2048 /* bulk tx queue length */
106 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
107 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
110 #define TXRETRIES 2 /* # of retries for tx frames */
112 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
115 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
118 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
120 #define MEMBLOCK 2048 /* Block size used for downloading
122 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
123 biggest possible glom */
125 #define BRCMF_FIRSTREAD (1 << 6)
127 #define BRCMF_CONSOLE 10 /* watchdog interval to poll console */
129 /* SBSDIO_DEVICE_CTL */
131 /* 1: device will assert busy signal when receiving CMD53 */
132 #define SBSDIO_DEVCTL_SETBUSY 0x01
133 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
134 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
135 /* 1: mask all interrupts to host except the chipActive (rev 8) */
136 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
137 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
138 * sdio bus power cycle to clear (rev 9) */
139 #define SBSDIO_DEVCTL_PADS_ISO 0x08
140 /* Force SD->SB reset mapping (rev 11) */
141 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
142 /* Determined by CoreControl bit */
143 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
144 /* Force backplane reset */
145 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
146 /* Force no backplane reset */
147 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
149 /* direct(mapped) cis space */
151 /* MAPPED common CIS address */
152 #define SBSDIO_CIS_BASE_COMMON 0x1000
153 /* maximum bytes in one CIS */
154 #define SBSDIO_CIS_SIZE_LIMIT 0x200
155 /* cis offset addr is < 17 bits */
156 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
158 /* manfid tuple length, include tuple, link bytes */
159 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
161 #define CORE_BUS_REG(base, field) \
162 (base + offsetof(struct sdpcmd_regs, field))
164 /* SDIO function 1 register CHIPCLKCSR */
165 /* Force ALP request to backplane */
166 #define SBSDIO_FORCE_ALP 0x01
167 /* Force HT request to backplane */
168 #define SBSDIO_FORCE_HT 0x02
169 /* Force ILP request to backplane */
170 #define SBSDIO_FORCE_ILP 0x04
171 /* Make ALP ready (power up xtal) */
172 #define SBSDIO_ALP_AVAIL_REQ 0x08
173 /* Make HT ready (power up PLL) */
174 #define SBSDIO_HT_AVAIL_REQ 0x10
175 /* Squelch clock requests from HW */
176 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
177 /* Status: ALP is ready */
178 #define SBSDIO_ALP_AVAIL 0x40
179 /* Status: HT is ready */
180 #define SBSDIO_HT_AVAIL 0x80
181 #define SBSDIO_CSR_MASK 0x1F
182 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
183 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
184 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
185 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
186 #define SBSDIO_CLKAV(regval, alponly) \
187 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
190 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
191 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
192 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
193 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
194 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
195 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
196 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
197 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
198 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
199 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
200 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
201 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
202 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
203 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
204 #define I_PC (1 << 10) /* descriptor error */
205 #define I_PD (1 << 11) /* data error */
206 #define I_DE (1 << 12) /* Descriptor protocol Error */
207 #define I_RU (1 << 13) /* Receive descriptor Underflow */
208 #define I_RO (1 << 14) /* Receive fifo Overflow */
209 #define I_XU (1 << 15) /* Transmit fifo Underflow */
210 #define I_RI (1 << 16) /* Receive Interrupt */
211 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
212 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
213 #define I_XI (1 << 24) /* Transmit Interrupt */
214 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
215 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
216 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
217 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
218 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
219 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
220 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
221 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
222 #define I_DMA (I_RI | I_XI | I_ERRORS)
225 #define CC_CISRDY (1 << 0) /* CIS Ready */
226 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
227 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
228 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
229 #define CC_XMTDATAAVAIL_MODE (1 << 4)
230 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
233 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
234 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
235 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
236 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
239 * Software allocation of To SB Mailbox resources
242 /* tosbmailbox bits corresponding to intstatus bits */
243 #define SMB_NAK (1 << 0) /* Frame NAK */
244 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
245 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
246 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
248 /* tosbmailboxdata */
249 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
252 * Software allocation of To Host Mailbox resources
256 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
257 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
258 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
259 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
261 /* tohostmailboxdata */
262 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
263 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
264 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
265 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
267 #define HMB_DATA_FCDATA_MASK 0xff000000
268 #define HMB_DATA_FCDATA_SHIFT 24
270 #define HMB_DATA_VERSION_MASK 0x00ff0000
271 #define HMB_DATA_VERSION_SHIFT 16
274 * Software-defined protocol header
277 /* Current protocol version */
278 #define SDPCM_PROT_VERSION 4
281 * Shared structure between dongle and the host.
282 * The structure contains pointers to trap or assert information.
284 #define SDPCM_SHARED_VERSION 0x0003
285 #define SDPCM_SHARED_VERSION_MASK 0x00FF
286 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
287 #define SDPCM_SHARED_ASSERT 0x0200
288 #define SDPCM_SHARED_TRAP 0x0400
290 /* Space for header read, limit for data packets */
291 #define MAX_HDR_READ (1 << 6)
292 #define MAX_RX_DATASZ 2048
294 /* Bump up limit on waiting for HT to account for first startup;
295 * if the image is doing a CRC calculation before programming the PMU
296 * for HT availability, it could take a couple hundred ms more, so
297 * max out at a 1 second (1000000us).
299 #undef PMU_MAX_TRANSITION_DLY
300 #define PMU_MAX_TRANSITION_DLY 1000000
302 /* Value for ChipClockCSR during initial setup */
303 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
304 SBSDIO_ALP_AVAIL_REQ)
306 /* Flags for SDH calls */
307 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
309 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
312 #define BRCMF_IDLE_INTERVAL 1
314 #define KSO_WAIT_US 50
315 #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
318 * Conversion of 802.1D priority to precedence level
320 static uint
prio2prec(u32 prio
)
322 return (prio
== PRIO_8021D_NONE
|| prio
== PRIO_8021D_BE
) ?
327 /* Device console log buffer state */
328 struct brcmf_console
{
329 uint count
; /* Poll interval msec counter */
330 uint log_addr
; /* Log struct address (fixed) */
331 struct rte_log_le log_le
; /* Log struct (host copy) */
332 uint bufsize
; /* Size of log buffer */
333 u8
*buf
; /* Log buffer (host copy) */
334 uint last
; /* Last buffer read index */
337 struct brcmf_trap_info
{
351 __le32 r9
; /* sb/v6 */
352 __le32 r10
; /* sl/v7 */
353 __le32 r11
; /* fp/v8 */
361 struct sdpcm_shared
{
365 u32 assert_file_addr
;
367 u32 console_addr
; /* Address of struct rte_console */
373 struct sdpcm_shared_le
{
376 __le32 assert_exp_addr
;
377 __le32 assert_file_addr
;
379 __le32 console_addr
; /* Address of struct rte_console */
380 __le32 msgtrace_addr
;
385 /* dongle SDIO bus specific header info */
386 struct brcmf_sdio_hdrinfo
{
398 * hold counter variables
400 struct brcmf_sdio_count
{
401 uint intrcount
; /* Count of device interrupt callbacks */
402 uint lastintrs
; /* Count as of last watchdog timer */
403 uint pollcnt
; /* Count of active polls */
404 uint regfails
; /* Count of R_REG failures */
405 uint tx_sderrs
; /* Count of tx attempts with sd errors */
406 uint fcqueued
; /* Tx packets that got queued */
407 uint rxrtx
; /* Count of rtx requests (NAK to dongle) */
408 uint rx_toolong
; /* Receive frames too long to receive */
409 uint rxc_errors
; /* SDIO errors when reading control frames */
410 uint rx_hdrfail
; /* SDIO errors on header reads */
411 uint rx_badhdr
; /* Bad received headers (roosync?) */
412 uint rx_badseq
; /* Mismatched rx sequence number */
413 uint fc_rcvd
; /* Number of flow-control events received */
414 uint fc_xoff
; /* Number which turned on flow-control */
415 uint fc_xon
; /* Number which turned off flow-control */
416 uint rxglomfail
; /* Failed deglom attempts */
417 uint rxglomframes
; /* Number of glom frames (superframes) */
418 uint rxglompkts
; /* Number of packets from glom frames */
419 uint f2rxhdrs
; /* Number of header reads */
420 uint f2rxdata
; /* Number of frame data reads */
421 uint f2txdata
; /* Number of f2 frame writes */
422 uint f1regdata
; /* Number of f1 register accesses */
423 uint tickcnt
; /* Number of watchdog been schedule */
424 ulong tx_ctlerrs
; /* Err of sending ctrl frames */
425 ulong tx_ctlpkts
; /* Ctrl frames sent to dongle */
426 ulong rx_ctlerrs
; /* Err of processing rx ctrl frames */
427 ulong rx_ctlpkts
; /* Ctrl frames processed from dongle */
428 ulong rx_readahead_cnt
; /* packets where header read-ahead was used */
431 /* misc chip info needed by some of the routines */
432 /* Private data for SDIO bus interaction */
434 struct brcmf_sdio_dev
*sdiodev
; /* sdio device handler */
435 struct brcmf_chip
*ci
; /* Chip info struct */
437 u32 hostintmask
; /* Copy of Host Interrupt Mask */
438 atomic_t intstatus
; /* Intstatus bits (events) pending */
439 atomic_t fcstate
; /* State of dongle flow-control */
441 uint blocksize
; /* Block size of SDIO transfers */
442 uint roundup
; /* Max roundup limit */
444 struct pktq txq
; /* Queue length used for flow-control */
445 u8 flowcontrol
; /* per prio flow control bitmask */
446 u8 tx_seq
; /* Transmit sequence number (next) */
447 u8 tx_max
; /* Maximum transmit sequence allowed */
449 u8
*hdrbuf
; /* buffer for handling rx frame */
450 u8
*rxhdr
; /* Header of current rx frame (in hdrbuf) */
451 u8 rx_seq
; /* Receive sequence number (expected) */
452 struct brcmf_sdio_hdrinfo cur_read
;
453 /* info of current read frame */
454 bool rxskip
; /* Skip receive (awaiting NAK ACK) */
455 bool rxpending
; /* Data frame pending in dongle */
457 uint rxbound
; /* Rx frames to read before resched */
458 uint txbound
; /* Tx frames to send before resched */
461 struct sk_buff
*glomd
; /* Packet containing glomming descriptor */
462 struct sk_buff_head glom
; /* Packet list for glommed superframe */
464 u8
*rxbuf
; /* Buffer for receiving control packets */
465 uint rxblen
; /* Allocated length of rxbuf */
466 u8
*rxctl
; /* Aligned pointer into rxbuf */
467 u8
*rxctl_orig
; /* pointer for freeing rxctl */
468 uint rxlen
; /* Length of valid data in buffer */
469 spinlock_t rxctl_lock
; /* protection lock for ctrl frame resources */
471 u8 sdpcm_ver
; /* Bus protocol reported by dongle */
473 bool intr
; /* Use interrupts */
474 bool poll
; /* Use polling */
475 atomic_t ipend
; /* Device interrupt is pending */
476 uint spurious
; /* Count of spurious interrupts */
477 uint pollrate
; /* Ticks between device polls */
478 uint polltick
; /* Tick counter */
481 uint console_interval
;
482 struct brcmf_console console
; /* Console output polling support */
483 uint console_addr
; /* Console address from shared struct */
486 uint clkstate
; /* State of sd and backplane clock(s) */
487 s32 idletime
; /* Control for activity timeout */
488 s32 idlecount
; /* Activity timeout counter */
489 s32 idleclock
; /* How to set bus driver when idle */
490 bool rxflow_mode
; /* Rx flow control mode */
491 bool rxflow
; /* Is rx flow control on */
492 bool alp_only
; /* Don't use HT clock (ALP only) */
496 bool ctrl_frame_stat
;
499 spinlock_t txq_lock
; /* protect bus->txq */
500 wait_queue_head_t ctrl_wait
;
501 wait_queue_head_t dcmd_resp_wait
;
503 struct timer_list timer
;
504 struct completion watchdog_wait
;
505 struct task_struct
*watchdog_tsk
;
508 struct workqueue_struct
*brcmf_wq
;
509 struct work_struct datawork
;
513 bool txoff
; /* Transmit flow-controlled */
514 struct brcmf_sdio_count sdcnt
;
515 bool sr_enabled
; /* SaveRestore enabled */
518 u8 tx_hdrlen
; /* sdio bus header length for tx packet */
519 bool txglom
; /* host tx glomming enable flag */
520 u16 head_align
; /* buffer pointer alignment */
521 u16 sgentry_align
; /* scatter-gather buffer alignment */
527 #define CLK_PENDING 2
531 static int qcount
[NUMPRIO
];
534 #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */
536 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
538 /* Limit on rounding up frames */
539 static const uint max_roundup
= 512;
543 enum brcmf_sdio_frmtype
{
544 BRCMF_SDIO_FT_NORMAL
,
549 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
551 /* SDIO Pad drive strength to select value mappings */
552 struct sdiod_drive_str
{
553 u8 strength
; /* Pad Drive Strength in mA */
554 u8 sel
; /* Chip-specific select value */
557 /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */
558 static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8
[] = {
569 /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
570 static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8
[] = {
580 /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
581 static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8
[] = {
587 /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
588 static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3
[] = {
595 BRCMF_FW_NVRAM_DEF(43143, "brcmfmac43143-sdio.bin", "brcmfmac43143-sdio.txt");
596 BRCMF_FW_NVRAM_DEF(43241B0
, "brcmfmac43241b0-sdio.bin",
597 "brcmfmac43241b0-sdio.txt");
598 BRCMF_FW_NVRAM_DEF(43241B4
, "brcmfmac43241b4-sdio.bin",
599 "brcmfmac43241b4-sdio.txt");
600 BRCMF_FW_NVRAM_DEF(43241B5
, "brcmfmac43241b5-sdio.bin",
601 "brcmfmac43241b5-sdio.txt");
602 BRCMF_FW_NVRAM_DEF(4329, "brcmfmac4329-sdio.bin", "brcmfmac4329-sdio.txt");
603 BRCMF_FW_NVRAM_DEF(4330, "brcmfmac4330-sdio.bin", "brcmfmac4330-sdio.txt");
604 BRCMF_FW_NVRAM_DEF(4334, "brcmfmac4334-sdio.bin", "brcmfmac4334-sdio.txt");
605 BRCMF_FW_NVRAM_DEF(43340, "brcmfmac43340-sdio.bin", "brcmfmac43340-sdio.txt");
606 BRCMF_FW_NVRAM_DEF(4335, "brcmfmac4335-sdio.bin", "brcmfmac4335-sdio.txt");
607 BRCMF_FW_NVRAM_DEF(43362, "brcmfmac43362-sdio.bin", "brcmfmac43362-sdio.txt");
608 BRCMF_FW_NVRAM_DEF(4339, "brcmfmac4339-sdio.bin", "brcmfmac4339-sdio.txt");
609 BRCMF_FW_NVRAM_DEF(43430, "brcmfmac43430-sdio.bin", "brcmfmac43430-sdio.txt");
610 BRCMF_FW_NVRAM_DEF(43455, "brcmfmac43455-sdio.bin", "brcmfmac43455-sdio.txt");
611 BRCMF_FW_NVRAM_DEF(4354, "brcmfmac4354-sdio.bin", "brcmfmac4354-sdio.txt");
612 BRCMF_FW_NVRAM_DEF(4356, "brcmfmac4356-sdio.bin", "brcmfmac4356-sdio.txt");
614 static struct brcmf_firmware_mapping brcmf_sdio_fwnames
[] = {
615 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43143_CHIP_ID
, 0xFFFFFFFF, 43143),
616 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID
, 0x0000001F, 43241B0
),
617 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID
, 0x00000020, 43241B4
),
618 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID
, 0xFFFFFFC0, 43241B5
),
619 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4329_CHIP_ID
, 0xFFFFFFFF, 4329),
620 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4330_CHIP_ID
, 0xFFFFFFFF, 4330),
621 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4334_CHIP_ID
, 0xFFFFFFFF, 4334),
622 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43340_CHIP_ID
, 0xFFFFFFFF, 43340),
623 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4335_CHIP_ID
, 0xFFFFFFFF, 4335),
624 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43362_CHIP_ID
, 0xFFFFFFFE, 43362),
625 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4339_CHIP_ID
, 0xFFFFFFFF, 4339),
626 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43430_CHIP_ID
, 0xFFFFFFFF, 43430),
627 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4345_CHIP_ID
, 0xFFFFFFC0, 43455),
628 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4354_CHIP_ID
, 0xFFFFFFFF, 4354),
629 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4356_CHIP_ID
, 0xFFFFFFFF, 4356)
632 static void pkt_align(struct sk_buff
*p
, int len
, int align
)
635 datalign
= (unsigned long)(p
->data
);
636 datalign
= roundup(datalign
, (align
)) - datalign
;
638 skb_pull(p
, datalign
);
642 /* To check if there's window offered */
643 static bool data_ok(struct brcmf_sdio
*bus
)
645 return (u8
)(bus
->tx_max
- bus
->tx_seq
) != 0 &&
646 ((u8
)(bus
->tx_max
- bus
->tx_seq
) & 0x80) == 0;
650 * Reads a register in the SDIO hardware block. This block occupies a series of
651 * adresses on the 32 bit backplane bus.
653 static int r_sdreg32(struct brcmf_sdio
*bus
, u32
*regvar
, u32 offset
)
655 struct brcmf_core
*core
;
658 core
= brcmf_chip_get_core(bus
->ci
, BCMA_CORE_SDIO_DEV
);
659 *regvar
= brcmf_sdiod_regrl(bus
->sdiodev
, core
->base
+ offset
, &ret
);
664 static int w_sdreg32(struct brcmf_sdio
*bus
, u32 regval
, u32 reg_offset
)
666 struct brcmf_core
*core
;
669 core
= brcmf_chip_get_core(bus
->ci
, BCMA_CORE_SDIO_DEV
);
670 brcmf_sdiod_regwl(bus
->sdiodev
, core
->base
+ reg_offset
, regval
, &ret
);
676 brcmf_sdio_kso_control(struct brcmf_sdio
*bus
, bool on
)
678 u8 wr_val
= 0, rd_val
, cmp_val
, bmask
;
682 brcmf_dbg(TRACE
, "Enter: on=%d\n", on
);
684 wr_val
= (on
<< SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT
);
685 /* 1st KSO write goes to AOS wake up core if device is asleep */
686 brcmf_sdiod_regwb(bus
->sdiodev
, SBSDIO_FUNC1_SLEEPCSR
,
690 /* device WAKEUP through KSO:
691 * write bit 0 & read back until
692 * both bits 0 (kso bit) & 1 (dev on status) are set
694 cmp_val
= SBSDIO_FUNC1_SLEEPCSR_KSO_MASK
|
695 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK
;
697 usleep_range(2000, 3000);
699 /* Put device to sleep, turn off KSO */
701 /* only check for bit0, bit1(dev on status) may not
702 * get cleared right away
704 bmask
= SBSDIO_FUNC1_SLEEPCSR_KSO_MASK
;
708 /* reliable KSO bit set/clr:
709 * the sdiod sleep write access is synced to PMU 32khz clk
710 * just one write attempt may fail,
711 * read it back until it matches written value
713 rd_val
= brcmf_sdiod_regrb(bus
->sdiodev
, SBSDIO_FUNC1_SLEEPCSR
,
715 if (((rd_val
& bmask
) == cmp_val
) && !err
)
719 brcmf_sdiod_regwb(bus
->sdiodev
, SBSDIO_FUNC1_SLEEPCSR
,
721 } while (try_cnt
++ < MAX_KSO_ATTEMPTS
);
724 brcmf_dbg(SDIO
, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt
,
727 if (try_cnt
> MAX_KSO_ATTEMPTS
)
728 brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val
, err
);
733 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
735 /* Turn backplane clock on or off */
736 static int brcmf_sdio_htclk(struct brcmf_sdio
*bus
, bool on
, bool pendok
)
739 u8 clkctl
, clkreq
, devctl
;
740 unsigned long timeout
;
742 brcmf_dbg(SDIO
, "Enter\n");
746 if (bus
->sr_enabled
) {
747 bus
->clkstate
= (on
? CLK_AVAIL
: CLK_SDONLY
);
752 /* Request HT Avail */
754 bus
->alp_only
? SBSDIO_ALP_AVAIL_REQ
: SBSDIO_HT_AVAIL_REQ
;
756 brcmf_sdiod_regwb(bus
->sdiodev
, SBSDIO_FUNC1_CHIPCLKCSR
,
759 brcmf_err("HT Avail request error: %d\n", err
);
763 /* Check current status */
764 clkctl
= brcmf_sdiod_regrb(bus
->sdiodev
,
765 SBSDIO_FUNC1_CHIPCLKCSR
, &err
);
767 brcmf_err("HT Avail read error: %d\n", err
);
771 /* Go to pending and await interrupt if appropriate */
772 if (!SBSDIO_CLKAV(clkctl
, bus
->alp_only
) && pendok
) {
773 /* Allow only clock-available interrupt */
774 devctl
= brcmf_sdiod_regrb(bus
->sdiodev
,
775 SBSDIO_DEVICE_CTL
, &err
);
777 brcmf_err("Devctl error setting CA: %d\n",
782 devctl
|= SBSDIO_DEVCTL_CA_INT_ONLY
;
783 brcmf_sdiod_regwb(bus
->sdiodev
, SBSDIO_DEVICE_CTL
,
785 brcmf_dbg(SDIO
, "CLKCTL: set PENDING\n");
786 bus
->clkstate
= CLK_PENDING
;
789 } else if (bus
->clkstate
== CLK_PENDING
) {
790 /* Cancel CA-only interrupt filter */
791 devctl
= brcmf_sdiod_regrb(bus
->sdiodev
,
792 SBSDIO_DEVICE_CTL
, &err
);
793 devctl
&= ~SBSDIO_DEVCTL_CA_INT_ONLY
;
794 brcmf_sdiod_regwb(bus
->sdiodev
, SBSDIO_DEVICE_CTL
,
798 /* Otherwise, wait here (polling) for HT Avail */
800 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY
/1000);
801 while (!SBSDIO_CLKAV(clkctl
, bus
->alp_only
)) {
802 clkctl
= brcmf_sdiod_regrb(bus
->sdiodev
,
803 SBSDIO_FUNC1_CHIPCLKCSR
,
805 if (time_after(jiffies
, timeout
))
808 usleep_range(5000, 10000);
811 brcmf_err("HT Avail request error: %d\n", err
);
814 if (!SBSDIO_CLKAV(clkctl
, bus
->alp_only
)) {
815 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",
816 PMU_MAX_TRANSITION_DLY
, clkctl
);
820 /* Mark clock available */
821 bus
->clkstate
= CLK_AVAIL
;
822 brcmf_dbg(SDIO
, "CLKCTL: turned ON\n");
825 if (!bus
->alp_only
) {
826 if (SBSDIO_ALPONLY(clkctl
))
827 brcmf_err("HT Clock should be on\n");
829 #endif /* defined (DEBUG) */
834 if (bus
->clkstate
== CLK_PENDING
) {
835 /* Cancel CA-only interrupt filter */
836 devctl
= brcmf_sdiod_regrb(bus
->sdiodev
,
837 SBSDIO_DEVICE_CTL
, &err
);
838 devctl
&= ~SBSDIO_DEVCTL_CA_INT_ONLY
;
839 brcmf_sdiod_regwb(bus
->sdiodev
, SBSDIO_DEVICE_CTL
,
843 bus
->clkstate
= CLK_SDONLY
;
844 brcmf_sdiod_regwb(bus
->sdiodev
, SBSDIO_FUNC1_CHIPCLKCSR
,
846 brcmf_dbg(SDIO
, "CLKCTL: turned OFF\n");
848 brcmf_err("Failed access turning clock off: %d\n",
856 /* Change idle/active SD state */
857 static int brcmf_sdio_sdclk(struct brcmf_sdio
*bus
, bool on
)
859 brcmf_dbg(SDIO
, "Enter\n");
862 bus
->clkstate
= CLK_SDONLY
;
864 bus
->clkstate
= CLK_NONE
;
869 /* Transition SD and backplane clock readiness */
870 static int brcmf_sdio_clkctl(struct brcmf_sdio
*bus
, uint target
, bool pendok
)
873 uint oldstate
= bus
->clkstate
;
876 brcmf_dbg(SDIO
, "Enter\n");
878 /* Early exit if we're already there */
879 if (bus
->clkstate
== target
)
884 /* Make sure SD clock is available */
885 if (bus
->clkstate
== CLK_NONE
)
886 brcmf_sdio_sdclk(bus
, true);
887 /* Now request HT Avail on the backplane */
888 brcmf_sdio_htclk(bus
, true, pendok
);
892 /* Remove HT request, or bring up SD clock */
893 if (bus
->clkstate
== CLK_NONE
)
894 brcmf_sdio_sdclk(bus
, true);
895 else if (bus
->clkstate
== CLK_AVAIL
)
896 brcmf_sdio_htclk(bus
, false, false);
898 brcmf_err("request for %d -> %d\n",
899 bus
->clkstate
, target
);
903 /* Make sure to remove HT request */
904 if (bus
->clkstate
== CLK_AVAIL
)
905 brcmf_sdio_htclk(bus
, false, false);
906 /* Now remove the SD clock */
907 brcmf_sdio_sdclk(bus
, false);
911 brcmf_dbg(SDIO
, "%d -> %d\n", oldstate
, bus
->clkstate
);
918 brcmf_sdio_bus_sleep(struct brcmf_sdio
*bus
, bool sleep
, bool pendok
)
923 brcmf_dbg(SDIO
, "Enter: request %s currently %s\n",
924 (sleep
? "SLEEP" : "WAKE"),
925 (bus
->sleeping
? "SLEEP" : "WAKE"));
927 /* If SR is enabled control bus state with KSO */
928 if (bus
->sr_enabled
) {
929 /* Done if we're already in the requested state */
930 if (sleep
== bus
->sleeping
)
935 clkcsr
= brcmf_sdiod_regrb(bus
->sdiodev
,
936 SBSDIO_FUNC1_CHIPCLKCSR
,
938 if ((clkcsr
& SBSDIO_CSR_MASK
) == 0) {
939 brcmf_dbg(SDIO
, "no clock, set ALP\n");
940 brcmf_sdiod_regwb(bus
->sdiodev
,
941 SBSDIO_FUNC1_CHIPCLKCSR
,
942 SBSDIO_ALP_AVAIL_REQ
, &err
);
944 err
= brcmf_sdio_kso_control(bus
, false);
946 err
= brcmf_sdio_kso_control(bus
, true);
949 brcmf_err("error while changing bus sleep state %d\n",
958 if (!bus
->sr_enabled
)
959 brcmf_sdio_clkctl(bus
, CLK_NONE
, pendok
);
961 brcmf_sdio_clkctl(bus
, CLK_AVAIL
, pendok
);
962 brcmf_sdio_wd_timer(bus
, true);
964 bus
->sleeping
= sleep
;
965 brcmf_dbg(SDIO
, "new state %s\n",
966 (sleep
? "SLEEP" : "WAKE"));
968 brcmf_dbg(SDIO
, "Exit: err=%d\n", err
);
974 static inline bool brcmf_sdio_valid_shared_address(u32 addr
)
976 return !(addr
== 0 || ((~addr
>> 16) & 0xffff) == (addr
& 0xffff));
979 static int brcmf_sdio_readshared(struct brcmf_sdio
*bus
,
980 struct sdpcm_shared
*sh
)
985 struct sdpcm_shared_le sh_le
;
988 sdio_claim_host(bus
->sdiodev
->func
[1]);
989 brcmf_sdio_bus_sleep(bus
, false, false);
992 * Read last word in socram to determine
993 * address of sdpcm_shared structure
995 shaddr
= bus
->ci
->rambase
+ bus
->ci
->ramsize
- 4;
996 if (!bus
->ci
->rambase
&& brcmf_chip_sr_capable(bus
->ci
))
997 shaddr
-= bus
->ci
->srsize
;
998 rv
= brcmf_sdiod_ramrw(bus
->sdiodev
, false, shaddr
,
1004 * Check if addr is valid.
1005 * NVRAM length at the end of memory should have been overwritten.
1007 addr
= le32_to_cpu(addr_le
);
1008 if (!brcmf_sdio_valid_shared_address(addr
)) {
1009 brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr
);
1014 brcmf_dbg(INFO
, "sdpcm_shared address 0x%08X\n", addr
);
1016 /* Read hndrte_shared structure */
1017 rv
= brcmf_sdiod_ramrw(bus
->sdiodev
, false, addr
, (u8
*)&sh_le
,
1018 sizeof(struct sdpcm_shared_le
));
1022 sdio_release_host(bus
->sdiodev
->func
[1]);
1025 sh
->flags
= le32_to_cpu(sh_le
.flags
);
1026 sh
->trap_addr
= le32_to_cpu(sh_le
.trap_addr
);
1027 sh
->assert_exp_addr
= le32_to_cpu(sh_le
.assert_exp_addr
);
1028 sh
->assert_file_addr
= le32_to_cpu(sh_le
.assert_file_addr
);
1029 sh
->assert_line
= le32_to_cpu(sh_le
.assert_line
);
1030 sh
->console_addr
= le32_to_cpu(sh_le
.console_addr
);
1031 sh
->msgtrace_addr
= le32_to_cpu(sh_le
.msgtrace_addr
);
1033 if ((sh
->flags
& SDPCM_SHARED_VERSION_MASK
) > SDPCM_SHARED_VERSION
) {
1034 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n",
1035 SDPCM_SHARED_VERSION
,
1036 sh
->flags
& SDPCM_SHARED_VERSION_MASK
);
1042 brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n",
1044 sdio_release_host(bus
->sdiodev
->func
[1]);
1048 static void brcmf_sdio_get_console_addr(struct brcmf_sdio
*bus
)
1050 struct sdpcm_shared sh
;
1052 if (brcmf_sdio_readshared(bus
, &sh
) == 0)
1053 bus
->console_addr
= sh
.console_addr
;
1056 static void brcmf_sdio_get_console_addr(struct brcmf_sdio
*bus
)
1061 static u32
brcmf_sdio_hostmail(struct brcmf_sdio
*bus
)
1068 brcmf_dbg(SDIO
, "Enter\n");
1070 /* Read mailbox data and ack that we did so */
1071 ret
= r_sdreg32(bus
, &hmb_data
,
1072 offsetof(struct sdpcmd_regs
, tohostmailboxdata
));
1075 w_sdreg32(bus
, SMB_INT_ACK
,
1076 offsetof(struct sdpcmd_regs
, tosbmailbox
));
1077 bus
->sdcnt
.f1regdata
+= 2;
1079 /* Dongle recomposed rx frames, accept them again */
1080 if (hmb_data
& HMB_DATA_NAKHANDLED
) {
1081 brcmf_dbg(SDIO
, "Dongle reports NAK handled, expect rtx of %d\n",
1084 brcmf_err("unexpected NAKHANDLED!\n");
1086 bus
->rxskip
= false;
1087 intstatus
|= I_HMB_FRAME_IND
;
1091 * DEVREADY does not occur with gSPI.
1093 if (hmb_data
& (HMB_DATA_DEVREADY
| HMB_DATA_FWREADY
)) {
1095 (hmb_data
& HMB_DATA_VERSION_MASK
) >>
1096 HMB_DATA_VERSION_SHIFT
;
1097 if (bus
->sdpcm_ver
!= SDPCM_PROT_VERSION
)
1098 brcmf_err("Version mismatch, dongle reports %d, "
1100 bus
->sdpcm_ver
, SDPCM_PROT_VERSION
);
1102 brcmf_dbg(SDIO
, "Dongle ready, protocol version %d\n",
1106 * Retrieve console state address now that firmware should have
1109 brcmf_sdio_get_console_addr(bus
);
1113 * Flow Control has been moved into the RX headers and this out of band
1114 * method isn't used any more.
1115 * remaining backward compatible with older dongles.
1117 if (hmb_data
& HMB_DATA_FC
) {
1118 fcbits
= (hmb_data
& HMB_DATA_FCDATA_MASK
) >>
1119 HMB_DATA_FCDATA_SHIFT
;
1121 if (fcbits
& ~bus
->flowcontrol
)
1122 bus
->sdcnt
.fc_xoff
++;
1124 if (bus
->flowcontrol
& ~fcbits
)
1125 bus
->sdcnt
.fc_xon
++;
1127 bus
->sdcnt
.fc_rcvd
++;
1128 bus
->flowcontrol
= fcbits
;
1131 /* Shouldn't be any others */
1132 if (hmb_data
& ~(HMB_DATA_DEVREADY
|
1133 HMB_DATA_NAKHANDLED
|
1136 HMB_DATA_FCDATA_MASK
| HMB_DATA_VERSION_MASK
))
1137 brcmf_err("Unknown mailbox data content: 0x%02x\n",
1143 static void brcmf_sdio_rxfail(struct brcmf_sdio
*bus
, bool abort
, bool rtx
)
1150 brcmf_err("%sterminate frame%s\n",
1151 abort
? "abort command, " : "",
1152 rtx
? ", send NAK" : "");
1155 brcmf_sdiod_abort(bus
->sdiodev
, SDIO_FUNC_2
);
1157 brcmf_sdiod_regwb(bus
->sdiodev
, SBSDIO_FUNC1_FRAMECTRL
,
1159 bus
->sdcnt
.f1regdata
++;
1161 /* Wait until the packet has been flushed (device/FIFO stable) */
1162 for (lastrbc
= retries
= 0xffff; retries
> 0; retries
--) {
1163 hi
= brcmf_sdiod_regrb(bus
->sdiodev
,
1164 SBSDIO_FUNC1_RFRAMEBCHI
, &err
);
1165 lo
= brcmf_sdiod_regrb(bus
->sdiodev
,
1166 SBSDIO_FUNC1_RFRAMEBCLO
, &err
);
1167 bus
->sdcnt
.f1regdata
+= 2;
1169 if ((hi
== 0) && (lo
== 0))
1172 if ((hi
> (lastrbc
>> 8)) && (lo
> (lastrbc
& 0x00ff))) {
1173 brcmf_err("count growing: last 0x%04x now 0x%04x\n",
1174 lastrbc
, (hi
<< 8) + lo
);
1176 lastrbc
= (hi
<< 8) + lo
;
1180 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc
);
1182 brcmf_dbg(SDIO
, "flush took %d iterations\n", 0xffff - retries
);
1186 err
= w_sdreg32(bus
, SMB_NAK
,
1187 offsetof(struct sdpcmd_regs
, tosbmailbox
));
1189 bus
->sdcnt
.f1regdata
++;
1194 /* Clear partial in any case */
1195 bus
->cur_read
.len
= 0;
1198 static void brcmf_sdio_txfail(struct brcmf_sdio
*bus
)
1200 struct brcmf_sdio_dev
*sdiodev
= bus
->sdiodev
;
1203 /* On failure, abort the command and terminate the frame */
1204 brcmf_err("sdio error, abort command and terminate frame\n");
1205 bus
->sdcnt
.tx_sderrs
++;
1207 brcmf_sdiod_abort(sdiodev
, SDIO_FUNC_2
);
1208 brcmf_sdiod_regwb(sdiodev
, SBSDIO_FUNC1_FRAMECTRL
, SFC_WF_TERM
, NULL
);
1209 bus
->sdcnt
.f1regdata
++;
1211 for (i
= 0; i
< 3; i
++) {
1212 hi
= brcmf_sdiod_regrb(sdiodev
, SBSDIO_FUNC1_WFRAMEBCHI
, NULL
);
1213 lo
= brcmf_sdiod_regrb(sdiodev
, SBSDIO_FUNC1_WFRAMEBCLO
, NULL
);
1214 bus
->sdcnt
.f1regdata
+= 2;
1215 if ((hi
== 0) && (lo
== 0))
1220 /* return total length of buffer chain */
1221 static uint
brcmf_sdio_glom_len(struct brcmf_sdio
*bus
)
1227 skb_queue_walk(&bus
->glom
, p
)
1232 static void brcmf_sdio_free_glom(struct brcmf_sdio
*bus
)
1234 struct sk_buff
*cur
, *next
;
1236 skb_queue_walk_safe(&bus
->glom
, cur
, next
) {
1237 skb_unlink(cur
, &bus
->glom
);
1238 brcmu_pkt_buf_free_skb(cur
);
1243 * brcmfmac sdio bus specific header
1244 * This is the lowest layer header wrapped on the packets transmitted between
1245 * host and WiFi dongle which contains information needed for SDIO core and
1248 * It consists of 3 parts: hardware header, hardware extension header and
1250 * hardware header (frame tag) - 4 bytes
1251 * Byte 0~1: Frame length
1252 * Byte 2~3: Checksum, bit-wise inverse of frame length
1253 * hardware extension header - 8 bytes
1254 * Tx glom mode only, N/A for Rx or normal Tx
1255 * Byte 0~1: Packet length excluding hw frame tag
1257 * Byte 3: Frame flags, bit 0: last frame indication
1258 * Byte 4~5: Reserved
1259 * Byte 6~7: Tail padding length
1260 * software header - 8 bytes
1261 * Byte 0: Rx/Tx sequence number
1262 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
1263 * Byte 2: Length of next data frame, reserved for Tx
1264 * Byte 3: Data offset
1265 * Byte 4: Flow control bits, reserved for Tx
1266 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet
1267 * Byte 6~7: Reserved
1269 #define SDPCM_HWHDR_LEN 4
1270 #define SDPCM_HWEXT_LEN 8
1271 #define SDPCM_SWHDR_LEN 8
1272 #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN)
1273 /* software header */
1274 #define SDPCM_SEQ_MASK 0x000000ff
1275 #define SDPCM_SEQ_WRAP 256
1276 #define SDPCM_CHANNEL_MASK 0x00000f00
1277 #define SDPCM_CHANNEL_SHIFT 8
1278 #define SDPCM_CONTROL_CHANNEL 0 /* Control */
1279 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */
1280 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */
1281 #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */
1282 #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */
1283 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
1284 #define SDPCM_NEXTLEN_MASK 0x00ff0000
1285 #define SDPCM_NEXTLEN_SHIFT 16
1286 #define SDPCM_DOFFSET_MASK 0xff000000
1287 #define SDPCM_DOFFSET_SHIFT 24
1288 #define SDPCM_FCMASK_MASK 0x000000ff
1289 #define SDPCM_WINDOW_MASK 0x0000ff00
1290 #define SDPCM_WINDOW_SHIFT 8
1292 static inline u8
brcmf_sdio_getdatoffset(u8
*swheader
)
1295 hdrvalue
= *(u32
*)swheader
;
1296 return (u8
)((hdrvalue
& SDPCM_DOFFSET_MASK
) >> SDPCM_DOFFSET_SHIFT
);
1299 static inline bool brcmf_sdio_fromevntchan(u8
*swheader
)
1304 hdrvalue
= *(u32
*)swheader
;
1305 ret
= (u8
)((hdrvalue
& SDPCM_CHANNEL_MASK
) >> SDPCM_CHANNEL_SHIFT
);
1307 return (ret
== SDPCM_EVENT_CHANNEL
);
1310 static int brcmf_sdio_hdparse(struct brcmf_sdio
*bus
, u8
*header
,
1311 struct brcmf_sdio_hdrinfo
*rd
,
1312 enum brcmf_sdio_frmtype type
)
1315 u8 rx_seq
, fc
, tx_seq_max
;
1318 trace_brcmf_sdpcm_hdr(SDPCM_RX
, header
);
1321 len
= get_unaligned_le16(header
);
1322 checksum
= get_unaligned_le16(header
+ sizeof(u16
));
1323 /* All zero means no more to read */
1324 if (!(len
| checksum
)) {
1325 bus
->rxpending
= false;
1328 if ((u16
)(~(len
^ checksum
))) {
1329 brcmf_err("HW header checksum error\n");
1330 bus
->sdcnt
.rx_badhdr
++;
1331 brcmf_sdio_rxfail(bus
, false, false);
1334 if (len
< SDPCM_HDRLEN
) {
1335 brcmf_err("HW header length error\n");
1338 if (type
== BRCMF_SDIO_FT_SUPER
&&
1339 (roundup(len
, bus
->blocksize
) != rd
->len
)) {
1340 brcmf_err("HW superframe header length error\n");
1343 if (type
== BRCMF_SDIO_FT_SUB
&& len
> rd
->len
) {
1344 brcmf_err("HW subframe header length error\n");
1349 /* software header */
1350 header
+= SDPCM_HWHDR_LEN
;
1351 swheader
= le32_to_cpu(*(__le32
*)header
);
1352 if (type
== BRCMF_SDIO_FT_SUPER
&& SDPCM_GLOMDESC(header
)) {
1353 brcmf_err("Glom descriptor found in superframe head\n");
1357 rx_seq
= (u8
)(swheader
& SDPCM_SEQ_MASK
);
1358 rd
->channel
= (swheader
& SDPCM_CHANNEL_MASK
) >> SDPCM_CHANNEL_SHIFT
;
1359 if (len
> MAX_RX_DATASZ
&& rd
->channel
!= SDPCM_CONTROL_CHANNEL
&&
1360 type
!= BRCMF_SDIO_FT_SUPER
) {
1361 brcmf_err("HW header length too long\n");
1362 bus
->sdcnt
.rx_toolong
++;
1363 brcmf_sdio_rxfail(bus
, false, false);
1367 if (type
== BRCMF_SDIO_FT_SUPER
&& rd
->channel
!= SDPCM_GLOM_CHANNEL
) {
1368 brcmf_err("Wrong channel for superframe\n");
1372 if (type
== BRCMF_SDIO_FT_SUB
&& rd
->channel
!= SDPCM_DATA_CHANNEL
&&
1373 rd
->channel
!= SDPCM_EVENT_CHANNEL
) {
1374 brcmf_err("Wrong channel for subframe\n");
1378 rd
->dat_offset
= brcmf_sdio_getdatoffset(header
);
1379 if (rd
->dat_offset
< SDPCM_HDRLEN
|| rd
->dat_offset
> rd
->len
) {
1380 brcmf_err("seq %d: bad data offset\n", rx_seq
);
1381 bus
->sdcnt
.rx_badhdr
++;
1382 brcmf_sdio_rxfail(bus
, false, false);
1386 if (rd
->seq_num
!= rx_seq
) {
1387 brcmf_dbg(SDIO
, "seq %d, expected %d\n", rx_seq
, rd
->seq_num
);
1388 bus
->sdcnt
.rx_badseq
++;
1389 rd
->seq_num
= rx_seq
;
1391 /* no need to check the reset for subframe */
1392 if (type
== BRCMF_SDIO_FT_SUB
)
1394 rd
->len_nxtfrm
= (swheader
& SDPCM_NEXTLEN_MASK
) >> SDPCM_NEXTLEN_SHIFT
;
1395 if (rd
->len_nxtfrm
<< 4 > MAX_RX_DATASZ
) {
1396 /* only warm for NON glom packet */
1397 if (rd
->channel
!= SDPCM_GLOM_CHANNEL
)
1398 brcmf_err("seq %d: next length error\n", rx_seq
);
1401 swheader
= le32_to_cpu(*(__le32
*)(header
+ 4));
1402 fc
= swheader
& SDPCM_FCMASK_MASK
;
1403 if (bus
->flowcontrol
!= fc
) {
1404 if (~bus
->flowcontrol
& fc
)
1405 bus
->sdcnt
.fc_xoff
++;
1406 if (bus
->flowcontrol
& ~fc
)
1407 bus
->sdcnt
.fc_xon
++;
1408 bus
->sdcnt
.fc_rcvd
++;
1409 bus
->flowcontrol
= fc
;
1411 tx_seq_max
= (swheader
& SDPCM_WINDOW_MASK
) >> SDPCM_WINDOW_SHIFT
;
1412 if ((u8
)(tx_seq_max
- bus
->tx_seq
) > 0x40) {
1413 brcmf_err("seq %d: max tx seq number error\n", rx_seq
);
1414 tx_seq_max
= bus
->tx_seq
+ 2;
1416 bus
->tx_max
= tx_seq_max
;
1421 static inline void brcmf_sdio_update_hwhdr(u8
*header
, u16 frm_length
)
1423 *(__le16
*)header
= cpu_to_le16(frm_length
);
1424 *(((__le16
*)header
) + 1) = cpu_to_le16(~frm_length
);
1427 static void brcmf_sdio_hdpack(struct brcmf_sdio
*bus
, u8
*header
,
1428 struct brcmf_sdio_hdrinfo
*hd_info
)
1433 brcmf_sdio_update_hwhdr(header
, hd_info
->len
);
1434 hdr_offset
= SDPCM_HWHDR_LEN
;
1437 hdrval
= (hd_info
->len
- hdr_offset
) | (hd_info
->lastfrm
<< 24);
1438 *((__le32
*)(header
+ hdr_offset
)) = cpu_to_le32(hdrval
);
1439 hdrval
= (u16
)hd_info
->tail_pad
<< 16;
1440 *(((__le32
*)(header
+ hdr_offset
)) + 1) = cpu_to_le32(hdrval
);
1441 hdr_offset
+= SDPCM_HWEXT_LEN
;
1444 hdrval
= hd_info
->seq_num
;
1445 hdrval
|= (hd_info
->channel
<< SDPCM_CHANNEL_SHIFT
) &
1447 hdrval
|= (hd_info
->dat_offset
<< SDPCM_DOFFSET_SHIFT
) &
1449 *((__le32
*)(header
+ hdr_offset
)) = cpu_to_le32(hdrval
);
1450 *(((__le32
*)(header
+ hdr_offset
)) + 1) = 0;
1451 trace_brcmf_sdpcm_hdr(SDPCM_TX
+ !!(bus
->txglom
), header
);
1454 static u8
brcmf_sdio_rxglom(struct brcmf_sdio
*bus
, u8 rxseq
)
1459 struct sk_buff
*pfirst
, *pnext
;
1464 struct brcmf_sdio_hdrinfo rd_new
;
1466 /* If packets, issue read(s) and send up packet chain */
1467 /* Return sequence numbers consumed? */
1469 brcmf_dbg(SDIO
, "start: glomd %p glom %p\n",
1470 bus
->glomd
, skb_peek(&bus
->glom
));
1472 /* If there's a descriptor, generate the packet chain */
1474 pfirst
= pnext
= NULL
;
1475 dlen
= (u16
) (bus
->glomd
->len
);
1476 dptr
= bus
->glomd
->data
;
1477 if (!dlen
|| (dlen
& 1)) {
1478 brcmf_err("bad glomd len(%d), ignore descriptor\n",
1483 for (totlen
= num
= 0; dlen
; num
++) {
1484 /* Get (and move past) next length */
1485 sublen
= get_unaligned_le16(dptr
);
1486 dlen
-= sizeof(u16
);
1487 dptr
+= sizeof(u16
);
1488 if ((sublen
< SDPCM_HDRLEN
) ||
1489 ((num
== 0) && (sublen
< (2 * SDPCM_HDRLEN
)))) {
1490 brcmf_err("descriptor len %d bad: %d\n",
1495 if (sublen
% bus
->sgentry_align
) {
1496 brcmf_err("sublen %d not multiple of %d\n",
1497 sublen
, bus
->sgentry_align
);
1501 /* For last frame, adjust read len so total
1502 is a block multiple */
1505 (roundup(totlen
, bus
->blocksize
) - totlen
);
1506 totlen
= roundup(totlen
, bus
->blocksize
);
1509 /* Allocate/chain packet for next subframe */
1510 pnext
= brcmu_pkt_buf_get_skb(sublen
+ bus
->sgentry_align
);
1511 if (pnext
== NULL
) {
1512 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n",
1516 skb_queue_tail(&bus
->glom
, pnext
);
1518 /* Adhere to start alignment requirements */
1519 pkt_align(pnext
, sublen
, bus
->sgentry_align
);
1522 /* If all allocations succeeded, save packet chain
1525 brcmf_dbg(GLOM
, "allocated %d-byte packet chain for %d subframes\n",
1527 if (BRCMF_GLOM_ON() && bus
->cur_read
.len
&&
1528 totlen
!= bus
->cur_read
.len
) {
1529 brcmf_dbg(GLOM
, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1530 bus
->cur_read
.len
, totlen
, rxseq
);
1532 pfirst
= pnext
= NULL
;
1534 brcmf_sdio_free_glom(bus
);
1538 /* Done with descriptor packet */
1539 brcmu_pkt_buf_free_skb(bus
->glomd
);
1541 bus
->cur_read
.len
= 0;
1544 /* Ok -- either we just generated a packet chain,
1545 or had one from before */
1546 if (!skb_queue_empty(&bus
->glom
)) {
1547 if (BRCMF_GLOM_ON()) {
1548 brcmf_dbg(GLOM
, "try superframe read, packet chain:\n");
1549 skb_queue_walk(&bus
->glom
, pnext
) {
1550 brcmf_dbg(GLOM
, " %p: %p len 0x%04x (%d)\n",
1551 pnext
, (u8
*) (pnext
->data
),
1552 pnext
->len
, pnext
->len
);
1556 pfirst
= skb_peek(&bus
->glom
);
1557 dlen
= (u16
) brcmf_sdio_glom_len(bus
);
1559 /* Do an SDIO read for the superframe. Configurable iovar to
1560 * read directly into the chained packet, or allocate a large
1561 * packet and and copy into the chain.
1563 sdio_claim_host(bus
->sdiodev
->func
[1]);
1564 errcode
= brcmf_sdiod_recv_chain(bus
->sdiodev
,
1566 sdio_release_host(bus
->sdiodev
->func
[1]);
1567 bus
->sdcnt
.f2rxdata
++;
1569 /* On failure, kill the superframe */
1571 brcmf_err("glom read of %d bytes failed: %d\n",
1574 sdio_claim_host(bus
->sdiodev
->func
[1]);
1575 brcmf_sdio_rxfail(bus
, true, false);
1576 bus
->sdcnt
.rxglomfail
++;
1577 brcmf_sdio_free_glom(bus
);
1578 sdio_release_host(bus
->sdiodev
->func
[1]);
1582 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1583 pfirst
->data
, min_t(int, pfirst
->len
, 48),
1586 rd_new
.seq_num
= rxseq
;
1588 sdio_claim_host(bus
->sdiodev
->func
[1]);
1589 errcode
= brcmf_sdio_hdparse(bus
, pfirst
->data
, &rd_new
,
1590 BRCMF_SDIO_FT_SUPER
);
1591 sdio_release_host(bus
->sdiodev
->func
[1]);
1592 bus
->cur_read
.len
= rd_new
.len_nxtfrm
<< 4;
1594 /* Remove superframe header, remember offset */
1595 skb_pull(pfirst
, rd_new
.dat_offset
);
1596 sfdoff
= rd_new
.dat_offset
;
1599 /* Validate all the subframe headers */
1600 skb_queue_walk(&bus
->glom
, pnext
) {
1601 /* leave when invalid subframe is found */
1605 rd_new
.len
= pnext
->len
;
1606 rd_new
.seq_num
= rxseq
++;
1607 sdio_claim_host(bus
->sdiodev
->func
[1]);
1608 errcode
= brcmf_sdio_hdparse(bus
, pnext
->data
, &rd_new
,
1610 sdio_release_host(bus
->sdiodev
->func
[1]);
1611 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1612 pnext
->data
, 32, "subframe:\n");
1618 /* Terminate frame on error */
1619 sdio_claim_host(bus
->sdiodev
->func
[1]);
1620 brcmf_sdio_rxfail(bus
, true, false);
1621 bus
->sdcnt
.rxglomfail
++;
1622 brcmf_sdio_free_glom(bus
);
1623 sdio_release_host(bus
->sdiodev
->func
[1]);
1624 bus
->cur_read
.len
= 0;
1628 /* Basic SD framing looks ok - process each packet (header) */
1630 skb_queue_walk_safe(&bus
->glom
, pfirst
, pnext
) {
1631 dptr
= (u8
*) (pfirst
->data
);
1632 sublen
= get_unaligned_le16(dptr
);
1633 doff
= brcmf_sdio_getdatoffset(&dptr
[SDPCM_HWHDR_LEN
]);
1635 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1637 "Rx Subframe Data:\n");
1639 __skb_trim(pfirst
, sublen
);
1640 skb_pull(pfirst
, doff
);
1642 if (pfirst
->len
== 0) {
1643 skb_unlink(pfirst
, &bus
->glom
);
1644 brcmu_pkt_buf_free_skb(pfirst
);
1648 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1650 min_t(int, pfirst
->len
, 32),
1651 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1652 bus
->glom
.qlen
, pfirst
, pfirst
->data
,
1653 pfirst
->len
, pfirst
->next
,
1655 skb_unlink(pfirst
, &bus
->glom
);
1656 if (brcmf_sdio_fromevntchan(pfirst
->data
))
1657 brcmf_rx_event(bus
->sdiodev
->dev
, pfirst
);
1659 brcmf_rx_frame(bus
->sdiodev
->dev
, pfirst
,
1661 bus
->sdcnt
.rxglompkts
++;
1664 bus
->sdcnt
.rxglomframes
++;
1669 static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio
*bus
, uint
*condition
,
1672 DECLARE_WAITQUEUE(wait
, current
);
1673 int timeout
= DCMD_RESP_TIMEOUT
;
1675 /* Wait until control frame is available */
1676 add_wait_queue(&bus
->dcmd_resp_wait
, &wait
);
1677 set_current_state(TASK_INTERRUPTIBLE
);
1679 while (!(*condition
) && (!signal_pending(current
) && timeout
))
1680 timeout
= schedule_timeout(timeout
);
1682 if (signal_pending(current
))
1685 set_current_state(TASK_RUNNING
);
1686 remove_wait_queue(&bus
->dcmd_resp_wait
, &wait
);
1691 static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio
*bus
)
1693 wake_up_interruptible(&bus
->dcmd_resp_wait
);
1698 brcmf_sdio_read_control(struct brcmf_sdio
*bus
, u8
*hdr
, uint len
, uint doff
)
1701 u8
*buf
= NULL
, *rbuf
;
1704 brcmf_dbg(TRACE
, "Enter\n");
1707 buf
= vzalloc(bus
->rxblen
);
1712 pad
= ((unsigned long)rbuf
% bus
->head_align
);
1714 rbuf
+= (bus
->head_align
- pad
);
1716 /* Copy the already-read portion over */
1717 memcpy(buf
, hdr
, BRCMF_FIRSTREAD
);
1718 if (len
<= BRCMF_FIRSTREAD
)
1721 /* Raise rdlen to next SDIO block to avoid tail command */
1722 rdlen
= len
- BRCMF_FIRSTREAD
;
1723 if (bus
->roundup
&& bus
->blocksize
&& (rdlen
> bus
->blocksize
)) {
1724 pad
= bus
->blocksize
- (rdlen
% bus
->blocksize
);
1725 if ((pad
<= bus
->roundup
) && (pad
< bus
->blocksize
) &&
1726 ((len
+ pad
) < bus
->sdiodev
->bus_if
->maxctl
))
1728 } else if (rdlen
% bus
->head_align
) {
1729 rdlen
+= bus
->head_align
- (rdlen
% bus
->head_align
);
1732 /* Drop if the read is too big or it exceeds our maximum */
1733 if ((rdlen
+ BRCMF_FIRSTREAD
) > bus
->sdiodev
->bus_if
->maxctl
) {
1734 brcmf_err("%d-byte control read exceeds %d-byte buffer\n",
1735 rdlen
, bus
->sdiodev
->bus_if
->maxctl
);
1736 brcmf_sdio_rxfail(bus
, false, false);
1740 if ((len
- doff
) > bus
->sdiodev
->bus_if
->maxctl
) {
1741 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1742 len
, len
- doff
, bus
->sdiodev
->bus_if
->maxctl
);
1743 bus
->sdcnt
.rx_toolong
++;
1744 brcmf_sdio_rxfail(bus
, false, false);
1748 /* Read remain of frame body */
1749 sdret
= brcmf_sdiod_recv_buf(bus
->sdiodev
, rbuf
, rdlen
);
1750 bus
->sdcnt
.f2rxdata
++;
1752 /* Control frame failures need retransmission */
1754 brcmf_err("read %d control bytes failed: %d\n",
1756 bus
->sdcnt
.rxc_errors
++;
1757 brcmf_sdio_rxfail(bus
, true, true);
1760 memcpy(buf
+ BRCMF_FIRSTREAD
, rbuf
, rdlen
);
1764 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
1765 buf
, len
, "RxCtrl:\n");
1767 /* Point to valid data and indicate its length */
1768 spin_lock_bh(&bus
->rxctl_lock
);
1770 brcmf_err("last control frame is being processed.\n");
1771 spin_unlock_bh(&bus
->rxctl_lock
);
1775 bus
->rxctl
= buf
+ doff
;
1776 bus
->rxctl_orig
= buf
;
1777 bus
->rxlen
= len
- doff
;
1778 spin_unlock_bh(&bus
->rxctl_lock
);
1781 /* Awake any waiters */
1782 brcmf_sdio_dcmd_resp_wake(bus
);
1785 /* Pad read to blocksize for efficiency */
1786 static void brcmf_sdio_pad(struct brcmf_sdio
*bus
, u16
*pad
, u16
*rdlen
)
1788 if (bus
->roundup
&& bus
->blocksize
&& *rdlen
> bus
->blocksize
) {
1789 *pad
= bus
->blocksize
- (*rdlen
% bus
->blocksize
);
1790 if (*pad
<= bus
->roundup
&& *pad
< bus
->blocksize
&&
1791 *rdlen
+ *pad
+ BRCMF_FIRSTREAD
< MAX_RX_DATASZ
)
1793 } else if (*rdlen
% bus
->head_align
) {
1794 *rdlen
+= bus
->head_align
- (*rdlen
% bus
->head_align
);
1798 static uint
brcmf_sdio_readframes(struct brcmf_sdio
*bus
, uint maxframes
)
1800 struct sk_buff
*pkt
; /* Packet for event or data frames */
1801 u16 pad
; /* Number of pad bytes to read */
1802 uint rxleft
= 0; /* Remaining number of frames allowed */
1803 int ret
; /* Return code from calls */
1804 uint rxcount
= 0; /* Total frames read */
1805 struct brcmf_sdio_hdrinfo
*rd
= &bus
->cur_read
, rd_new
;
1808 brcmf_dbg(TRACE
, "Enter\n");
1810 /* Not finished unless we encounter no more frames indication */
1811 bus
->rxpending
= true;
1813 for (rd
->seq_num
= bus
->rx_seq
, rxleft
= maxframes
;
1814 !bus
->rxskip
&& rxleft
&& bus
->sdiodev
->state
== BRCMF_SDIOD_DATA
;
1815 rd
->seq_num
++, rxleft
--) {
1817 /* Handle glomming separately */
1818 if (bus
->glomd
|| !skb_queue_empty(&bus
->glom
)) {
1820 brcmf_dbg(GLOM
, "calling rxglom: glomd %p, glom %p\n",
1821 bus
->glomd
, skb_peek(&bus
->glom
));
1822 cnt
= brcmf_sdio_rxglom(bus
, rd
->seq_num
);
1823 brcmf_dbg(GLOM
, "rxglom returned %d\n", cnt
);
1824 rd
->seq_num
+= cnt
- 1;
1825 rxleft
= (rxleft
> cnt
) ? (rxleft
- cnt
) : 1;
1829 rd
->len_left
= rd
->len
;
1830 /* read header first for unknow frame length */
1831 sdio_claim_host(bus
->sdiodev
->func
[1]);
1833 ret
= brcmf_sdiod_recv_buf(bus
->sdiodev
,
1834 bus
->rxhdr
, BRCMF_FIRSTREAD
);
1835 bus
->sdcnt
.f2rxhdrs
++;
1837 brcmf_err("RXHEADER FAILED: %d\n",
1839 bus
->sdcnt
.rx_hdrfail
++;
1840 brcmf_sdio_rxfail(bus
, true, true);
1841 sdio_release_host(bus
->sdiodev
->func
[1]);
1845 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
1846 bus
->rxhdr
, SDPCM_HDRLEN
,
1849 if (brcmf_sdio_hdparse(bus
, bus
->rxhdr
, rd
,
1850 BRCMF_SDIO_FT_NORMAL
)) {
1851 sdio_release_host(bus
->sdiodev
->func
[1]);
1852 if (!bus
->rxpending
)
1858 if (rd
->channel
== SDPCM_CONTROL_CHANNEL
) {
1859 brcmf_sdio_read_control(bus
, bus
->rxhdr
,
1862 /* prepare the descriptor for the next read */
1863 rd
->len
= rd
->len_nxtfrm
<< 4;
1865 /* treat all packet as event if we don't know */
1866 rd
->channel
= SDPCM_EVENT_CHANNEL
;
1867 sdio_release_host(bus
->sdiodev
->func
[1]);
1870 rd
->len_left
= rd
->len
> BRCMF_FIRSTREAD
?
1871 rd
->len
- BRCMF_FIRSTREAD
: 0;
1872 head_read
= BRCMF_FIRSTREAD
;
1875 brcmf_sdio_pad(bus
, &pad
, &rd
->len_left
);
1877 pkt
= brcmu_pkt_buf_get_skb(rd
->len_left
+ head_read
+
1880 /* Give up on data, request rtx of events */
1881 brcmf_err("brcmu_pkt_buf_get_skb failed\n");
1882 brcmf_sdio_rxfail(bus
, false,
1883 RETRYCHAN(rd
->channel
));
1884 sdio_release_host(bus
->sdiodev
->func
[1]);
1887 skb_pull(pkt
, head_read
);
1888 pkt_align(pkt
, rd
->len_left
, bus
->head_align
);
1890 ret
= brcmf_sdiod_recv_pkt(bus
->sdiodev
, pkt
);
1891 bus
->sdcnt
.f2rxdata
++;
1892 sdio_release_host(bus
->sdiodev
->func
[1]);
1895 brcmf_err("read %d bytes from channel %d failed: %d\n",
1896 rd
->len
, rd
->channel
, ret
);
1897 brcmu_pkt_buf_free_skb(pkt
);
1898 sdio_claim_host(bus
->sdiodev
->func
[1]);
1899 brcmf_sdio_rxfail(bus
, true,
1900 RETRYCHAN(rd
->channel
));
1901 sdio_release_host(bus
->sdiodev
->func
[1]);
1906 skb_push(pkt
, head_read
);
1907 memcpy(pkt
->data
, bus
->rxhdr
, head_read
);
1910 memcpy(bus
->rxhdr
, pkt
->data
, SDPCM_HDRLEN
);
1911 rd_new
.seq_num
= rd
->seq_num
;
1912 sdio_claim_host(bus
->sdiodev
->func
[1]);
1913 if (brcmf_sdio_hdparse(bus
, bus
->rxhdr
, &rd_new
,
1914 BRCMF_SDIO_FT_NORMAL
)) {
1916 brcmu_pkt_buf_free_skb(pkt
);
1918 bus
->sdcnt
.rx_readahead_cnt
++;
1919 if (rd
->len
!= roundup(rd_new
.len
, 16)) {
1920 brcmf_err("frame length mismatch:read %d, should be %d\n",
1922 roundup(rd_new
.len
, 16) >> 4);
1924 brcmf_sdio_rxfail(bus
, true, true);
1925 sdio_release_host(bus
->sdiodev
->func
[1]);
1926 brcmu_pkt_buf_free_skb(pkt
);
1929 sdio_release_host(bus
->sdiodev
->func
[1]);
1930 rd
->len_nxtfrm
= rd_new
.len_nxtfrm
;
1931 rd
->channel
= rd_new
.channel
;
1932 rd
->dat_offset
= rd_new
.dat_offset
;
1934 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
1937 bus
->rxhdr
, SDPCM_HDRLEN
,
1940 if (rd_new
.channel
== SDPCM_CONTROL_CHANNEL
) {
1941 brcmf_err("readahead on control packet %d?\n",
1943 /* Force retry w/normal header read */
1945 sdio_claim_host(bus
->sdiodev
->func
[1]);
1946 brcmf_sdio_rxfail(bus
, false, true);
1947 sdio_release_host(bus
->sdiodev
->func
[1]);
1948 brcmu_pkt_buf_free_skb(pkt
);
1953 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1954 pkt
->data
, rd
->len
, "Rx Data:\n");
1956 /* Save superframe descriptor and allocate packet frame */
1957 if (rd
->channel
== SDPCM_GLOM_CHANNEL
) {
1958 if (SDPCM_GLOMDESC(&bus
->rxhdr
[SDPCM_HWHDR_LEN
])) {
1959 brcmf_dbg(GLOM
, "glom descriptor, %d bytes:\n",
1961 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1964 __skb_trim(pkt
, rd
->len
);
1965 skb_pull(pkt
, SDPCM_HDRLEN
);
1968 brcmf_err("%s: glom superframe w/o "
1969 "descriptor!\n", __func__
);
1970 sdio_claim_host(bus
->sdiodev
->func
[1]);
1971 brcmf_sdio_rxfail(bus
, false, false);
1972 sdio_release_host(bus
->sdiodev
->func
[1]);
1974 /* prepare the descriptor for the next read */
1975 rd
->len
= rd
->len_nxtfrm
<< 4;
1977 /* treat all packet as event if we don't know */
1978 rd
->channel
= SDPCM_EVENT_CHANNEL
;
1982 /* Fill in packet len and prio, deliver upward */
1983 __skb_trim(pkt
, rd
->len
);
1984 skb_pull(pkt
, rd
->dat_offset
);
1987 brcmu_pkt_buf_free_skb(pkt
);
1988 else if (rd
->channel
== SDPCM_EVENT_CHANNEL
)
1989 brcmf_rx_event(bus
->sdiodev
->dev
, pkt
);
1991 brcmf_rx_frame(bus
->sdiodev
->dev
, pkt
,
1994 /* prepare the descriptor for the next read */
1995 rd
->len
= rd
->len_nxtfrm
<< 4;
1997 /* treat all packet as event if we don't know */
1998 rd
->channel
= SDPCM_EVENT_CHANNEL
;
2001 rxcount
= maxframes
- rxleft
;
2002 /* Message if we hit the limit */
2004 brcmf_dbg(DATA
, "hit rx limit of %d frames\n", maxframes
);
2006 brcmf_dbg(DATA
, "processed %d frames\n", rxcount
);
2007 /* Back off rxseq if awaiting rtx, update rx_seq */
2010 bus
->rx_seq
= rd
->seq_num
;
2016 brcmf_sdio_wait_event_wakeup(struct brcmf_sdio
*bus
)
2018 wake_up_interruptible(&bus
->ctrl_wait
);
2022 static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio
*bus
, struct sk_buff
*pkt
)
2027 dat_buf
= (u8
*)(pkt
->data
);
2029 /* Check head padding */
2030 head_pad
= ((unsigned long)dat_buf
% bus
->head_align
);
2032 if (skb_headroom(pkt
) < head_pad
) {
2033 bus
->sdiodev
->bus_if
->tx_realloc
++;
2035 if (skb_cow(pkt
, head_pad
))
2038 skb_push(pkt
, head_pad
);
2039 dat_buf
= (u8
*)(pkt
->data
);
2040 memset(dat_buf
, 0, head_pad
+ bus
->tx_hdrlen
);
2046 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for
2049 /* flag marking a dummy skb added for DMA alignment requirement */
2050 #define ALIGN_SKB_FLAG 0x8000
2051 /* bit mask of data length chopped from the previous packet */
2052 #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff
2054 static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio
*bus
,
2055 struct sk_buff_head
*pktq
,
2056 struct sk_buff
*pkt
, u16 total_len
)
2058 struct brcmf_sdio_dev
*sdiodev
;
2059 struct sk_buff
*pkt_pad
;
2060 u16 tail_pad
, tail_chop
, chain_pad
;
2061 unsigned int blksize
;
2065 sdiodev
= bus
->sdiodev
;
2066 blksize
= sdiodev
->func
[SDIO_FUNC_2
]->cur_blksize
;
2067 /* sg entry alignment should be a divisor of block size */
2068 WARN_ON(blksize
% bus
->sgentry_align
);
2070 /* Check tail padding */
2071 lastfrm
= skb_queue_is_last(pktq
, pkt
);
2073 tail_chop
= pkt
->len
% bus
->sgentry_align
;
2075 tail_pad
= bus
->sgentry_align
- tail_chop
;
2076 chain_pad
= (total_len
+ tail_pad
) % blksize
;
2077 if (lastfrm
&& chain_pad
)
2078 tail_pad
+= blksize
- chain_pad
;
2079 if (skb_tailroom(pkt
) < tail_pad
&& pkt
->len
> blksize
) {
2080 pkt_pad
= brcmu_pkt_buf_get_skb(tail_pad
+ tail_chop
+
2082 if (pkt_pad
== NULL
)
2084 ret
= brcmf_sdio_txpkt_hdalign(bus
, pkt_pad
);
2085 if (unlikely(ret
< 0)) {
2089 memcpy(pkt_pad
->data
,
2090 pkt
->data
+ pkt
->len
- tail_chop
,
2092 *(u16
*)(pkt_pad
->cb
) = ALIGN_SKB_FLAG
+ tail_chop
;
2093 skb_trim(pkt
, pkt
->len
- tail_chop
);
2094 skb_trim(pkt_pad
, tail_pad
+ tail_chop
);
2095 __skb_queue_after(pktq
, pkt
, pkt_pad
);
2097 ntail
= pkt
->data_len
+ tail_pad
-
2098 (pkt
->end
- pkt
->tail
);
2099 if (skb_cloned(pkt
) || ntail
> 0)
2100 if (pskb_expand_head(pkt
, 0, ntail
, GFP_ATOMIC
))
2102 if (skb_linearize(pkt
))
2104 __skb_put(pkt
, tail_pad
);
2111 * brcmf_sdio_txpkt_prep - packet preparation for transmit
2112 * @bus: brcmf_sdio structure pointer
2113 * @pktq: packet list pointer
2114 * @chan: virtual channel to transmit the packet
2116 * Processes to be applied to the packet
2117 * - Align data buffer pointer
2118 * - Align data buffer length
2120 * Return: negative value if there is error
2123 brcmf_sdio_txpkt_prep(struct brcmf_sdio
*bus
, struct sk_buff_head
*pktq
,
2126 u16 head_pad
, total_len
;
2127 struct sk_buff
*pkt_next
;
2130 struct brcmf_sdio_hdrinfo hd_info
= {0};
2132 txseq
= bus
->tx_seq
;
2134 skb_queue_walk(pktq
, pkt_next
) {
2135 /* alignment packet inserted in previous
2136 * loop cycle can be skipped as it is
2137 * already properly aligned and does not
2138 * need an sdpcm header.
2140 if (*(u16
*)(pkt_next
->cb
) & ALIGN_SKB_FLAG
)
2143 /* align packet data pointer */
2144 ret
= brcmf_sdio_txpkt_hdalign(bus
, pkt_next
);
2147 head_pad
= (u16
)ret
;
2149 memset(pkt_next
->data
+ bus
->tx_hdrlen
, 0, head_pad
);
2151 total_len
+= pkt_next
->len
;
2153 hd_info
.len
= pkt_next
->len
;
2154 hd_info
.lastfrm
= skb_queue_is_last(pktq
, pkt_next
);
2155 if (bus
->txglom
&& pktq
->qlen
> 1) {
2156 ret
= brcmf_sdio_txpkt_prep_sg(bus
, pktq
,
2157 pkt_next
, total_len
);
2160 hd_info
.tail_pad
= (u16
)ret
;
2161 total_len
+= (u16
)ret
;
2164 hd_info
.channel
= chan
;
2165 hd_info
.dat_offset
= head_pad
+ bus
->tx_hdrlen
;
2166 hd_info
.seq_num
= txseq
++;
2168 /* Now fill the header */
2169 brcmf_sdio_hdpack(bus
, pkt_next
->data
, &hd_info
);
2171 if (BRCMF_BYTES_ON() &&
2172 ((BRCMF_CTL_ON() && chan
== SDPCM_CONTROL_CHANNEL
) ||
2173 (BRCMF_DATA_ON() && chan
!= SDPCM_CONTROL_CHANNEL
)))
2174 brcmf_dbg_hex_dump(true, pkt_next
->data
, hd_info
.len
,
2176 else if (BRCMF_HDRS_ON())
2177 brcmf_dbg_hex_dump(true, pkt_next
->data
,
2178 head_pad
+ bus
->tx_hdrlen
,
2181 /* Hardware length tag of the first packet should be total
2182 * length of the chain (including padding)
2185 brcmf_sdio_update_hwhdr(pktq
->next
->data
, total_len
);
2190 * brcmf_sdio_txpkt_postp - packet post processing for transmit
2191 * @bus: brcmf_sdio structure pointer
2192 * @pktq: packet list pointer
2194 * Processes to be applied to the packet
2195 * - Remove head padding
2196 * - Remove tail padding
2199 brcmf_sdio_txpkt_postp(struct brcmf_sdio
*bus
, struct sk_buff_head
*pktq
)
2204 u16 dummy_flags
, chop_len
;
2205 struct sk_buff
*pkt_next
, *tmp
, *pkt_prev
;
2207 skb_queue_walk_safe(pktq
, pkt_next
, tmp
) {
2208 dummy_flags
= *(u16
*)(pkt_next
->cb
);
2209 if (dummy_flags
& ALIGN_SKB_FLAG
) {
2210 chop_len
= dummy_flags
& ALIGN_SKB_CHOP_LEN_MASK
;
2212 pkt_prev
= pkt_next
->prev
;
2213 skb_put(pkt_prev
, chop_len
);
2215 __skb_unlink(pkt_next
, pktq
);
2216 brcmu_pkt_buf_free_skb(pkt_next
);
2218 hdr
= pkt_next
->data
+ bus
->tx_hdrlen
- SDPCM_SWHDR_LEN
;
2219 dat_offset
= le32_to_cpu(*(__le32
*)hdr
);
2220 dat_offset
= (dat_offset
& SDPCM_DOFFSET_MASK
) >>
2221 SDPCM_DOFFSET_SHIFT
;
2222 skb_pull(pkt_next
, dat_offset
);
2224 tail_pad
= le16_to_cpu(*(__le16
*)(hdr
- 2));
2225 skb_trim(pkt_next
, pkt_next
->len
- tail_pad
);
2231 /* Writes a HW/SW header into the packet and sends it. */
2232 /* Assumes: (a) header space already there, (b) caller holds lock */
2233 static int brcmf_sdio_txpkt(struct brcmf_sdio
*bus
, struct sk_buff_head
*pktq
,
2237 struct sk_buff
*pkt_next
, *tmp
;
2239 brcmf_dbg(TRACE
, "Enter\n");
2241 ret
= brcmf_sdio_txpkt_prep(bus
, pktq
, chan
);
2245 sdio_claim_host(bus
->sdiodev
->func
[1]);
2246 ret
= brcmf_sdiod_send_pkt(bus
->sdiodev
, pktq
);
2247 bus
->sdcnt
.f2txdata
++;
2250 brcmf_sdio_txfail(bus
);
2252 sdio_release_host(bus
->sdiodev
->func
[1]);
2255 brcmf_sdio_txpkt_postp(bus
, pktq
);
2257 bus
->tx_seq
= (bus
->tx_seq
+ pktq
->qlen
) % SDPCM_SEQ_WRAP
;
2258 skb_queue_walk_safe(pktq
, pkt_next
, tmp
) {
2259 __skb_unlink(pkt_next
, pktq
);
2260 brcmf_txcomplete(bus
->sdiodev
->dev
, pkt_next
, ret
== 0);
2265 static uint
brcmf_sdio_sendfromq(struct brcmf_sdio
*bus
, uint maxframes
)
2267 struct sk_buff
*pkt
;
2268 struct sk_buff_head pktq
;
2270 int ret
= 0, prec_out
, i
;
2272 u8 tx_prec_map
, pkt_num
;
2274 brcmf_dbg(TRACE
, "Enter\n");
2276 tx_prec_map
= ~bus
->flowcontrol
;
2278 /* Send frames until the limit or some other event */
2279 for (cnt
= 0; (cnt
< maxframes
) && data_ok(bus
);) {
2282 pkt_num
= min_t(u8
, bus
->tx_max
- bus
->tx_seq
,
2283 bus
->sdiodev
->txglomsz
);
2284 pkt_num
= min_t(u32
, pkt_num
,
2285 brcmu_pktq_mlen(&bus
->txq
, ~bus
->flowcontrol
));
2286 __skb_queue_head_init(&pktq
);
2287 spin_lock_bh(&bus
->txq_lock
);
2288 for (i
= 0; i
< pkt_num
; i
++) {
2289 pkt
= brcmu_pktq_mdeq(&bus
->txq
, tx_prec_map
,
2293 __skb_queue_tail(&pktq
, pkt
);
2295 spin_unlock_bh(&bus
->txq_lock
);
2299 ret
= brcmf_sdio_txpkt(bus
, &pktq
, SDPCM_DATA_CHANNEL
);
2303 /* In poll mode, need to check for other events */
2305 /* Check device status, signal pending interrupt */
2306 sdio_claim_host(bus
->sdiodev
->func
[1]);
2307 ret
= r_sdreg32(bus
, &intstatus
,
2308 offsetof(struct sdpcmd_regs
,
2310 sdio_release_host(bus
->sdiodev
->func
[1]);
2311 bus
->sdcnt
.f2txdata
++;
2314 if (intstatus
& bus
->hostintmask
)
2315 atomic_set(&bus
->ipend
, 1);
2319 /* Deflow-control stack if needed */
2320 if ((bus
->sdiodev
->state
== BRCMF_SDIOD_DATA
) &&
2321 bus
->txoff
&& (pktq_len(&bus
->txq
) < TXLOW
)) {
2323 brcmf_txflowblock(bus
->sdiodev
->dev
, false);
2329 static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio
*bus
, u8
*frame
, u16 len
)
2334 struct brcmf_sdio_hdrinfo hd_info
= {0};
2337 brcmf_dbg(TRACE
, "Enter\n");
2339 /* Back the pointer to make room for bus header */
2340 frame
-= bus
->tx_hdrlen
;
2341 len
+= bus
->tx_hdrlen
;
2343 /* Add alignment padding (optional for ctl frames) */
2344 doff
= ((unsigned long)frame
% bus
->head_align
);
2348 memset(frame
+ bus
->tx_hdrlen
, 0, doff
);
2351 /* Round send length to next SDIO block */
2353 if (bus
->roundup
&& bus
->blocksize
&& (len
> bus
->blocksize
)) {
2354 pad
= bus
->blocksize
- (len
% bus
->blocksize
);
2355 if ((pad
> bus
->roundup
) || (pad
>= bus
->blocksize
))
2357 } else if (len
% bus
->head_align
) {
2358 pad
= bus
->head_align
- (len
% bus
->head_align
);
2362 hd_info
.len
= len
- pad
;
2363 hd_info
.channel
= SDPCM_CONTROL_CHANNEL
;
2364 hd_info
.dat_offset
= doff
+ bus
->tx_hdrlen
;
2365 hd_info
.seq_num
= bus
->tx_seq
;
2366 hd_info
.lastfrm
= true;
2367 hd_info
.tail_pad
= pad
;
2368 brcmf_sdio_hdpack(bus
, frame
, &hd_info
);
2371 brcmf_sdio_update_hwhdr(frame
, len
);
2373 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
2374 frame
, len
, "Tx Frame:\n");
2375 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
2377 frame
, min_t(u16
, len
, 16), "TxHdr:\n");
2380 ret
= brcmf_sdiod_send_buf(bus
->sdiodev
, frame
, len
);
2383 brcmf_sdio_txfail(bus
);
2385 bus
->tx_seq
= (bus
->tx_seq
+ 1) % SDPCM_SEQ_WRAP
;
2386 } while (ret
< 0 && retries
++ < TXRETRIES
);
2391 static void brcmf_sdio_bus_stop(struct device
*dev
)
2393 u32 local_hostintmask
;
2396 struct brcmf_bus
*bus_if
= dev_get_drvdata(dev
);
2397 struct brcmf_sdio_dev
*sdiodev
= bus_if
->bus_priv
.sdio
;
2398 struct brcmf_sdio
*bus
= sdiodev
->bus
;
2400 brcmf_dbg(TRACE
, "Enter\n");
2402 if (bus
->watchdog_tsk
) {
2403 send_sig(SIGTERM
, bus
->watchdog_tsk
, 1);
2404 kthread_stop(bus
->watchdog_tsk
);
2405 bus
->watchdog_tsk
= NULL
;
2408 if (sdiodev
->state
!= BRCMF_SDIOD_NOMEDIUM
) {
2409 sdio_claim_host(sdiodev
->func
[1]);
2411 /* Enable clock for device interrupts */
2412 brcmf_sdio_bus_sleep(bus
, false, false);
2414 /* Disable and clear interrupts at the chip level also */
2415 w_sdreg32(bus
, 0, offsetof(struct sdpcmd_regs
, hostintmask
));
2416 local_hostintmask
= bus
->hostintmask
;
2417 bus
->hostintmask
= 0;
2419 /* Force backplane clocks to assure F2 interrupt propagates */
2420 saveclk
= brcmf_sdiod_regrb(sdiodev
, SBSDIO_FUNC1_CHIPCLKCSR
,
2423 brcmf_sdiod_regwb(sdiodev
, SBSDIO_FUNC1_CHIPCLKCSR
,
2424 (saveclk
| SBSDIO_FORCE_HT
), &err
);
2426 brcmf_err("Failed to force clock for F2: err %d\n",
2429 /* Turn off the bus (F2), free any pending packets */
2430 brcmf_dbg(INTR
, "disable SDIO interrupts\n");
2431 sdio_disable_func(sdiodev
->func
[SDIO_FUNC_2
]);
2433 /* Clear any pending interrupts now that F2 is disabled */
2434 w_sdreg32(bus
, local_hostintmask
,
2435 offsetof(struct sdpcmd_regs
, intstatus
));
2437 sdio_release_host(sdiodev
->func
[1]);
2439 /* Clear the data packet queues */
2440 brcmu_pktq_flush(&bus
->txq
, true, NULL
, NULL
);
2442 /* Clear any held glomming stuff */
2443 brcmu_pkt_buf_free_skb(bus
->glomd
);
2444 brcmf_sdio_free_glom(bus
);
2446 /* Clear rx control and wake any waiters */
2447 spin_lock_bh(&bus
->rxctl_lock
);
2449 spin_unlock_bh(&bus
->rxctl_lock
);
2450 brcmf_sdio_dcmd_resp_wake(bus
);
2452 /* Reset some F2 state stuff */
2453 bus
->rxskip
= false;
2454 bus
->tx_seq
= bus
->rx_seq
= 0;
2457 static inline void brcmf_sdio_clrintr(struct brcmf_sdio
*bus
)
2459 struct brcmf_sdio_dev
*sdiodev
;
2460 unsigned long flags
;
2462 sdiodev
= bus
->sdiodev
;
2463 if (sdiodev
->oob_irq_requested
) {
2464 spin_lock_irqsave(&sdiodev
->irq_en_lock
, flags
);
2465 if (!sdiodev
->irq_en
&& !atomic_read(&bus
->ipend
)) {
2466 enable_irq(sdiodev
->settings
->bus
.sdio
.oob_irq_nr
);
2467 sdiodev
->irq_en
= true;
2469 spin_unlock_irqrestore(&sdiodev
->irq_en_lock
, flags
);
2473 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio
*bus
)
2475 struct brcmf_core
*buscore
;
2480 buscore
= brcmf_chip_get_core(bus
->ci
, BCMA_CORE_SDIO_DEV
);
2481 addr
= buscore
->base
+ offsetof(struct sdpcmd_regs
, intstatus
);
2483 val
= brcmf_sdiod_regrl(bus
->sdiodev
, addr
, &ret
);
2484 bus
->sdcnt
.f1regdata
++;
2488 val
&= bus
->hostintmask
;
2489 atomic_set(&bus
->fcstate
, !!(val
& I_HMB_FC_STATE
));
2491 /* Clear interrupts */
2493 brcmf_sdiod_regwl(bus
->sdiodev
, addr
, val
, &ret
);
2494 bus
->sdcnt
.f1regdata
++;
2495 atomic_or(val
, &bus
->intstatus
);
2501 static void brcmf_sdio_dpc(struct brcmf_sdio
*bus
)
2504 unsigned long intstatus
;
2505 uint txlimit
= bus
->txbound
; /* Tx frames to send before resched */
2506 uint framecnt
; /* Temporary counter of tx/rx frames */
2509 brcmf_dbg(TRACE
, "Enter\n");
2511 sdio_claim_host(bus
->sdiodev
->func
[1]);
2513 /* If waiting for HTAVAIL, check status */
2514 if (!bus
->sr_enabled
&& bus
->clkstate
== CLK_PENDING
) {
2515 u8 clkctl
, devctl
= 0;
2518 /* Check for inconsistent device control */
2519 devctl
= brcmf_sdiod_regrb(bus
->sdiodev
,
2520 SBSDIO_DEVICE_CTL
, &err
);
2523 /* Read CSR, if clock on switch to AVAIL, else ignore */
2524 clkctl
= brcmf_sdiod_regrb(bus
->sdiodev
,
2525 SBSDIO_FUNC1_CHIPCLKCSR
, &err
);
2527 brcmf_dbg(SDIO
, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2530 if (SBSDIO_HTAV(clkctl
)) {
2531 devctl
= brcmf_sdiod_regrb(bus
->sdiodev
,
2532 SBSDIO_DEVICE_CTL
, &err
);
2533 devctl
&= ~SBSDIO_DEVCTL_CA_INT_ONLY
;
2534 brcmf_sdiod_regwb(bus
->sdiodev
, SBSDIO_DEVICE_CTL
,
2536 bus
->clkstate
= CLK_AVAIL
;
2540 /* Make sure backplane clock is on */
2541 brcmf_sdio_bus_sleep(bus
, false, true);
2543 /* Pending interrupt indicates new device status */
2544 if (atomic_read(&bus
->ipend
) > 0) {
2545 atomic_set(&bus
->ipend
, 0);
2546 err
= brcmf_sdio_intr_rstatus(bus
);
2549 /* Start with leftover status bits */
2550 intstatus
= atomic_xchg(&bus
->intstatus
, 0);
2552 /* Handle flow-control change: read new state in case our ack
2553 * crossed another change interrupt. If change still set, assume
2554 * FC ON for safety, let next loop through do the debounce.
2556 if (intstatus
& I_HMB_FC_CHANGE
) {
2557 intstatus
&= ~I_HMB_FC_CHANGE
;
2558 err
= w_sdreg32(bus
, I_HMB_FC_CHANGE
,
2559 offsetof(struct sdpcmd_regs
, intstatus
));
2561 err
= r_sdreg32(bus
, &newstatus
,
2562 offsetof(struct sdpcmd_regs
, intstatus
));
2563 bus
->sdcnt
.f1regdata
+= 2;
2564 atomic_set(&bus
->fcstate
,
2565 !!(newstatus
& (I_HMB_FC_STATE
| I_HMB_FC_CHANGE
)));
2566 intstatus
|= (newstatus
& bus
->hostintmask
);
2569 /* Handle host mailbox indication */
2570 if (intstatus
& I_HMB_HOST_INT
) {
2571 intstatus
&= ~I_HMB_HOST_INT
;
2572 intstatus
|= brcmf_sdio_hostmail(bus
);
2575 sdio_release_host(bus
->sdiodev
->func
[1]);
2577 /* Generally don't ask for these, can get CRC errors... */
2578 if (intstatus
& I_WR_OOSYNC
) {
2579 brcmf_err("Dongle reports WR_OOSYNC\n");
2580 intstatus
&= ~I_WR_OOSYNC
;
2583 if (intstatus
& I_RD_OOSYNC
) {
2584 brcmf_err("Dongle reports RD_OOSYNC\n");
2585 intstatus
&= ~I_RD_OOSYNC
;
2588 if (intstatus
& I_SBINT
) {
2589 brcmf_err("Dongle reports SBINT\n");
2590 intstatus
&= ~I_SBINT
;
2593 /* Would be active due to wake-wlan in gSPI */
2594 if (intstatus
& I_CHIPACTIVE
) {
2595 brcmf_dbg(INFO
, "Dongle reports CHIPACTIVE\n");
2596 intstatus
&= ~I_CHIPACTIVE
;
2599 /* Ignore frame indications if rxskip is set */
2601 intstatus
&= ~I_HMB_FRAME_IND
;
2603 /* On frame indication, read available frames */
2604 if ((intstatus
& I_HMB_FRAME_IND
) && (bus
->clkstate
== CLK_AVAIL
)) {
2605 brcmf_sdio_readframes(bus
, bus
->rxbound
);
2606 if (!bus
->rxpending
)
2607 intstatus
&= ~I_HMB_FRAME_IND
;
2610 /* Keep still-pending events for next scheduling */
2612 atomic_or(intstatus
, &bus
->intstatus
);
2614 brcmf_sdio_clrintr(bus
);
2616 if (bus
->ctrl_frame_stat
&& (bus
->clkstate
== CLK_AVAIL
) &&
2618 sdio_claim_host(bus
->sdiodev
->func
[1]);
2619 if (bus
->ctrl_frame_stat
) {
2620 err
= brcmf_sdio_tx_ctrlframe(bus
, bus
->ctrl_frame_buf
,
2621 bus
->ctrl_frame_len
);
2622 bus
->ctrl_frame_err
= err
;
2624 bus
->ctrl_frame_stat
= false;
2626 sdio_release_host(bus
->sdiodev
->func
[1]);
2627 brcmf_sdio_wait_event_wakeup(bus
);
2629 /* Send queued frames (limit 1 if rx may still be pending) */
2630 if ((bus
->clkstate
== CLK_AVAIL
) && !atomic_read(&bus
->fcstate
) &&
2631 brcmu_pktq_mlen(&bus
->txq
, ~bus
->flowcontrol
) && txlimit
&&
2633 framecnt
= bus
->rxpending
? min(txlimit
, bus
->txminmax
) :
2635 brcmf_sdio_sendfromq(bus
, framecnt
);
2638 if ((bus
->sdiodev
->state
!= BRCMF_SDIOD_DATA
) || (err
!= 0)) {
2639 brcmf_err("failed backplane access over SDIO, halting operation\n");
2640 atomic_set(&bus
->intstatus
, 0);
2641 if (bus
->ctrl_frame_stat
) {
2642 sdio_claim_host(bus
->sdiodev
->func
[1]);
2643 if (bus
->ctrl_frame_stat
) {
2644 bus
->ctrl_frame_err
= -ENODEV
;
2646 bus
->ctrl_frame_stat
= false;
2647 brcmf_sdio_wait_event_wakeup(bus
);
2649 sdio_release_host(bus
->sdiodev
->func
[1]);
2651 } else if (atomic_read(&bus
->intstatus
) ||
2652 atomic_read(&bus
->ipend
) > 0 ||
2653 (!atomic_read(&bus
->fcstate
) &&
2654 brcmu_pktq_mlen(&bus
->txq
, ~bus
->flowcontrol
) &&
2656 bus
->dpc_triggered
= true;
2660 static struct pktq
*brcmf_sdio_bus_gettxq(struct device
*dev
)
2662 struct brcmf_bus
*bus_if
= dev_get_drvdata(dev
);
2663 struct brcmf_sdio_dev
*sdiodev
= bus_if
->bus_priv
.sdio
;
2664 struct brcmf_sdio
*bus
= sdiodev
->bus
;
2669 static bool brcmf_sdio_prec_enq(struct pktq
*q
, struct sk_buff
*pkt
, int prec
)
2672 int eprec
= -1; /* precedence to evict from */
2674 /* Fast case, precedence queue is not full and we are also not
2675 * exceeding total queue length
2677 if (!pktq_pfull(q
, prec
) && !pktq_full(q
)) {
2678 brcmu_pktq_penq(q
, prec
, pkt
);
2682 /* Determine precedence from which to evict packet, if any */
2683 if (pktq_pfull(q
, prec
)) {
2685 } else if (pktq_full(q
)) {
2686 p
= brcmu_pktq_peek_tail(q
, &eprec
);
2691 /* Evict if needed */
2693 /* Detect queueing to unconfigured precedence */
2695 return false; /* refuse newer (incoming) packet */
2696 /* Evict packet according to discard policy */
2697 p
= brcmu_pktq_pdeq_tail(q
, eprec
);
2699 brcmf_err("brcmu_pktq_pdeq_tail() failed\n");
2700 brcmu_pkt_buf_free_skb(p
);
2704 p
= brcmu_pktq_penq(q
, prec
, pkt
);
2706 brcmf_err("brcmu_pktq_penq() failed\n");
2711 static int brcmf_sdio_bus_txdata(struct device
*dev
, struct sk_buff
*pkt
)
2715 struct brcmf_bus
*bus_if
= dev_get_drvdata(dev
);
2716 struct brcmf_sdio_dev
*sdiodev
= bus_if
->bus_priv
.sdio
;
2717 struct brcmf_sdio
*bus
= sdiodev
->bus
;
2719 brcmf_dbg(TRACE
, "Enter: pkt: data %p len %d\n", pkt
->data
, pkt
->len
);
2720 if (sdiodev
->state
!= BRCMF_SDIOD_DATA
)
2723 /* Add space for the header */
2724 skb_push(pkt
, bus
->tx_hdrlen
);
2725 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2727 prec
= prio2prec((pkt
->priority
& PRIOMASK
));
2729 /* Check for existing queue, current flow-control,
2730 pending event, or pending clock */
2731 brcmf_dbg(TRACE
, "deferring pktq len %d\n", pktq_len(&bus
->txq
));
2732 bus
->sdcnt
.fcqueued
++;
2734 /* Priority based enq */
2735 spin_lock_bh(&bus
->txq_lock
);
2736 /* reset bus_flags in packet cb */
2737 *(u16
*)(pkt
->cb
) = 0;
2738 if (!brcmf_sdio_prec_enq(&bus
->txq
, pkt
, prec
)) {
2739 skb_pull(pkt
, bus
->tx_hdrlen
);
2740 brcmf_err("out of bus->txq !!!\n");
2746 if (pktq_len(&bus
->txq
) >= TXHI
) {
2748 brcmf_txflowblock(dev
, true);
2750 spin_unlock_bh(&bus
->txq_lock
);
2753 if (pktq_plen(&bus
->txq
, prec
) > qcount
[prec
])
2754 qcount
[prec
] = pktq_plen(&bus
->txq
, prec
);
2757 brcmf_sdio_trigger_dpc(bus
);
2762 #define CONSOLE_LINE_MAX 192
2764 static int brcmf_sdio_readconsole(struct brcmf_sdio
*bus
)
2766 struct brcmf_console
*c
= &bus
->console
;
2767 u8 line
[CONSOLE_LINE_MAX
], ch
;
2771 /* Don't do anything until FWREADY updates console address */
2772 if (bus
->console_addr
== 0)
2775 /* Read console log struct */
2776 addr
= bus
->console_addr
+ offsetof(struct rte_console
, log_le
);
2777 rv
= brcmf_sdiod_ramrw(bus
->sdiodev
, false, addr
, (u8
*)&c
->log_le
,
2782 /* Allocate console buffer (one time only) */
2783 if (c
->buf
== NULL
) {
2784 c
->bufsize
= le32_to_cpu(c
->log_le
.buf_size
);
2785 c
->buf
= kmalloc(c
->bufsize
, GFP_ATOMIC
);
2790 idx
= le32_to_cpu(c
->log_le
.idx
);
2792 /* Protect against corrupt value */
2793 if (idx
> c
->bufsize
)
2796 /* Skip reading the console buffer if the index pointer
2801 /* Read the console buffer */
2802 addr
= le32_to_cpu(c
->log_le
.buf
);
2803 rv
= brcmf_sdiod_ramrw(bus
->sdiodev
, false, addr
, c
->buf
, c
->bufsize
);
2807 while (c
->last
!= idx
) {
2808 for (n
= 0; n
< CONSOLE_LINE_MAX
- 2; n
++) {
2809 if (c
->last
== idx
) {
2810 /* This would output a partial line.
2812 * the buffer pointer and output this
2813 * line next time around.
2818 c
->last
= c
->bufsize
- n
;
2821 ch
= c
->buf
[c
->last
];
2822 c
->last
= (c
->last
+ 1) % c
->bufsize
;
2829 if (line
[n
- 1] == '\r')
2832 pr_debug("CONSOLE: %s\n", line
);
2842 brcmf_sdio_bus_txctl(struct device
*dev
, unsigned char *msg
, uint msglen
)
2844 struct brcmf_bus
*bus_if
= dev_get_drvdata(dev
);
2845 struct brcmf_sdio_dev
*sdiodev
= bus_if
->bus_priv
.sdio
;
2846 struct brcmf_sdio
*bus
= sdiodev
->bus
;
2849 brcmf_dbg(TRACE
, "Enter\n");
2850 if (sdiodev
->state
!= BRCMF_SDIOD_DATA
)
2854 bus
->ctrl_frame_buf
= msg
;
2855 bus
->ctrl_frame_len
= msglen
;
2857 bus
->ctrl_frame_stat
= true;
2859 brcmf_sdio_trigger_dpc(bus
);
2860 wait_event_interruptible_timeout(bus
->ctrl_wait
, !bus
->ctrl_frame_stat
,
2863 if (bus
->ctrl_frame_stat
) {
2864 sdio_claim_host(bus
->sdiodev
->func
[1]);
2865 if (bus
->ctrl_frame_stat
) {
2866 brcmf_dbg(SDIO
, "ctrl_frame timeout\n");
2867 bus
->ctrl_frame_stat
= false;
2870 sdio_release_host(bus
->sdiodev
->func
[1]);
2873 brcmf_dbg(SDIO
, "ctrl_frame complete, err=%d\n",
2874 bus
->ctrl_frame_err
);
2876 ret
= bus
->ctrl_frame_err
;
2880 bus
->sdcnt
.tx_ctlerrs
++;
2882 bus
->sdcnt
.tx_ctlpkts
++;
2888 static int brcmf_sdio_dump_console(struct seq_file
*seq
, struct brcmf_sdio
*bus
,
2889 struct sdpcm_shared
*sh
)
2891 u32 addr
, console_ptr
, console_size
, console_index
;
2892 char *conbuf
= NULL
;
2896 /* obtain console information from device memory */
2897 addr
= sh
->console_addr
+ offsetof(struct rte_console
, log_le
);
2898 rv
= brcmf_sdiod_ramrw(bus
->sdiodev
, false, addr
,
2899 (u8
*)&sh_val
, sizeof(u32
));
2902 console_ptr
= le32_to_cpu(sh_val
);
2904 addr
= sh
->console_addr
+ offsetof(struct rte_console
, log_le
.buf_size
);
2905 rv
= brcmf_sdiod_ramrw(bus
->sdiodev
, false, addr
,
2906 (u8
*)&sh_val
, sizeof(u32
));
2909 console_size
= le32_to_cpu(sh_val
);
2911 addr
= sh
->console_addr
+ offsetof(struct rte_console
, log_le
.idx
);
2912 rv
= brcmf_sdiod_ramrw(bus
->sdiodev
, false, addr
,
2913 (u8
*)&sh_val
, sizeof(u32
));
2916 console_index
= le32_to_cpu(sh_val
);
2918 /* allocate buffer for console data */
2919 if (console_size
<= CONSOLE_BUFFER_MAX
)
2920 conbuf
= vzalloc(console_size
+1);
2925 /* obtain the console data from device */
2926 conbuf
[console_size
] = '\0';
2927 rv
= brcmf_sdiod_ramrw(bus
->sdiodev
, false, console_ptr
, (u8
*)conbuf
,
2932 rv
= seq_write(seq
, conbuf
+ console_index
,
2933 console_size
- console_index
);
2937 if (console_index
> 0)
2938 rv
= seq_write(seq
, conbuf
, console_index
- 1);
2945 static int brcmf_sdio_trap_info(struct seq_file
*seq
, struct brcmf_sdio
*bus
,
2946 struct sdpcm_shared
*sh
)
2949 struct brcmf_trap_info tr
;
2951 if ((sh
->flags
& SDPCM_SHARED_TRAP
) == 0) {
2952 brcmf_dbg(INFO
, "no trap in firmware\n");
2956 error
= brcmf_sdiod_ramrw(bus
->sdiodev
, false, sh
->trap_addr
, (u8
*)&tr
,
2957 sizeof(struct brcmf_trap_info
));
2962 "dongle trap info: type 0x%x @ epc 0x%08x\n"
2963 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
2964 " lr 0x%08x pc 0x%08x offset 0x%x\n"
2965 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
2966 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
2967 le32_to_cpu(tr
.type
), le32_to_cpu(tr
.epc
),
2968 le32_to_cpu(tr
.cpsr
), le32_to_cpu(tr
.spsr
),
2969 le32_to_cpu(tr
.r13
), le32_to_cpu(tr
.r14
),
2970 le32_to_cpu(tr
.pc
), sh
->trap_addr
,
2971 le32_to_cpu(tr
.r0
), le32_to_cpu(tr
.r1
),
2972 le32_to_cpu(tr
.r2
), le32_to_cpu(tr
.r3
),
2973 le32_to_cpu(tr
.r4
), le32_to_cpu(tr
.r5
),
2974 le32_to_cpu(tr
.r6
), le32_to_cpu(tr
.r7
));
2979 static int brcmf_sdio_assert_info(struct seq_file
*seq
, struct brcmf_sdio
*bus
,
2980 struct sdpcm_shared
*sh
)
2983 char file
[80] = "?";
2984 char expr
[80] = "<???>";
2986 if ((sh
->flags
& SDPCM_SHARED_ASSERT_BUILT
) == 0) {
2987 brcmf_dbg(INFO
, "firmware not built with -assert\n");
2989 } else if ((sh
->flags
& SDPCM_SHARED_ASSERT
) == 0) {
2990 brcmf_dbg(INFO
, "no assert in dongle\n");
2994 sdio_claim_host(bus
->sdiodev
->func
[1]);
2995 if (sh
->assert_file_addr
!= 0) {
2996 error
= brcmf_sdiod_ramrw(bus
->sdiodev
, false,
2997 sh
->assert_file_addr
, (u8
*)file
, 80);
3001 if (sh
->assert_exp_addr
!= 0) {
3002 error
= brcmf_sdiod_ramrw(bus
->sdiodev
, false,
3003 sh
->assert_exp_addr
, (u8
*)expr
, 80);
3007 sdio_release_host(bus
->sdiodev
->func
[1]);
3009 seq_printf(seq
, "dongle assert: %s:%d: assert(%s)\n",
3010 file
, sh
->assert_line
, expr
);
3014 static int brcmf_sdio_checkdied(struct brcmf_sdio
*bus
)
3017 struct sdpcm_shared sh
;
3019 error
= brcmf_sdio_readshared(bus
, &sh
);
3024 if ((sh
.flags
& SDPCM_SHARED_ASSERT_BUILT
) == 0)
3025 brcmf_dbg(INFO
, "firmware not built with -assert\n");
3026 else if (sh
.flags
& SDPCM_SHARED_ASSERT
)
3027 brcmf_err("assertion in dongle\n");
3029 if (sh
.flags
& SDPCM_SHARED_TRAP
)
3030 brcmf_err("firmware trap in dongle\n");
3035 static int brcmf_sdio_died_dump(struct seq_file
*seq
, struct brcmf_sdio
*bus
)
3038 struct sdpcm_shared sh
;
3040 error
= brcmf_sdio_readshared(bus
, &sh
);
3044 error
= brcmf_sdio_assert_info(seq
, bus
, &sh
);
3048 error
= brcmf_sdio_trap_info(seq
, bus
, &sh
);
3052 error
= brcmf_sdio_dump_console(seq
, bus
, &sh
);
3058 static int brcmf_sdio_forensic_read(struct seq_file
*seq
, void *data
)
3060 struct brcmf_bus
*bus_if
= dev_get_drvdata(seq
->private);
3061 struct brcmf_sdio
*bus
= bus_if
->bus_priv
.sdio
->bus
;
3063 return brcmf_sdio_died_dump(seq
, bus
);
3066 static int brcmf_debugfs_sdio_count_read(struct seq_file
*seq
, void *data
)
3068 struct brcmf_bus
*bus_if
= dev_get_drvdata(seq
->private);
3069 struct brcmf_sdio_dev
*sdiodev
= bus_if
->bus_priv
.sdio
;
3070 struct brcmf_sdio_count
*sdcnt
= &sdiodev
->bus
->sdcnt
;
3073 "intrcount: %u\nlastintrs: %u\n"
3074 "pollcnt: %u\nregfails: %u\n"
3075 "tx_sderrs: %u\nfcqueued: %u\n"
3076 "rxrtx: %u\nrx_toolong: %u\n"
3077 "rxc_errors: %u\nrx_hdrfail: %u\n"
3078 "rx_badhdr: %u\nrx_badseq: %u\n"
3079 "fc_rcvd: %u\nfc_xoff: %u\n"
3080 "fc_xon: %u\nrxglomfail: %u\n"
3081 "rxglomframes: %u\nrxglompkts: %u\n"
3082 "f2rxhdrs: %u\nf2rxdata: %u\n"
3083 "f2txdata: %u\nf1regdata: %u\n"
3084 "tickcnt: %u\ntx_ctlerrs: %lu\n"
3085 "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n"
3086 "rx_ctlpkts: %lu\nrx_readahead: %lu\n",
3087 sdcnt
->intrcount
, sdcnt
->lastintrs
,
3088 sdcnt
->pollcnt
, sdcnt
->regfails
,
3089 sdcnt
->tx_sderrs
, sdcnt
->fcqueued
,
3090 sdcnt
->rxrtx
, sdcnt
->rx_toolong
,
3091 sdcnt
->rxc_errors
, sdcnt
->rx_hdrfail
,
3092 sdcnt
->rx_badhdr
, sdcnt
->rx_badseq
,
3093 sdcnt
->fc_rcvd
, sdcnt
->fc_xoff
,
3094 sdcnt
->fc_xon
, sdcnt
->rxglomfail
,
3095 sdcnt
->rxglomframes
, sdcnt
->rxglompkts
,
3096 sdcnt
->f2rxhdrs
, sdcnt
->f2rxdata
,
3097 sdcnt
->f2txdata
, sdcnt
->f1regdata
,
3098 sdcnt
->tickcnt
, sdcnt
->tx_ctlerrs
,
3099 sdcnt
->tx_ctlpkts
, sdcnt
->rx_ctlerrs
,
3100 sdcnt
->rx_ctlpkts
, sdcnt
->rx_readahead_cnt
);
3105 static void brcmf_sdio_debugfs_create(struct brcmf_sdio
*bus
)
3107 struct brcmf_pub
*drvr
= bus
->sdiodev
->bus_if
->drvr
;
3108 struct dentry
*dentry
= brcmf_debugfs_get_devdir(drvr
);
3110 if (IS_ERR_OR_NULL(dentry
))
3113 bus
->console_interval
= BRCMF_CONSOLE
;
3115 brcmf_debugfs_add_entry(drvr
, "forensics", brcmf_sdio_forensic_read
);
3116 brcmf_debugfs_add_entry(drvr
, "counters",
3117 brcmf_debugfs_sdio_count_read
);
3118 debugfs_create_u32("console_interval", 0644, dentry
,
3119 &bus
->console_interval
);
3122 static int brcmf_sdio_checkdied(struct brcmf_sdio
*bus
)
3127 static void brcmf_sdio_debugfs_create(struct brcmf_sdio
*bus
)
3133 brcmf_sdio_bus_rxctl(struct device
*dev
, unsigned char *msg
, uint msglen
)
3139 struct brcmf_bus
*bus_if
= dev_get_drvdata(dev
);
3140 struct brcmf_sdio_dev
*sdiodev
= bus_if
->bus_priv
.sdio
;
3141 struct brcmf_sdio
*bus
= sdiodev
->bus
;
3143 brcmf_dbg(TRACE
, "Enter\n");
3144 if (sdiodev
->state
!= BRCMF_SDIOD_DATA
)
3147 /* Wait until control frame is available */
3148 timeleft
= brcmf_sdio_dcmd_resp_wait(bus
, &bus
->rxlen
, &pending
);
3150 spin_lock_bh(&bus
->rxctl_lock
);
3152 memcpy(msg
, bus
->rxctl
, min(msglen
, rxlen
));
3154 buf
= bus
->rxctl_orig
;
3155 bus
->rxctl_orig
= NULL
;
3157 spin_unlock_bh(&bus
->rxctl_lock
);
3161 brcmf_dbg(CTL
, "resumed on rxctl frame, got %d expected %d\n",
3163 } else if (timeleft
== 0) {
3164 brcmf_err("resumed on timeout\n");
3165 brcmf_sdio_checkdied(bus
);
3166 } else if (pending
) {
3167 brcmf_dbg(CTL
, "cancelled\n");
3168 return -ERESTARTSYS
;
3170 brcmf_dbg(CTL
, "resumed for unknown reason?\n");
3171 brcmf_sdio_checkdied(bus
);
3175 bus
->sdcnt
.rx_ctlpkts
++;
3177 bus
->sdcnt
.rx_ctlerrs
++;
3179 return rxlen
? (int)rxlen
: -ETIMEDOUT
;
3184 brcmf_sdio_verifymemory(struct brcmf_sdio_dev
*sdiodev
, u32 ram_addr
,
3185 u8
*ram_data
, uint ram_sz
)
3194 /* read back and verify */
3195 brcmf_dbg(INFO
, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr
,
3197 ram_cmp
= kmalloc(MEMBLOCK
, GFP_KERNEL
);
3198 /* do not proceed while no memory but */
3204 while (offset
< ram_sz
) {
3205 len
= ((offset
+ MEMBLOCK
) < ram_sz
) ? MEMBLOCK
:
3207 err
= brcmf_sdiod_ramrw(sdiodev
, false, address
, ram_cmp
, len
);
3209 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3213 } else if (memcmp(ram_cmp
, &ram_data
[offset
], len
)) {
3214 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n",
3229 brcmf_sdio_verifymemory(struct brcmf_sdio_dev
*sdiodev
, u32 ram_addr
,
3230 u8
*ram_data
, uint ram_sz
)
3236 static int brcmf_sdio_download_code_file(struct brcmf_sdio
*bus
,
3237 const struct firmware
*fw
)
3241 brcmf_dbg(TRACE
, "Enter\n");
3243 err
= brcmf_sdiod_ramrw(bus
->sdiodev
, true, bus
->ci
->rambase
,
3244 (u8
*)fw
->data
, fw
->size
);
3246 brcmf_err("error %d on writing %d membytes at 0x%08x\n",
3247 err
, (int)fw
->size
, bus
->ci
->rambase
);
3248 else if (!brcmf_sdio_verifymemory(bus
->sdiodev
, bus
->ci
->rambase
,
3249 (u8
*)fw
->data
, fw
->size
))
3255 static int brcmf_sdio_download_nvram(struct brcmf_sdio
*bus
,
3256 void *vars
, u32 varsz
)
3261 brcmf_dbg(TRACE
, "Enter\n");
3263 address
= bus
->ci
->ramsize
- varsz
+ bus
->ci
->rambase
;
3264 err
= brcmf_sdiod_ramrw(bus
->sdiodev
, true, address
, vars
, varsz
);
3266 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
3267 err
, varsz
, address
);
3268 else if (!brcmf_sdio_verifymemory(bus
->sdiodev
, address
, vars
, varsz
))
3274 static int brcmf_sdio_download_firmware(struct brcmf_sdio
*bus
,
3275 const struct firmware
*fw
,
3276 void *nvram
, u32 nvlen
)
3281 sdio_claim_host(bus
->sdiodev
->func
[1]);
3282 brcmf_sdio_clkctl(bus
, CLK_AVAIL
, false);
3284 rstvec
= get_unaligned_le32(fw
->data
);
3285 brcmf_dbg(SDIO
, "firmware rstvec: %x\n", rstvec
);
3287 bcmerror
= brcmf_sdio_download_code_file(bus
, fw
);
3288 release_firmware(fw
);
3290 brcmf_err("dongle image file download failed\n");
3291 brcmf_fw_nvram_free(nvram
);
3295 bcmerror
= brcmf_sdio_download_nvram(bus
, nvram
, nvlen
);
3296 brcmf_fw_nvram_free(nvram
);
3298 brcmf_err("dongle nvram file download failed\n");
3302 /* Take arm out of reset */
3303 if (!brcmf_chip_set_active(bus
->ci
, rstvec
)) {
3304 brcmf_err("error getting out of ARM core reset\n");
3308 /* Allow full data communication using DPC from now on. */
3309 brcmf_sdiod_change_state(bus
->sdiodev
, BRCMF_SDIOD_DATA
);
3313 brcmf_sdio_clkctl(bus
, CLK_SDONLY
, false);
3314 sdio_release_host(bus
->sdiodev
->func
[1]);
3318 static void brcmf_sdio_sr_init(struct brcmf_sdio
*bus
)
3323 brcmf_dbg(TRACE
, "Enter\n");
3325 val
= brcmf_sdiod_regrb(bus
->sdiodev
, SBSDIO_FUNC1_WAKEUPCTRL
, &err
);
3327 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
3331 val
|= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT
;
3332 brcmf_sdiod_regwb(bus
->sdiodev
, SBSDIO_FUNC1_WAKEUPCTRL
, val
, &err
);
3334 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
3338 /* Add CMD14 Support */
3339 brcmf_sdiod_regwb(bus
->sdiodev
, SDIO_CCCR_BRCM_CARDCAP
,
3340 (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT
|
3341 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT
),
3344 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
3348 brcmf_sdiod_regwb(bus
->sdiodev
, SBSDIO_FUNC1_CHIPCLKCSR
,
3349 SBSDIO_FORCE_HT
, &err
);
3351 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
3356 bus
->sr_enabled
= true;
3357 brcmf_dbg(INFO
, "SR enabled\n");
3360 /* enable KSO bit */
3361 static int brcmf_sdio_kso_init(struct brcmf_sdio
*bus
)
3366 brcmf_dbg(TRACE
, "Enter\n");
3368 /* KSO bit added in SDIO core rev 12 */
3369 if (brcmf_chip_get_core(bus
->ci
, BCMA_CORE_SDIO_DEV
)->rev
< 12)
3372 val
= brcmf_sdiod_regrb(bus
->sdiodev
, SBSDIO_FUNC1_SLEEPCSR
, &err
);
3374 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
3378 if (!(val
& SBSDIO_FUNC1_SLEEPCSR_KSO_MASK
)) {
3379 val
|= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN
<<
3380 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT
);
3381 brcmf_sdiod_regwb(bus
->sdiodev
, SBSDIO_FUNC1_SLEEPCSR
,
3384 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
3393 static int brcmf_sdio_bus_preinit(struct device
*dev
)
3395 struct brcmf_bus
*bus_if
= dev_get_drvdata(dev
);
3396 struct brcmf_sdio_dev
*sdiodev
= bus_if
->bus_priv
.sdio
;
3397 struct brcmf_sdio
*bus
= sdiodev
->bus
;
3402 /* the commands below use the terms tx and rx from
3403 * a device perspective, ie. bus:txglom affects the
3404 * bus transfers from device to host.
3406 if (brcmf_chip_get_core(bus
->ci
, BCMA_CORE_SDIO_DEV
)->rev
< 12) {
3407 /* for sdio core rev < 12, disable txgloming */
3409 err
= brcmf_iovar_data_set(dev
, "bus:txglom", &value
,
3412 /* otherwise, set txglomalign */
3413 value
= sdiodev
->settings
->bus
.sdio
.sd_sgentry_align
;
3414 /* SDIO ADMA requires at least 32 bit alignment */
3415 value
= max_t(u32
, value
, 4);
3416 err
= brcmf_iovar_data_set(dev
, "bus:txglomalign", &value
,
3423 bus
->tx_hdrlen
= SDPCM_HWHDR_LEN
+ SDPCM_SWHDR_LEN
;
3424 if (sdiodev
->sg_support
) {
3425 bus
->txglom
= false;
3427 pad_size
= bus
->sdiodev
->func
[2]->cur_blksize
<< 1;
3428 err
= brcmf_iovar_data_set(bus
->sdiodev
->dev
, "bus:rxglom",
3429 &value
, sizeof(u32
));
3431 /* bus:rxglom is allowed to fail */
3435 bus
->tx_hdrlen
+= SDPCM_HWEXT_LEN
;
3438 brcmf_bus_add_txhdrlen(bus
->sdiodev
->dev
, bus
->tx_hdrlen
);
3444 static size_t brcmf_sdio_bus_get_ramsize(struct device
*dev
)
3446 struct brcmf_bus
*bus_if
= dev_get_drvdata(dev
);
3447 struct brcmf_sdio_dev
*sdiodev
= bus_if
->bus_priv
.sdio
;
3448 struct brcmf_sdio
*bus
= sdiodev
->bus
;
3450 return bus
->ci
->ramsize
- bus
->ci
->srsize
;
3453 static int brcmf_sdio_bus_get_memdump(struct device
*dev
, void *data
,
3456 struct brcmf_bus
*bus_if
= dev_get_drvdata(dev
);
3457 struct brcmf_sdio_dev
*sdiodev
= bus_if
->bus_priv
.sdio
;
3458 struct brcmf_sdio
*bus
= sdiodev
->bus
;
3464 brcmf_dbg(INFO
, "dump at 0x%08x: size=%zu\n", bus
->ci
->rambase
,
3467 address
= bus
->ci
->rambase
;
3469 sdio_claim_host(sdiodev
->func
[1]);
3470 while (offset
< mem_size
) {
3471 len
= ((offset
+ MEMBLOCK
) < mem_size
) ? MEMBLOCK
:
3473 err
= brcmf_sdiod_ramrw(sdiodev
, false, address
, data
, len
);
3475 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3485 sdio_release_host(sdiodev
->func
[1]);
3489 void brcmf_sdio_trigger_dpc(struct brcmf_sdio
*bus
)
3491 if (!bus
->dpc_triggered
) {
3492 bus
->dpc_triggered
= true;
3493 queue_work(bus
->brcmf_wq
, &bus
->datawork
);
3497 void brcmf_sdio_isr(struct brcmf_sdio
*bus
)
3499 brcmf_dbg(TRACE
, "Enter\n");
3502 brcmf_err("bus is null pointer, exiting\n");
3506 /* Count the interrupt call */
3507 bus
->sdcnt
.intrcount
++;
3509 atomic_set(&bus
->ipend
, 1);
3511 if (brcmf_sdio_intr_rstatus(bus
)) {
3512 brcmf_err("failed backplane access\n");
3515 /* Disable additional interrupts (is this needed now)? */
3517 brcmf_err("isr w/o interrupt configured!\n");
3519 bus
->dpc_triggered
= true;
3520 queue_work(bus
->brcmf_wq
, &bus
->datawork
);
3523 static void brcmf_sdio_bus_watchdog(struct brcmf_sdio
*bus
)
3525 brcmf_dbg(TIMER
, "Enter\n");
3527 /* Poll period: check device if appropriate. */
3528 if (!bus
->sr_enabled
&&
3529 bus
->poll
&& (++bus
->polltick
>= bus
->pollrate
)) {
3532 /* Reset poll tick */
3535 /* Check device if no interrupts */
3537 (bus
->sdcnt
.intrcount
== bus
->sdcnt
.lastintrs
)) {
3539 if (!bus
->dpc_triggered
) {
3542 sdio_claim_host(bus
->sdiodev
->func
[1]);
3543 devpend
= brcmf_sdiod_regrb(bus
->sdiodev
,
3546 sdio_release_host(bus
->sdiodev
->func
[1]);
3547 intstatus
= devpend
& (INTR_STATUS_FUNC1
|
3551 /* If there is something, make like the ISR and
3554 bus
->sdcnt
.pollcnt
++;
3555 atomic_set(&bus
->ipend
, 1);
3557 bus
->dpc_triggered
= true;
3558 queue_work(bus
->brcmf_wq
, &bus
->datawork
);
3562 /* Update interrupt tracking */
3563 bus
->sdcnt
.lastintrs
= bus
->sdcnt
.intrcount
;
3566 /* Poll for console output periodically */
3567 if (bus
->sdiodev
->state
== BRCMF_SDIOD_DATA
&& BRCMF_FWCON_ON() &&
3568 bus
->console_interval
!= 0) {
3569 bus
->console
.count
+= jiffies_to_msecs(BRCMF_WD_POLL
);
3570 if (bus
->console
.count
>= bus
->console_interval
) {
3571 bus
->console
.count
-= bus
->console_interval
;
3572 sdio_claim_host(bus
->sdiodev
->func
[1]);
3573 /* Make sure backplane clock is on */
3574 brcmf_sdio_bus_sleep(bus
, false, false);
3575 if (brcmf_sdio_readconsole(bus
) < 0)
3577 bus
->console_interval
= 0;
3578 sdio_release_host(bus
->sdiodev
->func
[1]);
3583 /* On idle timeout clear activity flag and/or turn off clock */
3584 if (!bus
->dpc_triggered
) {
3586 if ((!bus
->dpc_running
) && (bus
->idletime
> 0) &&
3587 (bus
->clkstate
== CLK_AVAIL
)) {
3589 if (bus
->idlecount
> bus
->idletime
) {
3590 brcmf_dbg(SDIO
, "idle\n");
3591 sdio_claim_host(bus
->sdiodev
->func
[1]);
3592 brcmf_sdio_wd_timer(bus
, false);
3594 brcmf_sdio_bus_sleep(bus
, true, false);
3595 sdio_release_host(bus
->sdiodev
->func
[1]);
3605 static void brcmf_sdio_dataworker(struct work_struct
*work
)
3607 struct brcmf_sdio
*bus
= container_of(work
, struct brcmf_sdio
,
3610 bus
->dpc_running
= true;
3612 while (ACCESS_ONCE(bus
->dpc_triggered
)) {
3613 bus
->dpc_triggered
= false;
3614 brcmf_sdio_dpc(bus
);
3617 bus
->dpc_running
= false;
3618 if (brcmf_sdiod_freezing(bus
->sdiodev
)) {
3619 brcmf_sdiod_change_state(bus
->sdiodev
, BRCMF_SDIOD_DOWN
);
3620 brcmf_sdiod_try_freeze(bus
->sdiodev
);
3621 brcmf_sdiod_change_state(bus
->sdiodev
, BRCMF_SDIOD_DATA
);
3626 brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev
*sdiodev
,
3627 struct brcmf_chip
*ci
, u32 drivestrength
)
3629 const struct sdiod_drive_str
*str_tab
= NULL
;
3633 u32 drivestrength_sel
= 0;
3637 if (!(ci
->cc_caps
& CC_CAP_PMU
))
3640 switch (SDIOD_DRVSTR_KEY(ci
->chip
, ci
->pmurev
)) {
3641 case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID
, 12):
3642 str_tab
= sdiod_drvstr_tab1_1v8
;
3643 str_mask
= 0x00003800;
3646 case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID
, 17):
3647 str_tab
= sdiod_drvstr_tab6_1v8
;
3648 str_mask
= 0x00001800;
3651 case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID
, 17):
3652 /* note: 43143 does not support tristate */
3653 i
= ARRAY_SIZE(sdiod_drvstr_tab2_3v3
) - 1;
3654 if (drivestrength
>= sdiod_drvstr_tab2_3v3
[i
].strength
) {
3655 str_tab
= sdiod_drvstr_tab2_3v3
;
3656 str_mask
= 0x00000007;
3659 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n",
3660 ci
->name
, drivestrength
);
3662 case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID
, 13):
3663 str_tab
= sdiod_drive_strength_tab5_1v8
;
3664 str_mask
= 0x00003800;
3668 brcmf_dbg(INFO
, "No SDIO driver strength init needed for chip %s rev %d pmurev %d\n",
3669 ci
->name
, ci
->chiprev
, ci
->pmurev
);
3673 if (str_tab
!= NULL
) {
3674 struct brcmf_core
*pmu
= brcmf_chip_get_pmu(ci
);
3676 for (i
= 0; str_tab
[i
].strength
!= 0; i
++) {
3677 if (drivestrength
>= str_tab
[i
].strength
) {
3678 drivestrength_sel
= str_tab
[i
].sel
;
3682 addr
= CORE_CC_REG(pmu
->base
, chipcontrol_addr
);
3683 brcmf_sdiod_regwl(sdiodev
, addr
, 1, NULL
);
3684 cc_data_temp
= brcmf_sdiod_regrl(sdiodev
, addr
, NULL
);
3685 cc_data_temp
&= ~str_mask
;
3686 drivestrength_sel
<<= str_shift
;
3687 cc_data_temp
|= drivestrength_sel
;
3688 brcmf_sdiod_regwl(sdiodev
, addr
, cc_data_temp
, NULL
);
3690 brcmf_dbg(INFO
, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n",
3691 str_tab
[i
].strength
, drivestrength
, cc_data_temp
);
3695 static int brcmf_sdio_buscoreprep(void *ctx
)
3697 struct brcmf_sdio_dev
*sdiodev
= ctx
;
3701 /* Try forcing SDIO core to do ALPAvail request only */
3702 clkset
= SBSDIO_FORCE_HW_CLKREQ_OFF
| SBSDIO_ALP_AVAIL_REQ
;
3703 brcmf_sdiod_regwb(sdiodev
, SBSDIO_FUNC1_CHIPCLKCSR
, clkset
, &err
);
3705 brcmf_err("error writing for HT off\n");
3709 /* If register supported, wait for ALPAvail and then force ALP */
3710 /* This may take up to 15 milliseconds */
3711 clkval
= brcmf_sdiod_regrb(sdiodev
,
3712 SBSDIO_FUNC1_CHIPCLKCSR
, NULL
);
3714 if ((clkval
& ~SBSDIO_AVBITS
) != clkset
) {
3715 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
3720 SPINWAIT(((clkval
= brcmf_sdiod_regrb(sdiodev
,
3721 SBSDIO_FUNC1_CHIPCLKCSR
, NULL
)),
3722 !SBSDIO_ALPAV(clkval
)),
3723 PMU_MAX_TRANSITION_DLY
);
3724 if (!SBSDIO_ALPAV(clkval
)) {
3725 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n",
3730 clkset
= SBSDIO_FORCE_HW_CLKREQ_OFF
| SBSDIO_FORCE_ALP
;
3731 brcmf_sdiod_regwb(sdiodev
, SBSDIO_FUNC1_CHIPCLKCSR
, clkset
, &err
);
3734 /* Also, disable the extra SDIO pull-ups */
3735 brcmf_sdiod_regwb(sdiodev
, SBSDIO_FUNC1_SDIOPULLUP
, 0, NULL
);
3740 static void brcmf_sdio_buscore_activate(void *ctx
, struct brcmf_chip
*chip
,
3743 struct brcmf_sdio_dev
*sdiodev
= ctx
;
3744 struct brcmf_core
*core
;
3747 /* clear all interrupts */
3748 core
= brcmf_chip_get_core(chip
, BCMA_CORE_SDIO_DEV
);
3749 reg_addr
= core
->base
+ offsetof(struct sdpcmd_regs
, intstatus
);
3750 brcmf_sdiod_regwl(sdiodev
, reg_addr
, 0xFFFFFFFF, NULL
);
3753 /* Write reset vector to address 0 */
3754 brcmf_sdiod_ramrw(sdiodev
, true, 0, (void *)&rstvec
,
3758 static u32
brcmf_sdio_buscore_read32(void *ctx
, u32 addr
)
3760 struct brcmf_sdio_dev
*sdiodev
= ctx
;
3763 val
= brcmf_sdiod_regrl(sdiodev
, addr
, NULL
);
3764 if (sdiodev
->func
[0]->device
== SDIO_DEVICE_ID_BROADCOM_4335_4339
&&
3765 addr
== CORE_CC_REG(SI_ENUM_BASE
, chipid
)) {
3766 rev
= (val
& CID_REV_MASK
) >> CID_REV_SHIFT
;
3768 val
&= ~CID_ID_MASK
;
3769 val
|= BRCM_CC_4339_CHIP_ID
;
3775 static void brcmf_sdio_buscore_write32(void *ctx
, u32 addr
, u32 val
)
3777 struct brcmf_sdio_dev
*sdiodev
= ctx
;
3779 brcmf_sdiod_regwl(sdiodev
, addr
, val
, NULL
);
3782 static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops
= {
3783 .prepare
= brcmf_sdio_buscoreprep
,
3784 .activate
= brcmf_sdio_buscore_activate
,
3785 .read32
= brcmf_sdio_buscore_read32
,
3786 .write32
= brcmf_sdio_buscore_write32
,
3790 brcmf_sdio_probe_attach(struct brcmf_sdio
*bus
)
3792 struct brcmf_sdio_dev
*sdiodev
;
3799 sdiodev
= bus
->sdiodev
;
3800 sdio_claim_host(sdiodev
->func
[1]);
3802 pr_debug("F1 signature read @0x18000000=0x%4x\n",
3803 brcmf_sdiod_regrl(sdiodev
, SI_ENUM_BASE
, NULL
));
3806 * Force PLL off until brcmf_chip_attach()
3807 * programs PLL control regs
3810 brcmf_sdiod_regwb(sdiodev
, SBSDIO_FUNC1_CHIPCLKCSR
,
3811 BRCMF_INIT_CLKCTL1
, &err
);
3813 clkctl
= brcmf_sdiod_regrb(sdiodev
,
3814 SBSDIO_FUNC1_CHIPCLKCSR
, &err
);
3816 if (err
|| ((clkctl
& ~SBSDIO_AVBITS
) != BRCMF_INIT_CLKCTL1
)) {
3817 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
3818 err
, BRCMF_INIT_CLKCTL1
, clkctl
);
3822 bus
->ci
= brcmf_chip_attach(sdiodev
, &brcmf_sdio_buscore_ops
);
3823 if (IS_ERR(bus
->ci
)) {
3824 brcmf_err("brcmf_chip_attach failed!\n");
3828 sdiodev
->settings
= brcmf_get_module_param(sdiodev
->dev
,
3832 if (!sdiodev
->settings
) {
3833 brcmf_err("Failed to get device parameters\n");
3836 /* platform specific configuration:
3837 * alignments must be at least 4 bytes for ADMA
3839 bus
->head_align
= ALIGNMENT
;
3840 bus
->sgentry_align
= ALIGNMENT
;
3841 if (sdiodev
->settings
->bus
.sdio
.sd_head_align
> ALIGNMENT
)
3842 bus
->head_align
= sdiodev
->settings
->bus
.sdio
.sd_head_align
;
3843 if (sdiodev
->settings
->bus
.sdio
.sd_sgentry_align
> ALIGNMENT
)
3844 bus
->sgentry_align
=
3845 sdiodev
->settings
->bus
.sdio
.sd_sgentry_align
;
3847 /* allocate scatter-gather table. sg support
3848 * will be disabled upon allocation failure.
3850 brcmf_sdiod_sgtable_alloc(sdiodev
);
3852 #ifdef CONFIG_PM_SLEEP
3853 /* wowl can be supported when KEEP_POWER is true and (WAKE_SDIO_IRQ
3854 * is true or when platform data OOB irq is true).
3856 if ((sdio_get_host_pm_caps(sdiodev
->func
[1]) & MMC_PM_KEEP_POWER
) &&
3857 ((sdio_get_host_pm_caps(sdiodev
->func
[1]) & MMC_PM_WAKE_SDIO_IRQ
) ||
3858 (sdiodev
->settings
->bus
.sdio
.oob_irq_supported
)))
3859 sdiodev
->bus_if
->wowl_supported
= true;
3862 if (brcmf_sdio_kso_init(bus
)) {
3863 brcmf_err("error enabling KSO\n");
3867 if (sdiodev
->settings
->bus
.sdio
.drive_strength
)
3868 drivestrength
= sdiodev
->settings
->bus
.sdio
.drive_strength
;
3870 drivestrength
= DEFAULT_SDIO_DRIVE_STRENGTH
;
3871 brcmf_sdio_drivestrengthinit(sdiodev
, bus
->ci
, drivestrength
);
3873 /* Set card control so an SDIO card reset does a WLAN backplane reset */
3874 reg_val
= brcmf_sdiod_regrb(sdiodev
, SDIO_CCCR_BRCM_CARDCTRL
, &err
);
3878 reg_val
|= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET
;
3880 brcmf_sdiod_regwb(sdiodev
, SDIO_CCCR_BRCM_CARDCTRL
, reg_val
, &err
);
3884 /* set PMUControl so a backplane reset does PMU state reload */
3885 reg_addr
= CORE_CC_REG(brcmf_chip_get_pmu(bus
->ci
)->base
, pmucontrol
);
3886 reg_val
= brcmf_sdiod_regrl(sdiodev
, reg_addr
, &err
);
3890 reg_val
|= (BCMA_CC_PMU_CTL_RES_RELOAD
<< BCMA_CC_PMU_CTL_RES_SHIFT
);
3892 brcmf_sdiod_regwl(sdiodev
, reg_addr
, reg_val
, &err
);
3896 sdio_release_host(sdiodev
->func
[1]);
3898 brcmu_pktq_init(&bus
->txq
, (PRIOMASK
+ 1), TXQLEN
);
3900 /* allocate header buffer */
3901 bus
->hdrbuf
= kzalloc(MAX_HDR_READ
+ bus
->head_align
, GFP_KERNEL
);
3904 /* Locate an appropriately-aligned portion of hdrbuf */
3905 bus
->rxhdr
= (u8
*) roundup((unsigned long)&bus
->hdrbuf
[0],
3908 /* Set the poll and/or interrupt flags */
3917 sdio_release_host(sdiodev
->func
[1]);
3922 brcmf_sdio_watchdog_thread(void *data
)
3924 struct brcmf_sdio
*bus
= (struct brcmf_sdio
*)data
;
3927 allow_signal(SIGTERM
);
3928 /* Run until signal received */
3929 brcmf_sdiod_freezer_count(bus
->sdiodev
);
3931 if (kthread_should_stop())
3933 brcmf_sdiod_freezer_uncount(bus
->sdiodev
);
3934 wait
= wait_for_completion_interruptible(&bus
->watchdog_wait
);
3935 brcmf_sdiod_freezer_count(bus
->sdiodev
);
3936 brcmf_sdiod_try_freeze(bus
->sdiodev
);
3938 brcmf_sdio_bus_watchdog(bus
);
3939 /* Count the tick for reference */
3940 bus
->sdcnt
.tickcnt
++;
3941 reinit_completion(&bus
->watchdog_wait
);
3949 brcmf_sdio_watchdog(unsigned long data
)
3951 struct brcmf_sdio
*bus
= (struct brcmf_sdio
*)data
;
3953 if (bus
->watchdog_tsk
) {
3954 complete(&bus
->watchdog_wait
);
3955 /* Reschedule the watchdog */
3957 mod_timer(&bus
->timer
,
3958 jiffies
+ BRCMF_WD_POLL
);
3962 static const struct brcmf_bus_ops brcmf_sdio_bus_ops
= {
3963 .stop
= brcmf_sdio_bus_stop
,
3964 .preinit
= brcmf_sdio_bus_preinit
,
3965 .txdata
= brcmf_sdio_bus_txdata
,
3966 .txctl
= brcmf_sdio_bus_txctl
,
3967 .rxctl
= brcmf_sdio_bus_rxctl
,
3968 .gettxq
= brcmf_sdio_bus_gettxq
,
3969 .wowl_config
= brcmf_sdio_wowl_config
,
3970 .get_ramsize
= brcmf_sdio_bus_get_ramsize
,
3971 .get_memdump
= brcmf_sdio_bus_get_memdump
,
3974 static void brcmf_sdio_firmware_callback(struct device
*dev
,
3975 const struct firmware
*code
,
3976 void *nvram
, u32 nvram_len
)
3978 struct brcmf_bus
*bus_if
= dev_get_drvdata(dev
);
3979 struct brcmf_sdio_dev
*sdiodev
= bus_if
->bus_priv
.sdio
;
3980 struct brcmf_sdio
*bus
= sdiodev
->bus
;
3984 brcmf_dbg(TRACE
, "Enter: dev=%s\n", dev_name(dev
));
3989 /* try to download image and nvram to the dongle */
3990 bus
->alp_only
= true;
3991 err
= brcmf_sdio_download_firmware(bus
, code
, nvram
, nvram_len
);
3994 bus
->alp_only
= false;
3996 /* Start the watchdog timer */
3997 bus
->sdcnt
.tickcnt
= 0;
3998 brcmf_sdio_wd_timer(bus
, true);
4000 sdio_claim_host(sdiodev
->func
[1]);
4002 /* Make sure backplane clock is on, needed to generate F2 interrupt */
4003 brcmf_sdio_clkctl(bus
, CLK_AVAIL
, false);
4004 if (bus
->clkstate
!= CLK_AVAIL
)
4007 /* Force clocks on backplane to be sure F2 interrupt propagates */
4008 saveclk
= brcmf_sdiod_regrb(sdiodev
, SBSDIO_FUNC1_CHIPCLKCSR
, &err
);
4010 brcmf_sdiod_regwb(sdiodev
, SBSDIO_FUNC1_CHIPCLKCSR
,
4011 (saveclk
| SBSDIO_FORCE_HT
), &err
);
4014 brcmf_err("Failed to force clock for F2: err %d\n", err
);
4018 /* Enable function 2 (frame transfers) */
4019 w_sdreg32(bus
, SDPCM_PROT_VERSION
<< SMB_DATA_VERSION_SHIFT
,
4020 offsetof(struct sdpcmd_regs
, tosbmailboxdata
));
4021 err
= sdio_enable_func(sdiodev
->func
[SDIO_FUNC_2
]);
4024 brcmf_dbg(INFO
, "enable F2: err=%d\n", err
);
4026 /* If F2 successfully enabled, set core and enable interrupts */
4028 /* Set up the interrupt mask and enable interrupts */
4029 bus
->hostintmask
= HOSTINTMASK
;
4030 w_sdreg32(bus
, bus
->hostintmask
,
4031 offsetof(struct sdpcmd_regs
, hostintmask
));
4033 brcmf_sdiod_regwb(sdiodev
, SBSDIO_WATERMARK
, 8, &err
);
4035 /* Disable F2 again */
4036 sdio_disable_func(sdiodev
->func
[SDIO_FUNC_2
]);
4040 if (brcmf_chip_sr_capable(bus
->ci
)) {
4041 brcmf_sdio_sr_init(bus
);
4043 /* Restore previous clock setting */
4044 brcmf_sdiod_regwb(sdiodev
, SBSDIO_FUNC1_CHIPCLKCSR
,
4049 err
= brcmf_sdiod_intr_register(sdiodev
);
4051 brcmf_err("intr register failed:%d\n", err
);
4054 /* If we didn't come up, turn off backplane clock */
4056 brcmf_sdio_clkctl(bus
, CLK_NONE
, false);
4058 sdio_release_host(sdiodev
->func
[1]);
4060 err
= brcmf_bus_start(dev
);
4062 brcmf_err("dongle is not responding\n");
4068 sdio_release_host(sdiodev
->func
[1]);
4070 brcmf_dbg(TRACE
, "failed: dev=%s, err=%d\n", dev_name(dev
), err
);
4071 device_release_driver(dev
);
4074 struct brcmf_sdio
*brcmf_sdio_probe(struct brcmf_sdio_dev
*sdiodev
)
4077 struct brcmf_sdio
*bus
;
4078 struct workqueue_struct
*wq
;
4080 brcmf_dbg(TRACE
, "Enter\n");
4082 /* Allocate private bus interface state */
4083 bus
= kzalloc(sizeof(struct brcmf_sdio
), GFP_ATOMIC
);
4087 bus
->sdiodev
= sdiodev
;
4089 skb_queue_head_init(&bus
->glom
);
4090 bus
->txbound
= BRCMF_TXBOUND
;
4091 bus
->rxbound
= BRCMF_RXBOUND
;
4092 bus
->txminmax
= BRCMF_TXMINMAX
;
4093 bus
->tx_seq
= SDPCM_SEQ_WRAP
- 1;
4095 /* single-threaded workqueue */
4096 wq
= alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM
,
4097 dev_name(&sdiodev
->func
[1]->dev
));
4099 brcmf_err("insufficient memory to create txworkqueue\n");
4102 brcmf_sdiod_freezer_count(sdiodev
);
4103 INIT_WORK(&bus
->datawork
, brcmf_sdio_dataworker
);
4106 /* attempt to attach to the dongle */
4107 if (!(brcmf_sdio_probe_attach(bus
))) {
4108 brcmf_err("brcmf_sdio_probe_attach failed\n");
4112 spin_lock_init(&bus
->rxctl_lock
);
4113 spin_lock_init(&bus
->txq_lock
);
4114 init_waitqueue_head(&bus
->ctrl_wait
);
4115 init_waitqueue_head(&bus
->dcmd_resp_wait
);
4117 /* Set up the watchdog timer */
4118 init_timer(&bus
->timer
);
4119 bus
->timer
.data
= (unsigned long)bus
;
4120 bus
->timer
.function
= brcmf_sdio_watchdog
;
4122 /* Initialize watchdog thread */
4123 init_completion(&bus
->watchdog_wait
);
4124 bus
->watchdog_tsk
= kthread_run(brcmf_sdio_watchdog_thread
,
4125 bus
, "brcmf_wdog/%s",
4126 dev_name(&sdiodev
->func
[1]->dev
));
4127 if (IS_ERR(bus
->watchdog_tsk
)) {
4128 pr_warn("brcmf_watchdog thread failed to start\n");
4129 bus
->watchdog_tsk
= NULL
;
4131 /* Initialize DPC thread */
4132 bus
->dpc_triggered
= false;
4133 bus
->dpc_running
= false;
4135 /* Assign bus interface call back */
4136 bus
->sdiodev
->bus_if
->dev
= bus
->sdiodev
->dev
;
4137 bus
->sdiodev
->bus_if
->ops
= &brcmf_sdio_bus_ops
;
4138 bus
->sdiodev
->bus_if
->chip
= bus
->ci
->chip
;
4139 bus
->sdiodev
->bus_if
->chiprev
= bus
->ci
->chiprev
;
4141 /* default sdio bus header length for tx packet */
4142 bus
->tx_hdrlen
= SDPCM_HWHDR_LEN
+ SDPCM_SWHDR_LEN
;
4144 /* Attach to the common layer, reserve hdr space */
4145 ret
= brcmf_attach(bus
->sdiodev
->dev
, bus
->sdiodev
->settings
);
4147 brcmf_err("brcmf_attach failed\n");
4151 /* allocate scatter-gather table. sg support
4152 * will be disabled upon allocation failure.
4154 brcmf_sdiod_sgtable_alloc(bus
->sdiodev
);
4156 /* Query the F2 block size, set roundup accordingly */
4157 bus
->blocksize
= bus
->sdiodev
->func
[2]->cur_blksize
;
4158 bus
->roundup
= min(max_roundup
, bus
->blocksize
);
4160 /* Allocate buffers */
4161 if (bus
->sdiodev
->bus_if
->maxctl
) {
4162 bus
->sdiodev
->bus_if
->maxctl
+= bus
->roundup
;
4164 roundup((bus
->sdiodev
->bus_if
->maxctl
+ SDPCM_HDRLEN
),
4165 ALIGNMENT
) + bus
->head_align
;
4166 bus
->rxbuf
= kmalloc(bus
->rxblen
, GFP_ATOMIC
);
4167 if (!(bus
->rxbuf
)) {
4168 brcmf_err("rxbuf allocation failed\n");
4173 sdio_claim_host(bus
->sdiodev
->func
[1]);
4175 /* Disable F2 to clear any intermediate frame state on the dongle */
4176 sdio_disable_func(bus
->sdiodev
->func
[SDIO_FUNC_2
]);
4178 bus
->rxflow
= false;
4180 /* Done with backplane-dependent accesses, can drop clock... */
4181 brcmf_sdiod_regwb(bus
->sdiodev
, SBSDIO_FUNC1_CHIPCLKCSR
, 0, NULL
);
4183 sdio_release_host(bus
->sdiodev
->func
[1]);
4185 /* ...and initialize clock/power states */
4186 bus
->clkstate
= CLK_SDONLY
;
4187 bus
->idletime
= BRCMF_IDLE_INTERVAL
;
4188 bus
->idleclock
= BRCMF_IDLE_ACTIVE
;
4191 bus
->sr_enabled
= false;
4193 brcmf_sdio_debugfs_create(bus
);
4194 brcmf_dbg(INFO
, "completed!!\n");
4196 ret
= brcmf_fw_map_chip_to_name(bus
->ci
->chip
, bus
->ci
->chiprev
,
4198 ARRAY_SIZE(brcmf_sdio_fwnames
),
4199 sdiodev
->fw_name
, sdiodev
->nvram_name
);
4203 ret
= brcmf_fw_get_firmwares(sdiodev
->dev
, BRCMF_FW_REQUEST_NVRAM
,
4204 sdiodev
->fw_name
, sdiodev
->nvram_name
,
4205 brcmf_sdio_firmware_callback
);
4207 brcmf_err("async firmware request failed: %d\n", ret
);
4214 brcmf_sdio_remove(bus
);
4218 /* Detach and free everything */
4219 void brcmf_sdio_remove(struct brcmf_sdio
*bus
)
4221 brcmf_dbg(TRACE
, "Enter\n");
4224 /* De-register interrupt handler */
4225 brcmf_sdiod_intr_unregister(bus
->sdiodev
);
4227 brcmf_detach(bus
->sdiodev
->dev
);
4229 cancel_work_sync(&bus
->datawork
);
4231 destroy_workqueue(bus
->brcmf_wq
);
4234 if (bus
->sdiodev
->state
!= BRCMF_SDIOD_NOMEDIUM
) {
4235 sdio_claim_host(bus
->sdiodev
->func
[1]);
4236 brcmf_sdio_wd_timer(bus
, false);
4237 brcmf_sdio_clkctl(bus
, CLK_AVAIL
, false);
4238 /* Leave the device in state where it is
4239 * 'passive'. This is done by resetting all
4243 brcmf_chip_set_passive(bus
->ci
);
4244 brcmf_sdio_clkctl(bus
, CLK_NONE
, false);
4245 sdio_release_host(bus
->sdiodev
->func
[1]);
4247 brcmf_chip_detach(bus
->ci
);
4249 if (bus
->sdiodev
->settings
)
4250 brcmf_release_module_param(bus
->sdiodev
->settings
);
4257 brcmf_dbg(TRACE
, "Disconnected\n");
4260 void brcmf_sdio_wd_timer(struct brcmf_sdio
*bus
, bool active
)
4262 /* Totally stop the timer */
4263 if (!active
&& bus
->wd_active
) {
4264 del_timer_sync(&bus
->timer
);
4265 bus
->wd_active
= false;
4269 /* don't start the wd until fw is loaded */
4270 if (bus
->sdiodev
->state
!= BRCMF_SDIOD_DATA
)
4274 if (!bus
->wd_active
) {
4275 /* Create timer again when watchdog period is
4276 dynamically changed or in the first instance
4278 bus
->timer
.expires
= jiffies
+ BRCMF_WD_POLL
;
4279 add_timer(&bus
->timer
);
4280 bus
->wd_active
= true;
4282 /* Re arm the timer, at last watchdog period */
4283 mod_timer(&bus
->timer
, jiffies
+ BRCMF_WD_POLL
);
4288 int brcmf_sdio_sleep(struct brcmf_sdio
*bus
, bool sleep
)
4292 sdio_claim_host(bus
->sdiodev
->func
[1]);
4293 ret
= brcmf_sdio_bus_sleep(bus
, sleep
, false);
4294 sdio_release_host(bus
->sdiodev
->func
[1]);