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i386: move xen
[linux-2.6/btrfs-unstable.git] / drivers / ata / ahci.c
blobc16820325d7bf127fc1989e3dede84665cc3fed6
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
47
48 #define DRV_NAME "ahci"
49 #define DRV_VERSION "2.3"
50
51
52 enum {
53 AHCI_PCI_BAR = 5,
54 AHCI_MAX_PORTS = 32,
55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
57 AHCI_USE_CLUSTERING = 1,
58 AHCI_MAX_CMDS = 32,
59 AHCI_CMD_SZ = 32,
60 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
61 AHCI_RX_FIS_SZ = 256,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_HDR_SZ = 0x80,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
67 AHCI_RX_FIS_SZ,
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
71 AHCI_CMD_PREFETCH = (1 << 7),
72 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
74
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
76 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
78
79 board_ahci = 0,
80 board_ahci_pi = 1,
81 board_ahci_vt8251 = 2,
82 board_ahci_ign_iferr = 3,
83 board_ahci_sb600 = 4,
84 board_ahci_mv = 5,
85
86 /* global controller registers */
87 HOST_CAP = 0x00, /* host capabilities */
88 HOST_CTL = 0x04, /* global host control */
89 HOST_IRQ_STAT = 0x08, /* interrupt status */
90 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
91 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
92
93 /* HOST_CTL bits */
94 HOST_RESET = (1 << 0), /* reset controller; self-clear */
95 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
96 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
97
98 /* HOST_CAP bits */
99 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
100 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
101 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
102 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
103 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
104 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
105
106 /* registers for each SATA port */
107 PORT_LST_ADDR = 0x00, /* command list DMA addr */
108 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
109 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
110 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
111 PORT_IRQ_STAT = 0x10, /* interrupt status */
112 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
113 PORT_CMD = 0x18, /* port command */
114 PORT_TFDATA = 0x20, /* taskfile data */
115 PORT_SIG = 0x24, /* device TF signature */
116 PORT_CMD_ISSUE = 0x38, /* command issue */
117 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
118 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
119 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
120 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
121 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
122
123 /* PORT_IRQ_{STAT,MASK} bits */
124 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
125 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
126 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
127 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
128 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
129 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
130 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
131 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
132
133 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
134 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
135 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
136 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
137 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
138 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
139 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
140 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
141 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
142
143 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
144 PORT_IRQ_IF_ERR |
145 PORT_IRQ_CONNECT |
146 PORT_IRQ_PHYRDY |
147 PORT_IRQ_UNK_FIS,
148 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
149 PORT_IRQ_TF_ERR |
150 PORT_IRQ_HBUS_DATA_ERR,
151 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
152 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
153 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
154
155 /* PORT_CMD bits */
156 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
157 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
158 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
159 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
160 PORT_CMD_CLO = (1 << 3), /* Command list override */
161 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
162 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
163 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
164
165 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
166 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
167 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
168 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
169
170 /* ap->flags bits */
171 AHCI_FLAG_NO_NCQ = (1 << 24),
172 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
173 AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
174 AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */
175 AHCI_FLAG_32BIT_ONLY = (1 << 28), /* force 32bit */
176 AHCI_FLAG_MV_PATA = (1 << 29), /* PATA port */
177 AHCI_FLAG_NO_MSI = (1 << 30), /* no PCI MSI */
178
179 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
180 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
181 ATA_FLAG_SKIP_D2H_BSY |
182 ATA_FLAG_ACPI_SATA,
183 };
184
185 struct ahci_cmd_hdr {
186 u32 opts;
187 u32 status;
188 u32 tbl_addr;
189 u32 tbl_addr_hi;
190 u32 reserved[4];
191 };
192
193 struct ahci_sg {
194 u32 addr;
195 u32 addr_hi;
196 u32 reserved;
197 u32 flags_size;
198 };
199
200 struct ahci_host_priv {
201 u32 cap; /* cap to use */
202 u32 port_map; /* port map to use */
203 u32 saved_cap; /* saved initial cap */
204 u32 saved_port_map; /* saved initial port_map */
205 };
206
207 struct ahci_port_priv {
208 struct ahci_cmd_hdr *cmd_slot;
209 dma_addr_t cmd_slot_dma;
210 void *cmd_tbl;
211 dma_addr_t cmd_tbl_dma;
212 void *rx_fis;
213 dma_addr_t rx_fis_dma;
214 /* for NCQ spurious interrupt analysis */
215 unsigned int ncq_saw_d2h:1;
216 unsigned int ncq_saw_dmas:1;
217 unsigned int ncq_saw_sdb:1;
218 };
219
220 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
221 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
222 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
223 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
224 static void ahci_irq_clear(struct ata_port *ap);
225 static int ahci_port_start(struct ata_port *ap);
226 static void ahci_port_stop(struct ata_port *ap);
227 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
228 static void ahci_qc_prep(struct ata_queued_cmd *qc);
229 static u8 ahci_check_status(struct ata_port *ap);
230 static void ahci_freeze(struct ata_port *ap);
231 static void ahci_thaw(struct ata_port *ap);
232 static void ahci_error_handler(struct ata_port *ap);
233 static void ahci_vt8251_error_handler(struct ata_port *ap);
234 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
235 static int ahci_port_resume(struct ata_port *ap);
236 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
237 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
238 u32 opts);
239 #ifdef CONFIG_PM
240 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
241 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
242 static int ahci_pci_device_resume(struct pci_dev *pdev);
243 #endif
244
245 static struct scsi_host_template ahci_sht = {
246 .module = THIS_MODULE,
247 .name = DRV_NAME,
248 .ioctl = ata_scsi_ioctl,
249 .queuecommand = ata_scsi_queuecmd,
250 .change_queue_depth = ata_scsi_change_queue_depth,
251 .can_queue = AHCI_MAX_CMDS - 1,
252 .this_id = ATA_SHT_THIS_ID,
253 .sg_tablesize = AHCI_MAX_SG,
254 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
255 .emulated = ATA_SHT_EMULATED,
256 .use_clustering = AHCI_USE_CLUSTERING,
257 .proc_name = DRV_NAME,
258 .dma_boundary = AHCI_DMA_BOUNDARY,
259 .slave_configure = ata_scsi_slave_config,
260 .slave_destroy = ata_scsi_slave_destroy,
261 .bios_param = ata_std_bios_param,
262 };
263
264 static const struct ata_port_operations ahci_ops = {
265 .port_disable = ata_port_disable,
266
267 .check_status = ahci_check_status,
268 .check_altstatus = ahci_check_status,
269 .dev_select = ata_noop_dev_select,
270
271 .tf_read = ahci_tf_read,
272
273 .qc_prep = ahci_qc_prep,
274 .qc_issue = ahci_qc_issue,
275
276 .irq_clear = ahci_irq_clear,
277 .irq_on = ata_dummy_irq_on,
278 .irq_ack = ata_dummy_irq_ack,
279
280 .scr_read = ahci_scr_read,
281 .scr_write = ahci_scr_write,
282
283 .freeze = ahci_freeze,
284 .thaw = ahci_thaw,
285
286 .error_handler = ahci_error_handler,
287 .post_internal_cmd = ahci_post_internal_cmd,
288
289 #ifdef CONFIG_PM
290 .port_suspend = ahci_port_suspend,
291 .port_resume = ahci_port_resume,
292 #endif
293
294 .port_start = ahci_port_start,
295 .port_stop = ahci_port_stop,
296 };
297
298 static const struct ata_port_operations ahci_vt8251_ops = {
299 .port_disable = ata_port_disable,
300
301 .check_status = ahci_check_status,
302 .check_altstatus = ahci_check_status,
303 .dev_select = ata_noop_dev_select,
304
305 .tf_read = ahci_tf_read,
306
307 .qc_prep = ahci_qc_prep,
308 .qc_issue = ahci_qc_issue,
309
310 .irq_clear = ahci_irq_clear,
311 .irq_on = ata_dummy_irq_on,
312 .irq_ack = ata_dummy_irq_ack,
313
314 .scr_read = ahci_scr_read,
315 .scr_write = ahci_scr_write,
316
317 .freeze = ahci_freeze,
318 .thaw = ahci_thaw,
319
320 .error_handler = ahci_vt8251_error_handler,
321 .post_internal_cmd = ahci_post_internal_cmd,
322
323 #ifdef CONFIG_PM
324 .port_suspend = ahci_port_suspend,
325 .port_resume = ahci_port_resume,
326 #endif
327
328 .port_start = ahci_port_start,
329 .port_stop = ahci_port_stop,
330 };
331
332 static const struct ata_port_info ahci_port_info[] = {
333 /* board_ahci */
334 {
335 .flags = AHCI_FLAG_COMMON,
336 .pio_mask = 0x1f, /* pio0-4 */
337 .udma_mask = ATA_UDMA6,
338 .port_ops = &ahci_ops,
339 },
340 /* board_ahci_pi */
341 {
342 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_HONOR_PI,
343 .pio_mask = 0x1f, /* pio0-4 */
344 .udma_mask = ATA_UDMA6,
345 .port_ops = &ahci_ops,
346 },
347 /* board_ahci_vt8251 */
348 {
349 .flags = AHCI_FLAG_COMMON | ATA_FLAG_HRST_TO_RESUME |
350 AHCI_FLAG_NO_NCQ,
351 .pio_mask = 0x1f, /* pio0-4 */
352 .udma_mask = ATA_UDMA6,
353 .port_ops = &ahci_vt8251_ops,
354 },
355 /* board_ahci_ign_iferr */
356 {
357 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_IGN_IRQ_IF_ERR,
358 .pio_mask = 0x1f, /* pio0-4 */
359 .udma_mask = ATA_UDMA6,
360 .port_ops = &ahci_ops,
361 },
362 /* board_ahci_sb600 */
363 {
364 .flags = AHCI_FLAG_COMMON |
365 AHCI_FLAG_IGN_SERR_INTERNAL |
366 AHCI_FLAG_32BIT_ONLY,
367 .pio_mask = 0x1f, /* pio0-4 */
368 .udma_mask = ATA_UDMA6,
369 .port_ops = &ahci_ops,
370 },
371 /* board_ahci_mv */
372 {
373 .sht = &ahci_sht,
374 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
375 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
376 ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI |
377 AHCI_FLAG_NO_NCQ | AHCI_FLAG_NO_MSI |
378 AHCI_FLAG_MV_PATA,
379 .pio_mask = 0x1f, /* pio0-4 */
380 .udma_mask = ATA_UDMA6,
381 .port_ops = &ahci_ops,
382 },
383 };
384
385 static const struct pci_device_id ahci_pci_tbl[] = {
386 /* Intel */
387 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
388 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
389 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
390 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
391 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
392 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
393 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
394 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
395 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
396 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
397 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */
398 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */
399 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */
400 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */
401 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */
402 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */
403 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */
404 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */
405 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */
406 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */
407 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */
408 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */
409 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */
410 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pi }, /* ICH9M */
411 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
412 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
413 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
414
415 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
416 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
417 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
418
419 /* ATI */
420 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
421 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */
422 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */
423 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */
424 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */
425 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */
426 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */
427
428 /* VIA */
429 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
430 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
431
432 /* NVIDIA */
433 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
434 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
435 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
436 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
437 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
438 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
439 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
440 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
441 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
442 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
443 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
444 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
445 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
446 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
447 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
448 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
449 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
450 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
451 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
452 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
453 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
454 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
455 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
456 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
457 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
458 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
459 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
460 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
461 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
462 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
463 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
464 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
465 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
466 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
467 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
468 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
469 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
470 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
471 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
472 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
473 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
474 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
475 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
476 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
477
478 /* SiS */
479 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
480 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
481 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
482
483 /* Marvell */
484 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
485
486 /* Generic, PCI class code for AHCI */
487 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
488 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
489
490 { } /* terminate list */
491 };
492
493
494 static struct pci_driver ahci_pci_driver = {
495 .name = DRV_NAME,
496 .id_table = ahci_pci_tbl,
497 .probe = ahci_init_one,
498 .remove = ata_pci_remove_one,
499 #ifdef CONFIG_PM
500 .suspend = ahci_pci_device_suspend,
501 .resume = ahci_pci_device_resume,
502 #endif
503 };
504
505
506 static inline int ahci_nr_ports(u32 cap)
507 {
508 return (cap & 0x1f) + 1;
509 }
510
511 static inline void __iomem *__ahci_port_base(struct ata_host *host,
512 unsigned int port_no)
513 {
514 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
515
516 return mmio + 0x100 + (port_no * 0x80);
517 }
518
519 static inline void __iomem *ahci_port_base(struct ata_port *ap)
520 {
521 return __ahci_port_base(ap->host, ap->port_no);
522 }
523
524 /**
525 * ahci_save_initial_config - Save and fixup initial config values
526 * @pdev: target PCI device
527 * @pi: associated ATA port info
528 * @hpriv: host private area to store config values
529 *
530 * Some registers containing configuration info might be setup by
531 * BIOS and might be cleared on reset. This function saves the
532 * initial values of those registers into @hpriv such that they
533 * can be restored after controller reset.
534 *
535 * If inconsistent, config values are fixed up by this function.
536 *
537 * LOCKING:
538 * None.
539 */
540 static void ahci_save_initial_config(struct pci_dev *pdev,
541 const struct ata_port_info *pi,
542 struct ahci_host_priv *hpriv)
543 {
544 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
545 u32 cap, port_map;
546 int i;
547
548 /* Values prefixed with saved_ are written back to host after
549 * reset. Values without are used for driver operation.
550 */
551 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
552 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
553
554 /* some chips have errata preventing 64bit use */
555 if ((cap & HOST_CAP_64) && (pi->flags & AHCI_FLAG_32BIT_ONLY)) {
556 dev_printk(KERN_INFO, &pdev->dev,
557 "controller can't do 64bit DMA, forcing 32bit\n");
558 cap &= ~HOST_CAP_64;
559 }
560
561 if ((cap & HOST_CAP_NCQ) && (pi->flags & AHCI_FLAG_NO_NCQ)) {
562 dev_printk(KERN_INFO, &pdev->dev,
563 "controller can't do NCQ, turning off CAP_NCQ\n");
564 cap &= ~HOST_CAP_NCQ;
565 }
566
567 /* fixup zero port_map */
568 if (!port_map) {
569 port_map = (1 << ahci_nr_ports(cap)) - 1;
570 dev_printk(KERN_WARNING, &pdev->dev,
571 "PORTS_IMPL is zero, forcing 0x%x\n", port_map);
572
573 /* write the fixed up value to the PI register */
574 hpriv->saved_port_map = port_map;
575 }
576
577 /*
578 * Temporary Marvell 6145 hack: PATA port presence
579 * is asserted through the standard AHCI port
580 * presence register, as bit 4 (counting from 0)
581 */
582 if (pi->flags & AHCI_FLAG_MV_PATA) {
583 dev_printk(KERN_ERR, &pdev->dev,
584 "MV_AHCI HACK: port_map %x -> %x\n",
585 hpriv->port_map,
586 hpriv->port_map & 0xf);
587
588 port_map &= 0xf;
589 }
590
591 /* cross check port_map and cap.n_ports */
592 if (pi->flags & AHCI_FLAG_HONOR_PI) {
593 u32 tmp_port_map = port_map;
594 int n_ports = ahci_nr_ports(cap);
595
596 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
597 if (tmp_port_map & (1 << i)) {
598 n_ports--;
599 tmp_port_map &= ~(1 << i);
600 }
601 }
602
603 /* Whine if inconsistent. No need to update cap.
604 * port_map is used to determine number of ports.
605 */
606 if (n_ports || tmp_port_map)
607 dev_printk(KERN_WARNING, &pdev->dev,
608 "nr_ports (%u) and implemented port map "
609 "(0x%x) don't match\n",
610 ahci_nr_ports(cap), port_map);
611 } else {
612 /* fabricate port_map from cap.nr_ports */
613 port_map = (1 << ahci_nr_ports(cap)) - 1;
614 }
615
616 /* record values to use during operation */
617 hpriv->cap = cap;
618 hpriv->port_map = port_map;
619 }
620
621 /**
622 * ahci_restore_initial_config - Restore initial config
623 * @host: target ATA host
624 *
625 * Restore initial config stored by ahci_save_initial_config().
626 *
627 * LOCKING:
628 * None.
629 */
630 static void ahci_restore_initial_config(struct ata_host *host)
631 {
632 struct ahci_host_priv *hpriv = host->private_data;
633 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
634
635 writel(hpriv->saved_cap, mmio + HOST_CAP);
636 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
637 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
638 }
639
640 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
641 {
642 static const int offset[] = {
643 [SCR_STATUS] = PORT_SCR_STAT,
644 [SCR_CONTROL] = PORT_SCR_CTL,
645 [SCR_ERROR] = PORT_SCR_ERR,
646 [SCR_ACTIVE] = PORT_SCR_ACT,
647 [SCR_NOTIFICATION] = PORT_SCR_NTF,
648 };
649 struct ahci_host_priv *hpriv = ap->host->private_data;
650
651 if (sc_reg < ARRAY_SIZE(offset) &&
652 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
653 return offset[sc_reg];
654 return 0;
655 }
656
657 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
658 {
659 void __iomem *port_mmio = ahci_port_base(ap);
660 int offset = ahci_scr_offset(ap, sc_reg);
661
662 if (offset) {
663 *val = readl(port_mmio + offset);
664 return 0;
665 }
666 return -EINVAL;
667 }
668
669 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
670 {
671 void __iomem *port_mmio = ahci_port_base(ap);
672 int offset = ahci_scr_offset(ap, sc_reg);
673
674 if (offset) {
675 writel(val, port_mmio + offset);
676 return 0;
677 }
678 return -EINVAL;
679 }
680
681 static void ahci_start_engine(struct ata_port *ap)
682 {
683 void __iomem *port_mmio = ahci_port_base(ap);
684 u32 tmp;
685
686 /* start DMA */
687 tmp = readl(port_mmio + PORT_CMD);
688 tmp |= PORT_CMD_START;
689 writel(tmp, port_mmio + PORT_CMD);
690 readl(port_mmio + PORT_CMD); /* flush */
691 }
692
693 static int ahci_stop_engine(struct ata_port *ap)
694 {
695 void __iomem *port_mmio = ahci_port_base(ap);
696 u32 tmp;
697
698 tmp = readl(port_mmio + PORT_CMD);
699
700 /* check if the HBA is idle */
701 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
702 return 0;
703
704 /* setting HBA to idle */
705 tmp &= ~PORT_CMD_START;
706 writel(tmp, port_mmio + PORT_CMD);
707
708 /* wait for engine to stop. This could be as long as 500 msec */
709 tmp = ata_wait_register(port_mmio + PORT_CMD,
710 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
711 if (tmp & PORT_CMD_LIST_ON)
712 return -EIO;
713
714 return 0;
715 }
716
717 static void ahci_start_fis_rx(struct ata_port *ap)
718 {
719 void __iomem *port_mmio = ahci_port_base(ap);
720 struct ahci_host_priv *hpriv = ap->host->private_data;
721 struct ahci_port_priv *pp = ap->private_data;
722 u32 tmp;
723
724 /* set FIS registers */
725 if (hpriv->cap & HOST_CAP_64)
726 writel((pp->cmd_slot_dma >> 16) >> 16,
727 port_mmio + PORT_LST_ADDR_HI);
728 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
729
730 if (hpriv->cap & HOST_CAP_64)
731 writel((pp->rx_fis_dma >> 16) >> 16,
732 port_mmio + PORT_FIS_ADDR_HI);
733 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
734
735 /* enable FIS reception */
736 tmp = readl(port_mmio + PORT_CMD);
737 tmp |= PORT_CMD_FIS_RX;
738 writel(tmp, port_mmio + PORT_CMD);
739
740 /* flush */
741 readl(port_mmio + PORT_CMD);
742 }
743
744 static int ahci_stop_fis_rx(struct ata_port *ap)
745 {
746 void __iomem *port_mmio = ahci_port_base(ap);
747 u32 tmp;
748
749 /* disable FIS reception */
750 tmp = readl(port_mmio + PORT_CMD);
751 tmp &= ~PORT_CMD_FIS_RX;
752 writel(tmp, port_mmio + PORT_CMD);
753
754 /* wait for completion, spec says 500ms, give it 1000 */
755 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
756 PORT_CMD_FIS_ON, 10, 1000);
757 if (tmp & PORT_CMD_FIS_ON)
758 return -EBUSY;
759
760 return 0;
761 }
762
763 static void ahci_power_up(struct ata_port *ap)
764 {
765 struct ahci_host_priv *hpriv = ap->host->private_data;
766 void __iomem *port_mmio = ahci_port_base(ap);
767 u32 cmd;
768
769 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
770
771 /* spin up device */
772 if (hpriv->cap & HOST_CAP_SSS) {
773 cmd |= PORT_CMD_SPIN_UP;
774 writel(cmd, port_mmio + PORT_CMD);
775 }
776
777 /* wake up link */
778 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
779 }
780
781 #ifdef CONFIG_PM
782 static void ahci_power_down(struct ata_port *ap)
783 {
784 struct ahci_host_priv *hpriv = ap->host->private_data;
785 void __iomem *port_mmio = ahci_port_base(ap);
786 u32 cmd, scontrol;
787
788 if (!(hpriv->cap & HOST_CAP_SSS))
789 return;
790
791 /* put device into listen mode, first set PxSCTL.DET to 0 */
792 scontrol = readl(port_mmio + PORT_SCR_CTL);
793 scontrol &= ~0xf;
794 writel(scontrol, port_mmio + PORT_SCR_CTL);
795
796 /* then set PxCMD.SUD to 0 */
797 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
798 cmd &= ~PORT_CMD_SPIN_UP;
799 writel(cmd, port_mmio + PORT_CMD);
800 }
801 #endif
802
803 static void ahci_start_port(struct ata_port *ap)
804 {
805 /* enable FIS reception */
806 ahci_start_fis_rx(ap);
807
808 /* enable DMA */
809 ahci_start_engine(ap);
810 }
811
812 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
813 {
814 int rc;
815
816 /* disable DMA */
817 rc = ahci_stop_engine(ap);
818 if (rc) {
819 *emsg = "failed to stop engine";
820 return rc;
821 }
822
823 /* disable FIS reception */
824 rc = ahci_stop_fis_rx(ap);
825 if (rc) {
826 *emsg = "failed stop FIS RX";
827 return rc;
828 }
829
830 return 0;
831 }
832
833 static int ahci_reset_controller(struct ata_host *host)
834 {
835 struct pci_dev *pdev = to_pci_dev(host->dev);
836 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
837 u32 tmp;
838
839 /* global controller reset */
840 tmp = readl(mmio + HOST_CTL);
841 if ((tmp & HOST_RESET) == 0) {
842 writel(tmp | HOST_RESET, mmio + HOST_CTL);
843 readl(mmio + HOST_CTL); /* flush */
844 }
845
846 /* reset must complete within 1 second, or
847 * the hardware should be considered fried.
848 */
849 ssleep(1);
850
851 tmp = readl(mmio + HOST_CTL);
852 if (tmp & HOST_RESET) {
853 dev_printk(KERN_ERR, host->dev,
854 "controller reset failed (0x%x)\n", tmp);
855 return -EIO;
856 }
857
858 /* turn on AHCI mode */
859 writel(HOST_AHCI_EN, mmio + HOST_CTL);
860 (void) readl(mmio + HOST_CTL); /* flush */
861
862 /* some registers might be cleared on reset. restore initial values */
863 ahci_restore_initial_config(host);
864
865 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
866 u16 tmp16;
867
868 /* configure PCS */
869 pci_read_config_word(pdev, 0x92, &tmp16);
870 tmp16 |= 0xf;
871 pci_write_config_word(pdev, 0x92, tmp16);
872 }
873
874 return 0;
875 }
876
877 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
878 int port_no, void __iomem *mmio,
879 void __iomem *port_mmio)
880 {
881 const char *emsg = NULL;
882 int rc;
883 u32 tmp;
884
885 /* make sure port is not active */
886 rc = ahci_deinit_port(ap, &emsg);
887 if (rc)
888 dev_printk(KERN_WARNING, &pdev->dev,
889 "%s (%d)\n", emsg, rc);
890
891 /* clear SError */
892 tmp = readl(port_mmio + PORT_SCR_ERR);
893 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
894 writel(tmp, port_mmio + PORT_SCR_ERR);
895
896 /* clear port IRQ */
897 tmp = readl(port_mmio + PORT_IRQ_STAT);
898 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
899 if (tmp)
900 writel(tmp, port_mmio + PORT_IRQ_STAT);
901
902 writel(1 << port_no, mmio + HOST_IRQ_STAT);
903 }
904
905 static void ahci_init_controller(struct ata_host *host)
906 {
907 struct pci_dev *pdev = to_pci_dev(host->dev);
908 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
909 int i;
910 void __iomem *port_mmio;
911 u32 tmp;
912
913 if (host->ports[0]->flags & AHCI_FLAG_MV_PATA) {
914 port_mmio = __ahci_port_base(host, 4);
915
916 writel(0, port_mmio + PORT_IRQ_MASK);
917
918 /* clear port IRQ */
919 tmp = readl(port_mmio + PORT_IRQ_STAT);
920 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
921 if (tmp)
922 writel(tmp, port_mmio + PORT_IRQ_STAT);
923 }
924
925 for (i = 0; i < host->n_ports; i++) {
926 struct ata_port *ap = host->ports[i];
927
928 port_mmio = ahci_port_base(ap);
929 if (ata_port_is_dummy(ap))
930 continue;
931
932 ahci_port_init(pdev, ap, i, mmio, port_mmio);
933 }
934
935 tmp = readl(mmio + HOST_CTL);
936 VPRINTK("HOST_CTL 0x%x\n", tmp);
937 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
938 tmp = readl(mmio + HOST_CTL);
939 VPRINTK("HOST_CTL 0x%x\n", tmp);
940 }
941
942 static unsigned int ahci_dev_classify(struct ata_port *ap)
943 {
944 void __iomem *port_mmio = ahci_port_base(ap);
945 struct ata_taskfile tf;
946 u32 tmp;
947
948 tmp = readl(port_mmio + PORT_SIG);
949 tf.lbah = (tmp >> 24) & 0xff;
950 tf.lbam = (tmp >> 16) & 0xff;
951 tf.lbal = (tmp >> 8) & 0xff;
952 tf.nsect = (tmp) & 0xff;
953
954 return ata_dev_classify(&tf);
955 }
956
957 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
958 u32 opts)
959 {
960 dma_addr_t cmd_tbl_dma;
961
962 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
963
964 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
965 pp->cmd_slot[tag].status = 0;
966 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
967 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
968 }
969
970 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
971 {
972 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
973 struct ahci_host_priv *hpriv = ap->host->private_data;
974 u32 tmp;
975 int busy, rc;
976
977 /* do we need to kick the port? */
978 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
979 if (!busy && !force_restart)
980 return 0;
981
982 /* stop engine */
983 rc = ahci_stop_engine(ap);
984 if (rc)
985 goto out_restart;
986
987 /* need to do CLO? */
988 if (!busy) {
989 rc = 0;
990 goto out_restart;
991 }
992
993 if (!(hpriv->cap & HOST_CAP_CLO)) {
994 rc = -EOPNOTSUPP;
995 goto out_restart;
996 }
997
998 /* perform CLO */
999 tmp = readl(port_mmio + PORT_CMD);
1000 tmp |= PORT_CMD_CLO;
1001 writel(tmp, port_mmio + PORT_CMD);
1002
1003 rc = 0;
1004 tmp = ata_wait_register(port_mmio + PORT_CMD,
1005 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1006 if (tmp & PORT_CMD_CLO)
1007 rc = -EIO;
1008
1009 /* restart engine */
1010 out_restart:
1011 ahci_start_engine(ap);
1012 return rc;
1013 }
1014
1015 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1016 struct ata_taskfile *tf, int is_cmd, u16 flags,
1017 unsigned long timeout_msec)
1018 {
1019 const u32 cmd_fis_len = 5; /* five dwords */
1020 struct ahci_port_priv *pp = ap->private_data;
1021 void __iomem *port_mmio = ahci_port_base(ap);
1022 u8 *fis = pp->cmd_tbl;
1023 u32 tmp;
1024
1025 /* prep the command */
1026 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1027 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1028
1029 /* issue & wait */
1030 writel(1, port_mmio + PORT_CMD_ISSUE);
1031
1032 if (timeout_msec) {
1033 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1034 1, timeout_msec);
1035 if (tmp & 0x1) {
1036 ahci_kick_engine(ap, 1);
1037 return -EBUSY;
1038 }
1039 } else
1040 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1041
1042 return 0;
1043 }
1044
1045 static int ahci_do_softreset(struct ata_port *ap, unsigned int *class,
1046 int pmp, unsigned long deadline)
1047 {
1048 const char *reason = NULL;
1049 unsigned long now, msecs;
1050 struct ata_taskfile tf;
1051 int rc;
1052
1053 DPRINTK("ENTER\n");
1054
1055 if (ata_port_offline(ap)) {
1056 DPRINTK("PHY reports no device\n");
1057 *class = ATA_DEV_NONE;
1058 return 0;
1059 }
1060
1061 /* prepare for SRST (AHCI-1.1 10.4.1) */
1062 rc = ahci_kick_engine(ap, 1);
1063 if (rc)
1064 ata_port_printk(ap, KERN_WARNING,
1065 "failed to reset engine (errno=%d)", rc);
1066
1067 ata_tf_init(ap->device, &tf);
1068
1069 /* issue the first D2H Register FIS */
1070 msecs = 0;
1071 now = jiffies;
1072 if (time_after(now, deadline))
1073 msecs = jiffies_to_msecs(deadline - now);
1074
1075 tf.ctl |= ATA_SRST;
1076 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1077 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1078 rc = -EIO;
1079 reason = "1st FIS failed";
1080 goto fail;
1081 }
1082
1083 /* spec says at least 5us, but be generous and sleep for 1ms */
1084 msleep(1);
1085
1086 /* issue the second D2H Register FIS */
1087 tf.ctl &= ~ATA_SRST;
1088 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1089
1090 /* spec mandates ">= 2ms" before checking status.
1091 * We wait 150ms, because that was the magic delay used for
1092 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1093 * between when the ATA command register is written, and then
1094 * status is checked. Because waiting for "a while" before
1095 * checking status is fine, post SRST, we perform this magic
1096 * delay here as well.
1097 */
1098 msleep(150);
1099
1100 rc = ata_wait_ready(ap, deadline);
1101 /* link occupied, -ENODEV too is an error */
1102 if (rc) {
1103 reason = "device not ready";
1104 goto fail;
1105 }
1106 *class = ahci_dev_classify(ap);
1107
1108 DPRINTK("EXIT, class=%u\n", *class);
1109 return 0;
1110
1111 fail:
1112 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
1113 return rc;
1114 }
1115
1116 static int ahci_softreset(struct ata_port *ap, unsigned int *class,
1117 unsigned long deadline)
1118 {
1119 return ahci_do_softreset(ap, class, 0, deadline);
1120 }
1121
1122 static int ahci_hardreset(struct ata_port *ap, unsigned int *class,
1123 unsigned long deadline)
1124 {
1125 struct ahci_port_priv *pp = ap->private_data;
1126 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1127 struct ata_taskfile tf;
1128 int rc;
1129
1130 DPRINTK("ENTER\n");
1131
1132 ahci_stop_engine(ap);
1133
1134 /* clear D2H reception area to properly wait for D2H FIS */
1135 ata_tf_init(ap->device, &tf);
1136 tf.command = 0x80;
1137 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1138
1139 rc = sata_std_hardreset(ap, class, deadline);
1140
1141 ahci_start_engine(ap);
1142
1143 if (rc == 0 && ata_port_online(ap))
1144 *class = ahci_dev_classify(ap);
1145 if (*class == ATA_DEV_UNKNOWN)
1146 *class = ATA_DEV_NONE;
1147
1148 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1149 return rc;
1150 }
1151
1152 static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class,
1153 unsigned long deadline)
1154 {
1155 u32 serror;
1156 int rc;
1157
1158 DPRINTK("ENTER\n");
1159
1160 ahci_stop_engine(ap);
1161
1162 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context),
1163 deadline);
1164
1165 /* vt8251 needs SError cleared for the port to operate */
1166 ahci_scr_read(ap, SCR_ERROR, &serror);
1167 ahci_scr_write(ap, SCR_ERROR, serror);
1168
1169 ahci_start_engine(ap);
1170
1171 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1172
1173 /* vt8251 doesn't clear BSY on signature FIS reception,
1174 * request follow-up softreset.
1175 */
1176 return rc ?: -EAGAIN;
1177 }
1178
1179 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
1180 {
1181 void __iomem *port_mmio = ahci_port_base(ap);
1182 u32 new_tmp, tmp;
1183
1184 ata_std_postreset(ap, class);
1185
1186 /* Make sure port's ATAPI bit is set appropriately */
1187 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1188 if (*class == ATA_DEV_ATAPI)
1189 new_tmp |= PORT_CMD_ATAPI;
1190 else
1191 new_tmp &= ~PORT_CMD_ATAPI;
1192 if (new_tmp != tmp) {
1193 writel(new_tmp, port_mmio + PORT_CMD);
1194 readl(port_mmio + PORT_CMD); /* flush */
1195 }
1196 }
1197
1198 static u8 ahci_check_status(struct ata_port *ap)
1199 {
1200 void __iomem *mmio = ap->ioaddr.cmd_addr;
1201
1202 return readl(mmio + PORT_TFDATA) & 0xFF;
1203 }
1204
1205 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1206 {
1207 struct ahci_port_priv *pp = ap->private_data;
1208 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1209
1210 ata_tf_from_fis(d2h_fis, tf);
1211 }
1212
1213 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1214 {
1215 struct scatterlist *sg;
1216 struct ahci_sg *ahci_sg;
1217 unsigned int n_sg = 0;
1218
1219 VPRINTK("ENTER\n");
1220
1221 /*
1222 * Next, the S/G list.
1223 */
1224 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1225 ata_for_each_sg(sg, qc) {
1226 dma_addr_t addr = sg_dma_address(sg);
1227 u32 sg_len = sg_dma_len(sg);
1228
1229 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1230 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1231 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
1232
1233 ahci_sg++;
1234 n_sg++;
1235 }
1236
1237 return n_sg;
1238 }
1239
1240 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1241 {
1242 struct ata_port *ap = qc->ap;
1243 struct ahci_port_priv *pp = ap->private_data;
1244 int is_atapi = is_atapi_taskfile(&qc->tf);
1245 void *cmd_tbl;
1246 u32 opts;
1247 const u32 cmd_fis_len = 5; /* five dwords */
1248 unsigned int n_elem;
1249
1250 /*
1251 * Fill in command table information. First, the header,
1252 * a SATA Register - Host to Device command FIS.
1253 */
1254 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1255
1256 ata_tf_to_fis(&qc->tf, 0, 1, cmd_tbl);
1257 if (is_atapi) {
1258 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1259 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1260 }
1261
1262 n_elem = 0;
1263 if (qc->flags & ATA_QCFLAG_DMAMAP)
1264 n_elem = ahci_fill_sg(qc, cmd_tbl);
1265
1266 /*
1267 * Fill in command slot information.
1268 */
1269 opts = cmd_fis_len | n_elem << 16;
1270 if (qc->tf.flags & ATA_TFLAG_WRITE)
1271 opts |= AHCI_CMD_WRITE;
1272 if (is_atapi)
1273 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1274
1275 ahci_fill_cmd_slot(pp, qc->tag, opts);
1276 }
1277
1278 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1279 {
1280 struct ahci_port_priv *pp = ap->private_data;
1281 struct ata_eh_info *ehi = &ap->eh_info;
1282 unsigned int err_mask = 0, action = 0;
1283 struct ata_queued_cmd *qc;
1284 u32 serror;
1285
1286 ata_ehi_clear_desc(ehi);
1287
1288 /* AHCI needs SError cleared; otherwise, it might lock up */
1289 ahci_scr_read(ap, SCR_ERROR, &serror);
1290 ahci_scr_write(ap, SCR_ERROR, serror);
1291
1292 /* analyze @irq_stat */
1293 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1294
1295 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1296 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1297 irq_stat &= ~PORT_IRQ_IF_ERR;
1298
1299 if (irq_stat & PORT_IRQ_TF_ERR) {
1300 err_mask |= AC_ERR_DEV;
1301 if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL)
1302 serror &= ~SERR_INTERNAL;
1303 }
1304
1305 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1306 err_mask |= AC_ERR_HOST_BUS;
1307 action |= ATA_EH_SOFTRESET;
1308 }
1309
1310 if (irq_stat & PORT_IRQ_IF_ERR) {
1311 err_mask |= AC_ERR_ATA_BUS;
1312 action |= ATA_EH_SOFTRESET;
1313 ata_ehi_push_desc(ehi, "interface fatal error");
1314 }
1315
1316 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1317 ata_ehi_hotplugged(ehi);
1318 ata_ehi_push_desc(ehi, "%s", irq_stat & PORT_IRQ_CONNECT ?
1319 "connection status changed" : "PHY RDY changed");
1320 }
1321
1322 if (irq_stat & PORT_IRQ_UNK_FIS) {
1323 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1324
1325 err_mask |= AC_ERR_HSM;
1326 action |= ATA_EH_SOFTRESET;
1327 ata_ehi_push_desc(ehi, "unknown FIS %08x %08x %08x %08x",
1328 unk[0], unk[1], unk[2], unk[3]);
1329 }
1330
1331 /* okay, let's hand over to EH */
1332 ehi->serror |= serror;
1333 ehi->action |= action;
1334
1335 qc = ata_qc_from_tag(ap, ap->active_tag);
1336 if (qc)
1337 qc->err_mask |= err_mask;
1338 else
1339 ehi->err_mask |= err_mask;
1340
1341 if (irq_stat & PORT_IRQ_FREEZE)
1342 ata_port_freeze(ap);
1343 else
1344 ata_port_abort(ap);
1345 }
1346
1347 static void ahci_port_intr(struct ata_port *ap)
1348 {
1349 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1350 struct ata_eh_info *ehi = &ap->eh_info;
1351 struct ahci_port_priv *pp = ap->private_data;
1352 u32 status, qc_active;
1353 int rc, known_irq = 0;
1354
1355 status = readl(port_mmio + PORT_IRQ_STAT);
1356 writel(status, port_mmio + PORT_IRQ_STAT);
1357
1358 if (unlikely(status & PORT_IRQ_ERROR)) {
1359 ahci_error_intr(ap, status);
1360 return;
1361 }
1362
1363 if (ap->sactive)
1364 qc_active = readl(port_mmio + PORT_SCR_ACT);
1365 else
1366 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1367
1368 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1369 if (rc > 0)
1370 return;
1371 if (rc < 0) {
1372 ehi->err_mask |= AC_ERR_HSM;
1373 ehi->action |= ATA_EH_SOFTRESET;
1374 ata_port_freeze(ap);
1375 return;
1376 }
1377
1378 /* hmmm... a spurious interupt */
1379
1380 /* if !NCQ, ignore. No modern ATA device has broken HSM
1381 * implementation for non-NCQ commands.
1382 */
1383 if (!ap->sactive)
1384 return;
1385
1386 if (status & PORT_IRQ_D2H_REG_FIS) {
1387 if (!pp->ncq_saw_d2h)
1388 ata_port_printk(ap, KERN_INFO,
1389 "D2H reg with I during NCQ, "
1390 "this message won't be printed again\n");
1391 pp->ncq_saw_d2h = 1;
1392 known_irq = 1;
1393 }
1394
1395 if (status & PORT_IRQ_DMAS_FIS) {
1396 if (!pp->ncq_saw_dmas)
1397 ata_port_printk(ap, KERN_INFO,
1398 "DMAS FIS during NCQ, "
1399 "this message won't be printed again\n");
1400 pp->ncq_saw_dmas = 1;
1401 known_irq = 1;
1402 }
1403
1404 if (status & PORT_IRQ_SDB_FIS) {
1405 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1406
1407 if (le32_to_cpu(f[1])) {
1408 /* SDB FIS containing spurious completions
1409 * might be dangerous, whine and fail commands
1410 * with HSM violation. EH will turn off NCQ
1411 * after several such failures.
1412 */
1413 ata_ehi_push_desc(ehi,
1414 "spurious completions during NCQ "
1415 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1416 readl(port_mmio + PORT_CMD_ISSUE),
1417 readl(port_mmio + PORT_SCR_ACT),
1418 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1419 ehi->err_mask |= AC_ERR_HSM;
1420 ehi->action |= ATA_EH_SOFTRESET;
1421 ata_port_freeze(ap);
1422 } else {
1423 if (!pp->ncq_saw_sdb)
1424 ata_port_printk(ap, KERN_INFO,
1425 "spurious SDB FIS %08x:%08x during NCQ, "
1426 "this message won't be printed again\n",
1427 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1428 pp->ncq_saw_sdb = 1;
1429 }
1430 known_irq = 1;
1431 }
1432
1433 if (!known_irq)
1434 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1435 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
1436 status, ap->active_tag, ap->sactive);
1437 }
1438
1439 static void ahci_irq_clear(struct ata_port *ap)
1440 {
1441 /* TODO */
1442 }
1443
1444 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1445 {
1446 struct ata_host *host = dev_instance;
1447 struct ahci_host_priv *hpriv;
1448 unsigned int i, handled = 0;
1449 void __iomem *mmio;
1450 u32 irq_stat, irq_ack = 0;
1451
1452 VPRINTK("ENTER\n");
1453
1454 hpriv = host->private_data;
1455 mmio = host->iomap[AHCI_PCI_BAR];
1456
1457 /* sigh. 0xffffffff is a valid return from h/w */
1458 irq_stat = readl(mmio + HOST_IRQ_STAT);
1459 irq_stat &= hpriv->port_map;
1460 if (!irq_stat)
1461 return IRQ_NONE;
1462
1463 spin_lock(&host->lock);
1464
1465 for (i = 0; i < host->n_ports; i++) {
1466 struct ata_port *ap;
1467
1468 if (!(irq_stat & (1 << i)))
1469 continue;
1470
1471 ap = host->ports[i];
1472 if (ap) {
1473 ahci_port_intr(ap);
1474 VPRINTK("port %u\n", i);
1475 } else {
1476 VPRINTK("port %u (no irq)\n", i);
1477 if (ata_ratelimit())
1478 dev_printk(KERN_WARNING, host->dev,
1479 "interrupt on disabled port %u\n", i);
1480 }
1481
1482 irq_ack |= (1 << i);
1483 }
1484
1485 if (irq_ack) {
1486 writel(irq_ack, mmio + HOST_IRQ_STAT);
1487 handled = 1;
1488 }
1489
1490 spin_unlock(&host->lock);
1491
1492 VPRINTK("EXIT\n");
1493
1494 return IRQ_RETVAL(handled);
1495 }
1496
1497 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1498 {
1499 struct ata_port *ap = qc->ap;
1500 void __iomem *port_mmio = ahci_port_base(ap);
1501
1502 if (qc->tf.protocol == ATA_PROT_NCQ)
1503 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1504 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1505 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1506
1507 return 0;
1508 }
1509
1510 static void ahci_freeze(struct ata_port *ap)
1511 {
1512 void __iomem *port_mmio = ahci_port_base(ap);
1513
1514 /* turn IRQ off */
1515 writel(0, port_mmio + PORT_IRQ_MASK);
1516 }
1517
1518 static void ahci_thaw(struct ata_port *ap)
1519 {
1520 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1521 void __iomem *port_mmio = ahci_port_base(ap);
1522 u32 tmp;
1523
1524 /* clear IRQ */
1525 tmp = readl(port_mmio + PORT_IRQ_STAT);
1526 writel(tmp, port_mmio + PORT_IRQ_STAT);
1527 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1528
1529 /* turn IRQ back on */
1530 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1531 }
1532
1533 static void ahci_error_handler(struct ata_port *ap)
1534 {
1535 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1536 /* restart engine */
1537 ahci_stop_engine(ap);
1538 ahci_start_engine(ap);
1539 }
1540
1541 /* perform recovery */
1542 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
1543 ahci_postreset);
1544 }
1545
1546 static void ahci_vt8251_error_handler(struct ata_port *ap)
1547 {
1548 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1549 /* restart engine */
1550 ahci_stop_engine(ap);
1551 ahci_start_engine(ap);
1552 }
1553
1554 /* perform recovery */
1555 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1556 ahci_postreset);
1557 }
1558
1559 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1560 {
1561 struct ata_port *ap = qc->ap;
1562
1563 /* make DMA engine forget about the failed command */
1564 if (qc->flags & ATA_QCFLAG_FAILED)
1565 ahci_kick_engine(ap, 1);
1566 }
1567
1568 static int ahci_port_resume(struct ata_port *ap)
1569 {
1570 ahci_power_up(ap);
1571 ahci_start_port(ap);
1572
1573 return 0;
1574 }
1575
1576 #ifdef CONFIG_PM
1577 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1578 {
1579 const char *emsg = NULL;
1580 int rc;
1581
1582 rc = ahci_deinit_port(ap, &emsg);
1583 if (rc == 0)
1584 ahci_power_down(ap);
1585 else {
1586 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1587 ahci_start_port(ap);
1588 }
1589
1590 return rc;
1591 }
1592
1593 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1594 {
1595 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1596 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1597 u32 ctl;
1598
1599 if (mesg.event == PM_EVENT_SUSPEND) {
1600 /* AHCI spec rev1.1 section 8.3.3:
1601 * Software must disable interrupts prior to requesting a
1602 * transition of the HBA to D3 state.
1603 */
1604 ctl = readl(mmio + HOST_CTL);
1605 ctl &= ~HOST_IRQ_EN;
1606 writel(ctl, mmio + HOST_CTL);
1607 readl(mmio + HOST_CTL); /* flush */
1608 }
1609
1610 return ata_pci_device_suspend(pdev, mesg);
1611 }
1612
1613 static int ahci_pci_device_resume(struct pci_dev *pdev)
1614 {
1615 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1616 int rc;
1617
1618 rc = ata_pci_device_do_resume(pdev);
1619 if (rc)
1620 return rc;
1621
1622 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1623 rc = ahci_reset_controller(host);
1624 if (rc)
1625 return rc;
1626
1627 ahci_init_controller(host);
1628 }
1629
1630 ata_host_resume(host);
1631
1632 return 0;
1633 }
1634 #endif
1635
1636 static int ahci_port_start(struct ata_port *ap)
1637 {
1638 struct device *dev = ap->host->dev;
1639 struct ahci_port_priv *pp;
1640 void *mem;
1641 dma_addr_t mem_dma;
1642 int rc;
1643
1644 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1645 if (!pp)
1646 return -ENOMEM;
1647
1648 rc = ata_pad_alloc(ap, dev);
1649 if (rc)
1650 return rc;
1651
1652 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1653 GFP_KERNEL);
1654 if (!mem)
1655 return -ENOMEM;
1656 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1657
1658 /*
1659 * First item in chunk of DMA memory: 32-slot command table,
1660 * 32 bytes each in size
1661 */
1662 pp->cmd_slot = mem;
1663 pp->cmd_slot_dma = mem_dma;
1664
1665 mem += AHCI_CMD_SLOT_SZ;
1666 mem_dma += AHCI_CMD_SLOT_SZ;
1667
1668 /*
1669 * Second item: Received-FIS area
1670 */
1671 pp->rx_fis = mem;
1672 pp->rx_fis_dma = mem_dma;
1673
1674 mem += AHCI_RX_FIS_SZ;
1675 mem_dma += AHCI_RX_FIS_SZ;
1676
1677 /*
1678 * Third item: data area for storing a single command
1679 * and its scatter-gather table
1680 */
1681 pp->cmd_tbl = mem;
1682 pp->cmd_tbl_dma = mem_dma;
1683
1684 ap->private_data = pp;
1685
1686 /* engage engines, captain */
1687 return ahci_port_resume(ap);
1688 }
1689
1690 static void ahci_port_stop(struct ata_port *ap)
1691 {
1692 const char *emsg = NULL;
1693 int rc;
1694
1695 /* de-initialize port */
1696 rc = ahci_deinit_port(ap, &emsg);
1697 if (rc)
1698 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1699 }
1700
1701 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1702 {
1703 int rc;
1704
1705 if (using_dac &&
1706 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1707 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1708 if (rc) {
1709 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1710 if (rc) {
1711 dev_printk(KERN_ERR, &pdev->dev,
1712 "64-bit DMA enable failed\n");
1713 return rc;
1714 }
1715 }
1716 } else {
1717 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1718 if (rc) {
1719 dev_printk(KERN_ERR, &pdev->dev,
1720 "32-bit DMA enable failed\n");
1721 return rc;
1722 }
1723 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1724 if (rc) {
1725 dev_printk(KERN_ERR, &pdev->dev,
1726 "32-bit consistent DMA enable failed\n");
1727 return rc;
1728 }
1729 }
1730 return 0;
1731 }
1732
1733 static void ahci_print_info(struct ata_host *host)
1734 {
1735 struct ahci_host_priv *hpriv = host->private_data;
1736 struct pci_dev *pdev = to_pci_dev(host->dev);
1737 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1738 u32 vers, cap, impl, speed;
1739 const char *speed_s;
1740 u16 cc;
1741 const char *scc_s;
1742
1743 vers = readl(mmio + HOST_VERSION);
1744 cap = hpriv->cap;
1745 impl = hpriv->port_map;
1746
1747 speed = (cap >> 20) & 0xf;
1748 if (speed == 1)
1749 speed_s = "1.5";
1750 else if (speed == 2)
1751 speed_s = "3";
1752 else
1753 speed_s = "?";
1754
1755 pci_read_config_word(pdev, 0x0a, &cc);
1756 if (cc == PCI_CLASS_STORAGE_IDE)
1757 scc_s = "IDE";
1758 else if (cc == PCI_CLASS_STORAGE_SATA)
1759 scc_s = "SATA";
1760 else if (cc == PCI_CLASS_STORAGE_RAID)
1761 scc_s = "RAID";
1762 else
1763 scc_s = "unknown";
1764
1765 dev_printk(KERN_INFO, &pdev->dev,
1766 "AHCI %02x%02x.%02x%02x "
1767 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1768 ,
1769
1770 (vers >> 24) & 0xff,
1771 (vers >> 16) & 0xff,
1772 (vers >> 8) & 0xff,
1773 vers & 0xff,
1774
1775 ((cap >> 8) & 0x1f) + 1,
1776 (cap & 0x1f) + 1,
1777 speed_s,
1778 impl,
1779 scc_s);
1780
1781 dev_printk(KERN_INFO, &pdev->dev,
1782 "flags: "
1783 "%s%s%s%s%s%s%s"
1784 "%s%s%s%s%s%s%s\n"
1785 ,
1786
1787 cap & (1 << 31) ? "64bit " : "",
1788 cap & (1 << 30) ? "ncq " : "",
1789 cap & (1 << 29) ? "sntf " : "",
1790 cap & (1 << 28) ? "ilck " : "",
1791 cap & (1 << 27) ? "stag " : "",
1792 cap & (1 << 26) ? "pm " : "",
1793 cap & (1 << 25) ? "led " : "",
1794
1795 cap & (1 << 24) ? "clo " : "",
1796 cap & (1 << 19) ? "nz " : "",
1797 cap & (1 << 18) ? "only " : "",
1798 cap & (1 << 17) ? "pmp " : "",
1799 cap & (1 << 15) ? "pio " : "",
1800 cap & (1 << 14) ? "slum " : "",
1801 cap & (1 << 13) ? "part " : ""
1802 );
1803 }
1804
1805 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1806 {
1807 static int printed_version;
1808 struct ata_port_info pi = ahci_port_info[ent->driver_data];
1809 const struct ata_port_info *ppi[] = { &pi, NULL };
1810 struct device *dev = &pdev->dev;
1811 struct ahci_host_priv *hpriv;
1812 struct ata_host *host;
1813 int i, rc;
1814
1815 VPRINTK("ENTER\n");
1816
1817 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1818
1819 if (!printed_version++)
1820 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1821
1822 /* acquire resources */
1823 rc = pcim_enable_device(pdev);
1824 if (rc)
1825 return rc;
1826
1827 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1828 if (rc == -EBUSY)
1829 pcim_pin_device(pdev);
1830 if (rc)
1831 return rc;
1832
1833 if ((pi.flags & AHCI_FLAG_NO_MSI) || pci_enable_msi(pdev))
1834 pci_intx(pdev, 1);
1835
1836 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1837 if (!hpriv)
1838 return -ENOMEM;
1839
1840 /* save initial config */
1841 ahci_save_initial_config(pdev, &pi, hpriv);
1842
1843 /* prepare host */
1844 if (hpriv->cap & HOST_CAP_NCQ)
1845 pi.flags |= ATA_FLAG_NCQ;
1846
1847 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
1848 if (!host)
1849 return -ENOMEM;
1850 host->iomap = pcim_iomap_table(pdev);
1851 host->private_data = hpriv;
1852
1853 for (i = 0; i < host->n_ports; i++) {
1854 struct ata_port *ap = host->ports[i];
1855 void __iomem *port_mmio = ahci_port_base(ap);
1856
1857 /* standard SATA port setup */
1858 if (hpriv->port_map & (1 << i))
1859 ap->ioaddr.cmd_addr = port_mmio;
1860
1861 /* disabled/not-implemented port */
1862 else
1863 ap->ops = &ata_dummy_port_ops;
1864 }
1865
1866 /* initialize adapter */
1867 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1868 if (rc)
1869 return rc;
1870
1871 rc = ahci_reset_controller(host);
1872 if (rc)
1873 return rc;
1874
1875 ahci_init_controller(host);
1876 ahci_print_info(host);
1877
1878 pci_set_master(pdev);
1879 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1880 &ahci_sht);
1881 }
1882
1883 static int __init ahci_init(void)
1884 {
1885 return pci_register_driver(&ahci_pci_driver);
1886 }
1887
1888 static void __exit ahci_exit(void)
1889 {
1890 pci_unregister_driver(&ahci_pci_driver);
1891 }
1892
1893
1894 MODULE_AUTHOR("Jeff Garzik");
1895 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1896 MODULE_LICENSE("GPL");
1897 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1898 MODULE_VERSION(DRV_VERSION);
1899
1900 module_init(ahci_init);
1901 module_exit(ahci_exit);
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