2 * ALSA SoC TLV320AIC3X codec driver
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33.
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 is as follows:
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
40 #include <linux/i2c.h>
41 #include <linux/platform_device.h>
42 #include <sound/core.h>
43 #include <sound/pcm.h>
44 #include <sound/pcm_params.h>
45 #include <sound/soc.h>
46 #include <sound/soc-dapm.h>
47 #include <sound/initval.h>
49 #include "tlv320aic3x.h"
51 #define AIC3X_VERSION "0.2"
53 /* codec private data */
60 * AIC3X register cache
61 * We can't read the AIC3X register space when we are
62 * using 2 wire for device control, so we cache them instead.
63 * There is no point in caching the reset register
65 static const u8 aic3x_reg
[AIC3X_CACHEREGNUM
] = {
66 0x00, 0x00, 0x00, 0x10, /* 0 */
67 0x04, 0x00, 0x00, 0x00, /* 4 */
68 0x00, 0x00, 0x00, 0x01, /* 8 */
69 0x00, 0x00, 0x00, 0x80, /* 12 */
70 0x80, 0xff, 0xff, 0x78, /* 16 */
71 0x78, 0x78, 0x78, 0x78, /* 20 */
72 0x78, 0x00, 0x00, 0xfe, /* 24 */
73 0x00, 0x00, 0xfe, 0x00, /* 28 */
74 0x18, 0x18, 0x00, 0x00, /* 32 */
75 0x00, 0x00, 0x00, 0x00, /* 36 */
76 0x00, 0x00, 0x00, 0x80, /* 40 */
77 0x80, 0x00, 0x00, 0x00, /* 44 */
78 0x00, 0x00, 0x00, 0x04, /* 48 */
79 0x00, 0x00, 0x00, 0x00, /* 52 */
80 0x00, 0x00, 0x04, 0x00, /* 56 */
81 0x00, 0x00, 0x00, 0x00, /* 60 */
82 0x00, 0x04, 0x00, 0x00, /* 64 */
83 0x00, 0x00, 0x00, 0x00, /* 68 */
84 0x04, 0x00, 0x00, 0x00, /* 72 */
85 0x00, 0x00, 0x00, 0x00, /* 76 */
86 0x00, 0x00, 0x00, 0x00, /* 80 */
87 0x00, 0x00, 0x00, 0x00, /* 84 */
88 0x00, 0x00, 0x00, 0x00, /* 88 */
89 0x00, 0x00, 0x00, 0x00, /* 92 */
90 0x00, 0x00, 0x00, 0x00, /* 96 */
91 0x00, 0x00, 0x02, /* 100 */
95 * read aic3x register cache
97 static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec
*codec
,
100 u8
*cache
= codec
->reg_cache
;
101 if (reg
>= AIC3X_CACHEREGNUM
)
107 * write aic3x register cache
109 static inline void aic3x_write_reg_cache(struct snd_soc_codec
*codec
,
112 u8
*cache
= codec
->reg_cache
;
113 if (reg
>= AIC3X_CACHEREGNUM
)
119 * write to the aic3x register space
121 static int aic3x_write(struct snd_soc_codec
*codec
, unsigned int reg
,
127 * D15..D8 aic3x register offset
128 * D7...D0 register data
130 data
[0] = reg
& 0xff;
131 data
[1] = value
& 0xff;
133 aic3x_write_reg_cache(codec
, data
[0], data
[1]);
134 if (codec
->hw_write(codec
->control_data
, data
, 2) == 2)
141 * read from the aic3x register space
143 static int aic3x_read(struct snd_soc_codec
*codec
, unsigned int reg
,
147 if (codec
->hw_read(codec
->control_data
, value
, 1) != 1)
150 aic3x_write_reg_cache(codec
, reg
, *value
);
154 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
155 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
156 .info = snd_soc_info_volsw, \
157 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
158 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
161 * All input lines are connected when !0xf and disconnected with 0xf bit field,
162 * so we have to use specific dapm_put call for input mixer
164 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol
*kcontrol
,
165 struct snd_ctl_elem_value
*ucontrol
)
167 struct snd_soc_dapm_widget
*widget
= snd_kcontrol_chip(kcontrol
);
168 int reg
= kcontrol
->private_value
& 0xff;
169 int shift
= (kcontrol
->private_value
>> 8) & 0x0f;
170 int mask
= (kcontrol
->private_value
>> 16) & 0xff;
171 int invert
= (kcontrol
->private_value
>> 24) & 0x01;
172 unsigned short val
, val_mask
;
174 struct snd_soc_dapm_path
*path
;
177 val
= (ucontrol
->value
.integer
.value
[0] & mask
);
185 val_mask
= mask
<< shift
;
188 mutex_lock(&widget
->codec
->mutex
);
190 if (snd_soc_test_bits(widget
->codec
, reg
, val_mask
, val
)) {
191 /* find dapm widget path assoc with kcontrol */
192 list_for_each_entry(path
, &widget
->codec
->dapm_paths
, list
) {
193 if (path
->kcontrol
!= kcontrol
)
196 /* found, now check type */
200 path
->connect
= invert
? 0 : 1;
202 /* old connection must be powered down */
203 path
->connect
= invert
? 1 : 0;
208 snd_soc_dapm_sync(widget
->codec
);
211 ret
= snd_soc_update_bits(widget
->codec
, reg
, val_mask
, val
);
213 mutex_unlock(&widget
->codec
->mutex
);
217 static const char *aic3x_left_dac_mux
[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
218 static const char *aic3x_right_dac_mux
[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
219 static const char *aic3x_left_hpcom_mux
[] =
220 { "differential of HPLOUT", "constant VCM", "single-ended" };
221 static const char *aic3x_right_hpcom_mux
[] =
222 { "differential of HPROUT", "constant VCM", "single-ended",
223 "differential of HPLCOM", "external feedback" };
224 static const char *aic3x_linein_mode_mux
[] = { "single-ended", "differential" };
225 static const char *aic3x_adc_hpf
[] =
226 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
230 #define LHPCOM_ENUM 2
231 #define RHPCOM_ENUM 3
232 #define LINE1L_ENUM 4
233 #define LINE1R_ENUM 5
234 #define LINE2L_ENUM 6
235 #define LINE2R_ENUM 7
236 #define ADC_HPF_ENUM 8
238 static const struct soc_enum aic3x_enum
[] = {
239 SOC_ENUM_SINGLE(DAC_LINE_MUX
, 6, 3, aic3x_left_dac_mux
),
240 SOC_ENUM_SINGLE(DAC_LINE_MUX
, 4, 3, aic3x_right_dac_mux
),
241 SOC_ENUM_SINGLE(HPLCOM_CFG
, 4, 3, aic3x_left_hpcom_mux
),
242 SOC_ENUM_SINGLE(HPRCOM_CFG
, 3, 5, aic3x_right_hpcom_mux
),
243 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL
, 7, 2, aic3x_linein_mode_mux
),
244 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL
, 7, 2, aic3x_linein_mode_mux
),
245 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL
, 7, 2, aic3x_linein_mode_mux
),
246 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL
, 7, 2, aic3x_linein_mode_mux
),
247 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL
, 6, 4, 4, aic3x_adc_hpf
),
250 static const struct snd_kcontrol_new aic3x_snd_controls
[] = {
252 SOC_DOUBLE_R("PCM Playback Volume", LDAC_VOL
, RDAC_VOL
, 0, 0x7f, 1),
254 SOC_DOUBLE_R("Line DAC Playback Volume", DACL1_2_LLOPM_VOL
,
255 DACR1_2_RLOPM_VOL
, 0, 0x7f, 1),
256 SOC_DOUBLE_R("Line DAC Playback Switch", LLOPM_CTRL
, RLOPM_CTRL
, 3,
258 SOC_DOUBLE_R("Line PGA Bypass Playback Volume", PGAL_2_LLOPM_VOL
,
259 PGAR_2_RLOPM_VOL
, 0, 0x7f, 1),
260 SOC_DOUBLE_R("Line Line2 Bypass Playback Volume", LINE2L_2_LLOPM_VOL
,
261 LINE2R_2_RLOPM_VOL
, 0, 0x7f, 1),
263 SOC_DOUBLE_R("Mono DAC Playback Volume", DACL1_2_MONOLOPM_VOL
,
264 DACR1_2_MONOLOPM_VOL
, 0, 0x7f, 1),
265 SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL
, 3, 0x01, 0),
266 SOC_DOUBLE_R("Mono PGA Bypass Playback Volume", PGAL_2_MONOLOPM_VOL
,
267 PGAR_2_MONOLOPM_VOL
, 0, 0x7f, 1),
268 SOC_DOUBLE_R("Mono Line2 Bypass Playback Volume", LINE2L_2_MONOLOPM_VOL
,
269 LINE2R_2_MONOLOPM_VOL
, 0, 0x7f, 1),
271 SOC_DOUBLE_R("HP DAC Playback Volume", DACL1_2_HPLOUT_VOL
,
272 DACR1_2_HPROUT_VOL
, 0, 0x7f, 1),
273 SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL
, HPROUT_CTRL
, 3,
275 SOC_SINGLE("HPL PGA Bypass Playback Volume", PGAL_2_HPLOUT_VOL
,
277 SOC_SINGLE("HPR PGA Bypass Playback Volume", PGAL_2_HPROUT_VOL
,
279 SOC_DOUBLE_R("HP Line2 Bypass Playback Volume", LINE2L_2_HPLOUT_VOL
,
280 LINE2R_2_HPROUT_VOL
, 0, 0x7f, 1),
282 SOC_DOUBLE_R("HPCOM DAC Playback Volume", DACL1_2_HPLCOM_VOL
,
283 DACR1_2_HPRCOM_VOL
, 0, 0x7f, 1),
284 SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL
, HPRCOM_CTRL
, 3,
286 SOC_SINGLE("HPLCOM PGA Bypass Playback Volume", PGAL_2_HPLCOM_VOL
,
288 SOC_SINGLE("HPRCOM PGA Bypass Playback Volume", PGAL_2_HPRCOM_VOL
,
290 SOC_DOUBLE_R("HPCOM Line2 Bypass Playback Volume", LINE2L_2_HPLCOM_VOL
,
291 LINE2R_2_HPRCOM_VOL
, 0, 0x7f, 1),
294 * Note: enable Automatic input Gain Controller with care. It can
295 * adjust PGA to max value when ADC is on and will never go back.
297 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A
, RAGC_CTRL_A
, 7, 0x01, 0),
300 SOC_DOUBLE_R("PGA Capture Volume", LADC_VOL
, RADC_VOL
, 0, 0x7f, 0),
301 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL
, RADC_VOL
, 7, 0x01, 1),
303 SOC_ENUM("ADC HPF Cut-off", aic3x_enum
[ADC_HPF_ENUM
]),
306 /* add non dapm controls */
307 static int aic3x_add_controls(struct snd_soc_codec
*codec
)
311 for (i
= 0; i
< ARRAY_SIZE(aic3x_snd_controls
); i
++) {
312 err
= snd_ctl_add(codec
->card
,
313 snd_soc_cnew(&aic3x_snd_controls
[i
],
323 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls
=
324 SOC_DAPM_ENUM("Route", aic3x_enum
[LDAC_ENUM
]);
327 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls
=
328 SOC_DAPM_ENUM("Route", aic3x_enum
[RDAC_ENUM
]);
331 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls
=
332 SOC_DAPM_ENUM("Route", aic3x_enum
[LHPCOM_ENUM
]);
334 /* Right HPCOM Mux */
335 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls
=
336 SOC_DAPM_ENUM("Route", aic3x_enum
[RHPCOM_ENUM
]);
338 /* Left DAC_L1 Mixer */
339 static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls
[] = {
340 SOC_DAPM_SINGLE("LineL Switch", DACL1_2_LLOPM_VOL
, 7, 1, 0),
341 SOC_DAPM_SINGLE("LineR Switch", DACL1_2_RLOPM_VOL
, 7, 1, 0),
342 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL
, 7, 1, 0),
343 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL
, 7, 1, 0),
344 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL
, 7, 1, 0),
347 /* Right DAC_R1 Mixer */
348 static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls
[] = {
349 SOC_DAPM_SINGLE("LineL Switch", DACR1_2_LLOPM_VOL
, 7, 1, 0),
350 SOC_DAPM_SINGLE("LineR Switch", DACR1_2_RLOPM_VOL
, 7, 1, 0),
351 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL
, 7, 1, 0),
352 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL
, 7, 1, 0),
353 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL
, 7, 1, 0),
357 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls
[] = {
358 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL
, 3, 1, 1),
359 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL
, 3, 1, 1),
360 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL
, 3, 1, 1),
361 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL
, 4, 1, 1),
362 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL
, 0, 1, 1),
365 /* Right PGA Mixer */
366 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls
[] = {
367 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL
, 3, 1, 1),
368 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL
, 3, 1, 1),
369 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL
, 3, 1, 1),
370 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL
, 4, 1, 1),
371 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL
, 0, 1, 1),
375 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls
=
376 SOC_DAPM_ENUM("Route", aic3x_enum
[LINE1L_ENUM
]);
378 /* Right Line1 Mux */
379 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls
=
380 SOC_DAPM_ENUM("Route", aic3x_enum
[LINE1R_ENUM
]);
383 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls
=
384 SOC_DAPM_ENUM("Route", aic3x_enum
[LINE2L_ENUM
]);
386 /* Right Line2 Mux */
387 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls
=
388 SOC_DAPM_ENUM("Route", aic3x_enum
[LINE2R_ENUM
]);
390 /* Left PGA Bypass Mixer */
391 static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls
[] = {
392 SOC_DAPM_SINGLE("LineL Switch", PGAL_2_LLOPM_VOL
, 7, 1, 0),
393 SOC_DAPM_SINGLE("LineR Switch", PGAL_2_RLOPM_VOL
, 7, 1, 0),
394 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL
, 7, 1, 0),
395 SOC_DAPM_SINGLE("HPL Switch", PGAL_2_HPLOUT_VOL
, 7, 1, 0),
396 SOC_DAPM_SINGLE("HPR Switch", PGAL_2_HPROUT_VOL
, 7, 1, 0),
397 SOC_DAPM_SINGLE("HPLCOM Switch", PGAL_2_HPLCOM_VOL
, 7, 1, 0),
398 SOC_DAPM_SINGLE("HPRCOM Switch", PGAL_2_HPRCOM_VOL
, 7, 1, 0),
401 /* Right PGA Bypass Mixer */
402 static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls
[] = {
403 SOC_DAPM_SINGLE("LineL Switch", PGAR_2_LLOPM_VOL
, 7, 1, 0),
404 SOC_DAPM_SINGLE("LineR Switch", PGAR_2_RLOPM_VOL
, 7, 1, 0),
405 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL
, 7, 1, 0),
406 SOC_DAPM_SINGLE("HPL Switch", PGAR_2_HPLOUT_VOL
, 7, 1, 0),
407 SOC_DAPM_SINGLE("HPR Switch", PGAR_2_HPROUT_VOL
, 7, 1, 0),
408 SOC_DAPM_SINGLE("HPLCOM Switch", PGAR_2_HPLCOM_VOL
, 7, 1, 0),
409 SOC_DAPM_SINGLE("HPRCOM Switch", PGAR_2_HPRCOM_VOL
, 7, 1, 0),
412 /* Left Line2 Bypass Mixer */
413 static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls
[] = {
414 SOC_DAPM_SINGLE("LineL Switch", LINE2L_2_LLOPM_VOL
, 7, 1, 0),
415 SOC_DAPM_SINGLE("LineR Switch", LINE2L_2_RLOPM_VOL
, 7, 1, 0),
416 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL
, 7, 1, 0),
417 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL
, 7, 1, 0),
418 SOC_DAPM_SINGLE("HPLCOM Switch", LINE2L_2_HPLCOM_VOL
, 7, 1, 0),
421 /* Right Line2 Bypass Mixer */
422 static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls
[] = {
423 SOC_DAPM_SINGLE("LineL Switch", LINE2R_2_LLOPM_VOL
, 7, 1, 0),
424 SOC_DAPM_SINGLE("LineR Switch", LINE2R_2_RLOPM_VOL
, 7, 1, 0),
425 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL
, 7, 1, 0),
426 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL
, 7, 1, 0),
427 SOC_DAPM_SINGLE("HPRCOM Switch", LINE2R_2_HPRCOM_VOL
, 7, 1, 0),
430 static const struct snd_soc_dapm_widget aic3x_dapm_widgets
[] = {
431 /* Left DAC to Left Outputs */
432 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR
, 7, 0),
433 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM
, 0, 0,
434 &aic3x_left_dac_mux_controls
),
435 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM
, 0, 0,
436 &aic3x_left_dac_mixer_controls
[0],
437 ARRAY_SIZE(aic3x_left_dac_mixer_controls
)),
438 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM
, 0, 0,
439 &aic3x_left_hpcom_mux_controls
),
440 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL
, 0, 0, NULL
, 0),
441 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL
, 0, 0, NULL
, 0),
442 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL
, 0, 0, NULL
, 0),
444 /* Right DAC to Right Outputs */
445 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR
, 6, 0),
446 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM
, 0, 0,
447 &aic3x_right_dac_mux_controls
),
448 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM
, 0, 0,
449 &aic3x_right_dac_mixer_controls
[0],
450 ARRAY_SIZE(aic3x_right_dac_mixer_controls
)),
451 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM
, 0, 0,
452 &aic3x_right_hpcom_mux_controls
),
453 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL
, 0, 0, NULL
, 0),
454 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL
, 0, 0, NULL
, 0),
455 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL
, 0, 0, NULL
, 0),
458 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL
, 0, 0, NULL
, 0),
460 /* Inputs to Left ADC */
461 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL
, 2, 0),
462 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM
, 0, 0,
463 &aic3x_left_pga_mixer_controls
[0],
464 ARRAY_SIZE(aic3x_left_pga_mixer_controls
)),
465 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM
, 0, 0,
466 &aic3x_left_line1_mux_controls
),
467 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM
, 0, 0,
468 &aic3x_left_line1_mux_controls
),
469 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM
, 0, 0,
470 &aic3x_left_line2_mux_controls
),
472 /* Inputs to Right ADC */
473 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
474 LINE1R_2_RADC_CTRL
, 2, 0),
475 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM
, 0, 0,
476 &aic3x_right_pga_mixer_controls
[0],
477 ARRAY_SIZE(aic3x_right_pga_mixer_controls
)),
478 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM
, 0, 0,
479 &aic3x_right_line1_mux_controls
),
480 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM
, 0, 0,
481 &aic3x_right_line1_mux_controls
),
482 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM
, 0, 0,
483 &aic3x_right_line2_mux_controls
),
486 * Not a real mic bias widget but similar function. This is for dynamic
487 * control of GPIO1 digital mic modulator clock output function when
490 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "GPIO1 dmic modclk",
491 AIC3X_GPIO1_REG
, 4, 0xf,
492 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK
,
493 AIC3X_GPIO1_FUNC_DISABLED
),
496 * Also similar function like mic bias. Selects digital mic with
497 * configurable oversampling rate instead of ADC converter.
499 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "DMic Rate 128",
500 AIC3X_ASD_INTF_CTRLA
, 0, 3, 1, 0),
501 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "DMic Rate 64",
502 AIC3X_ASD_INTF_CTRLA
, 0, 3, 2, 0),
503 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "DMic Rate 32",
504 AIC3X_ASD_INTF_CTRLA
, 0, 3, 3, 0),
507 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "Mic Bias 2V",
508 MICBIAS_CTRL
, 6, 3, 1, 0),
509 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "Mic Bias 2.5V",
510 MICBIAS_CTRL
, 6, 3, 2, 0),
511 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "Mic Bias AVDD",
512 MICBIAS_CTRL
, 6, 3, 3, 0),
514 /* Left PGA to Left Output bypass */
515 SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM
, 0, 0,
516 &aic3x_left_pga_bp_mixer_controls
[0],
517 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls
)),
519 /* Right PGA to Right Output bypass */
520 SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM
, 0, 0,
521 &aic3x_right_pga_bp_mixer_controls
[0],
522 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls
)),
524 /* Left Line2 to Left Output bypass */
525 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM
, 0, 0,
526 &aic3x_left_line2_bp_mixer_controls
[0],
527 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls
)),
529 /* Right Line2 to Right Output bypass */
530 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM
, 0, 0,
531 &aic3x_right_line2_bp_mixer_controls
[0],
532 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls
)),
534 SND_SOC_DAPM_OUTPUT("LLOUT"),
535 SND_SOC_DAPM_OUTPUT("RLOUT"),
536 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
537 SND_SOC_DAPM_OUTPUT("HPLOUT"),
538 SND_SOC_DAPM_OUTPUT("HPROUT"),
539 SND_SOC_DAPM_OUTPUT("HPLCOM"),
540 SND_SOC_DAPM_OUTPUT("HPRCOM"),
542 SND_SOC_DAPM_INPUT("MIC3L"),
543 SND_SOC_DAPM_INPUT("MIC3R"),
544 SND_SOC_DAPM_INPUT("LINE1L"),
545 SND_SOC_DAPM_INPUT("LINE1R"),
546 SND_SOC_DAPM_INPUT("LINE2L"),
547 SND_SOC_DAPM_INPUT("LINE2R"),
550 static const struct snd_soc_dapm_route intercon
[] = {
552 {"Left DAC Mux", "DAC_L1", "Left DAC"},
553 {"Left DAC Mux", "DAC_L2", "Left DAC"},
554 {"Left DAC Mux", "DAC_L3", "Left DAC"},
556 {"Left DAC_L1 Mixer", "LineL Switch", "Left DAC Mux"},
557 {"Left DAC_L1 Mixer", "LineR Switch", "Left DAC Mux"},
558 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
559 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
560 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
561 {"Left Line Out", NULL
, "Left DAC Mux"},
562 {"Left HP Out", NULL
, "Left DAC Mux"},
564 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
565 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
566 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
568 {"Left Line Out", NULL
, "Left DAC_L1 Mixer"},
569 {"Mono Out", NULL
, "Left DAC_L1 Mixer"},
570 {"Left HP Out", NULL
, "Left DAC_L1 Mixer"},
571 {"Left HP Com", NULL
, "Left HPCOM Mux"},
573 {"LLOUT", NULL
, "Left Line Out"},
574 {"LLOUT", NULL
, "Left Line Out"},
575 {"HPLOUT", NULL
, "Left HP Out"},
576 {"HPLCOM", NULL
, "Left HP Com"},
579 {"Right DAC Mux", "DAC_R1", "Right DAC"},
580 {"Right DAC Mux", "DAC_R2", "Right DAC"},
581 {"Right DAC Mux", "DAC_R3", "Right DAC"},
583 {"Right DAC_R1 Mixer", "LineL Switch", "Right DAC Mux"},
584 {"Right DAC_R1 Mixer", "LineR Switch", "Right DAC Mux"},
585 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
586 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
587 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
588 {"Right Line Out", NULL
, "Right DAC Mux"},
589 {"Right HP Out", NULL
, "Right DAC Mux"},
591 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
592 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
593 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
594 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
595 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
597 {"Right Line Out", NULL
, "Right DAC_R1 Mixer"},
598 {"Mono Out", NULL
, "Right DAC_R1 Mixer"},
599 {"Right HP Out", NULL
, "Right DAC_R1 Mixer"},
600 {"Right HP Com", NULL
, "Right HPCOM Mux"},
602 {"RLOUT", NULL
, "Right Line Out"},
603 {"RLOUT", NULL
, "Right Line Out"},
604 {"HPROUT", NULL
, "Right HP Out"},
605 {"HPRCOM", NULL
, "Right HP Com"},
608 {"MONO_LOUT", NULL
, "Mono Out"},
609 {"MONO_LOUT", NULL
, "Mono Out"},
612 {"Left Line1L Mux", "single-ended", "LINE1L"},
613 {"Left Line1L Mux", "differential", "LINE1L"},
615 {"Left Line2L Mux", "single-ended", "LINE2L"},
616 {"Left Line2L Mux", "differential", "LINE2L"},
618 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
619 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
620 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
621 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
622 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
624 {"Left ADC", NULL
, "Left PGA Mixer"},
625 {"Left ADC", NULL
, "GPIO1 dmic modclk"},
628 {"Right Line1R Mux", "single-ended", "LINE1R"},
629 {"Right Line1R Mux", "differential", "LINE1R"},
631 {"Right Line2R Mux", "single-ended", "LINE2R"},
632 {"Right Line2R Mux", "differential", "LINE2R"},
634 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
635 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
636 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
637 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
638 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
640 {"Right ADC", NULL
, "Right PGA Mixer"},
641 {"Right ADC", NULL
, "GPIO1 dmic modclk"},
643 /* Left PGA Bypass */
644 {"Left PGA Bypass Mixer", "LineL Switch", "Left PGA Mixer"},
645 {"Left PGA Bypass Mixer", "LineR Switch", "Left PGA Mixer"},
646 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
647 {"Left PGA Bypass Mixer", "HPL Switch", "Left PGA Mixer"},
648 {"Left PGA Bypass Mixer", "HPR Switch", "Left PGA Mixer"},
649 {"Left PGA Bypass Mixer", "HPLCOM Switch", "Left PGA Mixer"},
650 {"Left PGA Bypass Mixer", "HPRCOM Switch", "Left PGA Mixer"},
652 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
653 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
654 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
656 {"Left Line Out", NULL
, "Left PGA Bypass Mixer"},
657 {"Mono Out", NULL
, "Left PGA Bypass Mixer"},
658 {"Left HP Out", NULL
, "Left PGA Bypass Mixer"},
660 /* Right PGA Bypass */
661 {"Right PGA Bypass Mixer", "LineL Switch", "Right PGA Mixer"},
662 {"Right PGA Bypass Mixer", "LineR Switch", "Right PGA Mixer"},
663 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
664 {"Right PGA Bypass Mixer", "HPL Switch", "Right PGA Mixer"},
665 {"Right PGA Bypass Mixer", "HPR Switch", "Right PGA Mixer"},
666 {"Right PGA Bypass Mixer", "HPLCOM Switch", "Right PGA Mixer"},
667 {"Right PGA Bypass Mixer", "HPRCOM Switch", "Right PGA Mixer"},
669 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
670 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
671 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
672 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
673 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
675 {"Right Line Out", NULL
, "Right PGA Bypass Mixer"},
676 {"Mono Out", NULL
, "Right PGA Bypass Mixer"},
677 {"Right HP Out", NULL
, "Right PGA Bypass Mixer"},
679 /* Left Line2 Bypass */
680 {"Left Line2 Bypass Mixer", "LineL Switch", "Left Line2L Mux"},
681 {"Left Line2 Bypass Mixer", "LineR Switch", "Left Line2L Mux"},
682 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
683 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
684 {"Left Line2 Bypass Mixer", "HPLCOM Switch", "Left Line2L Mux"},
686 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
687 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
688 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
690 {"Left Line Out", NULL
, "Left Line2 Bypass Mixer"},
691 {"Mono Out", NULL
, "Left Line2 Bypass Mixer"},
692 {"Left HP Out", NULL
, "Left Line2 Bypass Mixer"},
694 /* Right Line2 Bypass */
695 {"Right Line2 Bypass Mixer", "LineL Switch", "Right Line2R Mux"},
696 {"Right Line2 Bypass Mixer", "LineR Switch", "Right Line2R Mux"},
697 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
698 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
699 {"Right Line2 Bypass Mixer", "HPRCOM Switch", "Right Line2R Mux"},
701 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
702 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
703 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
704 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
705 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
707 {"Right Line Out", NULL
, "Right Line2 Bypass Mixer"},
708 {"Mono Out", NULL
, "Right Line2 Bypass Mixer"},
709 {"Right HP Out", NULL
, "Right Line2 Bypass Mixer"},
712 * Logical path between digital mic enable and GPIO1 modulator clock
715 {"GPIO1 dmic modclk", NULL
, "DMic Rate 128"},
716 {"GPIO1 dmic modclk", NULL
, "DMic Rate 64"},
717 {"GPIO1 dmic modclk", NULL
, "DMic Rate 32"},
720 static int aic3x_add_widgets(struct snd_soc_codec
*codec
)
722 snd_soc_dapm_new_controls(codec
, aic3x_dapm_widgets
,
723 ARRAY_SIZE(aic3x_dapm_widgets
));
725 /* set up audio path interconnects */
726 snd_soc_dapm_add_routes(codec
, intercon
, ARRAY_SIZE(intercon
));
728 snd_soc_dapm_new_widgets(codec
);
732 static int aic3x_hw_params(struct snd_pcm_substream
*substream
,
733 struct snd_pcm_hw_params
*params
,
734 struct snd_soc_dai
*dai
)
736 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
737 struct snd_soc_device
*socdev
= rtd
->socdev
;
738 struct snd_soc_codec
*codec
= socdev
->codec
;
739 struct aic3x_priv
*aic3x
= codec
->private_data
;
740 int codec_clk
= 0, bypass_pll
= 0, fsref
, last_clk
= 0;
741 u8 data
, r
, p
, pll_q
, pll_p
= 1, pll_r
= 1, pll_j
= 1;
744 /* select data word length */
746 aic3x_read_reg_cache(codec
, AIC3X_ASD_INTF_CTRLB
) & (~(0x3 << 4));
747 switch (params_format(params
)) {
748 case SNDRV_PCM_FORMAT_S16_LE
:
750 case SNDRV_PCM_FORMAT_S20_3LE
:
753 case SNDRV_PCM_FORMAT_S24_LE
:
756 case SNDRV_PCM_FORMAT_S32_LE
:
760 aic3x_write(codec
, AIC3X_ASD_INTF_CTRLB
, data
);
762 /* Fsref can be 44100 or 48000 */
763 fsref
= (params_rate(params
) % 11025 == 0) ? 44100 : 48000;
765 /* Try to find a value for Q which allows us to bypass the PLL and
766 * generate CODEC_CLK directly. */
767 for (pll_q
= 2; pll_q
< 18; pll_q
++)
768 if (aic3x
->sysclk
/ (128 * pll_q
) == fsref
) {
775 aic3x_write(codec
, AIC3X_PLL_PROGA_REG
, pll_q
<< PLLQ_SHIFT
);
776 aic3x_write(codec
, AIC3X_GPIOB_REG
, CODEC_CLKIN_CLKDIV
);
778 aic3x_write(codec
, AIC3X_GPIOB_REG
, CODEC_CLKIN_PLLDIV
);
780 /* Route Left DAC to left channel input and
781 * right DAC to right channel input */
782 data
= (LDAC2LCH
| RDAC2RCH
);
783 data
|= (fsref
== 44100) ? FSREF_44100
: FSREF_48000
;
784 if (params_rate(params
) >= 64000)
785 data
|= DUAL_RATE_MODE
;
786 aic3x_write(codec
, AIC3X_CODEC_DATAPATH_REG
, data
);
788 /* codec sample rate select */
789 data
= (fsref
* 20) / params_rate(params
);
790 if (params_rate(params
) < 64000)
795 aic3x_write(codec
, AIC3X_SAMPLE_RATE_SEL_REG
, data
);
801 * find an apropriate setup for j, d, r and p by iterating over
802 * p and r - j and d are calculated for each fraction.
803 * Up to 128 values are probed, the closest one wins the game.
804 * The sysclk is divided by 1000 to prevent integer overflows.
806 codec_clk
= (2048 * fsref
) / (aic3x
->sysclk
/ 1000);
808 for (r
= 1; r
<= 16; r
++)
809 for (p
= 1; p
<= 8; p
++) {
810 int clk
, tmp
= (codec_clk
* pll_r
* 10) / pll_p
;
817 if (d
!= 0 && aic3x
->sysclk
< 10000000)
820 /* This is actually 1000 * ((j + (d/10000)) * r) / p
821 * The term had to be converted to get rid of the
822 * division by 10000 */
823 clk
= ((10000 * j
* r
) + (d
* r
)) / (10 * p
);
825 /* check whether this values get closer than the best
826 * ones we had before */
827 if (abs(codec_clk
- clk
) < abs(codec_clk
- last_clk
)) {
828 pll_j
= j
; pll_d
= d
; pll_r
= r
; pll_p
= p
;
832 /* Early exit for exact matches */
833 if (clk
== codec_clk
)
838 printk(KERN_ERR
"%s(): unable to setup PLL\n", __func__
);
842 data
= aic3x_read_reg_cache(codec
, AIC3X_PLL_PROGA_REG
);
843 aic3x_write(codec
, AIC3X_PLL_PROGA_REG
, data
| (pll_p
<< PLLP_SHIFT
));
844 aic3x_write(codec
, AIC3X_OVRF_STATUS_AND_PLLR_REG
, pll_r
<< PLLR_SHIFT
);
845 aic3x_write(codec
, AIC3X_PLL_PROGB_REG
, pll_j
<< PLLJ_SHIFT
);
846 aic3x_write(codec
, AIC3X_PLL_PROGC_REG
, (pll_d
>> 6) << PLLD_MSB_SHIFT
);
847 aic3x_write(codec
, AIC3X_PLL_PROGD_REG
,
848 (pll_d
& 0x3F) << PLLD_LSB_SHIFT
);
853 static int aic3x_mute(struct snd_soc_dai
*dai
, int mute
)
855 struct snd_soc_codec
*codec
= dai
->codec
;
856 u8 ldac_reg
= aic3x_read_reg_cache(codec
, LDAC_VOL
) & ~MUTE_ON
;
857 u8 rdac_reg
= aic3x_read_reg_cache(codec
, RDAC_VOL
) & ~MUTE_ON
;
860 aic3x_write(codec
, LDAC_VOL
, ldac_reg
| MUTE_ON
);
861 aic3x_write(codec
, RDAC_VOL
, rdac_reg
| MUTE_ON
);
863 aic3x_write(codec
, LDAC_VOL
, ldac_reg
);
864 aic3x_write(codec
, RDAC_VOL
, rdac_reg
);
870 static int aic3x_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
871 int clk_id
, unsigned int freq
, int dir
)
873 struct snd_soc_codec
*codec
= codec_dai
->codec
;
874 struct aic3x_priv
*aic3x
= codec
->private_data
;
876 aic3x
->sysclk
= freq
;
880 static int aic3x_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
883 struct snd_soc_codec
*codec
= codec_dai
->codec
;
884 struct aic3x_priv
*aic3x
= codec
->private_data
;
885 u8 iface_areg
, iface_breg
;
887 iface_areg
= aic3x_read_reg_cache(codec
, AIC3X_ASD_INTF_CTRLA
) & 0x3f;
888 iface_breg
= aic3x_read_reg_cache(codec
, AIC3X_ASD_INTF_CTRLB
) & 0x3f;
890 /* set master/slave audio interface */
891 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
892 case SND_SOC_DAIFMT_CBM_CFM
:
894 iface_areg
|= BIT_CLK_MASTER
| WORD_CLK_MASTER
;
896 case SND_SOC_DAIFMT_CBS_CFS
:
904 * match both interface format and signal polarities since they
907 switch (fmt
& (SND_SOC_DAIFMT_FORMAT_MASK
|
908 SND_SOC_DAIFMT_INV_MASK
)) {
909 case (SND_SOC_DAIFMT_I2S
| SND_SOC_DAIFMT_NB_NF
):
911 case (SND_SOC_DAIFMT_DSP_B
| SND_SOC_DAIFMT_IB_NF
):
912 iface_breg
|= (0x01 << 6);
914 case (SND_SOC_DAIFMT_RIGHT_J
| SND_SOC_DAIFMT_NB_NF
):
915 iface_breg
|= (0x02 << 6);
917 case (SND_SOC_DAIFMT_LEFT_J
| SND_SOC_DAIFMT_NB_NF
):
918 iface_breg
|= (0x03 << 6);
925 aic3x_write(codec
, AIC3X_ASD_INTF_CTRLA
, iface_areg
);
926 aic3x_write(codec
, AIC3X_ASD_INTF_CTRLB
, iface_breg
);
931 static int aic3x_set_bias_level(struct snd_soc_codec
*codec
,
932 enum snd_soc_bias_level level
)
934 struct aic3x_priv
*aic3x
= codec
->private_data
;
938 case SND_SOC_BIAS_ON
:
939 /* all power is driven by DAPM system */
942 reg
= aic3x_read_reg_cache(codec
, AIC3X_PLL_PROGA_REG
);
943 aic3x_write(codec
, AIC3X_PLL_PROGA_REG
,
947 case SND_SOC_BIAS_PREPARE
:
949 case SND_SOC_BIAS_STANDBY
:
951 * all power is driven by DAPM system,
952 * so output power is safe if bypass was set
956 reg
= aic3x_read_reg_cache(codec
, AIC3X_PLL_PROGA_REG
);
957 aic3x_write(codec
, AIC3X_PLL_PROGA_REG
,
961 case SND_SOC_BIAS_OFF
:
962 /* force all power off */
963 reg
= aic3x_read_reg_cache(codec
, LINE1L_2_LADC_CTRL
);
964 aic3x_write(codec
, LINE1L_2_LADC_CTRL
, reg
& ~LADC_PWR_ON
);
965 reg
= aic3x_read_reg_cache(codec
, LINE1R_2_RADC_CTRL
);
966 aic3x_write(codec
, LINE1R_2_RADC_CTRL
, reg
& ~RADC_PWR_ON
);
968 reg
= aic3x_read_reg_cache(codec
, DAC_PWR
);
969 aic3x_write(codec
, DAC_PWR
, reg
& ~(LDAC_PWR_ON
| RDAC_PWR_ON
));
971 reg
= aic3x_read_reg_cache(codec
, HPLOUT_CTRL
);
972 aic3x_write(codec
, HPLOUT_CTRL
, reg
& ~HPLOUT_PWR_ON
);
973 reg
= aic3x_read_reg_cache(codec
, HPROUT_CTRL
);
974 aic3x_write(codec
, HPROUT_CTRL
, reg
& ~HPROUT_PWR_ON
);
976 reg
= aic3x_read_reg_cache(codec
, HPLCOM_CTRL
);
977 aic3x_write(codec
, HPLCOM_CTRL
, reg
& ~HPLCOM_PWR_ON
);
978 reg
= aic3x_read_reg_cache(codec
, HPRCOM_CTRL
);
979 aic3x_write(codec
, HPRCOM_CTRL
, reg
& ~HPRCOM_PWR_ON
);
981 reg
= aic3x_read_reg_cache(codec
, MONOLOPM_CTRL
);
982 aic3x_write(codec
, MONOLOPM_CTRL
, reg
& ~MONOLOPM_PWR_ON
);
984 reg
= aic3x_read_reg_cache(codec
, LLOPM_CTRL
);
985 aic3x_write(codec
, LLOPM_CTRL
, reg
& ~LLOPM_PWR_ON
);
986 reg
= aic3x_read_reg_cache(codec
, RLOPM_CTRL
);
987 aic3x_write(codec
, RLOPM_CTRL
, reg
& ~RLOPM_PWR_ON
);
991 reg
= aic3x_read_reg_cache(codec
, AIC3X_PLL_PROGA_REG
);
992 aic3x_write(codec
, AIC3X_PLL_PROGA_REG
,
997 codec
->bias_level
= level
;
1002 void aic3x_set_gpio(struct snd_soc_codec
*codec
, int gpio
, int state
)
1004 u8 reg
= gpio
? AIC3X_GPIO2_REG
: AIC3X_GPIO1_REG
;
1005 u8 bit
= gpio
? 3: 0;
1006 u8 val
= aic3x_read_reg_cache(codec
, reg
) & ~(1 << bit
);
1007 aic3x_write(codec
, reg
, val
| (!!state
<< bit
));
1009 EXPORT_SYMBOL_GPL(aic3x_set_gpio
);
1011 int aic3x_get_gpio(struct snd_soc_codec
*codec
, int gpio
)
1013 u8 reg
= gpio
? AIC3X_GPIO2_REG
: AIC3X_GPIO1_REG
;
1014 u8 val
, bit
= gpio
? 2: 1;
1016 aic3x_read(codec
, reg
, &val
);
1017 return (val
>> bit
) & 1;
1019 EXPORT_SYMBOL_GPL(aic3x_get_gpio
);
1021 int aic3x_headset_detected(struct snd_soc_codec
*codec
)
1024 aic3x_read(codec
, AIC3X_RT_IRQ_FLAGS_REG
, &val
);
1025 return (val
>> 2) & 1;
1027 EXPORT_SYMBOL_GPL(aic3x_headset_detected
);
1029 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1030 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1031 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1033 struct snd_soc_dai aic3x_dai
= {
1034 .name
= "tlv320aic3x",
1036 .stream_name
= "Playback",
1039 .rates
= AIC3X_RATES
,
1040 .formats
= AIC3X_FORMATS
,},
1042 .stream_name
= "Capture",
1045 .rates
= AIC3X_RATES
,
1046 .formats
= AIC3X_FORMATS
,},
1048 .hw_params
= aic3x_hw_params
,
1049 .digital_mute
= aic3x_mute
,
1050 .set_sysclk
= aic3x_set_dai_sysclk
,
1051 .set_fmt
= aic3x_set_dai_fmt
,
1054 EXPORT_SYMBOL_GPL(aic3x_dai
);
1056 static int aic3x_suspend(struct platform_device
*pdev
, pm_message_t state
)
1058 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1059 struct snd_soc_codec
*codec
= socdev
->codec
;
1061 aic3x_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1066 static int aic3x_resume(struct platform_device
*pdev
)
1068 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1069 struct snd_soc_codec
*codec
= socdev
->codec
;
1072 u8
*cache
= codec
->reg_cache
;
1074 /* Sync reg_cache with the hardware */
1075 for (i
= 0; i
< ARRAY_SIZE(aic3x_reg
); i
++) {
1078 codec
->hw_write(codec
->control_data
, data
, 2);
1081 aic3x_set_bias_level(codec
, codec
->suspend_bias_level
);
1087 * initialise the AIC3X driver
1088 * register the mixer and dsp interfaces with the kernel
1090 static int aic3x_init(struct snd_soc_device
*socdev
)
1092 struct snd_soc_codec
*codec
= socdev
->codec
;
1093 struct aic3x_setup_data
*setup
= socdev
->codec_data
;
1096 codec
->name
= "tlv320aic3x";
1097 codec
->owner
= THIS_MODULE
;
1098 codec
->read
= aic3x_read_reg_cache
;
1099 codec
->write
= aic3x_write
;
1100 codec
->set_bias_level
= aic3x_set_bias_level
;
1101 codec
->dai
= &aic3x_dai
;
1103 codec
->reg_cache_size
= ARRAY_SIZE(aic3x_reg
);
1104 codec
->reg_cache
= kmemdup(aic3x_reg
, sizeof(aic3x_reg
), GFP_KERNEL
);
1105 if (codec
->reg_cache
== NULL
)
1108 aic3x_write(codec
, AIC3X_PAGE_SELECT
, PAGE0_SELECT
);
1109 aic3x_write(codec
, AIC3X_RESET
, SOFT_RESET
);
1112 ret
= snd_soc_new_pcms(socdev
, SNDRV_DEFAULT_IDX1
, SNDRV_DEFAULT_STR1
);
1114 printk(KERN_ERR
"aic3x: failed to create pcms\n");
1118 /* DAC default volume and mute */
1119 aic3x_write(codec
, LDAC_VOL
, DEFAULT_VOL
| MUTE_ON
);
1120 aic3x_write(codec
, RDAC_VOL
, DEFAULT_VOL
| MUTE_ON
);
1122 /* DAC to HP default volume and route to Output mixer */
1123 aic3x_write(codec
, DACL1_2_HPLOUT_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1124 aic3x_write(codec
, DACR1_2_HPROUT_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1125 aic3x_write(codec
, DACL1_2_HPLCOM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1126 aic3x_write(codec
, DACR1_2_HPRCOM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1127 /* DAC to Line Out default volume and route to Output mixer */
1128 aic3x_write(codec
, DACL1_2_LLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1129 aic3x_write(codec
, DACR1_2_RLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1130 /* DAC to Mono Line Out default volume and route to Output mixer */
1131 aic3x_write(codec
, DACL1_2_MONOLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1132 aic3x_write(codec
, DACR1_2_MONOLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1134 /* unmute all outputs */
1135 reg
= aic3x_read_reg_cache(codec
, LLOPM_CTRL
);
1136 aic3x_write(codec
, LLOPM_CTRL
, reg
| UNMUTE
);
1137 reg
= aic3x_read_reg_cache(codec
, RLOPM_CTRL
);
1138 aic3x_write(codec
, RLOPM_CTRL
, reg
| UNMUTE
);
1139 reg
= aic3x_read_reg_cache(codec
, MONOLOPM_CTRL
);
1140 aic3x_write(codec
, MONOLOPM_CTRL
, reg
| UNMUTE
);
1141 reg
= aic3x_read_reg_cache(codec
, HPLOUT_CTRL
);
1142 aic3x_write(codec
, HPLOUT_CTRL
, reg
| UNMUTE
);
1143 reg
= aic3x_read_reg_cache(codec
, HPROUT_CTRL
);
1144 aic3x_write(codec
, HPROUT_CTRL
, reg
| UNMUTE
);
1145 reg
= aic3x_read_reg_cache(codec
, HPLCOM_CTRL
);
1146 aic3x_write(codec
, HPLCOM_CTRL
, reg
| UNMUTE
);
1147 reg
= aic3x_read_reg_cache(codec
, HPRCOM_CTRL
);
1148 aic3x_write(codec
, HPRCOM_CTRL
, reg
| UNMUTE
);
1150 /* ADC default volume and unmute */
1151 aic3x_write(codec
, LADC_VOL
, DEFAULT_GAIN
);
1152 aic3x_write(codec
, RADC_VOL
, DEFAULT_GAIN
);
1153 /* By default route Line1 to ADC PGA mixer */
1154 aic3x_write(codec
, LINE1L_2_LADC_CTRL
, 0x0);
1155 aic3x_write(codec
, LINE1R_2_RADC_CTRL
, 0x0);
1157 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1158 aic3x_write(codec
, PGAL_2_HPLOUT_VOL
, DEFAULT_VOL
);
1159 aic3x_write(codec
, PGAR_2_HPROUT_VOL
, DEFAULT_VOL
);
1160 aic3x_write(codec
, PGAL_2_HPLCOM_VOL
, DEFAULT_VOL
);
1161 aic3x_write(codec
, PGAR_2_HPRCOM_VOL
, DEFAULT_VOL
);
1162 /* PGA to Line Out default volume, disconnect from Output Mixer */
1163 aic3x_write(codec
, PGAL_2_LLOPM_VOL
, DEFAULT_VOL
);
1164 aic3x_write(codec
, PGAR_2_RLOPM_VOL
, DEFAULT_VOL
);
1165 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1166 aic3x_write(codec
, PGAL_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1167 aic3x_write(codec
, PGAR_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1169 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1170 aic3x_write(codec
, LINE2L_2_HPLOUT_VOL
, DEFAULT_VOL
);
1171 aic3x_write(codec
, LINE2R_2_HPROUT_VOL
, DEFAULT_VOL
);
1172 aic3x_write(codec
, LINE2L_2_HPLCOM_VOL
, DEFAULT_VOL
);
1173 aic3x_write(codec
, LINE2R_2_HPRCOM_VOL
, DEFAULT_VOL
);
1174 /* Line2 Line Out default volume, disconnect from Output Mixer */
1175 aic3x_write(codec
, LINE2L_2_LLOPM_VOL
, DEFAULT_VOL
);
1176 aic3x_write(codec
, LINE2R_2_RLOPM_VOL
, DEFAULT_VOL
);
1177 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1178 aic3x_write(codec
, LINE2L_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1179 aic3x_write(codec
, LINE2R_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1181 /* off, with power on */
1182 aic3x_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1184 /* setup GPIO functions */
1185 aic3x_write(codec
, AIC3X_GPIO1_REG
, (setup
->gpio_func
[0] & 0xf) << 4);
1186 aic3x_write(codec
, AIC3X_GPIO2_REG
, (setup
->gpio_func
[1] & 0xf) << 4);
1188 aic3x_add_controls(codec
);
1189 aic3x_add_widgets(codec
);
1190 ret
= snd_soc_init_card(socdev
);
1192 printk(KERN_ERR
"aic3x: failed to register card\n");
1199 snd_soc_free_pcms(socdev
);
1200 snd_soc_dapm_free(socdev
);
1202 kfree(codec
->reg_cache
);
1206 static struct snd_soc_device
*aic3x_socdev
;
1208 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1210 * AIC3X 2 wire address can be up to 4 devices with device addresses
1211 * 0x18, 0x19, 0x1A, 0x1B
1215 * If the i2c layer weren't so broken, we could pass this kind of data
1218 static int aic3x_i2c_probe(struct i2c_client
*i2c
,
1219 const struct i2c_device_id
*id
)
1221 struct snd_soc_device
*socdev
= aic3x_socdev
;
1222 struct snd_soc_codec
*codec
= socdev
->codec
;
1225 i2c_set_clientdata(i2c
, codec
);
1226 codec
->control_data
= i2c
;
1228 ret
= aic3x_init(socdev
);
1230 printk(KERN_ERR
"aic3x: failed to initialise AIC3X\n");
1234 static int aic3x_i2c_remove(struct i2c_client
*client
)
1236 struct snd_soc_codec
*codec
= i2c_get_clientdata(client
);
1237 kfree(codec
->reg_cache
);
1241 static const struct i2c_device_id aic3x_i2c_id
[] = {
1242 { "tlv320aic3x", 0 },
1245 MODULE_DEVICE_TABLE(i2c
, aic3x_i2c_id
);
1247 /* machine i2c codec control layer */
1248 static struct i2c_driver aic3x_i2c_driver
= {
1250 .name
= "aic3x I2C Codec",
1251 .owner
= THIS_MODULE
,
1253 .probe
= aic3x_i2c_probe
,
1254 .remove
= aic3x_i2c_remove
,
1255 .id_table
= aic3x_i2c_id
,
1258 static int aic3x_i2c_read(struct i2c_client
*client
, u8
*value
, int len
)
1260 value
[0] = i2c_smbus_read_byte_data(client
, value
[0]);
1264 static int aic3x_add_i2c_device(struct platform_device
*pdev
,
1265 const struct aic3x_setup_data
*setup
)
1267 struct i2c_board_info info
;
1268 struct i2c_adapter
*adapter
;
1269 struct i2c_client
*client
;
1272 ret
= i2c_add_driver(&aic3x_i2c_driver
);
1274 dev_err(&pdev
->dev
, "can't add i2c driver\n");
1278 memset(&info
, 0, sizeof(struct i2c_board_info
));
1279 info
.addr
= setup
->i2c_address
;
1280 strlcpy(info
.type
, "tlv320aic3x", I2C_NAME_SIZE
);
1282 adapter
= i2c_get_adapter(setup
->i2c_bus
);
1284 dev_err(&pdev
->dev
, "can't get i2c adapter %d\n",
1289 client
= i2c_new_device(adapter
, &info
);
1290 i2c_put_adapter(adapter
);
1292 dev_err(&pdev
->dev
, "can't add i2c device at 0x%x\n",
1293 (unsigned int)info
.addr
);
1300 i2c_del_driver(&aic3x_i2c_driver
);
1305 static int aic3x_probe(struct platform_device
*pdev
)
1307 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1308 struct aic3x_setup_data
*setup
;
1309 struct snd_soc_codec
*codec
;
1310 struct aic3x_priv
*aic3x
;
1313 printk(KERN_INFO
"AIC3X Audio Codec %s\n", AIC3X_VERSION
);
1315 setup
= socdev
->codec_data
;
1316 codec
= kzalloc(sizeof(struct snd_soc_codec
), GFP_KERNEL
);
1320 aic3x
= kzalloc(sizeof(struct aic3x_priv
), GFP_KERNEL
);
1321 if (aic3x
== NULL
) {
1326 codec
->private_data
= aic3x
;
1327 socdev
->codec
= codec
;
1328 mutex_init(&codec
->mutex
);
1329 INIT_LIST_HEAD(&codec
->dapm_widgets
);
1330 INIT_LIST_HEAD(&codec
->dapm_paths
);
1332 aic3x_socdev
= socdev
;
1333 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1334 if (setup
->i2c_address
) {
1335 codec
->hw_write
= (hw_write_t
) i2c_master_send
;
1336 codec
->hw_read
= (hw_read_t
) aic3x_i2c_read
;
1337 ret
= aic3x_add_i2c_device(pdev
, setup
);
1340 /* Add other interfaces here */
1344 kfree(codec
->private_data
);
1350 static int aic3x_remove(struct platform_device
*pdev
)
1352 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1353 struct snd_soc_codec
*codec
= socdev
->codec
;
1355 /* power down chip */
1356 if (codec
->control_data
)
1357 aic3x_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1359 snd_soc_free_pcms(socdev
);
1360 snd_soc_dapm_free(socdev
);
1361 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1362 i2c_unregister_device(codec
->control_data
);
1363 i2c_del_driver(&aic3x_i2c_driver
);
1365 kfree(codec
->private_data
);
1371 struct snd_soc_codec_device soc_codec_dev_aic3x
= {
1372 .probe
= aic3x_probe
,
1373 .remove
= aic3x_remove
,
1374 .suspend
= aic3x_suspend
,
1375 .resume
= aic3x_resume
,
1377 EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x
);
1379 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1380 MODULE_AUTHOR("Vladimir Barinov");
1381 MODULE_LICENSE("GPL");