drivers/crypto/marvell/hash.c

   1 /*
   2  * Hash algorithms supported by the CESA: MD5, SHA1 and SHA256.
   3  *
   4  * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
   5  * Author: Arnaud Ebalard <arno@natisbad.org>
   6  *
   7  * This work is based on an initial version written by
   8  * Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published
  12  * by the Free Software Foundation.
  13  */
  14
  15 #include <crypto/md5.h>
  16 #include <crypto/sha.h>
  17
  18 #include "cesa.h"
  19
  20 struct mv_cesa_ahash_dma_iter {
  21         struct mv_cesa_dma_iter base;
  22         struct mv_cesa_sg_dma_iter src;
  23 };
  24
  25 static inline void
  26 mv_cesa_ahash_req_iter_init(struct mv_cesa_ahash_dma_iter *iter,
  27                             struct ahash_request *req)
  28 {
  29         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
  30         unsigned int len = req->nbytes;
  31
  32         if (!creq->last_req)
  33                 len = (len + creq->cache_ptr) & ~CESA_HASH_BLOCK_SIZE_MSK;
  34
  35         mv_cesa_req_dma_iter_init(&iter->base, len);
  36         mv_cesa_sg_dma_iter_init(&iter->src, req->src, DMA_TO_DEVICE);
  37         iter->src.op_offset = creq->cache_ptr;
  38 }
  39
  40 static inline bool
  41 mv_cesa_ahash_req_iter_next_op(struct mv_cesa_ahash_dma_iter *iter)
  42 {
  43         iter->src.op_offset = 0;
  44
  45         return mv_cesa_req_dma_iter_next_op(&iter->base);
  46 }
  47
  48 static inline int mv_cesa_ahash_dma_alloc_cache(struct mv_cesa_ahash_req *creq,
  49                                                 gfp_t flags)
  50 {
  51         struct mv_cesa_ahash_dma_req *dreq = &creq->req.dma;
  52
  53         creq->cache = dma_pool_alloc(cesa_dev->dma->cache_pool, flags,
  54                                      &dreq->cache_dma);
  55         if (!creq->cache)
  56                 return -ENOMEM;
  57
  58         return 0;
  59 }
  60
  61 static inline int mv_cesa_ahash_std_alloc_cache(struct mv_cesa_ahash_req *creq,
  62                                                 gfp_t flags)
  63 {
  64         creq->cache = kzalloc(CESA_MAX_HASH_BLOCK_SIZE, flags);
  65         if (!creq->cache)
  66                 return -ENOMEM;
  67
  68         return 0;
  69 }
  70
  71 static int mv_cesa_ahash_alloc_cache(struct ahash_request *req)
  72 {
  73         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
  74         gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
  75                       GFP_KERNEL : GFP_ATOMIC;
  76         int ret;
  77
  78         if (creq->cache)
  79                 return 0;
  80
  81         if (creq->req.base.type == CESA_DMA_REQ)
  82                 ret = mv_cesa_ahash_dma_alloc_cache(creq, flags);
  83         else
  84                 ret = mv_cesa_ahash_std_alloc_cache(creq, flags);
  85
  86         return ret;
  87 }
  88
  89 static inline void mv_cesa_ahash_dma_free_cache(struct mv_cesa_ahash_req *creq)
  90 {
  91         dma_pool_free(cesa_dev->dma->cache_pool, creq->cache,
  92                       creq->req.dma.cache_dma);
  93 }
  94
  95 static inline void mv_cesa_ahash_std_free_cache(struct mv_cesa_ahash_req *creq)
  96 {
  97         kfree(creq->cache);
  98 }
  99
 100 static void mv_cesa_ahash_free_cache(struct mv_cesa_ahash_req *creq)
 101 {
 102         if (!creq->cache)
 103                 return;
 104
 105         if (creq->req.base.type == CESA_DMA_REQ)
 106                 mv_cesa_ahash_dma_free_cache(creq);
 107         else
 108                 mv_cesa_ahash_std_free_cache(creq);
 109
 110         creq->cache = NULL;
 111 }
 112
 113 static int mv_cesa_ahash_dma_alloc_padding(struct mv_cesa_ahash_dma_req *req,
 114                                            gfp_t flags)
 115 {
 116         if (req->padding)
 117                 return 0;
 118
 119         req->padding = dma_pool_alloc(cesa_dev->dma->padding_pool, flags,
 120                                       &req->padding_dma);
 121         if (!req->padding)
 122                 return -ENOMEM;
 123
 124         return 0;
 125 }
 126
 127 static void mv_cesa_ahash_dma_free_padding(struct mv_cesa_ahash_dma_req *req)
 128 {
 129         if (!req->padding)
 130                 return;
 131
 132         dma_pool_free(cesa_dev->dma->padding_pool, req->padding,
 133                       req->padding_dma);
 134         req->padding = NULL;
 135 }
 136
 137 static inline void mv_cesa_ahash_dma_last_cleanup(struct ahash_request *req)
 138 {
 139         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 140
 141         mv_cesa_ahash_dma_free_padding(&creq->req.dma);
 142 }
 143
 144 static inline void mv_cesa_ahash_dma_cleanup(struct ahash_request *req)
 145 {
 146         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 147
 148         dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE);
 149         mv_cesa_dma_cleanup(&creq->req.dma.base);
 150 }
 151
 152 static inline void mv_cesa_ahash_cleanup(struct ahash_request *req)
 153 {
 154         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 155
 156         if (creq->req.base.type == CESA_DMA_REQ)
 157                 mv_cesa_ahash_dma_cleanup(req);
 158 }
 159
 160 static void mv_cesa_ahash_last_cleanup(struct ahash_request *req)
 161 {
 162         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 163
 164         mv_cesa_ahash_free_cache(creq);
 165
 166         if (creq->req.base.type == CESA_DMA_REQ)
 167                 mv_cesa_ahash_dma_last_cleanup(req);
 168 }
 169
 170 static int mv_cesa_ahash_pad_len(struct mv_cesa_ahash_req *creq)
 171 {
 172         unsigned int index, padlen;
 173
 174         index = creq->len & CESA_HASH_BLOCK_SIZE_MSK;
 175         padlen = (index < 56) ? (56 - index) : (64 + 56 - index);
 176
 177         return padlen;
 178 }
 179
 180 static int mv_cesa_ahash_pad_req(struct mv_cesa_ahash_req *creq, u8 *buf)
 181 {
 182         unsigned int index, padlen;
 183
 184         buf[0] = 0x80;
 185         /* Pad out to 56 mod 64 */
 186         index = creq->len & CESA_HASH_BLOCK_SIZE_MSK;
 187         padlen = mv_cesa_ahash_pad_len(creq);
 188         memset(buf + 1, 0, padlen - 1);
 189
 190         if (creq->algo_le) {
 191                 __le64 bits = cpu_to_le64(creq->len << 3);
 192                 memcpy(buf + padlen, &bits, sizeof(bits));
 193         } else {
 194                 __be64 bits = cpu_to_be64(creq->len << 3);
 195                 memcpy(buf + padlen, &bits, sizeof(bits));
 196         }
 197
 198         return padlen + 8;
 199 }
 200
 201 static void mv_cesa_ahash_std_step(struct ahash_request *req)
 202 {
 203         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 204         struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
 205         struct mv_cesa_engine *engine = sreq->base.engine;
 206         struct mv_cesa_op_ctx *op;
 207         unsigned int new_cache_ptr = 0;
 208         u32 frag_mode;
 209         size_t  len;
 210
 211         if (creq->cache_ptr)
 212                 memcpy(engine->sram + CESA_SA_DATA_SRAM_OFFSET, creq->cache,
 213                        creq->cache_ptr);
 214
 215         len = min_t(size_t, req->nbytes + creq->cache_ptr - sreq->offset,
 216                     CESA_SA_SRAM_PAYLOAD_SIZE);
 217
 218         if (!creq->last_req) {
 219                 new_cache_ptr = len & CESA_HASH_BLOCK_SIZE_MSK;
 220                 len &= ~CESA_HASH_BLOCK_SIZE_MSK;
 221         }
 222
 223         if (len - creq->cache_ptr)
 224                 sreq->offset += sg_pcopy_to_buffer(req->src, creq->src_nents,
 225                                                    engine->sram +
 226                                                    CESA_SA_DATA_SRAM_OFFSET +
 227                                                    creq->cache_ptr,
 228                                                    len - creq->cache_ptr,
 229                                                    sreq->offset);
 230
 231         op = &creq->op_tmpl;
 232
 233         frag_mode = mv_cesa_get_op_cfg(op) & CESA_SA_DESC_CFG_FRAG_MSK;
 234
 235         if (creq->last_req && sreq->offset == req->nbytes &&
 236             creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) {
 237                 if (frag_mode == CESA_SA_DESC_CFG_FIRST_FRAG)
 238                         frag_mode = CESA_SA_DESC_CFG_NOT_FRAG;
 239                 else if (frag_mode == CESA_SA_DESC_CFG_MID_FRAG)
 240                         frag_mode = CESA_SA_DESC_CFG_LAST_FRAG;
 241         }
 242
 243         if (frag_mode == CESA_SA_DESC_CFG_NOT_FRAG ||
 244             frag_mode == CESA_SA_DESC_CFG_LAST_FRAG) {
 245                 if (len &&
 246                     creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) {
 247                         mv_cesa_set_mac_op_total_len(op, creq->len);
 248                 } else {
 249                         int trailerlen = mv_cesa_ahash_pad_len(creq) + 8;
 250
 251                         if (len + trailerlen > CESA_SA_SRAM_PAYLOAD_SIZE) {
 252                                 len &= CESA_HASH_BLOCK_SIZE_MSK;
 253                                 new_cache_ptr = 64 - trailerlen;
 254                                 memcpy(creq->cache,
 255                                        engine->sram +
 256                                        CESA_SA_DATA_SRAM_OFFSET + len,
 257                                        new_cache_ptr);
 258                         } else {
 259                                 len += mv_cesa_ahash_pad_req(creq,
 260                                                 engine->sram + len +
 261                                                 CESA_SA_DATA_SRAM_OFFSET);
 262                         }
 263
 264                         if (frag_mode == CESA_SA_DESC_CFG_LAST_FRAG)
 265                                 frag_mode = CESA_SA_DESC_CFG_MID_FRAG;
 266                         else
 267                                 frag_mode = CESA_SA_DESC_CFG_FIRST_FRAG;
 268                 }
 269         }
 270
 271         mv_cesa_set_mac_op_frag_len(op, len);
 272         mv_cesa_update_op_cfg(op, frag_mode, CESA_SA_DESC_CFG_FRAG_MSK);
 273
 274         /* FIXME: only update enc_len field */
 275         memcpy(engine->sram, op, sizeof(*op));
 276
 277         if (frag_mode == CESA_SA_DESC_CFG_FIRST_FRAG)
 278                 mv_cesa_update_op_cfg(op, CESA_SA_DESC_CFG_MID_FRAG,
 279                                       CESA_SA_DESC_CFG_FRAG_MSK);
 280
 281         creq->cache_ptr = new_cache_ptr;
 282
 283         mv_cesa_set_int_mask(engine, CESA_SA_INT_ACCEL0_DONE);
 284         writel(CESA_SA_CFG_PARA_DIS, engine->regs + CESA_SA_CFG);
 285         writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
 286 }
 287
 288 static int mv_cesa_ahash_std_process(struct ahash_request *req, u32 status)
 289 {
 290         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 291         struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
 292
 293         if (sreq->offset < (req->nbytes - creq->cache_ptr))
 294                 return -EINPROGRESS;
 295
 296         return 0;
 297 }
 298
 299 static inline void mv_cesa_ahash_dma_prepare(struct ahash_request *req)
 300 {
 301         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 302         struct mv_cesa_tdma_req *dreq = &creq->req.dma.base;
 303
 304         mv_cesa_dma_prepare(dreq, dreq->base.engine);
 305 }
 306
 307 static void mv_cesa_ahash_std_prepare(struct ahash_request *req)
 308 {
 309         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 310         struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
 311         struct mv_cesa_engine *engine = sreq->base.engine;
 312
 313         sreq->offset = 0;
 314         mv_cesa_adjust_op(engine, &creq->op_tmpl);
 315         memcpy(engine->sram, &creq->op_tmpl, sizeof(creq->op_tmpl));
 316 }
 317
 318 static void mv_cesa_ahash_step(struct crypto_async_request *req)
 319 {
 320         struct ahash_request *ahashreq = ahash_request_cast(req);
 321         struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
 322
 323         if (creq->req.base.type == CESA_DMA_REQ)
 324                 mv_cesa_dma_step(&creq->req.dma.base);
 325         else
 326                 mv_cesa_ahash_std_step(ahashreq);
 327 }
 328
 329 static int mv_cesa_ahash_process(struct crypto_async_request *req, u32 status)
 330 {
 331         struct ahash_request *ahashreq = ahash_request_cast(req);
 332         struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
 333         struct mv_cesa_engine *engine = creq->req.base.engine;
 334         unsigned int digsize;
 335         int ret, i;
 336
 337         if (creq->req.base.type == CESA_DMA_REQ)
 338                 ret = mv_cesa_dma_process(&creq->req.dma.base, status);
 339         else
 340                 ret = mv_cesa_ahash_std_process(ahashreq, status);
 341
 342         if (ret == -EINPROGRESS)
 343                 return ret;
 344
 345         digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(ahashreq));
 346         for (i = 0; i < digsize / 4; i++)
 347                 creq->state[i] = readl(engine->regs + CESA_IVDIG(i));
 348
 349         if (creq->cache_ptr)
 350                 sg_pcopy_to_buffer(ahashreq->src, creq->src_nents,
 351                                    creq->cache,
 352                                    creq->cache_ptr,
 353                                    ahashreq->nbytes - creq->cache_ptr);
 354
 355         if (creq->last_req) {
 356                 /*
 357                  * Hardware's MD5 digest is in little endian format, but
 358                  * SHA in big endian format
 359                  */
 360                 if (creq->algo_le) {
 361                         __le32 *result = (void *)ahashreq->result;
 362
 363                         for (i = 0; i < digsize / 4; i++)
 364                                 result[i] = cpu_to_le32(creq->state[i]);
 365                 } else {
 366                         __be32 *result = (void *)ahashreq->result;
 367
 368                         for (i = 0; i < digsize / 4; i++)
 369                                 result[i] = cpu_to_be32(creq->state[i]);
 370                 }
 371         }
 372
 373         return ret;
 374 }
 375
 376 static void mv_cesa_ahash_prepare(struct crypto_async_request *req,
 377                                   struct mv_cesa_engine *engine)
 378 {
 379         struct ahash_request *ahashreq = ahash_request_cast(req);
 380         struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
 381         unsigned int digsize;
 382         int i;
 383
 384         creq->req.base.engine = engine;
 385
 386         if (creq->req.base.type == CESA_DMA_REQ)
 387                 mv_cesa_ahash_dma_prepare(ahashreq);
 388         else
 389                 mv_cesa_ahash_std_prepare(ahashreq);
 390
 391         digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(ahashreq));
 392         for (i = 0; i < digsize / 4; i++)
 393                 writel(creq->state[i],
 394                        engine->regs + CESA_IVDIG(i));
 395 }
 396
 397 static void mv_cesa_ahash_req_cleanup(struct crypto_async_request *req)
 398 {
 399         struct ahash_request *ahashreq = ahash_request_cast(req);
 400         struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
 401
 402         if (creq->last_req)
 403                 mv_cesa_ahash_last_cleanup(ahashreq);
 404
 405         mv_cesa_ahash_cleanup(ahashreq);
 406 }
 407
 408 static const struct mv_cesa_req_ops mv_cesa_ahash_req_ops = {
 409         .step = mv_cesa_ahash_step,
 410         .process = mv_cesa_ahash_process,
 411         .prepare = mv_cesa_ahash_prepare,
 412         .cleanup = mv_cesa_ahash_req_cleanup,
 413 };
 414
 415 static int mv_cesa_ahash_init(struct ahash_request *req,
 416                               struct mv_cesa_op_ctx *tmpl, bool algo_le)
 417 {
 418         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 419
 420         memset(creq, 0, sizeof(*creq));
 421         mv_cesa_update_op_cfg(tmpl,
 422                               CESA_SA_DESC_CFG_OP_MAC_ONLY |
 423                               CESA_SA_DESC_CFG_FIRST_FRAG,
 424                               CESA_SA_DESC_CFG_OP_MSK |
 425                               CESA_SA_DESC_CFG_FRAG_MSK);
 426         mv_cesa_set_mac_op_total_len(tmpl, 0);
 427         mv_cesa_set_mac_op_frag_len(tmpl, 0);
 428         creq->op_tmpl = *tmpl;
 429         creq->len = 0;
 430         creq->algo_le = algo_le;
 431
 432         return 0;
 433 }
 434
 435 static inline int mv_cesa_ahash_cra_init(struct crypto_tfm *tfm)
 436 {
 437         struct mv_cesa_hash_ctx *ctx = crypto_tfm_ctx(tfm);
 438
 439         ctx->base.ops = &mv_cesa_ahash_req_ops;
 440
 441         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
 442                                  sizeof(struct mv_cesa_ahash_req));
 443         return 0;
 444 }
 445
 446 static int mv_cesa_ahash_cache_req(struct ahash_request *req, bool *cached)
 447 {
 448         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 449         int ret;
 450
 451         if (((creq->cache_ptr + req->nbytes) & CESA_HASH_BLOCK_SIZE_MSK) &&
 452             !creq->last_req) {
 453                 ret = mv_cesa_ahash_alloc_cache(req);
 454                 if (ret)
 455                         return ret;
 456         }
 457
 458         if (creq->cache_ptr + req->nbytes < 64 && !creq->last_req) {
 459                 *cached = true;
 460
 461                 if (!req->nbytes)
 462                         return 0;
 463
 464                 sg_pcopy_to_buffer(req->src, creq->src_nents,
 465                                    creq->cache + creq->cache_ptr,
 466                                    req->nbytes, 0);
 467
 468                 creq->cache_ptr += req->nbytes;
 469         }
 470
 471         return 0;
 472 }
 473
 474 static struct mv_cesa_op_ctx *
 475 mv_cesa_dma_add_frag(struct mv_cesa_tdma_chain *chain,
 476                      struct mv_cesa_op_ctx *tmpl, unsigned int frag_len,
 477                      gfp_t flags)
 478 {
 479         struct mv_cesa_op_ctx *op;
 480         int ret;
 481
 482         op = mv_cesa_dma_add_op(chain, tmpl, false, flags);
 483         if (IS_ERR(op))
 484                 return op;
 485
 486         /* Set the operation block fragment length. */
 487         mv_cesa_set_mac_op_frag_len(op, frag_len);
 488
 489         /* Append dummy desc to launch operation */
 490         ret = mv_cesa_dma_add_dummy_launch(chain, flags);
 491         if (ret)
 492                 return ERR_PTR(ret);
 493
 494         return op;
 495 }
 496
 497 static struct mv_cesa_op_ctx *
 498 mv_cesa_ahash_dma_add_cache(struct mv_cesa_tdma_chain *chain,
 499                             struct mv_cesa_ahash_dma_iter *dma_iter,
 500                             struct mv_cesa_ahash_req *creq,
 501                             gfp_t flags)
 502 {
 503         struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma;
 504         struct mv_cesa_op_ctx *op = NULL;
 505         int ret;
 506
 507         if (!creq->cache_ptr)
 508                 return NULL;
 509
 510         ret = mv_cesa_dma_add_data_transfer(chain,
 511                                             CESA_SA_DATA_SRAM_OFFSET,
 512                                             ahashdreq->cache_dma,
 513                                             creq->cache_ptr,
 514                                             CESA_TDMA_DST_IN_SRAM,
 515                                             flags);
 516         if (ret)
 517                 return ERR_PTR(ret);
 518
 519         if (!dma_iter->base.op_len)
 520                 op = mv_cesa_dma_add_frag(chain, &creq->op_tmpl,
 521                                           creq->cache_ptr, flags);
 522
 523         return op;
 524 }
 525
 526 static struct mv_cesa_op_ctx *
 527 mv_cesa_ahash_dma_add_data(struct mv_cesa_tdma_chain *chain,
 528                            struct mv_cesa_ahash_dma_iter *dma_iter,
 529                            struct mv_cesa_ahash_req *creq,
 530                            gfp_t flags)
 531 {
 532         struct mv_cesa_op_ctx *op;
 533         int ret;
 534
 535         /* Add input transfers */
 536         ret = mv_cesa_dma_add_op_transfers(chain, &dma_iter->base,
 537                                            &dma_iter->src, flags);
 538         if (ret)
 539                 return ERR_PTR(ret);
 540
 541         op = mv_cesa_dma_add_frag(chain, &creq->op_tmpl, dma_iter->base.op_len,
 542                                   flags);
 543         if (IS_ERR(op))
 544                 return op;
 545
 546         if (mv_cesa_mac_op_is_first_frag(&creq->op_tmpl))
 547                 mv_cesa_update_op_cfg(&creq->op_tmpl,
 548                                       CESA_SA_DESC_CFG_MID_FRAG,
 549                                       CESA_SA_DESC_CFG_FRAG_MSK);
 550
 551         return op;
 552 }
 553
 554 static struct mv_cesa_op_ctx *
 555 mv_cesa_ahash_dma_last_req(struct mv_cesa_tdma_chain *chain,
 556                            struct mv_cesa_ahash_dma_iter *dma_iter,
 557                            struct mv_cesa_ahash_req *creq,
 558                            struct mv_cesa_op_ctx *op,
 559                            gfp_t flags)
 560 {
 561         struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma;
 562         unsigned int len, trailerlen, padoff = 0;
 563         int ret;
 564
 565         if (!creq->last_req)
 566                 return op;
 567
 568         if (op && creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) {
 569                 u32 frag = CESA_SA_DESC_CFG_NOT_FRAG;
 570
 571                 if (!mv_cesa_mac_op_is_first_frag(op))
 572                         frag = CESA_SA_DESC_CFG_LAST_FRAG;
 573
 574                 mv_cesa_update_op_cfg(op, frag, CESA_SA_DESC_CFG_FRAG_MSK);
 575
 576                 return op;
 577         }
 578
 579         ret = mv_cesa_ahash_dma_alloc_padding(ahashdreq, flags);
 580         if (ret)
 581                 return ERR_PTR(ret);
 582
 583         trailerlen = mv_cesa_ahash_pad_req(creq, ahashdreq->padding);
 584
 585         if (op) {
 586                 len = min(CESA_SA_SRAM_PAYLOAD_SIZE - dma_iter->base.op_len,
 587                           trailerlen);
 588                 if (len) {
 589                         ret = mv_cesa_dma_add_data_transfer(chain,
 590                                                 CESA_SA_DATA_SRAM_OFFSET +
 591                                                 dma_iter->base.op_len,
 592                                                 ahashdreq->padding_dma,
 593                                                 len, CESA_TDMA_DST_IN_SRAM,
 594                                                 flags);
 595                         if (ret)
 596                                 return ERR_PTR(ret);
 597
 598                         mv_cesa_update_op_cfg(op, CESA_SA_DESC_CFG_MID_FRAG,
 599                                               CESA_SA_DESC_CFG_FRAG_MSK);
 600                         mv_cesa_set_mac_op_frag_len(op,
 601                                         dma_iter->base.op_len + len);
 602                         padoff += len;
 603                 }
 604         }
 605
 606         if (padoff >= trailerlen)
 607                 return op;
 608
 609         if (!mv_cesa_mac_op_is_first_frag(&creq->op_tmpl))
 610                 mv_cesa_update_op_cfg(&creq->op_tmpl,
 611                                       CESA_SA_DESC_CFG_MID_FRAG,
 612                                       CESA_SA_DESC_CFG_FRAG_MSK);
 613
 614         ret = mv_cesa_dma_add_data_transfer(chain,
 615                                             CESA_SA_DATA_SRAM_OFFSET,
 616                                             ahashdreq->padding_dma +
 617                                             padoff,
 618                                             trailerlen - padoff,
 619                                             CESA_TDMA_DST_IN_SRAM,
 620                                             flags);
 621         if (ret)
 622                 return ERR_PTR(ret);
 623
 624         return mv_cesa_dma_add_frag(chain, &creq->op_tmpl, trailerlen - padoff,
 625                                     flags);
 626 }
 627
 628 static int mv_cesa_ahash_dma_req_init(struct ahash_request *req)
 629 {
 630         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 631         gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
 632                       GFP_KERNEL : GFP_ATOMIC;
 633         struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma;
 634         struct mv_cesa_tdma_req *dreq = &ahashdreq->base;
 635         struct mv_cesa_tdma_chain chain;
 636         struct mv_cesa_ahash_dma_iter iter;
 637         struct mv_cesa_op_ctx *op = NULL;
 638         int ret;
 639
 640         dreq->chain.first = NULL;
 641         dreq->chain.last = NULL;
 642
 643         if (creq->src_nents) {
 644                 ret = dma_map_sg(cesa_dev->dev, req->src, creq->src_nents,
 645                                  DMA_TO_DEVICE);
 646                 if (!ret) {
 647                         ret = -ENOMEM;
 648                         goto err;
 649                 }
 650         }
 651
 652         mv_cesa_tdma_desc_iter_init(&chain);
 653         mv_cesa_ahash_req_iter_init(&iter, req);
 654
 655         op = mv_cesa_ahash_dma_add_cache(&chain, &iter,
 656                                          creq, flags);
 657         if (IS_ERR(op)) {
 658                 ret = PTR_ERR(op);
 659                 goto err_free_tdma;
 660         }
 661
 662         do {
 663                 if (!iter.base.op_len)
 664                         break;
 665
 666                 op = mv_cesa_ahash_dma_add_data(&chain, &iter,
 667                                                 creq, flags);
 668                 if (IS_ERR(op)) {
 669                         ret = PTR_ERR(op);
 670                         goto err_free_tdma;
 671                 }
 672         } while (mv_cesa_ahash_req_iter_next_op(&iter));
 673
 674         op = mv_cesa_ahash_dma_last_req(&chain, &iter, creq, op, flags);
 675         if (IS_ERR(op)) {
 676                 ret = PTR_ERR(op);
 677                 goto err_free_tdma;
 678         }
 679
 680         if (op) {
 681                 /* Add dummy desc to wait for crypto operation end */
 682                 ret = mv_cesa_dma_add_dummy_end(&chain, flags);
 683                 if (ret)
 684                         goto err_free_tdma;
 685         }
 686
 687         if (!creq->last_req)
 688                 creq->cache_ptr = req->nbytes + creq->cache_ptr -
 689                                   iter.base.len;
 690         else
 691                 creq->cache_ptr = 0;
 692
 693         dreq->chain = chain;
 694
 695         return 0;
 696
 697 err_free_tdma:
 698         mv_cesa_dma_cleanup(dreq);
 699         dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE);
 700
 701 err:
 702         mv_cesa_ahash_last_cleanup(req);
 703
 704         return ret;
 705 }
 706
 707 static int mv_cesa_ahash_req_init(struct ahash_request *req, bool *cached)
 708 {
 709         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 710         int ret;
 711
 712         if (cesa_dev->caps->has_tdma)
 713                 creq->req.base.type = CESA_DMA_REQ;
 714         else
 715                 creq->req.base.type = CESA_STD_REQ;
 716
 717         creq->src_nents = sg_nents_for_len(req->src, req->nbytes);
 718
 719         ret = mv_cesa_ahash_cache_req(req, cached);
 720         if (ret)
 721                 return ret;
 722
 723         if (*cached)
 724                 return 0;
 725
 726         if (creq->req.base.type == CESA_DMA_REQ)
 727                 ret = mv_cesa_ahash_dma_req_init(req);
 728
 729         return ret;
 730 }
 731
 732 static int mv_cesa_ahash_update(struct ahash_request *req)
 733 {
 734         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 735         bool cached = false;
 736         int ret;
 737
 738         creq->len += req->nbytes;
 739         ret = mv_cesa_ahash_req_init(req, &cached);
 740         if (ret)
 741                 return ret;
 742
 743         if (cached)
 744                 return 0;
 745
 746         ret = mv_cesa_queue_req(&req->base);
 747         if (ret && ret != -EINPROGRESS) {
 748                 mv_cesa_ahash_cleanup(req);
 749                 return ret;
 750         }
 751
 752         return ret;
 753 }
 754
 755 static int mv_cesa_ahash_final(struct ahash_request *req)
 756 {
 757         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 758         struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl;
 759         bool cached = false;
 760         int ret;
 761
 762         mv_cesa_set_mac_op_total_len(tmpl, creq->len);
 763         creq->last_req = true;
 764         req->nbytes = 0;
 765
 766         ret = mv_cesa_ahash_req_init(req, &cached);
 767         if (ret)
 768                 return ret;
 769
 770         if (cached)
 771                 return 0;
 772
 773         ret = mv_cesa_queue_req(&req->base);
 774         if (ret && ret != -EINPROGRESS)
 775                 mv_cesa_ahash_cleanup(req);
 776
 777         return ret;
 778 }
 779
 780 static int mv_cesa_ahash_finup(struct ahash_request *req)
 781 {
 782         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 783         struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl;
 784         bool cached = false;
 785         int ret;
 786
 787         creq->len += req->nbytes;
 788         mv_cesa_set_mac_op_total_len(tmpl, creq->len);
 789         creq->last_req = true;
 790
 791         ret = mv_cesa_ahash_req_init(req, &cached);
 792         if (ret)
 793                 return ret;
 794
 795         if (cached)
 796                 return 0;
 797
 798         ret = mv_cesa_queue_req(&req->base);
 799         if (ret && ret != -EINPROGRESS)
 800                 mv_cesa_ahash_cleanup(req);
 801
 802         return ret;
 803 }
 804
 805 static int mv_cesa_ahash_export(struct ahash_request *req, void *hash,
 806                                 u64 *len, void *cache)
 807 {
 808         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
 809         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 810         unsigned int digsize = crypto_ahash_digestsize(ahash);
 811         unsigned int blocksize;
 812
 813         blocksize = crypto_ahash_blocksize(ahash);
 814
 815         *len = creq->len;
 816         memcpy(hash, creq->state, digsize);
 817         memset(cache, 0, blocksize);
 818         if (creq->cache)
 819                 memcpy(cache, creq->cache, creq->cache_ptr);
 820
 821         return 0;
 822 }
 823
 824 static int mv_cesa_ahash_import(struct ahash_request *req, const void *hash,
 825                                 u64 len, const void *cache)
 826 {
 827         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
 828         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 829         unsigned int digsize = crypto_ahash_digestsize(ahash);
 830         unsigned int blocksize;
 831         unsigned int cache_ptr;
 832         int ret;
 833
 834         ret = crypto_ahash_init(req);
 835         if (ret)
 836                 return ret;
 837
 838         blocksize = crypto_ahash_blocksize(ahash);
 839         if (len >= blocksize)
 840                 mv_cesa_update_op_cfg(&creq->op_tmpl,
 841                                       CESA_SA_DESC_CFG_MID_FRAG,
 842                                       CESA_SA_DESC_CFG_FRAG_MSK);
 843
 844         creq->len = len;
 845         memcpy(creq->state, hash, digsize);
 846         creq->cache_ptr = 0;
 847
 848         cache_ptr = do_div(len, blocksize);
 849         if (!cache_ptr)
 850                 return 0;
 851
 852         ret = mv_cesa_ahash_alloc_cache(req);
 853         if (ret)
 854                 return ret;
 855
 856         memcpy(creq->cache, cache, cache_ptr);
 857         creq->cache_ptr = cache_ptr;
 858
 859         return 0;
 860 }
 861
 862 static int mv_cesa_md5_init(struct ahash_request *req)
 863 {
 864         struct mv_cesa_op_ctx tmpl = { };
 865
 866         mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_MD5);
 867
 868         mv_cesa_ahash_init(req, &tmpl, true);
 869
 870         return 0;
 871 }
 872
 873 static int mv_cesa_md5_export(struct ahash_request *req, void *out)
 874 {
 875         struct md5_state *out_state = out;
 876
 877         return mv_cesa_ahash_export(req, out_state->hash,
 878                                     &out_state->byte_count, out_state->block);
 879 }
 880
 881 static int mv_cesa_md5_import(struct ahash_request *req, const void *in)
 882 {
 883         const struct md5_state *in_state = in;
 884
 885         return mv_cesa_ahash_import(req, in_state->hash, in_state->byte_count,
 886                                     in_state->block);
 887 }
 888
 889 static int mv_cesa_md5_digest(struct ahash_request *req)
 890 {
 891         int ret;
 892
 893         ret = mv_cesa_md5_init(req);
 894         if (ret)
 895                 return ret;
 896
 897         return mv_cesa_ahash_finup(req);
 898 }
 899
 900 struct ahash_alg mv_md5_alg = {
 901         .init = mv_cesa_md5_init,
 902         .update = mv_cesa_ahash_update,
 903         .final = mv_cesa_ahash_final,
 904         .finup = mv_cesa_ahash_finup,
 905         .digest = mv_cesa_md5_digest,
 906         .export = mv_cesa_md5_export,
 907         .import = mv_cesa_md5_import,
 908         .halg = {
 909                 .digestsize = MD5_DIGEST_SIZE,
 910                 .statesize = sizeof(struct md5_state),
 911                 .base = {
 912                         .cra_name = "md5",
 913                         .cra_driver_name = "mv-md5",
 914                         .cra_priority = 300,
 915                         .cra_flags = CRYPTO_ALG_ASYNC |
 916                                      CRYPTO_ALG_KERN_DRIVER_ONLY,
 917                         .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
 918                         .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
 919                         .cra_init = mv_cesa_ahash_cra_init,
 920                         .cra_module = THIS_MODULE,
 921                  }
 922         }
 923 };
 924
 925 static int mv_cesa_sha1_init(struct ahash_request *req)
 926 {
 927         struct mv_cesa_op_ctx tmpl = { };
 928
 929         mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_SHA1);
 930
 931         mv_cesa_ahash_init(req, &tmpl, false);
 932
 933         return 0;
 934 }
 935
 936 static int mv_cesa_sha1_export(struct ahash_request *req, void *out)
 937 {
 938         struct sha1_state *out_state = out;
 939
 940         return mv_cesa_ahash_export(req, out_state->state, &out_state->count,
 941                                     out_state->buffer);
 942 }
 943
 944 static int mv_cesa_sha1_import(struct ahash_request *req, const void *in)
 945 {
 946         const struct sha1_state *in_state = in;
 947
 948         return mv_cesa_ahash_import(req, in_state->state, in_state->count,
 949                                     in_state->buffer);
 950 }
 951
 952 static int mv_cesa_sha1_digest(struct ahash_request *req)
 953 {
 954         int ret;
 955
 956         ret = mv_cesa_sha1_init(req);
 957         if (ret)
 958                 return ret;
 959
 960         return mv_cesa_ahash_finup(req);
 961 }
 962
 963 struct ahash_alg mv_sha1_alg = {
 964         .init = mv_cesa_sha1_init,
 965         .update = mv_cesa_ahash_update,
 966         .final = mv_cesa_ahash_final,
 967         .finup = mv_cesa_ahash_finup,
 968         .digest = mv_cesa_sha1_digest,
 969         .export = mv_cesa_sha1_export,
 970         .import = mv_cesa_sha1_import,
 971         .halg = {
 972                 .digestsize = SHA1_DIGEST_SIZE,
 973                 .statesize = sizeof(struct sha1_state),
 974                 .base = {
 975                         .cra_name = "sha1",
 976                         .cra_driver_name = "mv-sha1",
 977                         .cra_priority = 300,
 978                         .cra_flags = CRYPTO_ALG_ASYNC |
 979                                      CRYPTO_ALG_KERN_DRIVER_ONLY,
 980                         .cra_blocksize = SHA1_BLOCK_SIZE,
 981                         .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
 982                         .cra_init = mv_cesa_ahash_cra_init,
 983                         .cra_module = THIS_MODULE,
 984                  }
 985         }
 986 };
 987
 988 static int mv_cesa_sha256_init(struct ahash_request *req)
 989 {
 990         struct mv_cesa_op_ctx tmpl = { };
 991
 992         mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_SHA256);
 993
 994         mv_cesa_ahash_init(req, &tmpl, false);
 995
 996         return 0;
 997 }
 998
 999 static int mv_cesa_sha256_digest(struct ahash_request *req)
1000 {
1001         int ret;
1002
1003         ret = mv_cesa_sha256_init(req);
1004         if (ret)
1005                 return ret;
1006
1007         return mv_cesa_ahash_finup(req);
1008 }
1009
1010 static int mv_cesa_sha256_export(struct ahash_request *req, void *out)
1011 {
1012         struct sha256_state *out_state = out;
1013
1014         return mv_cesa_ahash_export(req, out_state->state, &out_state->count,
1015                                     out_state->buf);
1016 }
1017
1018 static int mv_cesa_sha256_import(struct ahash_request *req, const void *in)
1019 {
1020         const struct sha256_state *in_state = in;
1021
1022         return mv_cesa_ahash_import(req, in_state->state, in_state->count,
1023                                     in_state->buf);
1024 }
1025
1026 struct ahash_alg mv_sha256_alg = {
1027         .init = mv_cesa_sha256_init,
1028         .update = mv_cesa_ahash_update,
1029         .final = mv_cesa_ahash_final,
1030         .finup = mv_cesa_ahash_finup,
1031         .digest = mv_cesa_sha256_digest,
1032         .export = mv_cesa_sha256_export,
1033         .import = mv_cesa_sha256_import,
1034         .halg = {
1035                 .digestsize = SHA256_DIGEST_SIZE,
1036                 .statesize = sizeof(struct sha256_state),
1037                 .base = {
1038                         .cra_name = "sha256",
1039                         .cra_driver_name = "mv-sha256",
1040                         .cra_priority = 300,
1041                         .cra_flags = CRYPTO_ALG_ASYNC |
1042                                      CRYPTO_ALG_KERN_DRIVER_ONLY,
1043                         .cra_blocksize = SHA256_BLOCK_SIZE,
1044                         .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
1045                         .cra_init = mv_cesa_ahash_cra_init,
1046                         .cra_module = THIS_MODULE,
1047                  }
1048         }
1049 };
1050
1051 struct mv_cesa_ahash_result {
1052         struct completion completion;
1053         int error;
1054 };
1055
1056 static void mv_cesa_hmac_ahash_complete(struct crypto_async_request *req,
1057                                         int error)
1058 {
1059         struct mv_cesa_ahash_result *result = req->data;
1060
1061         if (error == -EINPROGRESS)
1062                 return;
1063
1064         result->error = error;
1065         complete(&result->completion);
1066 }
1067
1068 static int mv_cesa_ahmac_iv_state_init(struct ahash_request *req, u8 *pad,
1069                                        void *state, unsigned int blocksize)
1070 {
1071         struct mv_cesa_ahash_result result;
1072         struct scatterlist sg;
1073         int ret;
1074
1075         ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1076                                    mv_cesa_hmac_ahash_complete, &result);
1077         sg_init_one(&sg, pad, blocksize);
1078         ahash_request_set_crypt(req, &sg, pad, blocksize);
1079         init_completion(&result.completion);
1080
1081         ret = crypto_ahash_init(req);
1082         if (ret)
1083                 return ret;
1084
1085         ret = crypto_ahash_update(req);
1086         if (ret && ret != -EINPROGRESS)
1087                 return ret;
1088
1089         wait_for_completion_interruptible(&result.completion);
1090         if (result.error)
1091                 return result.error;
1092
1093         ret = crypto_ahash_export(req, state);
1094         if (ret)
1095                 return ret;
1096
1097         return 0;
1098 }
1099
1100 static int mv_cesa_ahmac_pad_init(struct ahash_request *req,
1101                                   const u8 *key, unsigned int keylen,
1102                                   u8 *ipad, u8 *opad,
1103                                   unsigned int blocksize)
1104 {
1105         struct mv_cesa_ahash_result result;
1106         struct scatterlist sg;
1107         int ret;
1108         int i;
1109
1110         if (keylen <= blocksize) {
1111                 memcpy(ipad, key, keylen);
1112         } else {
1113                 u8 *keydup = kmemdup(key, keylen, GFP_KERNEL);
1114
1115                 if (!keydup)
1116                         return -ENOMEM;
1117
1118                 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1119                                            mv_cesa_hmac_ahash_complete,
1120                                            &result);
1121                 sg_init_one(&sg, keydup, keylen);
1122                 ahash_request_set_crypt(req, &sg, ipad, keylen);
1123                 init_completion(&result.completion);
1124
1125                 ret = crypto_ahash_digest(req);
1126                 if (ret == -EINPROGRESS) {
1127                         wait_for_completion_interruptible(&result.completion);
1128                         ret = result.error;
1129                 }
1130
1131                 /* Set the memory region to 0 to avoid any leak. */
1132                 memset(keydup, 0, keylen);
1133                 kfree(keydup);
1134
1135                 if (ret)
1136                         return ret;
1137
1138                 keylen = crypto_ahash_digestsize(crypto_ahash_reqtfm(req));
1139         }
1140
1141         memset(ipad + keylen, 0, blocksize - keylen);
1142         memcpy(opad, ipad, blocksize);
1143
1144         for (i = 0; i < blocksize; i++) {
1145                 ipad[i] ^= 0x36;
1146                 opad[i] ^= 0x5c;
1147         }
1148
1149         return 0;
1150 }
1151
1152 static int mv_cesa_ahmac_setkey(const char *hash_alg_name,
1153                                 const u8 *key, unsigned int keylen,
1154                                 void *istate, void *ostate)
1155 {
1156         struct ahash_request *req;
1157         struct crypto_ahash *tfm;
1158         unsigned int blocksize;
1159         u8 *ipad = NULL;
1160         u8 *opad;
1161         int ret;
1162
1163         tfm = crypto_alloc_ahash(hash_alg_name, CRYPTO_ALG_TYPE_AHASH,
1164                                  CRYPTO_ALG_TYPE_AHASH_MASK);
1165         if (IS_ERR(tfm))
1166                 return PTR_ERR(tfm);
1167
1168         req = ahash_request_alloc(tfm, GFP_KERNEL);
1169         if (!req) {
1170                 ret = -ENOMEM;
1171                 goto free_ahash;
1172         }
1173
1174         crypto_ahash_clear_flags(tfm, ~0);
1175
1176         blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1177
1178         ipad = kzalloc(2 * blocksize, GFP_KERNEL);
1179         if (!ipad) {
1180                 ret = -ENOMEM;
1181                 goto free_req;
1182         }
1183
1184         opad = ipad + blocksize;
1185
1186         ret = mv_cesa_ahmac_pad_init(req, key, keylen, ipad, opad, blocksize);
1187         if (ret)
1188                 goto free_ipad;
1189
1190         ret = mv_cesa_ahmac_iv_state_init(req, ipad, istate, blocksize);
1191         if (ret)
1192                 goto free_ipad;
1193
1194         ret = mv_cesa_ahmac_iv_state_init(req, opad, ostate, blocksize);
1195
1196 free_ipad:
1197         kfree(ipad);
1198 free_req:
1199         ahash_request_free(req);
1200 free_ahash:
1201         crypto_free_ahash(tfm);
1202
1203         return ret;
1204 }
1205
1206 static int mv_cesa_ahmac_cra_init(struct crypto_tfm *tfm)
1207 {
1208         struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(tfm);
1209
1210         ctx->base.ops = &mv_cesa_ahash_req_ops;
1211
1212         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1213                                  sizeof(struct mv_cesa_ahash_req));
1214         return 0;
1215 }
1216
1217 static int mv_cesa_ahmac_md5_init(struct ahash_request *req)
1218 {
1219         struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1220         struct mv_cesa_op_ctx tmpl = { };
1221
1222         mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_MD5);
1223         memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1224
1225         mv_cesa_ahash_init(req, &tmpl, true);
1226
1227         return 0;
1228 }
1229
1230 static int mv_cesa_ahmac_md5_setkey(struct crypto_ahash *tfm, const u8 *key,
1231                                     unsigned int keylen)
1232 {
1233         struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1234         struct md5_state istate, ostate;
1235         int ret, i;
1236
1237         ret = mv_cesa_ahmac_setkey("mv-md5", key, keylen, &istate, &ostate);
1238         if (ret)
1239                 return ret;
1240
1241         for (i = 0; i < ARRAY_SIZE(istate.hash); i++)
1242                 ctx->iv[i] = be32_to_cpu(istate.hash[i]);
1243
1244         for (i = 0; i < ARRAY_SIZE(ostate.hash); i++)
1245                 ctx->iv[i + 8] = be32_to_cpu(ostate.hash[i]);
1246
1247         return 0;
1248 }
1249
1250 static int mv_cesa_ahmac_md5_digest(struct ahash_request *req)
1251 {
1252         int ret;
1253
1254         ret = mv_cesa_ahmac_md5_init(req);
1255         if (ret)
1256                 return ret;
1257
1258         return mv_cesa_ahash_finup(req);
1259 }
1260
1261 struct ahash_alg mv_ahmac_md5_alg = {
1262         .init = mv_cesa_ahmac_md5_init,
1263         .update = mv_cesa_ahash_update,
1264         .final = mv_cesa_ahash_final,
1265         .finup = mv_cesa_ahash_finup,
1266         .digest = mv_cesa_ahmac_md5_digest,
1267         .setkey = mv_cesa_ahmac_md5_setkey,
1268         .export = mv_cesa_md5_export,
1269         .import = mv_cesa_md5_import,
1270         .halg = {
1271                 .digestsize = MD5_DIGEST_SIZE,
1272                 .statesize = sizeof(struct md5_state),
1273                 .base = {
1274                         .cra_name = "hmac(md5)",
1275                         .cra_driver_name = "mv-hmac-md5",
1276                         .cra_priority = 300,
1277                         .cra_flags = CRYPTO_ALG_ASYNC |
1278                                      CRYPTO_ALG_KERN_DRIVER_ONLY,
1279                         .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
1280                         .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1281                         .cra_init = mv_cesa_ahmac_cra_init,
1282                         .cra_module = THIS_MODULE,
1283                  }
1284         }
1285 };
1286
1287 static int mv_cesa_ahmac_sha1_init(struct ahash_request *req)
1288 {
1289         struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1290         struct mv_cesa_op_ctx tmpl = { };
1291
1292         mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_SHA1);
1293         memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1294
1295         mv_cesa_ahash_init(req, &tmpl, false);
1296
1297         return 0;
1298 }
1299
1300 static int mv_cesa_ahmac_sha1_setkey(struct crypto_ahash *tfm, const u8 *key,
1301                                      unsigned int keylen)
1302 {
1303         struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1304         struct sha1_state istate, ostate;
1305         int ret, i;
1306
1307         ret = mv_cesa_ahmac_setkey("mv-sha1", key, keylen, &istate, &ostate);
1308         if (ret)
1309                 return ret;
1310
1311         for (i = 0; i < ARRAY_SIZE(istate.state); i++)
1312                 ctx->iv[i] = be32_to_cpu(istate.state[i]);
1313
1314         for (i = 0; i < ARRAY_SIZE(ostate.state); i++)
1315                 ctx->iv[i + 8] = be32_to_cpu(ostate.state[i]);
1316
1317         return 0;
1318 }
1319
1320 static int mv_cesa_ahmac_sha1_digest(struct ahash_request *req)
1321 {
1322         int ret;
1323
1324         ret = mv_cesa_ahmac_sha1_init(req);
1325         if (ret)
1326                 return ret;
1327
1328         return mv_cesa_ahash_finup(req);
1329 }
1330
1331 struct ahash_alg mv_ahmac_sha1_alg = {
1332         .init = mv_cesa_ahmac_sha1_init,
1333         .update = mv_cesa_ahash_update,
1334         .final = mv_cesa_ahash_final,
1335         .finup = mv_cesa_ahash_finup,
1336         .digest = mv_cesa_ahmac_sha1_digest,
1337         .setkey = mv_cesa_ahmac_sha1_setkey,
1338         .export = mv_cesa_sha1_export,
1339         .import = mv_cesa_sha1_import,
1340         .halg = {
1341                 .digestsize = SHA1_DIGEST_SIZE,
1342                 .statesize = sizeof(struct sha1_state),
1343                 .base = {
1344                         .cra_name = "hmac(sha1)",
1345                         .cra_driver_name = "mv-hmac-sha1",
1346                         .cra_priority = 300,
1347                         .cra_flags = CRYPTO_ALG_ASYNC |
1348                                      CRYPTO_ALG_KERN_DRIVER_ONLY,
1349                         .cra_blocksize = SHA1_BLOCK_SIZE,
1350                         .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1351                         .cra_init = mv_cesa_ahmac_cra_init,
1352                         .cra_module = THIS_MODULE,
1353                  }
1354         }
1355 };
1356
1357 static int mv_cesa_ahmac_sha256_setkey(struct crypto_ahash *tfm, const u8 *key,
1358                                        unsigned int keylen)
1359 {
1360         struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1361         struct sha256_state istate, ostate;
1362         int ret, i;
1363
1364         ret = mv_cesa_ahmac_setkey("mv-sha256", key, keylen, &istate, &ostate);
1365         if (ret)
1366                 return ret;
1367
1368         for (i = 0; i < ARRAY_SIZE(istate.state); i++)
1369                 ctx->iv[i] = be32_to_cpu(istate.state[i]);
1370
1371         for (i = 0; i < ARRAY_SIZE(ostate.state); i++)
1372                 ctx->iv[i + 8] = be32_to_cpu(ostate.state[i]);
1373
1374         return 0;
1375 }
1376
1377 static int mv_cesa_ahmac_sha256_init(struct ahash_request *req)
1378 {
1379         struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1380         struct mv_cesa_op_ctx tmpl = { };
1381
1382         mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_SHA256);
1383         memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1384
1385         mv_cesa_ahash_init(req, &tmpl, false);
1386
1387         return 0;
1388 }
1389
1390 static int mv_cesa_ahmac_sha256_digest(struct ahash_request *req)
1391 {
1392         int ret;
1393
1394         ret = mv_cesa_ahmac_sha256_init(req);
1395         if (ret)
1396                 return ret;
1397
1398         return mv_cesa_ahash_finup(req);
1399 }
1400
1401 struct ahash_alg mv_ahmac_sha256_alg = {
1402         .init = mv_cesa_ahmac_sha256_init,
1403         .update = mv_cesa_ahash_update,
1404         .final = mv_cesa_ahash_final,
1405         .finup = mv_cesa_ahash_finup,
1406         .digest = mv_cesa_ahmac_sha256_digest,
1407         .setkey = mv_cesa_ahmac_sha256_setkey,
1408         .export = mv_cesa_sha256_export,
1409         .import = mv_cesa_sha256_import,
1410         .halg = {
1411                 .digestsize = SHA256_DIGEST_SIZE,
1412                 .statesize = sizeof(struct sha256_state),
1413                 .base = {
1414                         .cra_name = "hmac(sha256)",
1415                         .cra_driver_name = "mv-hmac-sha256",
1416                         .cra_priority = 300,
1417                         .cra_flags = CRYPTO_ALG_ASYNC |
1418                                      CRYPTO_ALG_KERN_DRIVER_ONLY,
1419                         .cra_blocksize = SHA256_BLOCK_SIZE,
1420                         .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1421                         .cra_init = mv_cesa_ahmac_cra_init,
1422                         .cra_module = THIS_MODULE,
1423                  }
1424         }
1425 };