| blob | 8c06c9d269d2290d94837253e8e55ab569da199d |
1 /*
2 * Low-level CPU initialisation
3 * Based on arch/arm/kernel/head.S
4 *
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2012 ARM Ltd.
7 * Authors: Catalin Marinas <catalin.marinas@arm.com>
8 * Will Deacon <will.deacon@arm.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
23 #include <linux/linkage.h>
24 #include <linux/init.h>
25 #include <linux/irqchip/arm-gic-v3.h>
27 #include <asm/assembler.h>
28 #include <asm/ptrace.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/cache.h>
31 #include <asm/cputype.h>
32 #include <asm/memory.h>
33 #include <asm/thread_info.h>
34 #include <asm/pgtable-hwdef.h>
35 #include <asm/pgtable.h>
36 #include <asm/page.h>
37 #include <asm/virt.h>
39 #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
41 #if (TEXT_OFFSET & 0xfff) != 0
42 #error TEXT_OFFSET must be at least 4KB aligned
43 #elif (PAGE_OFFSET & 0x1fffff) != 0
44 #error PAGE_OFFSET must be at least 2MB aligned
45 #elif TEXT_OFFSET > 0x1fffff
46 #error TEXT_OFFSET must be less than 2MB
47 #endif
49 .macro pgtbl, ttb0, ttb1, virt_to_phys
50 ldr \ttb1, =swapper_pg_dir
51 ldr \ttb0, =idmap_pg_dir
52 add \ttb1, \ttb1, \virt_to_phys
53 add \ttb0, \ttb0, \virt_to_phys
54 .endm
56 #ifdef CONFIG_ARM64_64K_PAGES
57 #define BLOCK_SHIFT PAGE_SHIFT
58 #define BLOCK_SIZE PAGE_SIZE
59 #define TABLE_SHIFT PMD_SHIFT
60 #else
61 #define BLOCK_SHIFT SECTION_SHIFT
62 #define BLOCK_SIZE SECTION_SIZE
63 #define TABLE_SHIFT PUD_SHIFT
64 #endif
66 #define KERNEL_START KERNEL_RAM_VADDR
67 #define KERNEL_END _end
69 /*
70 * Initial memory map attributes.
71 */
72 #ifndef CONFIG_SMP
73 #define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF
74 #define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF
75 #else
76 #define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF | PTE_SHARED
77 #define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S
78 #endif
80 #ifdef CONFIG_ARM64_64K_PAGES
81 #define MM_MMUFLAGS PTE_ATTRINDX(MT_NORMAL) | PTE_FLAGS
82 #else
83 #define MM_MMUFLAGS PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS
84 #endif
86 /*
87 * Kernel startup entry point.
88 * ---------------------------
89 *
90 * The requirements are:
91 * MMU = off, D-cache = off, I-cache = on or off,
92 * x0 = physical address to the FDT blob.
93 *
94 * This code is mostly position independent so you call this at
95 * __pa(PAGE_OFFSET + TEXT_OFFSET).
96 *
97 * Note that the callee-saved registers are used for storing variables
98 * that are useful before the MMU is enabled. The allocations are described
99 * in the entry routines.
100 */
101 __HEAD
103 /*
104 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
105 */
106 #ifdef CONFIG_EFI
107 efi_head:
108 /*
109 * This add instruction has no meaningful effect except that
110 * its opcode forms the magic "MZ" signature required by UEFI.
111 */
112 add x13, x18, #0x16
113 b stext
114 #else
115 b stext // branch to kernel start, magic
116 .long 0 // reserved
117 #endif
118 .quad _kernel_offset_le // Image load offset from start of RAM, little-endian
119 .quad _kernel_size_le // Effective size of kernel image, little-endian
120 .quad _kernel_flags_le // Informative flags, little-endian
121 .quad 0 // reserved
122 .quad 0 // reserved
123 .quad 0 // reserved
124 .byte 0x41 // Magic number, "ARM\x64"
125 .byte 0x52
126 .byte 0x4d
127 .byte 0x64
128 #ifdef CONFIG_EFI
129 .long pe_header - efi_head // Offset to the PE header.
130 #else
131 .word 0 // reserved
132 #endif
134 #ifdef CONFIG_EFI
135 .globl stext_offset
136 .set stext_offset, stext - efi_head
137 .align 3
138 pe_header:
139 .ascii "PE"
140 .short 0
141 coff_header:
142 .short 0xaa64 // AArch64
143 .short 2 // nr_sections
144 .long 0 // TimeDateStamp
145 .long 0 // PointerToSymbolTable
146 .long 1 // NumberOfSymbols
147 .short section_table - optional_header // SizeOfOptionalHeader
148 .short 0x206 // Characteristics.
149 // IMAGE_FILE_DEBUG_STRIPPED |
150 // IMAGE_FILE_EXECUTABLE_IMAGE |
151 // IMAGE_FILE_LINE_NUMS_STRIPPED
152 optional_header:
153 .short 0x20b // PE32+ format
154 .byte 0x02 // MajorLinkerVersion
155 .byte 0x14 // MinorLinkerVersion
156 .long _end - stext // SizeOfCode
157 .long 0 // SizeOfInitializedData
158 .long 0 // SizeOfUninitializedData
159 .long efi_stub_entry - efi_head // AddressOfEntryPoint
160 .long stext_offset // BaseOfCode
162 extra_header_fields:
163 .quad 0 // ImageBase
164 .long 0x20 // SectionAlignment
165 .long 0x8 // FileAlignment
166 .short 0 // MajorOperatingSystemVersion
167 .short 0 // MinorOperatingSystemVersion
168 .short 0 // MajorImageVersion
169 .short 0 // MinorImageVersion
170 .short 0 // MajorSubsystemVersion
171 .short 0 // MinorSubsystemVersion
172 .long 0 // Win32VersionValue
174 .long _end - efi_head // SizeOfImage
176 // Everything before the kernel image is considered part of the header
177 .long stext_offset // SizeOfHeaders
178 .long 0 // CheckSum
179 .short 0xa // Subsystem (EFI application)
180 .short 0 // DllCharacteristics
181 .quad 0 // SizeOfStackReserve
182 .quad 0 // SizeOfStackCommit
183 .quad 0 // SizeOfHeapReserve
184 .quad 0 // SizeOfHeapCommit
185 .long 0 // LoaderFlags
186 .long 0x6 // NumberOfRvaAndSizes
188 .quad 0 // ExportTable
189 .quad 0 // ImportTable
190 .quad 0 // ResourceTable
191 .quad 0 // ExceptionTable
192 .quad 0 // CertificationTable
193 .quad 0 // BaseRelocationTable
195 // Section table
196 section_table:
198 /*
199 * The EFI application loader requires a relocation section
200 * because EFI applications must be relocatable. This is a
201 * dummy section as far as we are concerned.
202 */
203 .ascii ".reloc"
204 .byte 0
205 .byte 0 // end of 0 padding of section name
206 .long 0
207 .long 0
208 .long 0 // SizeOfRawData
209 .long 0 // PointerToRawData
210 .long 0 // PointerToRelocations
211 .long 0 // PointerToLineNumbers
212 .short 0 // NumberOfRelocations
213 .short 0 // NumberOfLineNumbers
214 .long 0x42100040 // Characteristics (section flags)
217 .ascii ".text"
218 .byte 0
219 .byte 0
220 .byte 0 // end of 0 padding of section name
221 .long _end - stext // VirtualSize
222 .long stext_offset // VirtualAddress
223 .long _edata - stext // SizeOfRawData
224 .long stext_offset // PointerToRawData
226 .long 0 // PointerToRelocations (0 for executables)
227 .long 0 // PointerToLineNumbers (0 for executables)
228 .short 0 // NumberOfRelocations (0 for executables)
229 .short 0 // NumberOfLineNumbers (0 for executables)
230 .long 0xe0500020 // Characteristics (section flags)
231 .align 5
232 #endif
234 ENTRY(stext)
235 mov x21, x0 // x21=FDT
236 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
237 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
238 bl set_cpu_boot_mode_flag
239 mrs x22, midr_el1 // x22=cpuid
240 mov x0, x22
241 bl lookup_processor_type
242 mov x23, x0 // x23=current cpu_table
243 cbz x23, __error_p // invalid processor (x23=0)?
244 bl __vet_fdt
245 bl __create_page_tables // x25=TTBR0, x26=TTBR1
246 /*
247 * The following calls CPU specific code in a position independent
248 * manner. See arch/arm64/mm/proc.S for details. x23 = base of
249 * cpu_info structure selected by lookup_processor_type above.
250 * On return, the CPU will be ready for the MMU to be turned on and
251 * the TCR will have been set.
252 */
253 ldr x27, __switch_data // address to jump to after
254 // MMU has been enabled
255 adr lr, __enable_mmu // return (PIC) address
256 ldr x12, [x23, #CPU_INFO_SETUP]
257 add x12, x12, x28 // __virt_to_phys
258 br x12 // initialise processor
259 ENDPROC(stext)
261 /*
262 * If we're fortunate enough to boot at EL2, ensure that the world is
263 * sane before dropping to EL1.
264 *
265 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if
266 * booted in EL1 or EL2 respectively.
267 */
268 ENTRY(el2_setup)
269 mrs x0, CurrentEL
270 cmp x0, #CurrentEL_EL2
271 b.ne 1f
272 mrs x0, sctlr_el2
273 CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2
274 CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2
275 msr sctlr_el2, x0
276 b 2f
277 1: mrs x0, sctlr_el1
278 CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1
279 CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1
280 msr sctlr_el1, x0
281 mov w20, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1
282 isb
283 ret
285 /* Hyp configuration. */
286 2: mov x0, #(1 << 31) // 64-bit EL1
287 msr hcr_el2, x0
289 /* Generic timers. */
290 mrs x0, cnthctl_el2
291 orr x0, x0, #3 // Enable EL1 physical timers
292 msr cnthctl_el2, x0
293 msr cntvoff_el2, xzr // Clear virtual offset
295 #ifdef CONFIG_ARM_GIC_V3
296 /* GICv3 system register access */
297 mrs x0, id_aa64pfr0_el1
298 ubfx x0, x0, #24, #4
299 cmp x0, #1
300 b.ne 3f
302 mrs_s x0, ICC_SRE_EL2
303 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
304 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
305 msr_s ICC_SRE_EL2, x0
306 isb // Make sure SRE is now set
307 msr_s ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
309 3:
310 #endif
312 /* Populate ID registers. */
313 mrs x0, midr_el1
314 mrs x1, mpidr_el1
315 msr vpidr_el2, x0
316 msr vmpidr_el2, x1
318 /* sctlr_el1 */
319 mov x0, #0x0800 // Set/clear RES{1,0} bits
320 CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems
321 CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems
322 msr sctlr_el1, x0
324 /* Coprocessor traps. */
325 mov x0, #0x33ff
326 msr cptr_el2, x0 // Disable copro. traps to EL2
328 #ifdef CONFIG_COMPAT
329 msr hstr_el2, xzr // Disable CP15 traps to EL2
330 #endif
332 /* Stage-2 translation */
333 msr vttbr_el2, xzr
335 /* Hypervisor stub */
336 adr x0, __hyp_stub_vectors
337 msr vbar_el2, x0
339 /* spsr */
340 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
341 PSR_MODE_EL1h)
342 msr spsr_el2, x0
343 msr elr_el2, lr
344 mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
345 eret
346 ENDPROC(el2_setup)
348 /*
349 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
350 * in x20. See arch/arm64/include/asm/virt.h for more info.
351 */
352 ENTRY(set_cpu_boot_mode_flag)
353 ldr x1, =__boot_cpu_mode // Compute __boot_cpu_mode
354 add x1, x1, x28
355 cmp w20, #BOOT_CPU_MODE_EL2
356 b.ne 1f
357 add x1, x1, #4
358 1: str w20, [x1] // This CPU has booted in EL1
359 dmb sy
360 dc ivac, x1 // Invalidate potentially stale cache line
361 ret
362 ENDPROC(set_cpu_boot_mode_flag)
364 /*
365 * We need to find out the CPU boot mode long after boot, so we need to
366 * store it in a writable variable.
367 *
368 * This is not in .bss, because we set it sufficiently early that the boot-time
369 * zeroing of .bss would clobber it.
370 */
371 .pushsection .data..cacheline_aligned
372 ENTRY(__boot_cpu_mode)
373 .align L1_CACHE_SHIFT
374 .long BOOT_CPU_MODE_EL2
375 .long 0
376 .popsection
378 #ifdef CONFIG_SMP
379 .align 3
380 1: .quad .
381 .quad secondary_holding_pen_release
383 /*
384 * This provides a "holding pen" for platforms to hold all secondary
385 * cores are held until we're ready for them to initialise.
386 */
387 ENTRY(secondary_holding_pen)
388 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
389 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
390 bl set_cpu_boot_mode_flag
391 mrs x0, mpidr_el1
392 ldr x1, =MPIDR_HWID_BITMASK
393 and x0, x0, x1
394 adr x1, 1b
395 ldp x2, x3, [x1]
396 sub x1, x1, x2
397 add x3, x3, x1
398 pen: ldr x4, [x3]
399 cmp x4, x0
400 b.eq secondary_startup
401 wfe
402 b pen
403 ENDPROC(secondary_holding_pen)
405 /*
406 * Secondary entry point that jumps straight into the kernel. Only to
407 * be used where CPUs are brought online dynamically by the kernel.
408 */
409 ENTRY(secondary_entry)
410 bl el2_setup // Drop to EL1
411 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
412 bl set_cpu_boot_mode_flag
413 b secondary_startup
414 ENDPROC(secondary_entry)
416 ENTRY(secondary_startup)
417 /*
418 * Common entry point for secondary CPUs.
419 */
420 mrs x22, midr_el1 // x22=cpuid
421 mov x0, x22
422 bl lookup_processor_type
423 mov x23, x0 // x23=current cpu_table
424 cbz x23, __error_p // invalid processor (x23=0)?
426 pgtbl x25, x26, x28 // x25=TTBR0, x26=TTBR1
427 ldr x12, [x23, #CPU_INFO_SETUP]
428 add x12, x12, x28 // __virt_to_phys
429 blr x12 // initialise processor
431 ldr x21, =secondary_data
432 ldr x27, =__secondary_switched // address to jump to after enabling the MMU
433 b __enable_mmu
434 ENDPROC(secondary_startup)
436 ENTRY(__secondary_switched)
437 ldr x0, [x21] // get secondary_data.stack
438 mov sp, x0
439 mov x29, #0
440 b secondary_start_kernel
441 ENDPROC(__secondary_switched)
442 #endif /* CONFIG_SMP */
444 /*
445 * Setup common bits before finally enabling the MMU. Essentially this is just
446 * loading the page table pointer and vector base registers.
447 *
448 * On entry to this code, x0 must contain the SCTLR_EL1 value for turning on
449 * the MMU.
450 */
451 __enable_mmu:
452 ldr x5, =vectors
453 msr vbar_el1, x5
454 msr ttbr0_el1, x25 // load TTBR0
455 msr ttbr1_el1, x26 // load TTBR1
456 isb
457 b __turn_mmu_on
458 ENDPROC(__enable_mmu)
460 /*
461 * Enable the MMU. This completely changes the structure of the visible memory
462 * space. You will not be able to trace execution through this.
463 *
464 * x0 = system control register
465 * x27 = *virtual* address to jump to upon completion
466 *
467 * other registers depend on the function called upon completion
468 *
469 * We align the entire function to the smallest power of two larger than it to
470 * ensure it fits within a single block map entry. Otherwise were PHYS_OFFSET
471 * close to the end of a 512MB or 1GB block we might require an additional
472 * table to map the entire function.
473 */
474 .align 4
475 __turn_mmu_on:
476 msr sctlr_el1, x0
477 isb
478 br x27
479 ENDPROC(__turn_mmu_on)
481 /*
482 * Calculate the start of physical memory.
483 */
484 __calc_phys_offset:
485 adr x0, 1f
486 ldp x1, x2, [x0]
487 sub x28, x0, x1 // x28 = PHYS_OFFSET - PAGE_OFFSET
488 add x24, x2, x28 // x24 = PHYS_OFFSET
489 ret
490 ENDPROC(__calc_phys_offset)
492 .align 3
493 1: .quad .
494 .quad PAGE_OFFSET
496 /*
497 * Macro to create a table entry to the next page.
498 *
499 * tbl: page table address
500 * virt: virtual address
501 * shift: #imm page table shift
502 * ptrs: #imm pointers per table page
503 *
504 * Preserves: virt
505 * Corrupts: tmp1, tmp2
506 * Returns: tbl -> next level table page address
507 */
508 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
509 lsr \tmp1, \virt, #\shift
510 and \tmp1, \tmp1, #\ptrs - 1 // table index
511 add \tmp2, \tbl, #PAGE_SIZE
512 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type
513 str \tmp2, [\tbl, \tmp1, lsl #3]
514 add \tbl, \tbl, #PAGE_SIZE // next level table page
515 .endm
517 /*
518 * Macro to populate the PGD (and possibily PUD) for the corresponding
519 * block entry in the next level (tbl) for the given virtual address.
520 *
521 * Preserves: tbl, next, virt
522 * Corrupts: tmp1, tmp2
523 */
524 .macro create_pgd_entry, tbl, virt, tmp1, tmp2
525 create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2
526 #if SWAPPER_PGTABLE_LEVELS == 3
527 create_table_entry \tbl, \virt, TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2
528 #endif
529 .endm
531 /*
532 * Macro to populate block entries in the page table for the start..end
533 * virtual range (inclusive).
534 *
535 * Preserves: tbl, flags
536 * Corrupts: phys, start, end, pstate
537 */
538 .macro create_block_map, tbl, flags, phys, start, end
539 lsr \phys, \phys, #BLOCK_SHIFT
540 lsr \start, \start, #BLOCK_SHIFT
541 and \start, \start, #PTRS_PER_PTE - 1 // table index
542 orr \phys, \flags, \phys, lsl #BLOCK_SHIFT // table entry
543 lsr \end, \end, #BLOCK_SHIFT
544 and \end, \end, #PTRS_PER_PTE - 1 // table end index
545 9999: str \phys, [\tbl, \start, lsl #3] // store the entry
546 add \start, \start, #1 // next entry
547 add \phys, \phys, #BLOCK_SIZE // next block
548 cmp \start, \end
549 b.ls 9999b
550 .endm
552 /*
553 * Setup the initial page tables. We only setup the barest amount which is
554 * required to get the kernel running. The following sections are required:
555 * - identity mapping to enable the MMU (low address, TTBR0)
556 * - first few MB of the kernel linear mapping to jump to once the MMU has
557 * been enabled, including the FDT blob (TTBR1)
558 * - pgd entry for fixed mappings (TTBR1)
559 */
560 __create_page_tables:
561 pgtbl x25, x26, x28 // idmap_pg_dir and swapper_pg_dir addresses
562 mov x27, lr
564 /*
565 * Invalidate the idmap and swapper page tables to avoid potential
566 * dirty cache lines being evicted.
567 */
568 mov x0, x25
569 add x1, x26, #SWAPPER_DIR_SIZE
570 bl __inval_cache_range
572 /*
573 * Clear the idmap and swapper page tables.
574 */
575 mov x0, x25
576 add x6, x26, #SWAPPER_DIR_SIZE
577 1: stp xzr, xzr, [x0], #16
578 stp xzr, xzr, [x0], #16
579 stp xzr, xzr, [x0], #16
580 stp xzr, xzr, [x0], #16
581 cmp x0, x6
582 b.lo 1b
584 ldr x7, =MM_MMUFLAGS
586 /*
587 * Create the identity mapping.
588 */
589 mov x0, x25 // idmap_pg_dir
590 ldr x3, =KERNEL_START
591 add x3, x3, x28 // __pa(KERNEL_START)
592 create_pgd_entry x0, x3, x5, x6
593 ldr x6, =KERNEL_END
594 mov x5, x3 // __pa(KERNEL_START)
595 add x6, x6, x28 // __pa(KERNEL_END)
596 create_block_map x0, x7, x3, x5, x6
598 /*
599 * Map the kernel image (starting with PHYS_OFFSET).
600 */
601 mov x0, x26 // swapper_pg_dir
602 mov x5, #PAGE_OFFSET
603 create_pgd_entry x0, x5, x3, x6
604 ldr x6, =KERNEL_END
605 mov x3, x24 // phys offset
606 create_block_map x0, x7, x3, x5, x6
608 /*
609 * Map the FDT blob (maximum 2MB; must be within 512MB of
610 * PHYS_OFFSET).
611 */
612 mov x3, x21 // FDT phys address
613 and x3, x3, #~((1 << 21) - 1) // 2MB aligned
614 mov x6, #PAGE_OFFSET
615 sub x5, x3, x24 // subtract PHYS_OFFSET
616 tst x5, #~((1 << 29) - 1) // within 512MB?
617 csel x21, xzr, x21, ne // zero the FDT pointer
618 b.ne 1f
619 add x5, x5, x6 // __va(FDT blob)
620 add x6, x5, #1 << 21 // 2MB for the FDT blob
621 sub x6, x6, #1 // inclusive range
622 create_block_map x0, x7, x3, x5, x6
623 1:
624 /*
625 * Since the page tables have been populated with non-cacheable
626 * accesses (MMU disabled), invalidate the idmap and swapper page
627 * tables again to remove any speculatively loaded cache lines.
628 */
629 mov x0, x25
630 add x1, x26, #SWAPPER_DIR_SIZE
631 bl __inval_cache_range
633 mov lr, x27
634 ret
635 ENDPROC(__create_page_tables)
636 .ltorg
638 .align 3
639 .type __switch_data, %object
640 __switch_data:
641 .quad __mmap_switched
642 .quad __bss_start // x6
643 .quad __bss_stop // x7
644 .quad processor_id // x4
645 .quad __fdt_pointer // x5
646 .quad memstart_addr // x6
647 .quad init_thread_union + THREAD_START_SP // sp
649 /*
650 * The following fragment of code is executed with the MMU on in MMU mode, and
651 * uses absolute addresses; this is not position independent.
652 */
653 __mmap_switched:
654 adr x3, __switch_data + 8
656 ldp x6, x7, [x3], #16
657 1: cmp x6, x7
658 b.hs 2f
659 str xzr, [x6], #8 // Clear BSS
660 b 1b
661 2:
662 ldp x4, x5, [x3], #16
663 ldr x6, [x3], #8
664 ldr x16, [x3]
665 mov sp, x16
666 str x22, [x4] // Save processor ID
667 str x21, [x5] // Save FDT pointer
668 str x24, [x6] // Save PHYS_OFFSET
669 mov x29, #0
670 b start_kernel
671 ENDPROC(__mmap_switched)
673 /*
674 * Exception handling. Something went wrong and we can't proceed. We ought to
675 * tell the user, but since we don't have any guarantee that we're even
676 * running on the right architecture, we do virtually nothing.
677 */
678 __error_p:
679 ENDPROC(__error_p)
681 __error:
682 1: nop
683 b 1b
684 ENDPROC(__error)
686 /*
687 * This function gets the processor ID in w0 and searches the cpu_table[] for
688 * a match. It returns a pointer to the struct cpu_info it found. The
689 * cpu_table[] must end with an empty (all zeros) structure.
690 *
691 * This routine can be called via C code and it needs to work with the MMU
692 * both disabled and enabled (the offset is calculated automatically).
693 */
694 ENTRY(lookup_processor_type)
695 adr x1, __lookup_processor_type_data
696 ldp x2, x3, [x1]
697 sub x1, x1, x2 // get offset between VA and PA
698 add x3, x3, x1 // convert VA to PA
699 1:
700 ldp w5, w6, [x3] // load cpu_id_val and cpu_id_mask
701 cbz w5, 2f // end of list?
702 and w6, w6, w0
703 cmp w5, w6
704 b.eq 3f
705 add x3, x3, #CPU_INFO_SZ
706 b 1b
707 2:
708 mov x3, #0 // unknown processor
709 3:
710 mov x0, x3
711 ret
712 ENDPROC(lookup_processor_type)
714 .align 3
715 .type __lookup_processor_type_data, %object
716 __lookup_processor_type_data:
717 .quad .
718 .quad cpu_table
719 .size __lookup_processor_type_data, . - __lookup_processor_type_data
721 /*
722 * Determine validity of the x21 FDT pointer.
723 * The dtb must be 8-byte aligned and live in the first 512M of memory.
724 */
725 __vet_fdt:
726 tst x21, #0x7
727 b.ne 1f
728 cmp x21, x24
729 b.lt 1f
730 mov x0, #(1 << 29)
731 add x0, x0, x24
732 cmp x21, x0
733 b.ge 1f
734 ret
735 1:
736 mov x21, #0
737 ret
738 ENDPROC(__vet_fdt)