drivers/clk/clk-npcm7xx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Nuvoton NPCM7xx Clock Generator
   4  * All the clocks are initialized by the bootloader, so this driver allow only
   5  * reading of current settings directly from the hardware.
   6  *
   7  * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/clk-provider.h>
  12 #include <linux/io.h>
  13 #include <linux/kernel.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/slab.h>
  17 #include <linux/err.h>
  18 #include <linux/bitfield.h>
  19
  20 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
  21
  22 struct npcm7xx_clk_pll {
  23         struct clk_hw   hw;
  24         void __iomem    *pllcon;
  25         u8              flags;
  26 };
  27
  28 #define to_npcm7xx_clk_pll(_hw) container_of(_hw, struct npcm7xx_clk_pll, hw)
  29
  30 #define PLLCON_LOKI     BIT(31)
  31 #define PLLCON_LOKS     BIT(30)
  32 #define PLLCON_FBDV     GENMASK(27, 16)
  33 #define PLLCON_OTDV2    GENMASK(15, 13)
  34 #define PLLCON_PWDEN    BIT(12)
  35 #define PLLCON_OTDV1    GENMASK(10, 8)
  36 #define PLLCON_INDV     GENMASK(5, 0)
  37
  38 static unsigned long npcm7xx_clk_pll_recalc_rate(struct clk_hw *hw,
  39                                                  unsigned long parent_rate)
  40 {
  41         struct npcm7xx_clk_pll *pll = to_npcm7xx_clk_pll(hw);
  42         unsigned long fbdv, indv, otdv1, otdv2;
  43         unsigned int val;
  44         u64 ret;
  45
  46         if (parent_rate == 0) {
  47                 pr_err("%s: parent rate is zero", __func__);
  48                 return 0;
  49         }
  50
  51         val = readl_relaxed(pll->pllcon);
  52
  53         indv = FIELD_GET(PLLCON_INDV, val);
  54         fbdv = FIELD_GET(PLLCON_FBDV, val);
  55         otdv1 = FIELD_GET(PLLCON_OTDV1, val);
  56         otdv2 = FIELD_GET(PLLCON_OTDV2, val);
  57
  58         ret = (u64)parent_rate * fbdv;
  59         do_div(ret, indv * otdv1 * otdv2);
  60
  61         return ret;
  62 }
  63
  64 static const struct clk_ops npcm7xx_clk_pll_ops = {
  65         .recalc_rate = npcm7xx_clk_pll_recalc_rate,
  66 };
  67
  68 static struct clk_hw *
  69 npcm7xx_clk_register_pll(void __iomem *pllcon, const char *name,
  70                          const char *parent_name, unsigned long flags)
  71 {
  72         struct npcm7xx_clk_pll *pll;
  73         struct clk_init_data init;
  74         struct clk_hw *hw;
  75         int ret;
  76
  77         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  78         if (!pll)
  79                 return ERR_PTR(-ENOMEM);
  80
  81         pr_debug("%s reg, name=%s, p=%s\n", __func__, name, parent_name);
  82
  83         init.name = name;
  84         init.ops = &npcm7xx_clk_pll_ops;
  85         init.parent_names = &parent_name;
  86         init.num_parents = 1;
  87         init.flags = flags;
  88
  89         pll->pllcon = pllcon;
  90         pll->hw.init = &init;
  91
  92         hw = &pll->hw;
  93
  94         ret = clk_hw_register(NULL, hw);
  95         if (ret) {
  96                 kfree(pll);
  97                 hw = ERR_PTR(ret);
  98         }
  99
 100         return hw;
 101 }
 102
 103 #define NPCM7XX_CLKEN1          (0x00)
 104 #define NPCM7XX_CLKEN2          (0x28)
 105 #define NPCM7XX_CLKEN3          (0x30)
 106 #define NPCM7XX_CLKSEL          (0x04)
 107 #define NPCM7XX_CLKDIV1         (0x08)
 108 #define NPCM7XX_CLKDIV2         (0x2C)
 109 #define NPCM7XX_CLKDIV3         (0x58)
 110 #define NPCM7XX_PLLCON0         (0x0C)
 111 #define NPCM7XX_PLLCON1         (0x10)
 112 #define NPCM7XX_PLLCON2         (0x54)
 113 #define NPCM7XX_SWRSTR          (0x14)
 114 #define NPCM7XX_IRQWAKECON      (0x18)
 115 #define NPCM7XX_IRQWAKEFLAG     (0x1C)
 116 #define NPCM7XX_IPSRST1         (0x20)
 117 #define NPCM7XX_IPSRST2         (0x24)
 118 #define NPCM7XX_IPSRST3         (0x34)
 119 #define NPCM7XX_WD0RCR          (0x38)
 120 #define NPCM7XX_WD1RCR          (0x3C)
 121 #define NPCM7XX_WD2RCR          (0x40)
 122 #define NPCM7XX_SWRSTC1         (0x44)
 123 #define NPCM7XX_SWRSTC2         (0x48)
 124 #define NPCM7XX_SWRSTC3         (0x4C)
 125 #define NPCM7XX_SWRSTC4         (0x50)
 126 #define NPCM7XX_CORSTC          (0x5C)
 127 #define NPCM7XX_PLLCONG         (0x60)
 128 #define NPCM7XX_AHBCKFI         (0x64)
 129 #define NPCM7XX_SECCNT          (0x68)
 130 #define NPCM7XX_CNTR25M         (0x6C)
 131
 132 struct npcm7xx_clk_gate_data {
 133         u32 reg;
 134         u8 bit_idx;
 135         const char *name;
 136         const char *parent_name;
 137         unsigned long flags;
 138         /*
 139          * If this clock is exported via DT, set onecell_idx to constant
 140          * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
 141          * this specific clock.  Otherwise, set to -1.
 142          */
 143         int onecell_idx;
 144 };
 145
 146 struct npcm7xx_clk_mux_data {
 147         u8 shift;
 148         u8 mask;
 149         u32 *table;
 150         const char *name;
 151         const char * const *parent_names;
 152         u8 num_parents;
 153         unsigned long flags;
 154         /*
 155          * If this clock is exported via DT, set onecell_idx to constant
 156          * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
 157          * this specific clock.  Otherwise, set to -1.
 158          */
 159         int onecell_idx;
 160
 161 };
 162
 163 struct npcm7xx_clk_div_fixed_data {
 164         u8 mult;
 165         u8 div;
 166         const char *name;
 167         const char *parent_name;
 168         u8 clk_divider_flags;
 169         /*
 170          * If this clock is exported via DT, set onecell_idx to constant
 171          * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
 172          * this specific clock.  Otherwise, set to -1.
 173          */
 174         int onecell_idx;
 175 };
 176
 177
 178 struct npcm7xx_clk_div_data {
 179         u32 reg;
 180         u8 shift;
 181         u8 width;
 182         const char *name;
 183         const char *parent_name;
 184         u8 clk_divider_flags;
 185         unsigned long flags;
 186         /*
 187          * If this clock is exported via DT, set onecell_idx to constant
 188          * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
 189          * this specific clock.  Otherwise, set to -1.
 190          */
 191         int onecell_idx;
 192 };
 193
 194 struct npcm7xx_clk_pll_data {
 195         u32 reg;
 196         const char *name;
 197         const char *parent_name;
 198         unsigned long flags;
 199         /*
 200          * If this clock is exported via DT, set onecell_idx to constant
 201          * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
 202          * this specific clock.  Otherwise, set to -1.
 203          */
 204         int onecell_idx;
 205 };
 206
 207 /*
 208  * Single copy of strings used to refer to clocks within this driver indexed by
 209  * above enum.
 210  */
 211 #define NPCM7XX_CLK_S_REFCLK      "refclk"
 212 #define NPCM7XX_CLK_S_SYSBYPCK    "sysbypck"
 213 #define NPCM7XX_CLK_S_MCBYPCK     "mcbypck"
 214 #define NPCM7XX_CLK_S_GFXBYPCK    "gfxbypck"
 215 #define NPCM7XX_CLK_S_PLL0        "pll0"
 216 #define NPCM7XX_CLK_S_PLL1        "pll1"
 217 #define NPCM7XX_CLK_S_PLL1_DIV2   "pll1_div2"
 218 #define NPCM7XX_CLK_S_PLL2        "pll2"
 219 #define NPCM7XX_CLK_S_PLL_GFX     "pll_gfx"
 220 #define NPCM7XX_CLK_S_PLL2_DIV2   "pll2_div2"
 221 #define NPCM7XX_CLK_S_PIX_MUX     "gfx_pixel"
 222 #define NPCM7XX_CLK_S_GPRFSEL_MUX "gprfsel_mux"
 223 #define NPCM7XX_CLK_S_MC_MUX      "mc_phy"
 224 #define NPCM7XX_CLK_S_CPU_MUX     "cpu"  /*AKA system clock.*/
 225 #define NPCM7XX_CLK_S_MC          "mc"
 226 #define NPCM7XX_CLK_S_AXI         "axi"  /*AKA CLK2*/
 227 #define NPCM7XX_CLK_S_AHB         "ahb"  /*AKA CLK4*/
 228 #define NPCM7XX_CLK_S_CLKOUT_MUX  "clkout_mux"
 229 #define NPCM7XX_CLK_S_UART_MUX    "uart_mux"
 230 #define NPCM7XX_CLK_S_TIM_MUX     "timer_mux"
 231 #define NPCM7XX_CLK_S_SD_MUX      "sd_mux"
 232 #define NPCM7XX_CLK_S_GFXM_MUX    "gfxm_mux"
 233 #define NPCM7XX_CLK_S_SU_MUX      "serial_usb_mux"
 234 #define NPCM7XX_CLK_S_DVC_MUX     "dvc_mux"
 235 #define NPCM7XX_CLK_S_GFX_MUX     "gfx_mux"
 236 #define NPCM7XX_CLK_S_GFX_PIXEL   "gfx_pixel"
 237 #define NPCM7XX_CLK_S_SPI0        "spi0"
 238 #define NPCM7XX_CLK_S_SPI3        "spi3"
 239 #define NPCM7XX_CLK_S_SPIX        "spix"
 240 #define NPCM7XX_CLK_S_APB1        "apb1"
 241 #define NPCM7XX_CLK_S_APB2        "apb2"
 242 #define NPCM7XX_CLK_S_APB3        "apb3"
 243 #define NPCM7XX_CLK_S_APB4        "apb4"
 244 #define NPCM7XX_CLK_S_APB5        "apb5"
 245 #define NPCM7XX_CLK_S_TOCK        "tock"
 246 #define NPCM7XX_CLK_S_CLKOUT      "clkout"
 247 #define NPCM7XX_CLK_S_UART        "uart"
 248 #define NPCM7XX_CLK_S_TIMER       "timer"
 249 #define NPCM7XX_CLK_S_MMC         "mmc"
 250 #define NPCM7XX_CLK_S_SDHC        "sdhc"
 251 #define NPCM7XX_CLK_S_ADC         "adc"
 252 #define NPCM7XX_CLK_S_GFX         "gfx0_gfx1_mem"
 253 #define NPCM7XX_CLK_S_USBIF       "serial_usbif"
 254 #define NPCM7XX_CLK_S_USB_HOST    "usb_host"
 255 #define NPCM7XX_CLK_S_USB_BRIDGE  "usb_bridge"
 256 #define NPCM7XX_CLK_S_PCI         "pci"
 257
 258 static u32 pll_mux_table[] = {0, 1, 2, 3};
 259 static const char * const pll_mux_parents[] __initconst = {
 260         NPCM7XX_CLK_S_PLL0,
 261         NPCM7XX_CLK_S_PLL1_DIV2,
 262         NPCM7XX_CLK_S_REFCLK,
 263         NPCM7XX_CLK_S_PLL2_DIV2,
 264 };
 265
 266 static u32 cpuck_mux_table[] = {0, 1, 2, 3};
 267 static const char * const cpuck_mux_parents[] __initconst = {
 268         NPCM7XX_CLK_S_PLL0,
 269         NPCM7XX_CLK_S_PLL1_DIV2,
 270         NPCM7XX_CLK_S_REFCLK,
 271         NPCM7XX_CLK_S_SYSBYPCK,
 272 };
 273
 274 static u32 pixcksel_mux_table[] = {0, 2};
 275 static const char * const pixcksel_mux_parents[] __initconst = {
 276         NPCM7XX_CLK_S_PLL_GFX,
 277         NPCM7XX_CLK_S_REFCLK,
 278 };
 279
 280 static u32 sucksel_mux_table[] = {2, 3};
 281 static const char * const sucksel_mux_parents[] __initconst = {
 282         NPCM7XX_CLK_S_REFCLK,
 283         NPCM7XX_CLK_S_PLL2_DIV2,
 284 };
 285
 286 static u32 mccksel_mux_table[] = {0, 2, 3};
 287 static const char * const mccksel_mux_parents[] __initconst = {
 288         NPCM7XX_CLK_S_PLL1_DIV2,
 289         NPCM7XX_CLK_S_REFCLK,
 290         NPCM7XX_CLK_S_MCBYPCK,
 291 };
 292
 293 static u32 clkoutsel_mux_table[] = {0, 1, 2, 3, 4};
 294 static const char * const clkoutsel_mux_parents[] __initconst = {
 295         NPCM7XX_CLK_S_PLL0,
 296         NPCM7XX_CLK_S_PLL1_DIV2,
 297         NPCM7XX_CLK_S_REFCLK,
 298         NPCM7XX_CLK_S_PLL_GFX, // divided by 2
 299         NPCM7XX_CLK_S_PLL2_DIV2,
 300 };
 301
 302 static u32 gfxmsel_mux_table[] = {2, 3};
 303 static const char * const gfxmsel_mux_parents[] __initconst = {
 304         NPCM7XX_CLK_S_REFCLK,
 305         NPCM7XX_CLK_S_PLL2_DIV2,
 306 };
 307
 308 static u32 dvcssel_mux_table[] = {2, 3};
 309 static const char * const dvcssel_mux_parents[] __initconst = {
 310         NPCM7XX_CLK_S_REFCLK,
 311         NPCM7XX_CLK_S_PLL2,
 312 };
 313
 314 static const struct npcm7xx_clk_pll_data npcm7xx_plls[] __initconst = {
 315         {NPCM7XX_PLLCON0, NPCM7XX_CLK_S_PLL0, NPCM7XX_CLK_S_REFCLK, 0, -1},
 316
 317         {NPCM7XX_PLLCON1, NPCM7XX_CLK_S_PLL1,
 318         NPCM7XX_CLK_S_REFCLK, 0, -1},
 319
 320         {NPCM7XX_PLLCON2, NPCM7XX_CLK_S_PLL2,
 321         NPCM7XX_CLK_S_REFCLK, 0, -1},
 322
 323         {NPCM7XX_PLLCONG, NPCM7XX_CLK_S_PLL_GFX,
 324         NPCM7XX_CLK_S_REFCLK, 0, -1},
 325 };
 326
 327 static const struct npcm7xx_clk_mux_data npcm7xx_muxes[] __initconst = {
 328         {0, GENMASK(1, 0), cpuck_mux_table, NPCM7XX_CLK_S_CPU_MUX,
 329         cpuck_mux_parents, ARRAY_SIZE(cpuck_mux_parents), CLK_IS_CRITICAL,
 330         NPCM7XX_CLK_CPU},
 331
 332         {4, GENMASK(1, 0), pixcksel_mux_table, NPCM7XX_CLK_S_PIX_MUX,
 333         pixcksel_mux_parents, ARRAY_SIZE(pixcksel_mux_parents), 0,
 334         NPCM7XX_CLK_GFX_PIXEL},
 335
 336         {6, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_SD_MUX,
 337         pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
 338
 339         {8, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_UART_MUX,
 340         pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
 341
 342         {10, GENMASK(1, 0), sucksel_mux_table, NPCM7XX_CLK_S_SU_MUX,
 343         sucksel_mux_parents, ARRAY_SIZE(sucksel_mux_parents), 0, -1},
 344
 345         {12, GENMASK(1, 0), mccksel_mux_table, NPCM7XX_CLK_S_MC_MUX,
 346         mccksel_mux_parents, ARRAY_SIZE(mccksel_mux_parents), 0, -1},
 347
 348         {14, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_TIM_MUX,
 349         pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
 350
 351         {16, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_GFX_MUX,
 352         pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
 353
 354         {18, GENMASK(2, 0), clkoutsel_mux_table, NPCM7XX_CLK_S_CLKOUT_MUX,
 355         clkoutsel_mux_parents, ARRAY_SIZE(clkoutsel_mux_parents), 0, -1},
 356
 357         {21, GENMASK(1, 0), gfxmsel_mux_table, NPCM7XX_CLK_S_GFXM_MUX,
 358         gfxmsel_mux_parents, ARRAY_SIZE(gfxmsel_mux_parents), 0, -1},
 359
 360         {23, GENMASK(1, 0), dvcssel_mux_table, NPCM7XX_CLK_S_DVC_MUX,
 361         dvcssel_mux_parents, ARRAY_SIZE(dvcssel_mux_parents), 0, -1},
 362 };
 363
 364 /* fixed ratio dividers (no register): */
 365 static const struct npcm7xx_clk_div_fixed_data npcm7xx_divs_fx[] __initconst = {
 366         { 1, 2, NPCM7XX_CLK_S_MC, NPCM7XX_CLK_S_MC_MUX, 0, NPCM7XX_CLK_MC},
 367         { 1, 2, NPCM7XX_CLK_S_PLL1_DIV2, NPCM7XX_CLK_S_PLL1, 0, -1},
 368         { 1, 2, NPCM7XX_CLK_S_PLL2_DIV2, NPCM7XX_CLK_S_PLL2, 0, -1},
 369 };
 370
 371 /* configurable dividers: */
 372 static const struct npcm7xx_clk_div_data npcm7xx_divs[] __initconst = {
 373         {NPCM7XX_CLKDIV1, 28, 3, NPCM7XX_CLK_S_ADC,
 374         NPCM7XX_CLK_S_TIMER, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_ADC},
 375         /*30-28 ADCCKDIV*/
 376         {NPCM7XX_CLKDIV1, 26, 2, NPCM7XX_CLK_S_AHB,
 377         NPCM7XX_CLK_S_AXI, 0, CLK_IS_CRITICAL, NPCM7XX_CLK_AHB},
 378         /*27-26 CLK4DIV*/
 379         {NPCM7XX_CLKDIV1, 21, 5, NPCM7XX_CLK_S_TIMER,
 380         NPCM7XX_CLK_S_TIM_MUX, 0, 0, NPCM7XX_CLK_TIMER},
 381         /*25-21 TIMCKDIV*/
 382         {NPCM7XX_CLKDIV1, 16, 5, NPCM7XX_CLK_S_UART,
 383         NPCM7XX_CLK_S_UART_MUX, 0, 0, NPCM7XX_CLK_UART},
 384         /*20-16 UARTDIV*/
 385         {NPCM7XX_CLKDIV1, 11, 5, NPCM7XX_CLK_S_MMC,
 386         NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_MMC},
 387         /*15-11 MMCCKDIV*/
 388         {NPCM7XX_CLKDIV1, 6, 5, NPCM7XX_CLK_S_SPI3,
 389         NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI3},
 390         /*10-6 AHB3CKDIV*/
 391         {NPCM7XX_CLKDIV1, 2, 4, NPCM7XX_CLK_S_PCI,
 392         NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_PCI},
 393         /*5-2 PCICKDIV*/
 394         {NPCM7XX_CLKDIV1, 0, 1, NPCM7XX_CLK_S_AXI,
 395         NPCM7XX_CLK_S_CPU_MUX, CLK_DIVIDER_POWER_OF_TWO, CLK_IS_CRITICAL,
 396         NPCM7XX_CLK_AXI},/*0 CLK2DIV*/
 397
 398         {NPCM7XX_CLKDIV2, 30, 2, NPCM7XX_CLK_S_APB4,
 399         NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB4},
 400         /*31-30 APB4CKDIV*/
 401         {NPCM7XX_CLKDIV2, 28, 2, NPCM7XX_CLK_S_APB3,
 402         NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB3},
 403         /*29-28 APB3CKDIV*/
 404         {NPCM7XX_CLKDIV2, 26, 2, NPCM7XX_CLK_S_APB2,
 405         NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB2},
 406         /*27-26 APB2CKDIV*/
 407         {NPCM7XX_CLKDIV2, 24, 2, NPCM7XX_CLK_S_APB1,
 408         NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB1},
 409         /*25-24 APB1CKDIV*/
 410         {NPCM7XX_CLKDIV2, 22, 2, NPCM7XX_CLK_S_APB5,
 411         NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB5},
 412         /*23-22 APB5CKDIV*/
 413         {NPCM7XX_CLKDIV2, 16, 5, NPCM7XX_CLK_S_CLKOUT,
 414         NPCM7XX_CLK_S_CLKOUT_MUX, 0, 0, NPCM7XX_CLK_CLKOUT},
 415         /*20-16 CLKOUTDIV*/
 416         {NPCM7XX_CLKDIV2, 13, 3, NPCM7XX_CLK_S_GFX,
 417         NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_GFX},
 418         /*15-13 GFXCKDIV*/
 419         {NPCM7XX_CLKDIV2, 8, 5, NPCM7XX_CLK_S_USB_BRIDGE,
 420         NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU},
 421         /*12-8 SUCKDIV*/
 422         {NPCM7XX_CLKDIV2, 4, 4, NPCM7XX_CLK_S_USB_HOST,
 423         NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU48},
 424         /*7-4 SU48CKDIV*/
 425         {NPCM7XX_CLKDIV2, 0, 4, NPCM7XX_CLK_S_SDHC,
 426         NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_SDHC}
 427         ,/*3-0 SD1CKDIV*/
 428
 429         {NPCM7XX_CLKDIV3, 6, 5, NPCM7XX_CLK_S_SPI0,
 430         NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI0},
 431         /*10-6 SPI0CKDV*/
 432         {NPCM7XX_CLKDIV3, 1, 5, NPCM7XX_CLK_S_SPIX,
 433         NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPIX},
 434         /*5-1 SPIXCKDV*/
 435
 436 };
 437
 438 static const struct npcm7xx_clk_gate_data npcm7xx_gates[] __initconst = {
 439         {NPCM7XX_CLKEN1, 31, "smb1-gate", NPCM7XX_CLK_S_APB2, 0},
 440         {NPCM7XX_CLKEN1, 30, "smb0-gate", NPCM7XX_CLK_S_APB2, 0},
 441         {NPCM7XX_CLKEN1, 29, "smb7-gate", NPCM7XX_CLK_S_APB2, 0},
 442         {NPCM7XX_CLKEN1, 28, "smb6-gate", NPCM7XX_CLK_S_APB2, 0},
 443         {NPCM7XX_CLKEN1, 27, "adc-gate", NPCM7XX_CLK_S_APB1, 0},
 444         {NPCM7XX_CLKEN1, 26, "wdt-gate", NPCM7XX_CLK_S_TIMER, 0},
 445         {NPCM7XX_CLKEN1, 25, "usbdev3-gate", NPCM7XX_CLK_S_AHB, 0},
 446         {NPCM7XX_CLKEN1, 24, "usbdev6-gate", NPCM7XX_CLK_S_AHB, 0},
 447         {NPCM7XX_CLKEN1, 23, "usbdev5-gate", NPCM7XX_CLK_S_AHB, 0},
 448         {NPCM7XX_CLKEN1, 22, "usbdev4-gate", NPCM7XX_CLK_S_AHB, 0},
 449         {NPCM7XX_CLKEN1, 21, "emc2-gate", NPCM7XX_CLK_S_AHB, 0},
 450         {NPCM7XX_CLKEN1, 20, "timer5_9-gate", NPCM7XX_CLK_S_APB1, 0},
 451         {NPCM7XX_CLKEN1, 19, "timer0_4-gate", NPCM7XX_CLK_S_APB1, 0},
 452         {NPCM7XX_CLKEN1, 18, "pwmm0-gate", NPCM7XX_CLK_S_APB3, 0},
 453         {NPCM7XX_CLKEN1, 17, "huart-gate", NPCM7XX_CLK_S_UART, 0},
 454         {NPCM7XX_CLKEN1, 16, "smb5-gate", NPCM7XX_CLK_S_APB2, 0},
 455         {NPCM7XX_CLKEN1, 15, "smb4-gate", NPCM7XX_CLK_S_APB2, 0},
 456         {NPCM7XX_CLKEN1, 14, "smb3-gate", NPCM7XX_CLK_S_APB2, 0},
 457         {NPCM7XX_CLKEN1, 13, "smb2-gate", NPCM7XX_CLK_S_APB2, 0},
 458         {NPCM7XX_CLKEN1, 12, "mc-gate", NPCM7XX_CLK_S_MC, 0},
 459         {NPCM7XX_CLKEN1, 11, "uart01-gate", NPCM7XX_CLK_S_APB1, 0},
 460         {NPCM7XX_CLKEN1, 10, "aes-gate", NPCM7XX_CLK_S_AHB, 0},
 461         {NPCM7XX_CLKEN1, 9, "peci-gate", NPCM7XX_CLK_S_APB3, 0},
 462         {NPCM7XX_CLKEN1, 8, "usbdev2-gate", NPCM7XX_CLK_S_AHB, 0},
 463         {NPCM7XX_CLKEN1, 7, "uart23-gate", NPCM7XX_CLK_S_APB1, 0},
 464         {NPCM7XX_CLKEN1, 6, "emc1-gate", NPCM7XX_CLK_S_AHB, 0},
 465         {NPCM7XX_CLKEN1, 5, "usbdev1-gate", NPCM7XX_CLK_S_AHB, 0},
 466         {NPCM7XX_CLKEN1, 4, "shm-gate", NPCM7XX_CLK_S_AHB, 0},
 467         /* bit 3 is reserved */
 468         {NPCM7XX_CLKEN1, 2, "kcs-gate", NPCM7XX_CLK_S_APB1, 0},
 469         {NPCM7XX_CLKEN1, 1, "spi3-gate", NPCM7XX_CLK_S_AHB, 0},
 470         {NPCM7XX_CLKEN1, 0, "spi0-gate", NPCM7XX_CLK_S_AHB, 0},
 471
 472         {NPCM7XX_CLKEN2, 31, "cp-gate", NPCM7XX_CLK_S_AHB, 0},
 473         {NPCM7XX_CLKEN2, 30, "tock-gate", NPCM7XX_CLK_S_TOCK, 0},
 474         /* bit 29 is reserved */
 475         {NPCM7XX_CLKEN2, 28, "gmac1-gate", NPCM7XX_CLK_S_AHB, 0},
 476         {NPCM7XX_CLKEN2, 27, "usbif-gate", NPCM7XX_CLK_S_USBIF, 0},
 477         {NPCM7XX_CLKEN2, 26, "usbhost-gate", NPCM7XX_CLK_S_AHB, 0},
 478         {NPCM7XX_CLKEN2, 25, "gmac2-gate", NPCM7XX_CLK_S_AHB, 0},
 479         /* bit 24 is reserved */
 480         {NPCM7XX_CLKEN2, 23, "pspi2-gate", NPCM7XX_CLK_S_APB5, 0},
 481         {NPCM7XX_CLKEN2, 22, "pspi1-gate", NPCM7XX_CLK_S_APB5, 0},
 482         {NPCM7XX_CLKEN2, 21, "3des-gate", NPCM7XX_CLK_S_AHB, 0},
 483         /* bit 20 is reserved */
 484         {NPCM7XX_CLKEN2, 19, "siox2-gate", NPCM7XX_CLK_S_APB3, 0},
 485         {NPCM7XX_CLKEN2, 18, "siox1-gate", NPCM7XX_CLK_S_APB3, 0},
 486         /* bit 17 is reserved */
 487         {NPCM7XX_CLKEN2, 16, "fuse-gate", NPCM7XX_CLK_S_APB4, 0},
 488         /*  bit 15 is reserved */
 489         {NPCM7XX_CLKEN2, 14, "vcd-gate", NPCM7XX_CLK_S_AHB, 0},
 490         {NPCM7XX_CLKEN2, 13, "ece-gate", NPCM7XX_CLK_S_AHB, 0},
 491         {NPCM7XX_CLKEN2, 12, "vdma-gate", NPCM7XX_CLK_S_AHB, 0},
 492         {NPCM7XX_CLKEN2, 11, "ahbpcibrg-gate", NPCM7XX_CLK_S_AHB, 0},
 493         {NPCM7XX_CLKEN2, 10, "gfxsys-gate", NPCM7XX_CLK_S_APB1, 0},
 494         {NPCM7XX_CLKEN2, 9, "sdhc-gate", NPCM7XX_CLK_S_AHB, 0},
 495         {NPCM7XX_CLKEN2, 8, "mmc-gate", NPCM7XX_CLK_S_AHB, 0},
 496         {NPCM7XX_CLKEN2, 7, "mft7-gate", NPCM7XX_CLK_S_APB4, 0},
 497         {NPCM7XX_CLKEN2, 6, "mft6-gate", NPCM7XX_CLK_S_APB4, 0},
 498         {NPCM7XX_CLKEN2, 5, "mft5-gate", NPCM7XX_CLK_S_APB4, 0},
 499         {NPCM7XX_CLKEN2, 4, "mft4-gate", NPCM7XX_CLK_S_APB4, 0},
 500         {NPCM7XX_CLKEN2, 3, "mft3-gate", NPCM7XX_CLK_S_APB4, 0},
 501         {NPCM7XX_CLKEN2, 2, "mft2-gate", NPCM7XX_CLK_S_APB4, 0},
 502         {NPCM7XX_CLKEN2, 1, "mft1-gate", NPCM7XX_CLK_S_APB4, 0},
 503         {NPCM7XX_CLKEN2, 0, "mft0-gate", NPCM7XX_CLK_S_APB4, 0},
 504
 505         {NPCM7XX_CLKEN3, 31, "gpiom7-gate", NPCM7XX_CLK_S_APB1, 0},
 506         {NPCM7XX_CLKEN3, 30, "gpiom6-gate", NPCM7XX_CLK_S_APB1, 0},
 507         {NPCM7XX_CLKEN3, 29, "gpiom5-gate", NPCM7XX_CLK_S_APB1, 0},
 508         {NPCM7XX_CLKEN3, 28, "gpiom4-gate", NPCM7XX_CLK_S_APB1, 0},
 509         {NPCM7XX_CLKEN3, 27, "gpiom3-gate", NPCM7XX_CLK_S_APB1, 0},
 510         {NPCM7XX_CLKEN3, 26, "gpiom2-gate", NPCM7XX_CLK_S_APB1, 0},
 511         {NPCM7XX_CLKEN3, 25, "gpiom1-gate", NPCM7XX_CLK_S_APB1, 0},
 512         {NPCM7XX_CLKEN3, 24, "gpiom0-gate", NPCM7XX_CLK_S_APB1, 0},
 513         {NPCM7XX_CLKEN3, 23, "espi-gate", NPCM7XX_CLK_S_APB2, 0},
 514         {NPCM7XX_CLKEN3, 22, "smb11-gate", NPCM7XX_CLK_S_APB2, 0},
 515         {NPCM7XX_CLKEN3, 21, "smb10-gate", NPCM7XX_CLK_S_APB2, 0},
 516         {NPCM7XX_CLKEN3, 20, "smb9-gate", NPCM7XX_CLK_S_APB2, 0},
 517         {NPCM7XX_CLKEN3, 19, "smb8-gate", NPCM7XX_CLK_S_APB2, 0},
 518         {NPCM7XX_CLKEN3, 18, "smb15-gate", NPCM7XX_CLK_S_APB2, 0},
 519         {NPCM7XX_CLKEN3, 17, "rng-gate", NPCM7XX_CLK_S_APB1, 0},
 520         {NPCM7XX_CLKEN3, 16, "timer10_14-gate", NPCM7XX_CLK_S_APB1, 0},
 521         {NPCM7XX_CLKEN3, 15, "pcirc-gate", NPCM7XX_CLK_S_AHB, 0},
 522         {NPCM7XX_CLKEN3, 14, "sececc-gate", NPCM7XX_CLK_S_AHB, 0},
 523         {NPCM7XX_CLKEN3, 13, "sha-gate", NPCM7XX_CLK_S_AHB, 0},
 524         {NPCM7XX_CLKEN3, 12, "smb14-gate", NPCM7XX_CLK_S_APB2, 0},
 525         /* bit 11 is reserved */
 526         /* bit 10 is reserved */
 527         {NPCM7XX_CLKEN3, 9, "pcimbx-gate", NPCM7XX_CLK_S_AHB, 0},
 528         /* bit 8 is reserved */
 529         {NPCM7XX_CLKEN3, 7, "usbdev9-gate", NPCM7XX_CLK_S_AHB, 0},
 530         {NPCM7XX_CLKEN3, 6, "usbdev8-gate", NPCM7XX_CLK_S_AHB, 0},
 531         {NPCM7XX_CLKEN3, 5, "usbdev7-gate", NPCM7XX_CLK_S_AHB, 0},
 532         {NPCM7XX_CLKEN3, 4, "usbdev0-gate", NPCM7XX_CLK_S_AHB, 0},
 533         {NPCM7XX_CLKEN3, 3, "smb13-gate", NPCM7XX_CLK_S_APB2, 0},
 534         {NPCM7XX_CLKEN3, 2, "spix-gate", NPCM7XX_CLK_S_AHB, 0},
 535         {NPCM7XX_CLKEN3, 1, "smb12-gate", NPCM7XX_CLK_S_APB2, 0},
 536         {NPCM7XX_CLKEN3, 0, "pwmm1-gate", NPCM7XX_CLK_S_APB3, 0},
 537 };
 538
 539 static DEFINE_SPINLOCK(npcm7xx_clk_lock);
 540
 541 static void __init npcm7xx_clk_init(struct device_node *clk_np)
 542 {
 543         struct clk_hw_onecell_data *npcm7xx_clk_data;
 544         void __iomem *clk_base;
 545         struct resource res;
 546         struct clk_hw *hw;
 547         int ret;
 548         int i;
 549
 550         ret = of_address_to_resource(clk_np, 0, &res);
 551         if (ret) {
 552                 pr_err("%s: failed to get resource, ret %d\n", clk_np->name,
 553                         ret);
 554                 return;
 555         }
 556
 557         clk_base = ioremap(res.start, resource_size(&res));
 558         if (!clk_base)
 559                 goto npcm7xx_init_error;
 560
 561         npcm7xx_clk_data = kzalloc(sizeof(*npcm7xx_clk_data->hws) *
 562                 NPCM7XX_NUM_CLOCKS + sizeof(npcm7xx_clk_data), GFP_KERNEL);
 563         if (!npcm7xx_clk_data)
 564                 goto npcm7xx_init_np_err;
 565
 566         npcm7xx_clk_data->num = NPCM7XX_NUM_CLOCKS;
 567
 568         for (i = 0; i < NPCM7XX_NUM_CLOCKS; i++)
 569                 npcm7xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
 570
 571         /* Register plls */
 572         for (i = 0; i < ARRAY_SIZE(npcm7xx_plls); i++) {
 573                 const struct npcm7xx_clk_pll_data *pll_data = &npcm7xx_plls[i];
 574
 575                 hw = npcm7xx_clk_register_pll(clk_base + pll_data->reg,
 576                         pll_data->name, pll_data->parent_name, pll_data->flags);
 577                 if (IS_ERR(hw)) {
 578                         pr_err("npcm7xx_clk: Can't register pll\n");
 579                         goto npcm7xx_init_fail;
 580                 }
 581
 582                 if (pll_data->onecell_idx >= 0)
 583                         npcm7xx_clk_data->hws[pll_data->onecell_idx] = hw;
 584         }
 585
 586         /* Register fixed dividers */
 587         hw = clk_hw_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL1_DIV2,
 588                         NPCM7XX_CLK_S_PLL1, 0, 1, 2);
 589         if (IS_ERR(hw)) {
 590                 pr_err("npcm7xx_clk: Can't register fixed div\n");
 591                 goto npcm7xx_init_fail;
 592         }
 593
 594         hw = clk_hw_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL2_DIV2,
 595                         NPCM7XX_CLK_S_PLL2, 0, 1, 2);
 596         if (IS_ERR(hw)) {
 597                 pr_err("npcm7xx_clk: Can't register div2\n");
 598                 goto npcm7xx_init_fail;
 599         }
 600
 601         /* Register muxes */
 602         for (i = 0; i < ARRAY_SIZE(npcm7xx_muxes); i++) {
 603                 const struct npcm7xx_clk_mux_data *mux_data = &npcm7xx_muxes[i];
 604
 605                 hw = clk_hw_register_mux_table(NULL,
 606                         mux_data->name,
 607                         mux_data->parent_names, mux_data->num_parents,
 608                         mux_data->flags, clk_base + NPCM7XX_CLKSEL,
 609                         mux_data->shift, mux_data->mask, 0,
 610                         mux_data->table, &npcm7xx_clk_lock);
 611
 612                 if (IS_ERR(hw)) {
 613                         pr_err("npcm7xx_clk: Can't register mux\n");
 614                         goto npcm7xx_init_fail;
 615                 }
 616
 617                 if (mux_data->onecell_idx >= 0)
 618                         npcm7xx_clk_data->hws[mux_data->onecell_idx] = hw;
 619         }
 620
 621         /* Register clock dividers specified in npcm7xx_divs */
 622         for (i = 0; i < ARRAY_SIZE(npcm7xx_divs); i++) {
 623                 const struct npcm7xx_clk_div_data *div_data = &npcm7xx_divs[i];
 624
 625                 hw = clk_hw_register_divider(NULL, div_data->name,
 626                                 div_data->parent_name,
 627                                 div_data->flags,
 628                                 clk_base + div_data->reg,
 629                                 div_data->shift, div_data->width,
 630                                 div_data->clk_divider_flags, &npcm7xx_clk_lock);
 631                 if (IS_ERR(hw)) {
 632                         pr_err("npcm7xx_clk: Can't register div table\n");
 633                         goto npcm7xx_init_fail;
 634                 }
 635
 636                 if (div_data->onecell_idx >= 0)
 637                         npcm7xx_clk_data->hws[div_data->onecell_idx] = hw;
 638         }
 639
 640         ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get,
 641                                         npcm7xx_clk_data);
 642         if (ret)
 643                 pr_err("failed to add DT provider: %d\n", ret);
 644
 645         of_node_put(clk_np);
 646
 647         return;
 648
 649 npcm7xx_init_fail:
 650         kfree(npcm7xx_clk_data->hws);
 651 npcm7xx_init_np_err:
 652         iounmap(clk_base);
 653 npcm7xx_init_error:
 654         of_node_put(clk_np);
 655 }
 656 CLK_OF_DECLARE(npcm7xx_clk_init, "nuvoton,npcm750-clk", npcm7xx_clk_init);