2 * linux/arch/arm/plat-pxa/gpio.c
4 * Generic PXA GPIO handling
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/gpio-pxa.h>
19 #include <linux/init.h>
20 #include <linux/irq.h>
21 #include <linux/irqdomain.h>
24 #include <linux/of_device.h>
25 #include <linux/platform_device.h>
26 #include <linux/syscore_ops.h>
27 #include <linux/slab.h>
29 #include <mach/irqs.h>
32 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
33 * one set of registers. The register offsets are organized below:
35 * GPLR GPDR GPSR GPCR GRER GFER GEDR
36 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
37 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
38 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
40 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
41 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
42 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
45 * BANK 3 is only available on PXA27x and later processors.
46 * BANK 4 and 5 are only available on PXA935
49 #define GPLR_OFFSET 0x00
50 #define GPDR_OFFSET 0x0C
51 #define GPSR_OFFSET 0x18
52 #define GPCR_OFFSET 0x24
53 #define GRER_OFFSET 0x30
54 #define GFER_OFFSET 0x3C
55 #define GEDR_OFFSET 0x48
56 #define GAFR_OFFSET 0x54
57 #define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
59 #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
64 static struct irq_domain
*domain
;
65 static struct device_node
*pxa_gpio_of_node
;
68 struct pxa_gpio_chip
{
69 struct gpio_chip chip
;
70 void __iomem
*regbase
;
73 unsigned long irq_mask
;
74 unsigned long irq_edge_rise
;
75 unsigned long irq_edge_fall
;
76 int (*set_wake
)(unsigned int gpio
, unsigned int on
);
79 unsigned long saved_gplr
;
80 unsigned long saved_gpdr
;
81 unsigned long saved_grer
;
82 unsigned long saved_gfer
;
95 static DEFINE_SPINLOCK(gpio_lock
);
96 static struct pxa_gpio_chip
*pxa_gpio_chips
;
98 static void __iomem
*gpio_reg_base
;
100 #define for_each_gpio_chip(i, c) \
101 for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
103 static inline void __iomem
*gpio_chip_base(struct gpio_chip
*c
)
105 return container_of(c
, struct pxa_gpio_chip
, chip
)->regbase
;
108 static inline struct pxa_gpio_chip
*gpio_to_pxachip(unsigned gpio
)
110 return &pxa_gpio_chips
[gpio_to_bank(gpio
)];
113 static inline int gpio_is_pxa_type(int type
)
115 return (type
& MMP_GPIO
) == 0;
118 static inline int gpio_is_mmp_type(int type
)
120 return (type
& MMP_GPIO
) != 0;
123 /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
124 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
126 static inline int __gpio_is_inverted(int gpio
)
128 if ((gpio_type
== PXA26X_GPIO
) && (gpio
> 85))
134 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
135 * function of a GPIO, and GPDRx cannot be altered once configured. It
136 * is attributed as "occupied" here (I know this terminology isn't
137 * accurate, you are welcome to propose a better one :-)
139 static inline int __gpio_is_occupied(unsigned gpio
)
141 struct pxa_gpio_chip
*pxachip
;
143 unsigned long gafr
= 0, gpdr
= 0;
144 int ret
, af
= 0, dir
= 0;
146 pxachip
= gpio_to_pxachip(gpio
);
147 base
= gpio_chip_base(&pxachip
->chip
);
148 gpdr
= readl_relaxed(base
+ GPDR_OFFSET
);
154 gafr
= readl_relaxed(base
+ GAFR_OFFSET
);
155 af
= (gafr
>> ((gpio
& 0xf) * 2)) & 0x3;
156 dir
= gpdr
& GPIO_bit(gpio
);
158 if (__gpio_is_inverted(gpio
))
159 ret
= (af
!= 1) || (dir
== 0);
161 ret
= (af
!= 0) || (dir
!= 0);
164 ret
= gpdr
& GPIO_bit(gpio
);
170 #ifdef CONFIG_ARCH_PXA
171 static inline int __pxa_gpio_to_irq(int gpio
)
173 if (gpio_is_pxa_type(gpio_type
))
174 return PXA_GPIO_TO_IRQ(gpio
);
178 static inline int __pxa_irq_to_gpio(int irq
)
180 if (gpio_is_pxa_type(gpio_type
))
181 return irq
- PXA_GPIO_TO_IRQ(0);
185 static inline int __pxa_gpio_to_irq(int gpio
) { return -1; }
186 static inline int __pxa_irq_to_gpio(int irq
) { return -1; }
189 #ifdef CONFIG_ARCH_MMP
190 static inline int __mmp_gpio_to_irq(int gpio
)
192 if (gpio_is_mmp_type(gpio_type
))
193 return MMP_GPIO_TO_IRQ(gpio
);
197 static inline int __mmp_irq_to_gpio(int irq
)
199 if (gpio_is_mmp_type(gpio_type
))
200 return irq
- MMP_GPIO_TO_IRQ(0);
204 static inline int __mmp_gpio_to_irq(int gpio
) { return -1; }
205 static inline int __mmp_irq_to_gpio(int irq
) { return -1; }
208 static int pxa_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
212 gpio
= chip
->base
+ offset
;
213 ret
= __pxa_gpio_to_irq(gpio
);
216 return __mmp_gpio_to_irq(gpio
);
219 int pxa_irq_to_gpio(int irq
)
223 ret
= __pxa_irq_to_gpio(irq
);
226 return __mmp_irq_to_gpio(irq
);
229 static int pxa_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
231 void __iomem
*base
= gpio_chip_base(chip
);
232 uint32_t value
, mask
= 1 << offset
;
235 spin_lock_irqsave(&gpio_lock
, flags
);
237 value
= readl_relaxed(base
+ GPDR_OFFSET
);
238 if (__gpio_is_inverted(chip
->base
+ offset
))
242 writel_relaxed(value
, base
+ GPDR_OFFSET
);
244 spin_unlock_irqrestore(&gpio_lock
, flags
);
248 static int pxa_gpio_direction_output(struct gpio_chip
*chip
,
249 unsigned offset
, int value
)
251 void __iomem
*base
= gpio_chip_base(chip
);
252 uint32_t tmp
, mask
= 1 << offset
;
255 writel_relaxed(mask
, base
+ (value
? GPSR_OFFSET
: GPCR_OFFSET
));
257 spin_lock_irqsave(&gpio_lock
, flags
);
259 tmp
= readl_relaxed(base
+ GPDR_OFFSET
);
260 if (__gpio_is_inverted(chip
->base
+ offset
))
264 writel_relaxed(tmp
, base
+ GPDR_OFFSET
);
266 spin_unlock_irqrestore(&gpio_lock
, flags
);
270 static int pxa_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
272 return readl_relaxed(gpio_chip_base(chip
) + GPLR_OFFSET
) & (1 << offset
);
275 static void pxa_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
277 writel_relaxed(1 << offset
, gpio_chip_base(chip
) +
278 (value
? GPSR_OFFSET
: GPCR_OFFSET
));
281 #ifdef CONFIG_OF_GPIO
282 static int pxa_gpio_of_xlate(struct gpio_chip
*gc
,
283 const struct of_phandle_args
*gpiospec
,
286 if (gpiospec
->args
[0] > pxa_last_gpio
)
289 if (gc
!= &pxa_gpio_chips
[gpiospec
->args
[0] / 32].chip
)
293 *flags
= gpiospec
->args
[1];
295 return gpiospec
->args
[0] % 32;
299 static int __devinit
pxa_init_gpio_chip(int gpio_end
,
300 int (*set_wake
)(unsigned int, unsigned int))
302 int i
, gpio
, nbanks
= gpio_to_bank(gpio_end
) + 1;
303 struct pxa_gpio_chip
*chips
;
305 chips
= kzalloc(nbanks
* sizeof(struct pxa_gpio_chip
), GFP_KERNEL
);
307 pr_err("%s: failed to allocate GPIO chips\n", __func__
);
311 for (i
= 0, gpio
= 0; i
< nbanks
; i
++, gpio
+= 32) {
312 struct gpio_chip
*c
= &chips
[i
].chip
;
314 sprintf(chips
[i
].label
, "gpio-%d", i
);
315 chips
[i
].regbase
= gpio_reg_base
+ BANK_OFF(i
);
316 chips
[i
].set_wake
= set_wake
;
319 c
->label
= chips
[i
].label
;
321 c
->direction_input
= pxa_gpio_direction_input
;
322 c
->direction_output
= pxa_gpio_direction_output
;
323 c
->get
= pxa_gpio_get
;
324 c
->set
= pxa_gpio_set
;
325 c
->to_irq
= pxa_gpio_to_irq
;
326 #ifdef CONFIG_OF_GPIO
327 c
->of_node
= pxa_gpio_of_node
;
328 c
->of_xlate
= pxa_gpio_of_xlate
;
329 c
->of_gpio_n_cells
= 2;
332 /* number of GPIOs on last bank may be less than 32 */
333 c
->ngpio
= (gpio
+ 31 > gpio_end
) ? (gpio_end
- gpio
+ 1) : 32;
336 pxa_gpio_chips
= chips
;
340 /* Update only those GRERx and GFERx edge detection register bits if those
341 * bits are set in c->irq_mask
343 static inline void update_edge_detect(struct pxa_gpio_chip
*c
)
347 grer
= readl_relaxed(c
->regbase
+ GRER_OFFSET
) & ~c
->irq_mask
;
348 gfer
= readl_relaxed(c
->regbase
+ GFER_OFFSET
) & ~c
->irq_mask
;
349 grer
|= c
->irq_edge_rise
& c
->irq_mask
;
350 gfer
|= c
->irq_edge_fall
& c
->irq_mask
;
351 writel_relaxed(grer
, c
->regbase
+ GRER_OFFSET
);
352 writel_relaxed(gfer
, c
->regbase
+ GFER_OFFSET
);
355 static int pxa_gpio_irq_type(struct irq_data
*d
, unsigned int type
)
357 struct pxa_gpio_chip
*c
;
358 int gpio
= pxa_irq_to_gpio(d
->irq
);
359 unsigned long gpdr
, mask
= GPIO_bit(gpio
);
361 c
= gpio_to_pxachip(gpio
);
363 if (type
== IRQ_TYPE_PROBE
) {
364 /* Don't mess with enabled GPIOs using preconfigured edges or
365 * GPIOs set to alternate function or to output during probe
367 if ((c
->irq_edge_rise
| c
->irq_edge_fall
) & GPIO_bit(gpio
))
370 if (__gpio_is_occupied(gpio
))
373 type
= IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
;
376 gpdr
= readl_relaxed(c
->regbase
+ GPDR_OFFSET
);
378 if (__gpio_is_inverted(gpio
))
379 writel_relaxed(gpdr
| mask
, c
->regbase
+ GPDR_OFFSET
);
381 writel_relaxed(gpdr
& ~mask
, c
->regbase
+ GPDR_OFFSET
);
383 if (type
& IRQ_TYPE_EDGE_RISING
)
384 c
->irq_edge_rise
|= mask
;
386 c
->irq_edge_rise
&= ~mask
;
388 if (type
& IRQ_TYPE_EDGE_FALLING
)
389 c
->irq_edge_fall
|= mask
;
391 c
->irq_edge_fall
&= ~mask
;
393 update_edge_detect(c
);
395 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__
, d
->irq
, gpio
,
396 ((type
& IRQ_TYPE_EDGE_RISING
) ? " rising" : ""),
397 ((type
& IRQ_TYPE_EDGE_FALLING
) ? " falling" : ""));
401 static void pxa_gpio_demux_handler(unsigned int irq
, struct irq_desc
*desc
)
403 struct pxa_gpio_chip
*c
;
404 int loop
, gpio
, gpio_base
, n
;
409 for_each_gpio_chip(gpio
, c
) {
410 gpio_base
= c
->chip
.base
;
412 gedr
= readl_relaxed(c
->regbase
+ GEDR_OFFSET
);
413 gedr
= gedr
& c
->irq_mask
;
414 writel_relaxed(gedr
, c
->regbase
+ GEDR_OFFSET
);
416 n
= find_first_bit(&gedr
, BITS_PER_LONG
);
417 while (n
< BITS_PER_LONG
) {
420 generic_handle_irq(gpio_to_irq(gpio_base
+ n
));
421 n
= find_next_bit(&gedr
, BITS_PER_LONG
, n
+ 1);
427 static void pxa_ack_muxed_gpio(struct irq_data
*d
)
429 int gpio
= pxa_irq_to_gpio(d
->irq
);
430 struct pxa_gpio_chip
*c
= gpio_to_pxachip(gpio
);
432 writel_relaxed(GPIO_bit(gpio
), c
->regbase
+ GEDR_OFFSET
);
435 static void pxa_mask_muxed_gpio(struct irq_data
*d
)
437 int gpio
= pxa_irq_to_gpio(d
->irq
);
438 struct pxa_gpio_chip
*c
= gpio_to_pxachip(gpio
);
441 c
->irq_mask
&= ~GPIO_bit(gpio
);
443 grer
= readl_relaxed(c
->regbase
+ GRER_OFFSET
) & ~GPIO_bit(gpio
);
444 gfer
= readl_relaxed(c
->regbase
+ GFER_OFFSET
) & ~GPIO_bit(gpio
);
445 writel_relaxed(grer
, c
->regbase
+ GRER_OFFSET
);
446 writel_relaxed(gfer
, c
->regbase
+ GFER_OFFSET
);
449 static int pxa_gpio_set_wake(struct irq_data
*d
, unsigned int on
)
451 int gpio
= pxa_irq_to_gpio(d
->irq
);
452 struct pxa_gpio_chip
*c
= gpio_to_pxachip(gpio
);
455 return c
->set_wake(gpio
, on
);
460 static void pxa_unmask_muxed_gpio(struct irq_data
*d
)
462 int gpio
= pxa_irq_to_gpio(d
->irq
);
463 struct pxa_gpio_chip
*c
= gpio_to_pxachip(gpio
);
465 c
->irq_mask
|= GPIO_bit(gpio
);
466 update_edge_detect(c
);
469 static struct irq_chip pxa_muxed_gpio_chip
= {
471 .irq_ack
= pxa_ack_muxed_gpio
,
472 .irq_mask
= pxa_mask_muxed_gpio
,
473 .irq_unmask
= pxa_unmask_muxed_gpio
,
474 .irq_set_type
= pxa_gpio_irq_type
,
475 .irq_set_wake
= pxa_gpio_set_wake
,
478 static int pxa_gpio_nums(void)
482 #ifdef CONFIG_ARCH_PXA
483 if (cpu_is_pxa25x()) {
484 #ifdef CONFIG_CPU_PXA26x
486 gpio_type
= PXA26X_GPIO
;
487 #elif defined(CONFIG_PXA25x)
489 gpio_type
= PXA26X_GPIO
;
490 #endif /* CONFIG_CPU_PXA26x */
491 } else if (cpu_is_pxa27x()) {
493 gpio_type
= PXA27X_GPIO
;
494 } else if (cpu_is_pxa93x() || cpu_is_pxa95x()) {
496 gpio_type
= PXA93X_GPIO
;
497 } else if (cpu_is_pxa3xx()) {
499 gpio_type
= PXA3XX_GPIO
;
501 #endif /* CONFIG_ARCH_PXA */
503 #ifdef CONFIG_ARCH_MMP
504 if (cpu_is_pxa168() || cpu_is_pxa910()) {
506 gpio_type
= MMP_GPIO
;
507 } else if (cpu_is_mmp2()) {
509 gpio_type
= MMP_GPIO
;
511 #endif /* CONFIG_ARCH_MMP */
516 static struct of_device_id pxa_gpio_dt_ids
[] = {
517 { .compatible
= "mrvl,pxa-gpio" },
518 { .compatible
= "mrvl,mmp-gpio", .data
= (void *)MMP_GPIO
},
522 static int pxa_irq_domain_map(struct irq_domain
*d
, unsigned int irq
,
525 irq_set_chip_and_handler(irq
, &pxa_muxed_gpio_chip
,
527 set_irq_flags(irq
, IRQF_VALID
| IRQF_PROBE
);
531 const struct irq_domain_ops pxa_irq_domain_ops
= {
532 .map
= pxa_irq_domain_map
,
533 .xlate
= irq_domain_xlate_twocell
,
536 static int __devinit
pxa_gpio_probe_dt(struct platform_device
*pdev
)
538 int ret
, nr_banks
, nr_gpios
, irq_base
;
539 struct device_node
*prev
, *next
, *np
= pdev
->dev
.of_node
;
540 const struct of_device_id
*of_id
=
541 of_match_device(pxa_gpio_dt_ids
, &pdev
->dev
);
544 dev_err(&pdev
->dev
, "Failed to find gpio controller\n");
547 gpio_type
= (int)of_id
->data
;
549 next
= of_get_next_child(np
, NULL
);
552 dev_err(&pdev
->dev
, "Failed to find child gpio node\n");
556 for (nr_banks
= 1; ; nr_banks
++) {
557 next
= of_get_next_child(np
, prev
);
563 nr_gpios
= nr_banks
<< 5;
564 pxa_last_gpio
= nr_gpios
- 1;
566 irq_base
= irq_alloc_descs(-1, 0, nr_gpios
, 0);
568 dev_err(&pdev
->dev
, "Failed to allocate IRQ numbers\n");
571 domain
= irq_domain_add_legacy(np
, nr_gpios
, irq_base
, 0,
572 &pxa_irq_domain_ops
, NULL
);
573 pxa_gpio_of_node
= np
;
576 iounmap(gpio_reg_base
);
580 #define pxa_gpio_probe_dt(pdev) (-1)
583 static int __devinit
pxa_gpio_probe(struct platform_device
*pdev
)
585 struct pxa_gpio_chip
*c
;
586 struct resource
*res
;
588 struct pxa_gpio_platform_data
*info
;
589 int gpio
, irq
, ret
, use_of
= 0;
590 int irq0
= 0, irq1
= 0, irq_mux
, gpio_offset
= 0;
592 ret
= pxa_gpio_probe_dt(pdev
);
594 pxa_last_gpio
= pxa_gpio_nums();
600 irq0
= platform_get_irq_byname(pdev
, "gpio0");
601 irq1
= platform_get_irq_byname(pdev
, "gpio1");
602 irq_mux
= platform_get_irq_byname(pdev
, "gpio_mux");
603 if ((irq0
> 0 && irq1
<= 0) || (irq0
<= 0 && irq1
> 0)
606 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
609 gpio_reg_base
= ioremap(res
->start
, resource_size(res
));
616 clk
= clk_get(&pdev
->dev
, NULL
);
618 dev_err(&pdev
->dev
, "Error %ld to get gpio clock\n",
620 iounmap(gpio_reg_base
);
623 ret
= clk_prepare(clk
);
626 iounmap(gpio_reg_base
);
629 ret
= clk_enable(clk
);
633 iounmap(gpio_reg_base
);
637 /* Initialize GPIO chips */
638 info
= dev_get_platdata(&pdev
->dev
);
639 pxa_init_gpio_chip(pxa_last_gpio
, info
? info
->gpio_set_wake
: NULL
);
641 /* clear all GPIO edge detects */
642 for_each_gpio_chip(gpio
, c
) {
643 writel_relaxed(0, c
->regbase
+ GFER_OFFSET
);
644 writel_relaxed(0, c
->regbase
+ GRER_OFFSET
);
645 writel_relaxed(~0,c
->regbase
+ GEDR_OFFSET
);
646 /* unmask GPIO edge detect for AP side */
647 if (gpio_is_mmp_type(gpio_type
))
648 writel_relaxed(~0, c
->regbase
+ ED_MASK_OFFSET
);
652 #ifdef CONFIG_ARCH_PXA
653 irq
= gpio_to_irq(0);
654 irq_set_chip_and_handler(irq
, &pxa_muxed_gpio_chip
,
656 set_irq_flags(irq
, IRQF_VALID
| IRQF_PROBE
);
657 irq_set_chained_handler(IRQ_GPIO0
, pxa_gpio_demux_handler
);
659 irq
= gpio_to_irq(1);
660 irq_set_chip_and_handler(irq
, &pxa_muxed_gpio_chip
,
662 set_irq_flags(irq
, IRQF_VALID
| IRQF_PROBE
);
663 irq_set_chained_handler(IRQ_GPIO1
, pxa_gpio_demux_handler
);
666 for (irq
= gpio_to_irq(gpio_offset
);
667 irq
<= gpio_to_irq(pxa_last_gpio
); irq
++) {
668 irq_set_chip_and_handler(irq
, &pxa_muxed_gpio_chip
,
670 set_irq_flags(irq
, IRQF_VALID
| IRQF_PROBE
);
674 irq_set_chained_handler(irq_mux
, pxa_gpio_demux_handler
);
678 static struct platform_driver pxa_gpio_driver
= {
679 .probe
= pxa_gpio_probe
,
682 .of_match_table
= of_match_ptr(pxa_gpio_dt_ids
),
686 static int __init
pxa_gpio_init(void)
688 return platform_driver_register(&pxa_gpio_driver
);
690 postcore_initcall(pxa_gpio_init
);
693 static int pxa_gpio_suspend(void)
695 struct pxa_gpio_chip
*c
;
698 for_each_gpio_chip(gpio
, c
) {
699 c
->saved_gplr
= readl_relaxed(c
->regbase
+ GPLR_OFFSET
);
700 c
->saved_gpdr
= readl_relaxed(c
->regbase
+ GPDR_OFFSET
);
701 c
->saved_grer
= readl_relaxed(c
->regbase
+ GRER_OFFSET
);
702 c
->saved_gfer
= readl_relaxed(c
->regbase
+ GFER_OFFSET
);
704 /* Clear GPIO transition detect bits */
705 writel_relaxed(0xffffffff, c
->regbase
+ GEDR_OFFSET
);
710 static void pxa_gpio_resume(void)
712 struct pxa_gpio_chip
*c
;
715 for_each_gpio_chip(gpio
, c
) {
716 /* restore level with set/clear */
717 writel_relaxed( c
->saved_gplr
, c
->regbase
+ GPSR_OFFSET
);
718 writel_relaxed(~c
->saved_gplr
, c
->regbase
+ GPCR_OFFSET
);
720 writel_relaxed(c
->saved_grer
, c
->regbase
+ GRER_OFFSET
);
721 writel_relaxed(c
->saved_gfer
, c
->regbase
+ GFER_OFFSET
);
722 writel_relaxed(c
->saved_gpdr
, c
->regbase
+ GPDR_OFFSET
);
726 #define pxa_gpio_suspend NULL
727 #define pxa_gpio_resume NULL
730 struct syscore_ops pxa_gpio_syscore_ops
= {
731 .suspend
= pxa_gpio_suspend
,
732 .resume
= pxa_gpio_resume
,
735 static int __init
pxa_gpio_sysinit(void)
737 register_syscore_ops(&pxa_gpio_syscore_ops
);
740 postcore_initcall(pxa_gpio_sysinit
);