2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/debugfs.h>
39 #include <linux/device.h>
40 #include <linux/delay.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/of_address.h>
44 #include <linux/of_irq.h>
45 #include <linux/of_platform.h>
47 #include <sound/core.h>
48 #include <sound/pcm.h>
49 #include <sound/pcm_params.h>
50 #include <sound/initval.h>
51 #include <sound/soc.h>
52 #include <sound/dmaengine_pcm.h>
58 #define read_ssi(addr) in_be32(addr)
59 #define write_ssi(val, addr) out_be32(addr, val)
60 #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
62 #define read_ssi(addr) readl(addr)
63 #define write_ssi(val, addr) writel(val, addr)
65 * FIXME: Proper locking should be added at write_ssi_mask caller level
66 * to ensure this register read/modify/write sequence is race free.
68 static inline void write_ssi_mask(u32 __iomem
*addr
, u32 clear
, u32 set
)
70 u32 val
= readl(addr
);
71 val
= (val
& ~clear
) | set
;
77 * FSLSSI_I2S_RATES: sample rates supported by the I2S
79 * This driver currently only supports the SSI running in I2S slave mode,
80 * which means the codec determines the sample rate. Therefore, we tell
81 * ALSA that we support all rates and let the codec driver decide what rates
82 * are really supported.
84 #define FSLSSI_I2S_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \
85 SNDRV_PCM_RATE_CONTINUOUS)
88 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
90 * This driver currently only supports the SSI running in I2S slave mode.
92 * The SSI has a limitation in that the samples must be in the same byte
93 * order as the host CPU. This is because when multiple bytes are written
94 * to the STX register, the bytes and bits must be written in the same
95 * order. The STX is a shift register, so all the bits need to be aligned
96 * (bit-endianness must match byte-endianness). Processors typically write
97 * the bits within a byte in the same order that the bytes of a word are
98 * written in. So if the host CPU is big-endian, then only big-endian
99 * samples will be written to STX properly.
102 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
103 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
104 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
106 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
107 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
108 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
111 /* SIER bitflag of interrupts to enable */
112 #define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE | \
113 CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN | \
114 CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN | \
115 CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE | \
116 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN)
118 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
119 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
120 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
121 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
122 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
123 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
124 #define FSLSSI_SISR_MASK (FSLSSI_SIER_DBG_RX_FLAGS | FSLSSI_SIER_DBG_TX_FLAGS)
127 * fsl_ssi_private: per-SSI private data
129 * @ssi: pointer to the SSI's registers
130 * @ssi_phys: physical address of the SSI registers
131 * @irq: IRQ of this SSI
132 * @playback: the number of playback streams opened
133 * @capture: the number of capture streams opened
134 * @cpu_dai: the CPU DAI for this device
135 * @dev_attr: the sysfs device attribute structure
136 * @stats: SSI statistics
137 * @name: name for this device
139 struct fsl_ssi_private
{
140 struct ccsr_ssi __iomem
*ssi
;
143 unsigned int fifo_depth
;
144 struct snd_soc_dai_driver cpu_dai_drv
;
145 struct platform_device
*pdev
;
154 spinlock_t baudclk_lock
;
157 struct snd_dmaengine_dai_dma_data dma_params_tx
;
158 struct snd_dmaengine_dai_dma_data dma_params_rx
;
159 struct imx_dma_data filter_data_tx
;
160 struct imx_dma_data filter_data_rx
;
161 struct imx_pcm_fiq_params fiq_params
;
186 struct dentry
*dbg_dir
;
187 struct dentry
*dbg_stats
;
193 * fsl_ssi_isr: SSI interrupt handler
195 * Although it's possible to use the interrupt handler to send and receive
196 * data to/from the SSI, we use the DMA instead. Programming is more
197 * complicated, but the performance is much better.
199 * This interrupt handler is used only to gather statistics.
201 * @irq: IRQ of the SSI device
202 * @dev_id: pointer to the ssi_private structure for this SSI device
204 static irqreturn_t
fsl_ssi_isr(int irq
, void *dev_id
)
206 struct fsl_ssi_private
*ssi_private
= dev_id
;
207 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
208 irqreturn_t ret
= IRQ_NONE
;
212 /* We got an interrupt, so read the status register to see what we
213 were interrupted for. We mask it with the Interrupt Enable register
214 so that we only check for events that we're interested in.
216 sisr
= read_ssi(&ssi
->sisr
) & FSLSSI_SISR_MASK
;
218 if (sisr
& CCSR_SSI_SISR_RFRC
) {
219 ssi_private
->stats
.rfrc
++;
220 sisr2
|= CCSR_SSI_SISR_RFRC
;
224 if (sisr
& CCSR_SSI_SISR_TFRC
) {
225 ssi_private
->stats
.tfrc
++;
226 sisr2
|= CCSR_SSI_SISR_TFRC
;
230 if (sisr
& CCSR_SSI_SISR_CMDAU
) {
231 ssi_private
->stats
.cmdau
++;
235 if (sisr
& CCSR_SSI_SISR_CMDDU
) {
236 ssi_private
->stats
.cmddu
++;
240 if (sisr
& CCSR_SSI_SISR_RXT
) {
241 ssi_private
->stats
.rxt
++;
245 if (sisr
& CCSR_SSI_SISR_RDR1
) {
246 ssi_private
->stats
.rdr1
++;
250 if (sisr
& CCSR_SSI_SISR_RDR0
) {
251 ssi_private
->stats
.rdr0
++;
255 if (sisr
& CCSR_SSI_SISR_TDE1
) {
256 ssi_private
->stats
.tde1
++;
260 if (sisr
& CCSR_SSI_SISR_TDE0
) {
261 ssi_private
->stats
.tde0
++;
265 if (sisr
& CCSR_SSI_SISR_ROE1
) {
266 ssi_private
->stats
.roe1
++;
267 sisr2
|= CCSR_SSI_SISR_ROE1
;
271 if (sisr
& CCSR_SSI_SISR_ROE0
) {
272 ssi_private
->stats
.roe0
++;
273 sisr2
|= CCSR_SSI_SISR_ROE0
;
277 if (sisr
& CCSR_SSI_SISR_TUE1
) {
278 ssi_private
->stats
.tue1
++;
279 sisr2
|= CCSR_SSI_SISR_TUE1
;
283 if (sisr
& CCSR_SSI_SISR_TUE0
) {
284 ssi_private
->stats
.tue0
++;
285 sisr2
|= CCSR_SSI_SISR_TUE0
;
289 if (sisr
& CCSR_SSI_SISR_TFS
) {
290 ssi_private
->stats
.tfs
++;
294 if (sisr
& CCSR_SSI_SISR_RFS
) {
295 ssi_private
->stats
.rfs
++;
299 if (sisr
& CCSR_SSI_SISR_TLS
) {
300 ssi_private
->stats
.tls
++;
304 if (sisr
& CCSR_SSI_SISR_RLS
) {
305 ssi_private
->stats
.rls
++;
309 if (sisr
& CCSR_SSI_SISR_RFF1
) {
310 ssi_private
->stats
.rff1
++;
314 if (sisr
& CCSR_SSI_SISR_RFF0
) {
315 ssi_private
->stats
.rff0
++;
319 if (sisr
& CCSR_SSI_SISR_TFE1
) {
320 ssi_private
->stats
.tfe1
++;
324 if (sisr
& CCSR_SSI_SISR_TFE0
) {
325 ssi_private
->stats
.tfe0
++;
329 /* Clear the bits that we set */
331 write_ssi(sisr2
, &ssi
->sisr
);
336 #if IS_ENABLED(CONFIG_DEBUG_FS)
337 /* Show the statistics of a flag only if its interrupt is enabled. The
338 * compiler will optimze this code to a no-op if the interrupt is not
341 #define SIER_SHOW(flag, name) \
343 if (FSLSSI_SISR_MASK & CCSR_SSI_SIER_##flag) \
344 seq_printf(s, #name "=%u\n", ssi_private->stats.name); \
349 * fsl_sysfs_ssi_show: display SSI statistics
351 * Display the statistics for the current SSI device. To avoid confusion,
352 * we only show those counts that are enabled.
354 static ssize_t
fsl_ssi_stats_show(struct seq_file
*s
, void *unused
)
356 struct fsl_ssi_private
*ssi_private
= s
->private;
358 SIER_SHOW(RFRC_EN
, rfrc
);
359 SIER_SHOW(TFRC_EN
, tfrc
);
360 SIER_SHOW(CMDAU_EN
, cmdau
);
361 SIER_SHOW(CMDDU_EN
, cmddu
);
362 SIER_SHOW(RXT_EN
, rxt
);
363 SIER_SHOW(RDR1_EN
, rdr1
);
364 SIER_SHOW(RDR0_EN
, rdr0
);
365 SIER_SHOW(TDE1_EN
, tde1
);
366 SIER_SHOW(TDE0_EN
, tde0
);
367 SIER_SHOW(ROE1_EN
, roe1
);
368 SIER_SHOW(ROE0_EN
, roe0
);
369 SIER_SHOW(TUE1_EN
, tue1
);
370 SIER_SHOW(TUE0_EN
, tue0
);
371 SIER_SHOW(TFS_EN
, tfs
);
372 SIER_SHOW(RFS_EN
, rfs
);
373 SIER_SHOW(TLS_EN
, tls
);
374 SIER_SHOW(RLS_EN
, rls
);
375 SIER_SHOW(RFF1_EN
, rff1
);
376 SIER_SHOW(RFF0_EN
, rff0
);
377 SIER_SHOW(TFE1_EN
, tfe1
);
378 SIER_SHOW(TFE0_EN
, tfe0
);
383 static int fsl_ssi_stats_open(struct inode
*inode
, struct file
*file
)
385 return single_open(file
, fsl_ssi_stats_show
, inode
->i_private
);
388 static const struct file_operations fsl_ssi_stats_ops
= {
389 .open
= fsl_ssi_stats_open
,
392 .release
= single_release
,
395 static int fsl_ssi_debugfs_create(struct fsl_ssi_private
*ssi_private
,
398 ssi_private
->dbg_dir
= debugfs_create_dir(dev_name(dev
), NULL
);
399 if (!ssi_private
->dbg_dir
)
402 ssi_private
->dbg_stats
= debugfs_create_file("stats", S_IRUGO
,
403 ssi_private
->dbg_dir
, ssi_private
, &fsl_ssi_stats_ops
);
404 if (!ssi_private
->dbg_stats
) {
405 debugfs_remove(ssi_private
->dbg_dir
);
412 static void fsl_ssi_debugfs_remove(struct fsl_ssi_private
*ssi_private
)
414 debugfs_remove(ssi_private
->dbg_stats
);
415 debugfs_remove(ssi_private
->dbg_dir
);
420 static int fsl_ssi_debugfs_create(struct fsl_ssi_private
*ssi_private
,
426 static void fsl_ssi_debugfs_remove(struct fsl_ssi_private
*ssi_private
)
430 #endif /* IS_ENABLED(CONFIG_DEBUG_FS) */
432 static void fsl_ssi_setup_ac97(struct fsl_ssi_private
*ssi_private
)
434 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
437 * Setup the clock control register
439 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
441 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
445 * Enable AC97 mode and startup the SSI
447 write_ssi(CCSR_SSI_SACNT_AC97EN
| CCSR_SSI_SACNT_FV
,
449 write_ssi(0xff, &ssi
->saccdis
);
450 write_ssi(0x300, &ssi
->saccen
);
453 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
454 * codec before a stream is started.
456 write_ssi_mask(&ssi
->scr
, 0, CCSR_SSI_SCR_SSIEN
|
457 CCSR_SSI_SCR_TE
| CCSR_SSI_SCR_RE
);
459 write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi
->sor
);
462 static int fsl_ssi_setup(struct fsl_ssi_private
*ssi_private
)
464 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
466 int synchronous
= ssi_private
->cpu_dai_drv
.symmetric_rates
;
468 if (ssi_private
->imx_ac97
)
469 ssi_private
->i2s_mode
= CCSR_SSI_SCR_I2S_MODE_NORMAL
| CCSR_SSI_SCR_NET
;
471 ssi_private
->i2s_mode
= CCSR_SSI_SCR_I2S_MODE_SLAVE
;
474 * Section 16.5 of the MPC8610 reference manual says that the SSI needs
475 * to be disabled before updating the registers we set here.
477 write_ssi_mask(&ssi
->scr
, CCSR_SSI_SCR_SSIEN
, 0);
480 * Program the SSI into I2S Slave Non-Network Synchronous mode. Also
481 * enable the transmit and receive FIFO.
483 * FIXME: Little-endian samples require a different shift dir
485 write_ssi_mask(&ssi
->scr
,
486 CCSR_SSI_SCR_I2S_MODE_MASK
| CCSR_SSI_SCR_SYN
,
487 CCSR_SSI_SCR_TFR_CLK_DIS
|
488 ssi_private
->i2s_mode
|
489 (synchronous
? CCSR_SSI_SCR_SYN
: 0));
491 write_ssi(CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TFEN0
|
492 CCSR_SSI_STCR_TFSI
| CCSR_SSI_STCR_TEFS
|
493 CCSR_SSI_STCR_TSCKP
, &ssi
->stcr
);
495 write_ssi(CCSR_SSI_SRCR_RXBIT0
| CCSR_SSI_SRCR_RFEN0
|
496 CCSR_SSI_SRCR_RFSI
| CCSR_SSI_SRCR_REFS
|
497 CCSR_SSI_SRCR_RSCKP
, &ssi
->srcr
);
499 * The DC and PM bits are only used if the SSI is the clock master.
503 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
504 * use FIFO 1. We program the transmit water to signal a DMA transfer
505 * if there are only two (or fewer) elements left in the FIFO. Two
506 * elements equals one frame (left channel, right channel). This value,
507 * however, depends on the depth of the transmit buffer.
509 * We set the watermark on the same level as the DMA burstsize. For
510 * fiq it is probably better to use the biggest possible watermark
513 if (ssi_private
->use_dma
)
514 wm
= ssi_private
->fifo_depth
- 2;
516 wm
= ssi_private
->fifo_depth
;
518 write_ssi(CCSR_SSI_SFCSR_TFWM0(wm
) | CCSR_SSI_SFCSR_RFWM0(wm
) |
519 CCSR_SSI_SFCSR_TFWM1(wm
) | CCSR_SSI_SFCSR_RFWM1(wm
),
523 * For ac97 interrupts are enabled with the startup of the substream
524 * because it is also running without an active substream. Normally SSI
525 * is only enabled when there is a substream.
527 if (ssi_private
->imx_ac97
)
528 fsl_ssi_setup_ac97(ssi_private
);
535 * fsl_ssi_startup: create a new substream
537 * This is the first function called when a stream is opened.
539 * If this is the first stream open, then grab the IRQ and program most of
542 static int fsl_ssi_startup(struct snd_pcm_substream
*substream
,
543 struct snd_soc_dai
*dai
)
545 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
546 struct fsl_ssi_private
*ssi_private
=
547 snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
550 /* First, we only do fsl_ssi_setup() when SSI is going to be active.
551 * Second, fsl_ssi_setup was already called by ac97_init earlier if
552 * the driver is in ac97 mode.
554 if (!dai
->active
&& !ssi_private
->imx_ac97
) {
555 fsl_ssi_setup(ssi_private
);
556 spin_lock_irqsave(&ssi_private
->baudclk_lock
, flags
);
557 ssi_private
->baudclk_locked
= false;
558 spin_unlock_irqrestore(&ssi_private
->baudclk_lock
, flags
);
565 * fsl_ssi_hw_params - program the sample size
567 * Most of the SSI registers have been programmed in the startup function,
568 * but the word length must be programmed here. Unfortunately, programming
569 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
570 * cause a problem with supporting simultaneous playback and capture. If
571 * the SSI is already playing a stream, then that stream may be temporarily
572 * stopped when you start capture.
574 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
577 static int fsl_ssi_hw_params(struct snd_pcm_substream
*substream
,
578 struct snd_pcm_hw_params
*hw_params
, struct snd_soc_dai
*cpu_dai
)
580 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
581 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
582 unsigned int channels
= params_channels(hw_params
);
583 unsigned int sample_size
=
584 snd_pcm_format_width(params_format(hw_params
));
585 u32 wl
= CCSR_SSI_SxCCR_WL(sample_size
);
586 int enabled
= read_ssi(&ssi
->scr
) & CCSR_SSI_SCR_SSIEN
;
589 * If we're in synchronous mode, and the SSI is already enabled,
590 * then STCCR is already set properly.
592 if (enabled
&& ssi_private
->cpu_dai_drv
.symmetric_rates
)
596 * FIXME: The documentation says that SxCCR[WL] should not be
597 * modified while the SSI is enabled. The only time this can
598 * happen is if we're trying to do simultaneous playback and
599 * capture in asynchronous mode. Unfortunately, I have been enable
600 * to get that to work at all on the P1022DS. Therefore, we don't
601 * bother to disable/enable the SSI when setting SxCCR[WL], because
602 * the SSI will stop anyway. Maybe one day, this will get fixed.
605 /* In synchronous mode, the SSI uses STCCR for capture */
606 if ((substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) ||
607 ssi_private
->cpu_dai_drv
.symmetric_rates
)
608 write_ssi_mask(&ssi
->stccr
, CCSR_SSI_SxCCR_WL_MASK
, wl
);
610 write_ssi_mask(&ssi
->srccr
, CCSR_SSI_SxCCR_WL_MASK
, wl
);
612 if (!ssi_private
->imx_ac97
)
613 write_ssi_mask(&ssi
->scr
,
614 CCSR_SSI_SCR_NET
| CCSR_SSI_SCR_I2S_MODE_MASK
,
615 channels
== 1 ? 0 : ssi_private
->i2s_mode
);
621 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
623 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai
*cpu_dai
, unsigned int fmt
)
625 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
626 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
627 u32 strcr
= 0, stcr
, srcr
, scr
, mask
;
629 scr
= read_ssi(&ssi
->scr
) & ~(CCSR_SSI_SCR_SYN
| CCSR_SSI_SCR_I2S_MODE_MASK
);
630 scr
|= CCSR_SSI_SCR_NET
;
632 mask
= CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TFDIR
| CCSR_SSI_STCR_TXDIR
|
633 CCSR_SSI_STCR_TSCKP
| CCSR_SSI_STCR_TFSI
| CCSR_SSI_STCR_TFSL
|
635 stcr
= read_ssi(&ssi
->stcr
) & ~mask
;
636 srcr
= read_ssi(&ssi
->srcr
) & ~mask
;
638 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
639 case SND_SOC_DAIFMT_I2S
:
640 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
641 case SND_SOC_DAIFMT_CBS_CFS
:
642 ssi_private
->i2s_mode
= CCSR_SSI_SCR_I2S_MODE_MASTER
;
644 case SND_SOC_DAIFMT_CBM_CFM
:
645 ssi_private
->i2s_mode
= CCSR_SSI_SCR_I2S_MODE_SLAVE
;
650 scr
|= ssi_private
->i2s_mode
;
652 /* Data on rising edge of bclk, frame low, 1clk before data */
653 strcr
|= CCSR_SSI_STCR_TFSI
| CCSR_SSI_STCR_TSCKP
|
654 CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TEFS
;
656 case SND_SOC_DAIFMT_LEFT_J
:
657 /* Data on rising edge of bclk, frame high */
658 strcr
|= CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TSCKP
;
660 case SND_SOC_DAIFMT_DSP_A
:
661 /* Data on rising edge of bclk, frame high, 1clk before data */
662 strcr
|= CCSR_SSI_STCR_TFSL
| CCSR_SSI_STCR_TSCKP
|
663 CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TEFS
;
665 case SND_SOC_DAIFMT_DSP_B
:
666 /* Data on rising edge of bclk, frame high */
667 strcr
|= CCSR_SSI_STCR_TFSL
| CCSR_SSI_STCR_TSCKP
|
668 CCSR_SSI_STCR_TXBIT0
;
674 /* DAI clock inversion */
675 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
676 case SND_SOC_DAIFMT_NB_NF
:
677 /* Nothing to do for both normal cases */
679 case SND_SOC_DAIFMT_IB_NF
:
680 /* Invert bit clock */
681 strcr
^= CCSR_SSI_STCR_TSCKP
;
683 case SND_SOC_DAIFMT_NB_IF
:
684 /* Invert frame clock */
685 strcr
^= CCSR_SSI_STCR_TFSI
;
687 case SND_SOC_DAIFMT_IB_IF
:
688 /* Invert both clocks */
689 strcr
^= CCSR_SSI_STCR_TSCKP
;
690 strcr
^= CCSR_SSI_STCR_TFSI
;
696 /* DAI clock master masks */
697 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
698 case SND_SOC_DAIFMT_CBS_CFS
:
699 strcr
|= CCSR_SSI_STCR_TFDIR
| CCSR_SSI_STCR_TXDIR
;
700 scr
|= CCSR_SSI_SCR_SYS_CLK_EN
;
702 case SND_SOC_DAIFMT_CBM_CFM
:
703 scr
&= ~CCSR_SSI_SCR_SYS_CLK_EN
;
712 if (ssi_private
->cpu_dai_drv
.symmetric_rates
) {
713 /* Need to clear RXDIR when using SYNC mode */
714 srcr
&= ~CCSR_SSI_SRCR_RXDIR
;
715 scr
|= CCSR_SSI_SCR_SYN
;
718 write_ssi(stcr
, &ssi
->stcr
);
719 write_ssi(srcr
, &ssi
->srcr
);
720 write_ssi(scr
, &ssi
->scr
);
726 * fsl_ssi_set_dai_sysclk - configure Digital Audio Interface bit clock
728 * Note: This function can be only called when using SSI as DAI master
730 * Quick instruction for parameters:
731 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
732 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
734 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai
*cpu_dai
,
735 int clk_id
, unsigned int freq
, int dir
)
737 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
738 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
739 int synchronous
= ssi_private
->cpu_dai_drv
.symmetric_rates
, ret
;
740 u32 pm
= 999, div2
, psr
, stccr
, mask
, afreq
, factor
, i
;
741 unsigned long flags
, clkrate
, baudrate
, tmprate
;
742 u64 sub
, savesub
= 100000;
744 /* Don't apply it to any non-baudclk circumstance */
745 if (IS_ERR(ssi_private
->baudclk
))
748 /* It should be already enough to divide clock by setting pm alone */
752 factor
= (div2
+ 1) * (7 * psr
+ 1) * 2;
754 for (i
= 0; i
< 255; i
++) {
755 /* The bclk rate must be smaller than 1/5 sysclk rate */
756 if (factor
* (i
+ 1) < 5)
759 tmprate
= freq
* factor
* (i
+ 2);
760 clkrate
= clk_round_rate(ssi_private
->baudclk
, tmprate
);
762 do_div(clkrate
, factor
);
763 afreq
= (u32
)clkrate
/ (i
+ 1);
767 else if (freq
/ afreq
== 1)
769 else if (afreq
/ freq
== 1)
774 /* Calculate the fraction */
789 /* No proper pm found if it is still remaining the initial value */
791 dev_err(cpu_dai
->dev
, "failed to handle the required sysclk\n");
795 stccr
= CCSR_SSI_SxCCR_PM(pm
+ 1) | (div2
? CCSR_SSI_SxCCR_DIV2
: 0) |
796 (psr
? CCSR_SSI_SxCCR_PSR
: 0);
797 mask
= CCSR_SSI_SxCCR_PM_MASK
| CCSR_SSI_SxCCR_DIV2
| CCSR_SSI_SxCCR_PSR
;
799 if (dir
== SND_SOC_CLOCK_OUT
|| synchronous
)
800 write_ssi_mask(&ssi
->stccr
, mask
, stccr
);
802 write_ssi_mask(&ssi
->srccr
, mask
, stccr
);
804 spin_lock_irqsave(&ssi_private
->baudclk_lock
, flags
);
805 if (!ssi_private
->baudclk_locked
) {
806 ret
= clk_set_rate(ssi_private
->baudclk
, baudrate
);
808 spin_unlock_irqrestore(&ssi_private
->baudclk_lock
, flags
);
809 dev_err(cpu_dai
->dev
, "failed to set baudclk rate\n");
812 ssi_private
->baudclk_locked
= true;
814 spin_unlock_irqrestore(&ssi_private
->baudclk_lock
, flags
);
820 * fsl_ssi_set_dai_tdm_slot - set TDM slot number
822 * Note: This function can be only called when using SSI as DAI master
824 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai
*cpu_dai
, u32 tx_mask
,
825 u32 rx_mask
, int slots
, int slot_width
)
827 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
828 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
831 /* The slot number should be >= 2 if using Network mode or I2S mode */
832 val
= read_ssi(&ssi
->scr
) & (CCSR_SSI_SCR_I2S_MODE_MASK
| CCSR_SSI_SCR_NET
);
833 if (val
&& slots
< 2) {
834 dev_err(cpu_dai
->dev
, "slot number should be >= 2 in I2S or NET\n");
838 write_ssi_mask(&ssi
->stccr
, CCSR_SSI_SxCCR_DC_MASK
,
839 CCSR_SSI_SxCCR_DC(slots
));
840 write_ssi_mask(&ssi
->srccr
, CCSR_SSI_SxCCR_DC_MASK
,
841 CCSR_SSI_SxCCR_DC(slots
));
843 /* The register SxMSKs needs SSI to provide essential clock due to
844 * hardware design. So we here temporarily enable SSI to set them.
846 val
= read_ssi(&ssi
->scr
) & CCSR_SSI_SCR_SSIEN
;
847 write_ssi_mask(&ssi
->scr
, 0, CCSR_SSI_SCR_SSIEN
);
849 write_ssi(tx_mask
, &ssi
->stmsk
);
850 write_ssi(rx_mask
, &ssi
->srmsk
);
852 write_ssi_mask(&ssi
->scr
, CCSR_SSI_SCR_SSIEN
, val
);
858 * fsl_ssi_trigger: start and stop the DMA transfer.
860 * This function is called by ALSA to start, stop, pause, and resume the DMA
863 * The DMA channel is in external master start and pause mode, which
864 * means the SSI completely controls the flow of data.
866 static int fsl_ssi_trigger(struct snd_pcm_substream
*substream
, int cmd
,
867 struct snd_soc_dai
*dai
)
869 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
870 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
871 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
872 unsigned int sier_bits
;
876 * Enable only the interrupts and DMA requests
877 * that are needed for the channel. As the fiq
878 * is polling for this bits, we have to ensure
879 * that this are aligned with the preallocated
883 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
884 if (ssi_private
->use_dma
)
885 sier_bits
= SIER_FLAGS
;
887 sier_bits
= CCSR_SSI_SIER_TIE
| CCSR_SSI_SIER_TFE0_EN
;
889 if (ssi_private
->use_dma
)
890 sier_bits
= SIER_FLAGS
;
892 sier_bits
= CCSR_SSI_SIER_RIE
| CCSR_SSI_SIER_RFF0_EN
;
896 case SNDRV_PCM_TRIGGER_START
:
897 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
898 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
899 write_ssi_mask(&ssi
->scr
, 0,
900 CCSR_SSI_SCR_SSIEN
| CCSR_SSI_SCR_TE
);
902 write_ssi_mask(&ssi
->scr
, 0,
903 CCSR_SSI_SCR_SSIEN
| CCSR_SSI_SCR_RE
);
906 case SNDRV_PCM_TRIGGER_STOP
:
907 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
908 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
909 write_ssi_mask(&ssi
->scr
, CCSR_SSI_SCR_TE
, 0);
911 write_ssi_mask(&ssi
->scr
, CCSR_SSI_SCR_RE
, 0);
913 if (!ssi_private
->imx_ac97
&& (read_ssi(&ssi
->scr
) &
914 (CCSR_SSI_SCR_TE
| CCSR_SSI_SCR_RE
)) == 0) {
915 write_ssi_mask(&ssi
->scr
, CCSR_SSI_SCR_SSIEN
, 0);
916 spin_lock_irqsave(&ssi_private
->baudclk_lock
, flags
);
917 ssi_private
->baudclk_locked
= false;
918 spin_unlock_irqrestore(&ssi_private
->baudclk_lock
, flags
);
926 write_ssi(sier_bits
, &ssi
->sier
);
931 static int fsl_ssi_dai_probe(struct snd_soc_dai
*dai
)
933 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(dai
);
935 if (ssi_private
->ssi_on_imx
&& ssi_private
->use_dma
) {
936 dai
->playback_dma_data
= &ssi_private
->dma_params_tx
;
937 dai
->capture_dma_data
= &ssi_private
->dma_params_rx
;
943 static const struct snd_soc_dai_ops fsl_ssi_dai_ops
= {
944 .startup
= fsl_ssi_startup
,
945 .hw_params
= fsl_ssi_hw_params
,
946 .set_fmt
= fsl_ssi_set_dai_fmt
,
947 .set_sysclk
= fsl_ssi_set_dai_sysclk
,
948 .set_tdm_slot
= fsl_ssi_set_dai_tdm_slot
,
949 .trigger
= fsl_ssi_trigger
,
952 /* Template for the CPU dai driver structure */
953 static struct snd_soc_dai_driver fsl_ssi_dai_template
= {
954 .probe
= fsl_ssi_dai_probe
,
958 .rates
= FSLSSI_I2S_RATES
,
959 .formats
= FSLSSI_I2S_FORMATS
,
964 .rates
= FSLSSI_I2S_RATES
,
965 .formats
= FSLSSI_I2S_FORMATS
,
967 .ops
= &fsl_ssi_dai_ops
,
970 static const struct snd_soc_component_driver fsl_ssi_component
= {
975 * fsl_ssi_ac97_trigger: start and stop the AC97 receive/transmit.
977 * This function is called by ALSA to start, stop, pause, and resume the
980 static int fsl_ssi_ac97_trigger(struct snd_pcm_substream
*substream
, int cmd
,
981 struct snd_soc_dai
*dai
)
983 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
984 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(
986 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
989 case SNDRV_PCM_TRIGGER_START
:
990 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
991 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
992 write_ssi_mask(&ssi
->sier
, 0, CCSR_SSI_SIER_TIE
|
993 CCSR_SSI_SIER_TFE0_EN
);
995 write_ssi_mask(&ssi
->sier
, 0, CCSR_SSI_SIER_RIE
|
996 CCSR_SSI_SIER_RFF0_EN
);
999 case SNDRV_PCM_TRIGGER_STOP
:
1000 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1001 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1002 write_ssi_mask(&ssi
->sier
, CCSR_SSI_SIER_TIE
|
1003 CCSR_SSI_SIER_TFE0_EN
, 0);
1005 write_ssi_mask(&ssi
->sier
, CCSR_SSI_SIER_RIE
|
1006 CCSR_SSI_SIER_RFF0_EN
, 0);
1013 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1014 write_ssi(CCSR_SSI_SOR_TX_CLR
, &ssi
->sor
);
1016 write_ssi(CCSR_SSI_SOR_RX_CLR
, &ssi
->sor
);
1021 static const struct snd_soc_dai_ops fsl_ssi_ac97_dai_ops
= {
1022 .startup
= fsl_ssi_startup
,
1023 .trigger
= fsl_ssi_ac97_trigger
,
1026 static struct snd_soc_dai_driver fsl_ssi_ac97_dai
= {
1029 .stream_name
= "AC97 Playback",
1032 .rates
= SNDRV_PCM_RATE_8000_48000
,
1033 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1036 .stream_name
= "AC97 Capture",
1039 .rates
= SNDRV_PCM_RATE_48000
,
1040 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1042 .ops
= &fsl_ssi_ac97_dai_ops
,
1046 static struct fsl_ssi_private
*fsl_ac97_data
;
1048 static void fsl_ssi_ac97_init(void)
1050 fsl_ssi_setup(fsl_ac97_data
);
1053 static void fsl_ssi_ac97_write(struct snd_ac97
*ac97
, unsigned short reg
,
1056 struct ccsr_ssi
*ssi
= fsl_ac97_data
->ssi
;
1065 write_ssi(lreg
, &ssi
->sacadd
);
1068 write_ssi(lval
, &ssi
->sacdat
);
1070 write_ssi_mask(&ssi
->sacnt
, CCSR_SSI_SACNT_RDWR_MASK
,
1075 static unsigned short fsl_ssi_ac97_read(struct snd_ac97
*ac97
,
1078 struct ccsr_ssi
*ssi
= fsl_ac97_data
->ssi
;
1080 unsigned short val
= -1;
1083 lreg
= (reg
& 0x7f) << 12;
1084 write_ssi(lreg
, &ssi
->sacadd
);
1085 write_ssi_mask(&ssi
->sacnt
, CCSR_SSI_SACNT_RDWR_MASK
,
1090 val
= (read_ssi(&ssi
->sacdat
) >> 4) & 0xffff;
1095 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops
= {
1096 .read
= fsl_ssi_ac97_read
,
1097 .write
= fsl_ssi_ac97_write
,
1101 * Make every character in a string lower-case
1103 static void make_lowercase(char *s
)
1109 if ((c
>= 'A') && (c
<= 'Z'))
1110 *p
= c
+ ('a' - 'A');
1115 static int fsl_ssi_probe(struct platform_device
*pdev
)
1117 struct fsl_ssi_private
*ssi_private
;
1119 struct device_attribute
*dev_attr
= NULL
;
1120 struct device_node
*np
= pdev
->dev
.of_node
;
1121 const char *p
, *sprop
;
1122 const uint32_t *iprop
;
1123 struct resource res
;
1128 /* SSIs that are not connected on the board should have a
1129 * status = "disabled"
1130 * property in their device tree nodes.
1132 if (!of_device_is_available(np
))
1135 /* We only support the SSI in "I2S Slave" mode */
1136 sprop
= of_get_property(np
, "fsl,mode", NULL
);
1138 dev_err(&pdev
->dev
, "fsl,mode property is necessary\n");
1141 if (!strcmp(sprop
, "ac97-slave")) {
1143 } else if (strcmp(sprop
, "i2s-slave")) {
1144 dev_notice(&pdev
->dev
, "mode %s is unsupported\n", sprop
);
1148 /* The DAI name is the last part of the full name of the node. */
1149 p
= strrchr(np
->full_name
, '/') + 1;
1150 ssi_private
= devm_kzalloc(&pdev
->dev
, sizeof(*ssi_private
) + strlen(p
),
1153 dev_err(&pdev
->dev
, "could not allocate DAI object\n");
1157 strcpy(ssi_private
->name
, p
);
1159 ssi_private
->use_dma
= !of_property_read_bool(np
,
1160 "fsl,fiq-stream-filter");
1163 memcpy(&ssi_private
->cpu_dai_drv
, &fsl_ssi_ac97_dai
,
1164 sizeof(fsl_ssi_ac97_dai
));
1166 fsl_ac97_data
= ssi_private
;
1167 ssi_private
->imx_ac97
= true;
1169 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops
, pdev
);
1171 /* Initialize this copy of the CPU DAI driver structure */
1172 memcpy(&ssi_private
->cpu_dai_drv
, &fsl_ssi_dai_template
,
1173 sizeof(fsl_ssi_dai_template
));
1175 ssi_private
->cpu_dai_drv
.name
= ssi_private
->name
;
1177 /* Get the addresses and IRQ */
1178 ret
= of_address_to_resource(np
, 0, &res
);
1180 dev_err(&pdev
->dev
, "could not determine device resources\n");
1183 ssi_private
->ssi
= of_iomap(np
, 0);
1184 if (!ssi_private
->ssi
) {
1185 dev_err(&pdev
->dev
, "could not map device resources\n");
1188 ssi_private
->ssi_phys
= res
.start
;
1190 ssi_private
->irq
= irq_of_parse_and_map(np
, 0);
1191 if (!ssi_private
->irq
) {
1192 dev_err(&pdev
->dev
, "no irq for node %s\n", np
->full_name
);
1196 /* Are the RX and the TX clocks locked? */
1197 if (!of_find_property(np
, "fsl,ssi-asynchronous", NULL
)) {
1198 ssi_private
->cpu_dai_drv
.symmetric_rates
= 1;
1199 ssi_private
->cpu_dai_drv
.symmetric_channels
= 1;
1200 ssi_private
->cpu_dai_drv
.symmetric_samplebits
= 1;
1203 /* Determine the FIFO depth. */
1204 iprop
= of_get_property(np
, "fsl,fifo-depth", NULL
);
1206 ssi_private
->fifo_depth
= be32_to_cpup(iprop
);
1208 /* Older 8610 DTs didn't have the fifo-depth property */
1209 ssi_private
->fifo_depth
= 8;
1211 ssi_private
->baudclk_locked
= false;
1212 spin_lock_init(&ssi_private
->baudclk_lock
);
1214 if (of_device_is_compatible(pdev
->dev
.of_node
, "fsl,imx21-ssi")) {
1216 ssi_private
->ssi_on_imx
= true;
1218 ssi_private
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1219 if (IS_ERR(ssi_private
->clk
)) {
1220 ret
= PTR_ERR(ssi_private
->clk
);
1221 dev_err(&pdev
->dev
, "could not get clock: %d\n", ret
);
1224 ret
= clk_prepare_enable(ssi_private
->clk
);
1226 dev_err(&pdev
->dev
, "clk_prepare_enable failed: %d\n",
1231 /* For those SLAVE implementations, we ingore non-baudclk cases
1232 * and, instead, abandon MASTER mode that needs baud clock.
1234 ssi_private
->baudclk
= devm_clk_get(&pdev
->dev
, "baud");
1235 if (IS_ERR(ssi_private
->baudclk
))
1236 dev_warn(&pdev
->dev
, "could not get baud clock: %ld\n",
1237 PTR_ERR(ssi_private
->baudclk
));
1239 clk_prepare_enable(ssi_private
->baudclk
);
1242 * We have burstsize be "fifo_depth - 2" to match the SSI
1243 * watermark setting in fsl_ssi_startup().
1245 ssi_private
->dma_params_tx
.maxburst
=
1246 ssi_private
->fifo_depth
- 2;
1247 ssi_private
->dma_params_rx
.maxburst
=
1248 ssi_private
->fifo_depth
- 2;
1249 ssi_private
->dma_params_tx
.addr
=
1250 ssi_private
->ssi_phys
+ offsetof(struct ccsr_ssi
, stx0
);
1251 ssi_private
->dma_params_rx
.addr
=
1252 ssi_private
->ssi_phys
+ offsetof(struct ccsr_ssi
, srx0
);
1253 ssi_private
->dma_params_tx
.filter_data
=
1254 &ssi_private
->filter_data_tx
;
1255 ssi_private
->dma_params_rx
.filter_data
=
1256 &ssi_private
->filter_data_rx
;
1257 if (!of_property_read_bool(pdev
->dev
.of_node
, "dmas") &&
1258 ssi_private
->use_dma
) {
1260 * FIXME: This is a temporary solution until all
1261 * necessary dma drivers support the generic dma
1264 ret
= of_property_read_u32_array(pdev
->dev
.of_node
,
1265 "fsl,ssi-dma-events", dma_events
, 2);
1266 if (ret
&& ssi_private
->use_dma
) {
1267 dev_err(&pdev
->dev
, "could not get dma events but fsl-ssi is configured to use DMA\n");
1272 shared
= of_device_is_compatible(of_get_parent(np
),
1275 imx_pcm_dma_params_init_data(&ssi_private
->filter_data_tx
,
1276 dma_events
[0], shared
? IMX_DMATYPE_SSI_SP
: IMX_DMATYPE_SSI
);
1277 imx_pcm_dma_params_init_data(&ssi_private
->filter_data_rx
,
1278 dma_events
[1], shared
? IMX_DMATYPE_SSI_SP
: IMX_DMATYPE_SSI
);
1279 } else if (ssi_private
->use_dma
) {
1280 /* The 'name' should not have any slashes in it. */
1281 ret
= devm_request_irq(&pdev
->dev
, ssi_private
->irq
,
1282 fsl_ssi_isr
, 0, ssi_private
->name
,
1284 ssi_private
->irq_stats
= true;
1286 dev_err(&pdev
->dev
, "could not claim irq %u\n",
1292 /* Register with ASoC */
1293 dev_set_drvdata(&pdev
->dev
, ssi_private
);
1295 ret
= snd_soc_register_component(&pdev
->dev
, &fsl_ssi_component
,
1296 &ssi_private
->cpu_dai_drv
, 1);
1298 dev_err(&pdev
->dev
, "failed to register DAI: %d\n", ret
);
1302 ret
= fsl_ssi_debugfs_create(ssi_private
, &pdev
->dev
);
1306 if (ssi_private
->ssi_on_imx
) {
1307 if (!ssi_private
->use_dma
) {
1310 * Some boards use an incompatible codec. To get it
1311 * working, we are using imx-fiq-pcm-audio, that
1312 * can handle those codecs. DMA is not possible in this
1316 ssi_private
->fiq_params
.irq
= ssi_private
->irq
;
1317 ssi_private
->fiq_params
.base
= ssi_private
->ssi
;
1318 ssi_private
->fiq_params
.dma_params_rx
=
1319 &ssi_private
->dma_params_rx
;
1320 ssi_private
->fiq_params
.dma_params_tx
=
1321 &ssi_private
->dma_params_tx
;
1323 ret
= imx_pcm_fiq_init(pdev
, &ssi_private
->fiq_params
);
1327 ret
= imx_pcm_dma_init(pdev
);
1334 * If codec-handle property is missing from SSI node, we assume
1335 * that the machine driver uses new binding which does not require
1336 * SSI driver to trigger machine driver's probe.
1338 if (!of_get_property(np
, "codec-handle", NULL
)) {
1339 ssi_private
->new_binding
= true;
1343 /* Trigger the machine driver's probe function. The platform driver
1344 * name of the machine driver is taken from /compatible property of the
1345 * device tree. We also pass the address of the CPU DAI driver
1348 sprop
= of_get_property(of_find_node_by_path("/"), "compatible", NULL
);
1349 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1350 p
= strrchr(sprop
, ',');
1353 snprintf(name
, sizeof(name
), "snd-soc-%s", sprop
);
1354 make_lowercase(name
);
1357 platform_device_register_data(&pdev
->dev
, name
, 0, NULL
, 0);
1358 if (IS_ERR(ssi_private
->pdev
)) {
1359 ret
= PTR_ERR(ssi_private
->pdev
);
1360 dev_err(&pdev
->dev
, "failed to register platform: %d\n", ret
);
1365 if (ssi_private
->imx_ac97
)
1366 fsl_ssi_ac97_init();
1371 if (ssi_private
->ssi_on_imx
&& !ssi_private
->use_dma
)
1372 imx_pcm_fiq_exit(pdev
);
1375 fsl_ssi_debugfs_remove(ssi_private
);
1378 snd_soc_unregister_component(&pdev
->dev
);
1381 device_remove_file(&pdev
->dev
, dev_attr
);
1384 if (ssi_private
->ssi_on_imx
) {
1385 if (!IS_ERR(ssi_private
->baudclk
))
1386 clk_disable_unprepare(ssi_private
->baudclk
);
1387 clk_disable_unprepare(ssi_private
->clk
);
1391 if (ssi_private
->irq_stats
)
1392 irq_dispose_mapping(ssi_private
->irq
);
1397 static int fsl_ssi_remove(struct platform_device
*pdev
)
1399 struct fsl_ssi_private
*ssi_private
= dev_get_drvdata(&pdev
->dev
);
1401 fsl_ssi_debugfs_remove(ssi_private
);
1403 if (!ssi_private
->new_binding
)
1404 platform_device_unregister(ssi_private
->pdev
);
1405 snd_soc_unregister_component(&pdev
->dev
);
1406 if (ssi_private
->ssi_on_imx
) {
1407 if (!IS_ERR(ssi_private
->baudclk
))
1408 clk_disable_unprepare(ssi_private
->baudclk
);
1409 clk_disable_unprepare(ssi_private
->clk
);
1411 if (ssi_private
->irq_stats
)
1412 irq_dispose_mapping(ssi_private
->irq
);
1417 static const struct of_device_id fsl_ssi_ids
[] = {
1418 { .compatible
= "fsl,mpc8610-ssi", },
1419 { .compatible
= "fsl,imx21-ssi", },
1422 MODULE_DEVICE_TABLE(of
, fsl_ssi_ids
);
1424 static struct platform_driver fsl_ssi_driver
= {
1426 .name
= "fsl-ssi-dai",
1427 .owner
= THIS_MODULE
,
1428 .of_match_table
= fsl_ssi_ids
,
1430 .probe
= fsl_ssi_probe
,
1431 .remove
= fsl_ssi_remove
,
1434 module_platform_driver(fsl_ssi_driver
);
1436 MODULE_ALIAS("platform:fsl-ssi-dai");
1437 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1438 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1439 MODULE_LICENSE("GPL v2");