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drm/tegra: dc - Compute shift clock divider in output drivers
[linux-2.6/btrfs-unstable.git] / drivers / gpu / drm / tegra / dsi.c
blobbeab9c85db922e44f2e2bea0e5304272b9b31651
1 /*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/debugfs.h>
11 #include <linux/host1x.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/platform_device.h>
15 #include <linux/reset.h>
16
17 #include <linux/regulator/consumer.h>
18
19 #include <drm/drm_mipi_dsi.h>
20 #include <drm/drm_panel.h>
21
22 #include <video/mipi_display.h>
23
24 #include "dc.h"
25 #include "drm.h"
26 #include "dsi.h"
27 #include "mipi-phy.h"
28
29 #define DSI_VIDEO_FIFO_DEPTH (1920 / 4)
30 #define DSI_HOST_FIFO_DEPTH 64
31
32 struct tegra_dsi {
33 struct host1x_client client;
34 struct tegra_output output;
35 struct device *dev;
36
37 void __iomem *regs;
38
39 struct reset_control *rst;
40 struct clk *clk_parent;
41 struct clk *clk_lp;
42 struct clk *clk;
43
44 struct drm_info_list *debugfs_files;
45 struct drm_minor *minor;
46 struct dentry *debugfs;
47
48 unsigned long flags;
49 enum mipi_dsi_pixel_format format;
50 unsigned int lanes;
51
52 struct tegra_mipi_device *mipi;
53 struct mipi_dsi_host host;
54
55 struct regulator *vdd;
56 bool enabled;
57 };
58
59 static inline struct tegra_dsi *
60 host1x_client_to_dsi(struct host1x_client *client)
61 {
62 return container_of(client, struct tegra_dsi, client);
63 }
64
65 static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
66 {
67 return container_of(host, struct tegra_dsi, host);
68 }
69
70 static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
71 {
72 return container_of(output, struct tegra_dsi, output);
73 }
74
75 static inline unsigned long tegra_dsi_readl(struct tegra_dsi *dsi,
76 unsigned long reg)
77 {
78 return readl(dsi->regs + (reg << 2));
79 }
80
81 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, unsigned long value,
82 unsigned long reg)
83 {
84 writel(value, dsi->regs + (reg << 2));
85 }
86
87 static int tegra_dsi_show_regs(struct seq_file *s, void *data)
88 {
89 struct drm_info_node *node = s->private;
90 struct tegra_dsi *dsi = node->info_ent->data;
91
92 #define DUMP_REG(name) \
93 seq_printf(s, "%-32s %#05x %08lx\n", #name, name, \
94 tegra_dsi_readl(dsi, name))
95
96 DUMP_REG(DSI_INCR_SYNCPT);
97 DUMP_REG(DSI_INCR_SYNCPT_CONTROL);
98 DUMP_REG(DSI_INCR_SYNCPT_ERROR);
99 DUMP_REG(DSI_CTXSW);
100 DUMP_REG(DSI_RD_DATA);
101 DUMP_REG(DSI_WR_DATA);
102 DUMP_REG(DSI_POWER_CONTROL);
103 DUMP_REG(DSI_INT_ENABLE);
104 DUMP_REG(DSI_INT_STATUS);
105 DUMP_REG(DSI_INT_MASK);
106 DUMP_REG(DSI_HOST_CONTROL);
107 DUMP_REG(DSI_CONTROL);
108 DUMP_REG(DSI_SOL_DELAY);
109 DUMP_REG(DSI_MAX_THRESHOLD);
110 DUMP_REG(DSI_TRIGGER);
111 DUMP_REG(DSI_TX_CRC);
112 DUMP_REG(DSI_STATUS);
113
114 DUMP_REG(DSI_INIT_SEQ_CONTROL);
115 DUMP_REG(DSI_INIT_SEQ_DATA_0);
116 DUMP_REG(DSI_INIT_SEQ_DATA_1);
117 DUMP_REG(DSI_INIT_SEQ_DATA_2);
118 DUMP_REG(DSI_INIT_SEQ_DATA_3);
119 DUMP_REG(DSI_INIT_SEQ_DATA_4);
120 DUMP_REG(DSI_INIT_SEQ_DATA_5);
121 DUMP_REG(DSI_INIT_SEQ_DATA_6);
122 DUMP_REG(DSI_INIT_SEQ_DATA_7);
123
124 DUMP_REG(DSI_PKT_SEQ_0_LO);
125 DUMP_REG(DSI_PKT_SEQ_0_HI);
126 DUMP_REG(DSI_PKT_SEQ_1_LO);
127 DUMP_REG(DSI_PKT_SEQ_1_HI);
128 DUMP_REG(DSI_PKT_SEQ_2_LO);
129 DUMP_REG(DSI_PKT_SEQ_2_HI);
130 DUMP_REG(DSI_PKT_SEQ_3_LO);
131 DUMP_REG(DSI_PKT_SEQ_3_HI);
132 DUMP_REG(DSI_PKT_SEQ_4_LO);
133 DUMP_REG(DSI_PKT_SEQ_4_HI);
134 DUMP_REG(DSI_PKT_SEQ_5_LO);
135 DUMP_REG(DSI_PKT_SEQ_5_HI);
136
137 DUMP_REG(DSI_DCS_CMDS);
138
139 DUMP_REG(DSI_PKT_LEN_0_1);
140 DUMP_REG(DSI_PKT_LEN_2_3);
141 DUMP_REG(DSI_PKT_LEN_4_5);
142 DUMP_REG(DSI_PKT_LEN_6_7);
143
144 DUMP_REG(DSI_PHY_TIMING_0);
145 DUMP_REG(DSI_PHY_TIMING_1);
146 DUMP_REG(DSI_PHY_TIMING_2);
147 DUMP_REG(DSI_BTA_TIMING);
148
149 DUMP_REG(DSI_TIMEOUT_0);
150 DUMP_REG(DSI_TIMEOUT_1);
151 DUMP_REG(DSI_TO_TALLY);
152
153 DUMP_REG(DSI_PAD_CONTROL_0);
154 DUMP_REG(DSI_PAD_CONTROL_CD);
155 DUMP_REG(DSI_PAD_CD_STATUS);
156 DUMP_REG(DSI_VIDEO_MODE_CONTROL);
157 DUMP_REG(DSI_PAD_CONTROL_1);
158 DUMP_REG(DSI_PAD_CONTROL_2);
159 DUMP_REG(DSI_PAD_CONTROL_3);
160 DUMP_REG(DSI_PAD_CONTROL_4);
161
162 DUMP_REG(DSI_GANGED_MODE_CONTROL);
163 DUMP_REG(DSI_GANGED_MODE_START);
164 DUMP_REG(DSI_GANGED_MODE_SIZE);
165
166 DUMP_REG(DSI_RAW_DATA_BYTE_COUNT);
167 DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL);
168
169 DUMP_REG(DSI_INIT_SEQ_DATA_8);
170 DUMP_REG(DSI_INIT_SEQ_DATA_9);
171 DUMP_REG(DSI_INIT_SEQ_DATA_10);
172 DUMP_REG(DSI_INIT_SEQ_DATA_11);
173 DUMP_REG(DSI_INIT_SEQ_DATA_12);
174 DUMP_REG(DSI_INIT_SEQ_DATA_13);
175 DUMP_REG(DSI_INIT_SEQ_DATA_14);
176 DUMP_REG(DSI_INIT_SEQ_DATA_15);
177
178 #undef DUMP_REG
179
180 return 0;
181 }
182
183 static struct drm_info_list debugfs_files[] = {
184 { "regs", tegra_dsi_show_regs, 0, NULL },
185 };
186
187 static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi,
188 struct drm_minor *minor)
189 {
190 const char *name = dev_name(dsi->dev);
191 unsigned int i;
192 int err;
193
194 dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root);
195 if (!dsi->debugfs)
196 return -ENOMEM;
197
198 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
199 GFP_KERNEL);
200 if (!dsi->debugfs_files) {
201 err = -ENOMEM;
202 goto remove;
203 }
204
205 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
206 dsi->debugfs_files[i].data = dsi;
207
208 err = drm_debugfs_create_files(dsi->debugfs_files,
209 ARRAY_SIZE(debugfs_files),
210 dsi->debugfs, minor);
211 if (err < 0)
212 goto free;
213
214 dsi->minor = minor;
215
216 return 0;
217
218 free:
219 kfree(dsi->debugfs_files);
220 dsi->debugfs_files = NULL;
221 remove:
222 debugfs_remove(dsi->debugfs);
223 dsi->debugfs = NULL;
224
225 return err;
226 }
227
228 static int tegra_dsi_debugfs_exit(struct tegra_dsi *dsi)
229 {
230 drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files),
231 dsi->minor);
232 dsi->minor = NULL;
233
234 kfree(dsi->debugfs_files);
235 dsi->debugfs_files = NULL;
236
237 debugfs_remove(dsi->debugfs);
238 dsi->debugfs = NULL;
239
240 return 0;
241 }
242
243 #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
244 #define PKT_LEN0(len) (((len) & 0x07) << 0)
245 #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
246 #define PKT_LEN1(len) (((len) & 0x07) << 10)
247 #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
248 #define PKT_LEN2(len) (((len) & 0x07) << 20)
249
250 #define PKT_LP (1 << 30)
251 #define NUM_PKT_SEQ 12
252
253 /*
254 * non-burst mode with sync pulses
255 */
256 static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
257 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
258 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
259 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
260 PKT_LP,
261 [ 1] = 0,
262 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
263 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
264 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
265 PKT_LP,
266 [ 3] = 0,
267 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
268 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
269 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
270 PKT_LP,
271 [ 5] = 0,
272 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
273 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
274 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
275 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
276 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
277 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
278 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
279 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
280 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
281 PKT_LP,
282 [ 9] = 0,
283 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
284 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
285 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
286 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
287 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
288 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
289 };
290
291 /*
292 * non-burst mode with sync events
293 */
294 static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
295 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
296 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
297 PKT_LP,
298 [ 1] = 0,
299 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
300 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
301 PKT_LP,
302 [ 3] = 0,
303 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
304 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
305 PKT_LP,
306 [ 5] = 0,
307 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
308 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
309 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
310 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
311 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
312 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
313 PKT_LP,
314 [ 9] = 0,
315 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
316 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
317 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
318 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
319 };
320
321 static int tegra_dsi_set_phy_timing(struct tegra_dsi *dsi)
322 {
323 struct mipi_dphy_timing timing;
324 unsigned long value, period;
325 long rate;
326 int err;
327
328 rate = clk_get_rate(dsi->clk);
329 if (rate < 0)
330 return rate;
331
332 period = DIV_ROUND_CLOSEST(1000000000UL, rate * 2);
333
334 err = mipi_dphy_timing_get_default(&timing, period);
335 if (err < 0)
336 return err;
337
338 err = mipi_dphy_timing_validate(&timing, period);
339 if (err < 0) {
340 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
341 return err;
342 }
343
344 /*
345 * The D-PHY timing fields below are expressed in byte-clock cycles,
346 * so multiply the period by 8.
347 */
348 period *= 8;
349
350 value = DSI_TIMING_FIELD(timing.hsexit, period, 1) << 24 |
351 DSI_TIMING_FIELD(timing.hstrail, period, 0) << 16 |
352 DSI_TIMING_FIELD(timing.hszero, period, 3) << 8 |
353 DSI_TIMING_FIELD(timing.hsprepare, period, 1);
354 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
355
356 value = DSI_TIMING_FIELD(timing.clktrail, period, 1) << 24 |
357 DSI_TIMING_FIELD(timing.clkpost, period, 1) << 16 |
358 DSI_TIMING_FIELD(timing.clkzero, period, 1) << 8 |
359 DSI_TIMING_FIELD(timing.lpx, period, 1);
360 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
361
362 value = DSI_TIMING_FIELD(timing.clkprepare, period, 1) << 16 |
363 DSI_TIMING_FIELD(timing.clkpre, period, 1) << 8 |
364 DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
365 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
366
367 value = DSI_TIMING_FIELD(timing.taget, period, 1) << 16 |
368 DSI_TIMING_FIELD(timing.tasure, period, 1) << 8 |
369 DSI_TIMING_FIELD(timing.tago, period, 1);
370 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
371
372 return 0;
373 }
374
375 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
376 unsigned int *mulp, unsigned int *divp)
377 {
378 switch (format) {
379 case MIPI_DSI_FMT_RGB666_PACKED:
380 case MIPI_DSI_FMT_RGB888:
381 *mulp = 3;
382 *divp = 1;
383 break;
384
385 case MIPI_DSI_FMT_RGB565:
386 *mulp = 2;
387 *divp = 1;
388 break;
389
390 case MIPI_DSI_FMT_RGB666:
391 *mulp = 9;
392 *divp = 4;
393 break;
394
395 default:
396 return -EINVAL;
397 }
398
399 return 0;
400 }
401
402 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
403 enum tegra_dsi_format *fmt)
404 {
405 switch (format) {
406 case MIPI_DSI_FMT_RGB888:
407 *fmt = TEGRA_DSI_FORMAT_24P;
408 break;
409
410 case MIPI_DSI_FMT_RGB666:
411 *fmt = TEGRA_DSI_FORMAT_18NP;
412 break;
413
414 case MIPI_DSI_FMT_RGB666_PACKED:
415 *fmt = TEGRA_DSI_FORMAT_18P;
416 break;
417
418 case MIPI_DSI_FMT_RGB565:
419 *fmt = TEGRA_DSI_FORMAT_16P;
420 break;
421
422 default:
423 return -EINVAL;
424 }
425
426 return 0;
427 }
428
429 static int tegra_output_dsi_enable(struct tegra_output *output)
430 {
431 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
432 struct drm_display_mode *mode = &dc->base.mode;
433 unsigned int hact, hsw, hbp, hfp, i, mul, div;
434 struct tegra_dsi *dsi = to_dsi(output);
435 enum tegra_dsi_format format;
436 unsigned long value;
437 const u32 *pkt_seq;
438 int err;
439
440 if (dsi->enabled)
441 return 0;
442
443 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
444 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
445 pkt_seq = pkt_seq_video_non_burst_sync_pulses;
446 } else {
447 DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
448 pkt_seq = pkt_seq_video_non_burst_sync_events;
449 }
450
451 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
452 if (err < 0)
453 return err;
454
455 err = tegra_dsi_get_format(dsi->format, &format);
456 if (err < 0)
457 return err;
458
459 err = clk_enable(dsi->clk);
460 if (err < 0)
461 return err;
462
463 reset_control_deassert(dsi->rst);
464
465 value = DSI_CONTROL_CHANNEL(0) | DSI_CONTROL_FORMAT(format) |
466 DSI_CONTROL_LANES(dsi->lanes - 1) |
467 DSI_CONTROL_SOURCE(dc->pipe);
468 tegra_dsi_writel(dsi, value, DSI_CONTROL);
469
470 tegra_dsi_writel(dsi, DSI_VIDEO_FIFO_DEPTH, DSI_MAX_THRESHOLD);
471
472 value = DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS |
473 DSI_HOST_CONTROL_ECC;
474 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
475
476 value = tegra_dsi_readl(dsi, DSI_CONTROL);
477 value |= DSI_CONTROL_HS_CLK_CTRL;
478 value &= ~DSI_CONTROL_TX_TRIG(3);
479 value &= ~DSI_CONTROL_DCS_ENABLE;
480 value |= DSI_CONTROL_VIDEO_ENABLE;
481 value &= ~DSI_CONTROL_HOST_ENABLE;
482 tegra_dsi_writel(dsi, value, DSI_CONTROL);
483
484 err = tegra_dsi_set_phy_timing(dsi);
485 if (err < 0)
486 return err;
487
488 for (i = 0; i < NUM_PKT_SEQ; i++)
489 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
490
491 /* horizontal active pixels */
492 hact = mode->hdisplay * mul / div;
493
494 /* horizontal sync width */
495 hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
496 hsw -= 10;
497
498 /* horizontal back porch */
499 hbp = (mode->htotal - mode->hsync_end) * mul / div;
500 hbp -= 14;
501
502 /* horizontal front porch */
503 hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
504 hfp -= 8;
505
506 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
507 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
508 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
509 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
510
511 /* set SOL delay */
512 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
513
514 /* enable display controller */
515 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
516 value |= DSI_ENABLE;
517 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
518
519 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
520 value &= ~DISP_CTRL_MODE_MASK;
521 value |= DISP_CTRL_MODE_C_DISPLAY;
522 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
523
524 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
525 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
526 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
527 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
528
529 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
530 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
531
532 /* enable DSI controller */
533 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
534 value |= DSI_POWER_CONTROL_ENABLE;
535 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
536
537 dsi->enabled = true;
538
539 return 0;
540 }
541
542 static int tegra_output_dsi_disable(struct tegra_output *output)
543 {
544 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
545 struct tegra_dsi *dsi = to_dsi(output);
546 unsigned long value;
547
548 if (!dsi->enabled)
549 return 0;
550
551 /* disable DSI controller */
552 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
553 value &= ~DSI_POWER_CONTROL_ENABLE;
554 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
555
556 /*
557 * The following accesses registers of the display controller, so make
558 * sure it's only executed when the output is attached to one.
559 */
560 if (dc) {
561 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
562 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
563 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
564 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
565
566 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
567 value &= ~DISP_CTRL_MODE_MASK;
568 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
569
570 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
571 value &= ~DSI_ENABLE;
572 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
573
574 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
575 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
576 }
577
578 clk_disable(dsi->clk);
579
580 dsi->enabled = false;
581
582 return 0;
583 }
584
585 static int tegra_output_dsi_setup_clock(struct tegra_output *output,
586 struct clk *clk, unsigned long pclk,
587 unsigned int *divp)
588 {
589 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
590 struct drm_display_mode *mode = &dc->base.mode;
591 unsigned int timeout, mul, div, vrefresh;
592 struct tegra_dsi *dsi = to_dsi(output);
593 unsigned long bclk, plld, value;
594 int err;
595
596 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
597 if (err < 0)
598 return err;
599
600 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", mul, div, dsi->lanes);
601 vrefresh = drm_mode_vrefresh(mode);
602 DRM_DEBUG_KMS("vrefresh: %u\n", vrefresh);
603
604 /* compute byte clock */
605 pclk = mode->htotal * mode->vtotal * vrefresh;
606 bclk = (pclk * mul) / (div * dsi->lanes);
607
608 /*
609 * Compute bit clock and round up to the next MHz.
610 */
611 plld = DIV_ROUND_UP(bclk * 8, 1000000) * 1000000;
612
613 /*
614 * We divide the frequency by two here, but we make up for that by
615 * setting the shift clock divider (further below) to half of the
616 * correct value.
617 */
618 plld /= 2;
619
620 err = clk_set_parent(clk, dsi->clk_parent);
621 if (err < 0) {
622 dev_err(dsi->dev, "failed to set parent clock: %d\n", err);
623 return err;
624 }
625
626 err = clk_set_rate(dsi->clk_parent, plld);
627 if (err < 0) {
628 dev_err(dsi->dev, "failed to set base clock rate to %lu Hz\n",
629 plld);
630 return err;
631 }
632
633 /*
634 * Derive pixel clock from bit clock using the shift clock divider.
635 * Note that this is only half of what we would expect, but we need
636 * that to make up for the fact that we divided the bit clock by a
637 * factor of two above.
638 *
639 * It's not clear exactly why this is necessary, but the display is
640 * not working properly otherwise. Perhaps the PLLs cannot generate
641 * frequencies sufficiently high.
642 */
643 *divp = ((8 * mul) / (div * dsi->lanes)) - 2;
644
645 /*
646 * XXX: Move the below somewhere else so that we don't need to have
647 * access to the vrefresh in this function?
648 */
649
650 /* one frame high-speed transmission timeout */
651 timeout = (bclk / vrefresh) / 512;
652 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
653 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
654
655 /* 2 ms peripheral timeout for panel */
656 timeout = 2 * bclk / 512 * 1000;
657 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
658 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
659
660 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
661 tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
662
663 return 0;
664 }
665
666 static int tegra_output_dsi_check_mode(struct tegra_output *output,
667 struct drm_display_mode *mode,
668 enum drm_mode_status *status)
669 {
670 /*
671 * FIXME: For now, always assume that the mode is okay.
672 */
673
674 *status = MODE_OK;
675
676 return 0;
677 }
678
679 static const struct tegra_output_ops dsi_ops = {
680 .enable = tegra_output_dsi_enable,
681 .disable = tegra_output_dsi_disable,
682 .setup_clock = tegra_output_dsi_setup_clock,
683 .check_mode = tegra_output_dsi_check_mode,
684 };
685
686 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
687 {
688 unsigned long value;
689
690 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
691 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
692
693 return 0;
694 }
695
696 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
697 {
698 unsigned long value;
699
700 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
701 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
702 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
703 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
704 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
705
706 /* start calibration */
707 tegra_dsi_pad_enable(dsi);
708
709 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
710 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
711 DSI_PAD_OUT_CLK(0x0);
712 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
713
714 return tegra_mipi_calibrate(dsi->mipi);
715 }
716
717 static int tegra_dsi_init(struct host1x_client *client)
718 {
719 struct tegra_drm *tegra = dev_get_drvdata(client->parent);
720 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
721 int err;
722
723 dsi->output.type = TEGRA_OUTPUT_DSI;
724 dsi->output.dev = client->dev;
725 dsi->output.ops = &dsi_ops;
726
727 err = tegra_output_init(tegra->drm, &dsi->output);
728 if (err < 0) {
729 dev_err(client->dev, "output setup failed: %d\n", err);
730 return err;
731 }
732
733 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
734 err = tegra_dsi_debugfs_init(dsi, tegra->drm->primary);
735 if (err < 0)
736 dev_err(dsi->dev, "debugfs setup failed: %d\n", err);
737 }
738
739 err = tegra_dsi_pad_calibrate(dsi);
740 if (err < 0) {
741 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
742 return err;
743 }
744
745 return 0;
746 }
747
748 static int tegra_dsi_exit(struct host1x_client *client)
749 {
750 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
751 int err;
752
753 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
754 err = tegra_dsi_debugfs_exit(dsi);
755 if (err < 0)
756 dev_err(dsi->dev, "debugfs cleanup failed: %d\n", err);
757 }
758
759 err = tegra_output_disable(&dsi->output);
760 if (err < 0) {
761 dev_err(client->dev, "output failed to disable: %d\n", err);
762 return err;
763 }
764
765 err = tegra_output_exit(&dsi->output);
766 if (err < 0) {
767 dev_err(client->dev, "output cleanup failed: %d\n", err);
768 return err;
769 }
770
771 return 0;
772 }
773
774 static const struct host1x_client_ops dsi_client_ops = {
775 .init = tegra_dsi_init,
776 .exit = tegra_dsi_exit,
777 };
778
779 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
780 {
781 struct clk *parent;
782 int err;
783
784 parent = clk_get_parent(dsi->clk);
785 if (!parent)
786 return -EINVAL;
787
788 err = clk_set_parent(parent, dsi->clk_parent);
789 if (err < 0)
790 return err;
791
792 return 0;
793 }
794
795 static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
796 struct mipi_dsi_device *device)
797 {
798 struct tegra_dsi *dsi = host_to_tegra(host);
799 struct tegra_output *output = &dsi->output;
800
801 dsi->flags = device->mode_flags;
802 dsi->format = device->format;
803 dsi->lanes = device->lanes;
804
805 output->panel = of_drm_find_panel(device->dev.of_node);
806 if (output->panel) {
807 if (output->connector.dev)
808 drm_helper_hpd_irq_event(output->connector.dev);
809 }
810
811 return 0;
812 }
813
814 static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
815 struct mipi_dsi_device *device)
816 {
817 struct tegra_dsi *dsi = host_to_tegra(host);
818 struct tegra_output *output = &dsi->output;
819
820 if (output->panel && &device->dev == output->panel->dev) {
821 if (output->connector.dev)
822 drm_helper_hpd_irq_event(output->connector.dev);
823
824 output->panel = NULL;
825 }
826
827 return 0;
828 }
829
830 static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
831 .attach = tegra_dsi_host_attach,
832 .detach = tegra_dsi_host_detach,
833 };
834
835 static int tegra_dsi_probe(struct platform_device *pdev)
836 {
837 struct tegra_dsi *dsi;
838 struct resource *regs;
839 int err;
840
841 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
842 if (!dsi)
843 return -ENOMEM;
844
845 dsi->output.dev = dsi->dev = &pdev->dev;
846
847 err = tegra_output_probe(&dsi->output);
848 if (err < 0)
849 return err;
850
851 /*
852 * Assume these values by default. When a DSI peripheral driver
853 * attaches to the DSI host, the parameters will be taken from
854 * the attached device.
855 */
856 dsi->flags = MIPI_DSI_MODE_VIDEO;
857 dsi->format = MIPI_DSI_FMT_RGB888;
858 dsi->lanes = 4;
859
860 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
861 if (IS_ERR(dsi->rst))
862 return PTR_ERR(dsi->rst);
863
864 dsi->clk = devm_clk_get(&pdev->dev, NULL);
865 if (IS_ERR(dsi->clk)) {
866 dev_err(&pdev->dev, "cannot get DSI clock\n");
867 return PTR_ERR(dsi->clk);
868 }
869
870 err = clk_prepare_enable(dsi->clk);
871 if (err < 0) {
872 dev_err(&pdev->dev, "cannot enable DSI clock\n");
873 return err;
874 }
875
876 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
877 if (IS_ERR(dsi->clk_lp)) {
878 dev_err(&pdev->dev, "cannot get low-power clock\n");
879 return PTR_ERR(dsi->clk_lp);
880 }
881
882 err = clk_prepare_enable(dsi->clk_lp);
883 if (err < 0) {
884 dev_err(&pdev->dev, "cannot enable low-power clock\n");
885 return err;
886 }
887
888 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
889 if (IS_ERR(dsi->clk_parent)) {
890 dev_err(&pdev->dev, "cannot get parent clock\n");
891 return PTR_ERR(dsi->clk_parent);
892 }
893
894 err = clk_prepare_enable(dsi->clk_parent);
895 if (err < 0) {
896 dev_err(&pdev->dev, "cannot enable parent clock\n");
897 return err;
898 }
899
900 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
901 if (IS_ERR(dsi->vdd)) {
902 dev_err(&pdev->dev, "cannot get VDD supply\n");
903 return PTR_ERR(dsi->vdd);
904 }
905
906 err = regulator_enable(dsi->vdd);
907 if (err < 0) {
908 dev_err(&pdev->dev, "cannot enable VDD supply\n");
909 return err;
910 }
911
912 err = tegra_dsi_setup_clocks(dsi);
913 if (err < 0) {
914 dev_err(&pdev->dev, "cannot setup clocks\n");
915 return err;
916 }
917
918 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
919 dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
920 if (IS_ERR(dsi->regs))
921 return PTR_ERR(dsi->regs);
922
923 dsi->mipi = tegra_mipi_request(&pdev->dev);
924 if (IS_ERR(dsi->mipi))
925 return PTR_ERR(dsi->mipi);
926
927 dsi->host.ops = &tegra_dsi_host_ops;
928 dsi->host.dev = &pdev->dev;
929
930 err = mipi_dsi_host_register(&dsi->host);
931 if (err < 0) {
932 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
933 return err;
934 }
935
936 INIT_LIST_HEAD(&dsi->client.list);
937 dsi->client.ops = &dsi_client_ops;
938 dsi->client.dev = &pdev->dev;
939
940 err = host1x_client_register(&dsi->client);
941 if (err < 0) {
942 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
943 err);
944 return err;
945 }
946
947 platform_set_drvdata(pdev, dsi);
948
949 return 0;
950 }
951
952 static int tegra_dsi_remove(struct platform_device *pdev)
953 {
954 struct tegra_dsi *dsi = platform_get_drvdata(pdev);
955 int err;
956
957 err = host1x_client_unregister(&dsi->client);
958 if (err < 0) {
959 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
960 err);
961 return err;
962 }
963
964 mipi_dsi_host_unregister(&dsi->host);
965 tegra_mipi_free(dsi->mipi);
966
967 regulator_disable(dsi->vdd);
968 clk_disable_unprepare(dsi->clk_parent);
969 clk_disable_unprepare(dsi->clk_lp);
970 clk_disable_unprepare(dsi->clk);
971 reset_control_assert(dsi->rst);
972
973 err = tegra_output_remove(&dsi->output);
974 if (err < 0) {
975 dev_err(&pdev->dev, "failed to remove output: %d\n", err);
976 return err;
977 }
978
979 return 0;
980 }
981
982 static const struct of_device_id tegra_dsi_of_match[] = {
983 { .compatible = "nvidia,tegra114-dsi", },
984 { },
985 };
986
987 struct platform_driver tegra_dsi_driver = {
988 .driver = {
989 .name = "tegra-dsi",
990 .of_match_table = tegra_dsi_of_match,
991 },
992 .probe = tegra_dsi_probe,
993 .remove = tegra_dsi_remove,
994 };
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