2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
63 #include <asm/uv/uv_hub.h>
64 #include <asm/uv/uv_irq.h>
68 #define __apicdebuginit(type) static type __init
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug
= -1;
76 static DEFINE_SPINLOCK(ioapic_lock
);
77 static DEFINE_SPINLOCK(vector_lock
);
80 * # of IRQ routing registers
82 int nr_ioapic_registers
[MAX_IO_APICS
];
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics
[MAX_IO_APICS
];
88 /* MP IRQ source entries */
89 struct mpc_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
91 /* # of MP IRQ source entries */
94 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
98 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
100 int skip_ioapic_setup
;
102 void arch_disable_smp_support(void)
106 noioapicreroute
= -1;
108 skip_ioapic_setup
= 1;
111 static int __init
parse_noapic(char *str
)
113 /* disable IO-APIC */
114 arch_disable_smp_support();
117 early_param("noapic", parse_noapic
);
122 * This is performance-critical, we want to do it O(1)
124 * the indexing order of this array favors 1:1 mappings
125 * between pins and IRQs.
128 struct irq_pin_list
{
130 struct irq_pin_list
*next
;
133 static struct irq_pin_list
*get_one_free_irq_2_pin(int node
)
135 struct irq_pin_list
*pin
;
137 pin
= kzalloc_node(sizeof(*pin
), GFP_ATOMIC
, node
);
143 struct irq_pin_list
*irq_2_pin
;
144 cpumask_var_t domain
;
145 cpumask_var_t old_domain
;
146 unsigned move_cleanup_count
;
148 u8 move_in_progress
: 1;
151 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
152 #ifdef CONFIG_SPARSE_IRQ
153 static struct irq_cfg irq_cfgx
[] = {
155 static struct irq_cfg irq_cfgx
[NR_IRQS
] = {
157 [0] = { .vector
= IRQ0_VECTOR
, },
158 [1] = { .vector
= IRQ1_VECTOR
, },
159 [2] = { .vector
= IRQ2_VECTOR
, },
160 [3] = { .vector
= IRQ3_VECTOR
, },
161 [4] = { .vector
= IRQ4_VECTOR
, },
162 [5] = { .vector
= IRQ5_VECTOR
, },
163 [6] = { .vector
= IRQ6_VECTOR
, },
164 [7] = { .vector
= IRQ7_VECTOR
, },
165 [8] = { .vector
= IRQ8_VECTOR
, },
166 [9] = { .vector
= IRQ9_VECTOR
, },
167 [10] = { .vector
= IRQ10_VECTOR
, },
168 [11] = { .vector
= IRQ11_VECTOR
, },
169 [12] = { .vector
= IRQ12_VECTOR
, },
170 [13] = { .vector
= IRQ13_VECTOR
, },
171 [14] = { .vector
= IRQ14_VECTOR
, },
172 [15] = { .vector
= IRQ15_VECTOR
, },
175 int __init
arch_early_irq_init(void)
178 struct irq_desc
*desc
;
184 count
= ARRAY_SIZE(irq_cfgx
);
185 node
= cpu_to_node(boot_cpu_id
);
187 for (i
= 0; i
< count
; i
++) {
188 desc
= irq_to_desc(i
);
189 desc
->chip_data
= &cfg
[i
];
190 zalloc_cpumask_var_node(&cfg
[i
].domain
, GFP_NOWAIT
, node
);
191 zalloc_cpumask_var_node(&cfg
[i
].old_domain
, GFP_NOWAIT
, node
);
192 if (i
< NR_IRQS_LEGACY
)
193 cpumask_setall(cfg
[i
].domain
);
199 #ifdef CONFIG_SPARSE_IRQ
200 static struct irq_cfg
*irq_cfg(unsigned int irq
)
202 struct irq_cfg
*cfg
= NULL
;
203 struct irq_desc
*desc
;
205 desc
= irq_to_desc(irq
);
207 cfg
= desc
->chip_data
;
212 static struct irq_cfg
*get_one_free_irq_cfg(int node
)
216 cfg
= kzalloc_node(sizeof(*cfg
), GFP_ATOMIC
, node
);
218 if (!alloc_cpumask_var_node(&cfg
->domain
, GFP_ATOMIC
, node
)) {
221 } else if (!alloc_cpumask_var_node(&cfg
->old_domain
,
223 free_cpumask_var(cfg
->domain
);
227 cpumask_clear(cfg
->domain
);
228 cpumask_clear(cfg
->old_domain
);
235 int arch_init_chip_data(struct irq_desc
*desc
, int node
)
239 cfg
= desc
->chip_data
;
241 desc
->chip_data
= get_one_free_irq_cfg(node
);
242 if (!desc
->chip_data
) {
243 printk(KERN_ERR
"can not alloc irq_cfg\n");
251 /* for move_irq_desc */
253 init_copy_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
, int node
)
255 struct irq_pin_list
*old_entry
, *head
, *tail
, *entry
;
257 cfg
->irq_2_pin
= NULL
;
258 old_entry
= old_cfg
->irq_2_pin
;
262 entry
= get_one_free_irq_2_pin(node
);
266 entry
->apic
= old_entry
->apic
;
267 entry
->pin
= old_entry
->pin
;
270 old_entry
= old_entry
->next
;
272 entry
= get_one_free_irq_2_pin(node
);
280 /* still use the old one */
283 entry
->apic
= old_entry
->apic
;
284 entry
->pin
= old_entry
->pin
;
287 old_entry
= old_entry
->next
;
291 cfg
->irq_2_pin
= head
;
294 static void free_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
)
296 struct irq_pin_list
*entry
, *next
;
298 if (old_cfg
->irq_2_pin
== cfg
->irq_2_pin
)
301 entry
= old_cfg
->irq_2_pin
;
308 old_cfg
->irq_2_pin
= NULL
;
311 void arch_init_copy_chip_data(struct irq_desc
*old_desc
,
312 struct irq_desc
*desc
, int node
)
315 struct irq_cfg
*old_cfg
;
317 cfg
= get_one_free_irq_cfg(node
);
322 desc
->chip_data
= cfg
;
324 old_cfg
= old_desc
->chip_data
;
326 memcpy(cfg
, old_cfg
, sizeof(struct irq_cfg
));
328 init_copy_irq_2_pin(old_cfg
, cfg
, node
);
331 static void free_irq_cfg(struct irq_cfg
*old_cfg
)
336 void arch_free_chip_data(struct irq_desc
*old_desc
, struct irq_desc
*desc
)
338 struct irq_cfg
*old_cfg
, *cfg
;
340 old_cfg
= old_desc
->chip_data
;
341 cfg
= desc
->chip_data
;
347 free_irq_2_pin(old_cfg
, cfg
);
348 free_irq_cfg(old_cfg
);
349 old_desc
->chip_data
= NULL
;
352 /* end for move_irq_desc */
355 static struct irq_cfg
*irq_cfg(unsigned int irq
)
357 return irq
< nr_irqs
? irq_cfgx
+ irq
: NULL
;
364 unsigned int unused
[3];
366 unsigned int unused2
[11];
370 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
372 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
373 + (mp_ioapics
[idx
].apicaddr
& ~PAGE_MASK
);
376 static inline void io_apic_eoi(unsigned int apic
, unsigned int vector
)
378 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
379 writel(vector
, &io_apic
->eoi
);
382 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
384 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
385 writel(reg
, &io_apic
->index
);
386 return readl(&io_apic
->data
);
389 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
391 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
392 writel(reg
, &io_apic
->index
);
393 writel(value
, &io_apic
->data
);
397 * Re-write a value: to be used for read-modify-write
398 * cycles where the read already set up the index register.
400 * Older SiS APIC requires we rewrite the index register
402 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
404 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
407 writel(reg
, &io_apic
->index
);
408 writel(value
, &io_apic
->data
);
411 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
413 struct irq_pin_list
*entry
;
416 spin_lock_irqsave(&ioapic_lock
, flags
);
417 entry
= cfg
->irq_2_pin
;
425 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
426 /* Is the remote IRR bit set? */
427 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
428 spin_unlock_irqrestore(&ioapic_lock
, flags
);
435 spin_unlock_irqrestore(&ioapic_lock
, flags
);
441 struct { u32 w1
, w2
; };
442 struct IO_APIC_route_entry entry
;
445 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
447 union entry_union eu
;
449 spin_lock_irqsave(&ioapic_lock
, flags
);
450 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
451 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
452 spin_unlock_irqrestore(&ioapic_lock
, flags
);
457 * When we write a new IO APIC routing entry, we need to write the high
458 * word first! If the mask bit in the low word is clear, we will enable
459 * the interrupt, and we need to make sure the entry is fully populated
460 * before that happens.
463 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
465 union entry_union eu
= {{0, 0}};
468 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
469 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
472 void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
475 spin_lock_irqsave(&ioapic_lock
, flags
);
476 __ioapic_write_entry(apic
, pin
, e
);
477 spin_unlock_irqrestore(&ioapic_lock
, flags
);
481 * When we mask an IO APIC routing entry, we need to write the low
482 * word first, in order to set the mask bit before we change the
485 static void ioapic_mask_entry(int apic
, int pin
)
488 union entry_union eu
= { .entry
.mask
= 1 };
490 spin_lock_irqsave(&ioapic_lock
, flags
);
491 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
492 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
493 spin_unlock_irqrestore(&ioapic_lock
, flags
);
497 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
498 * shared ISA-space IRQs, so we have to support them. We are super
499 * fast in the common case, and fast for shared ISA-space IRQs.
501 static void add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
503 struct irq_pin_list
*entry
;
505 entry
= cfg
->irq_2_pin
;
507 entry
= get_one_free_irq_2_pin(node
);
509 printk(KERN_ERR
"can not alloc irq_2_pin to add %d - %d\n",
513 cfg
->irq_2_pin
= entry
;
519 while (entry
->next
) {
520 /* not again, please */
521 if (entry
->apic
== apic
&& entry
->pin
== pin
)
527 entry
->next
= get_one_free_irq_2_pin(node
);
534 * Reroute an IRQ to a different pin.
536 static void __init
replace_pin_at_irq_node(struct irq_cfg
*cfg
, int node
,
537 int oldapic
, int oldpin
,
538 int newapic
, int newpin
)
540 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
544 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
545 entry
->apic
= newapic
;
548 /* every one is different, right? */
554 /* why? call replace before add? */
556 add_pin_to_irq_node(cfg
, node
, newapic
, newpin
);
559 static void io_apic_modify_irq(struct irq_cfg
*cfg
,
560 int mask_and
, int mask_or
,
561 void (*final
)(struct irq_pin_list
*entry
))
564 struct irq_pin_list
*entry
;
566 for (entry
= cfg
->irq_2_pin
; entry
!= NULL
; entry
= entry
->next
) {
569 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
572 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
578 static void __unmask_IO_APIC_irq(struct irq_cfg
*cfg
)
580 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
583 static void io_apic_sync(struct irq_pin_list
*entry
)
586 * Synchronize the IO-APIC and the CPU by doing
587 * a dummy read from the IO-APIC
589 struct io_apic __iomem
*io_apic
;
590 io_apic
= io_apic_base(entry
->apic
);
591 readl(&io_apic
->data
);
594 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
596 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
599 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg
*cfg
)
601 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_LEVEL_TRIGGER
,
602 IO_APIC_REDIR_MASKED
, NULL
);
605 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg
*cfg
)
607 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
,
608 IO_APIC_REDIR_LEVEL_TRIGGER
, NULL
);
611 static void mask_IO_APIC_irq_desc(struct irq_desc
*desc
)
613 struct irq_cfg
*cfg
= desc
->chip_data
;
618 spin_lock_irqsave(&ioapic_lock
, flags
);
619 __mask_IO_APIC_irq(cfg
);
620 spin_unlock_irqrestore(&ioapic_lock
, flags
);
623 static void unmask_IO_APIC_irq_desc(struct irq_desc
*desc
)
625 struct irq_cfg
*cfg
= desc
->chip_data
;
628 spin_lock_irqsave(&ioapic_lock
, flags
);
629 __unmask_IO_APIC_irq(cfg
);
630 spin_unlock_irqrestore(&ioapic_lock
, flags
);
633 static void mask_IO_APIC_irq(unsigned int irq
)
635 struct irq_desc
*desc
= irq_to_desc(irq
);
637 mask_IO_APIC_irq_desc(desc
);
639 static void unmask_IO_APIC_irq(unsigned int irq
)
641 struct irq_desc
*desc
= irq_to_desc(irq
);
643 unmask_IO_APIC_irq_desc(desc
);
646 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
648 struct IO_APIC_route_entry entry
;
650 /* Check delivery_mode to be sure we're not clearing an SMI pin */
651 entry
= ioapic_read_entry(apic
, pin
);
652 if (entry
.delivery_mode
== dest_SMI
)
655 * Disable it in the IO-APIC irq-routing table:
657 ioapic_mask_entry(apic
, pin
);
660 static void clear_IO_APIC (void)
664 for (apic
= 0; apic
< nr_ioapics
; apic
++)
665 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
666 clear_IO_APIC_pin(apic
, pin
);
671 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
672 * specific CPU-side IRQs.
676 static int pirq_entries
[MAX_PIRQS
] = {
677 [0 ... MAX_PIRQS
- 1] = -1
680 static int __init
ioapic_pirq_setup(char *str
)
683 int ints
[MAX_PIRQS
+1];
685 get_options(str
, ARRAY_SIZE(ints
), ints
);
687 apic_printk(APIC_VERBOSE
, KERN_INFO
688 "PIRQ redirection, working around broken MP-BIOS.\n");
690 if (ints
[0] < MAX_PIRQS
)
693 for (i
= 0; i
< max
; i
++) {
694 apic_printk(APIC_VERBOSE
, KERN_DEBUG
695 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
697 * PIRQs are mapped upside down, usually.
699 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
704 __setup("pirq=", ioapic_pirq_setup
);
705 #endif /* CONFIG_X86_32 */
707 struct IO_APIC_route_entry
**alloc_ioapic_entries(void)
710 struct IO_APIC_route_entry
**ioapic_entries
;
712 ioapic_entries
= kzalloc(sizeof(*ioapic_entries
) * nr_ioapics
,
717 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
718 ioapic_entries
[apic
] =
719 kzalloc(sizeof(struct IO_APIC_route_entry
) *
720 nr_ioapic_registers
[apic
], GFP_ATOMIC
);
721 if (!ioapic_entries
[apic
])
725 return ioapic_entries
;
729 kfree(ioapic_entries
[apic
]);
730 kfree(ioapic_entries
);
736 * Saves all the IO-APIC RTE's
738 int save_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
745 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
746 if (!ioapic_entries
[apic
])
749 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
750 ioapic_entries
[apic
][pin
] =
751 ioapic_read_entry(apic
, pin
);
758 * Mask all IO APIC entries.
760 void mask_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
767 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
768 if (!ioapic_entries
[apic
])
771 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
772 struct IO_APIC_route_entry entry
;
774 entry
= ioapic_entries
[apic
][pin
];
777 ioapic_write_entry(apic
, pin
, entry
);
784 * Restore IO APIC entries which was saved in ioapic_entries.
786 int restore_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
793 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
794 if (!ioapic_entries
[apic
])
797 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
798 ioapic_write_entry(apic
, pin
,
799 ioapic_entries
[apic
][pin
]);
804 void free_ioapic_entries(struct IO_APIC_route_entry
**ioapic_entries
)
808 for (apic
= 0; apic
< nr_ioapics
; apic
++)
809 kfree(ioapic_entries
[apic
]);
811 kfree(ioapic_entries
);
815 * Find the IRQ entry number of a certain pin.
817 static int find_irq_entry(int apic
, int pin
, int type
)
821 for (i
= 0; i
< mp_irq_entries
; i
++)
822 if (mp_irqs
[i
].irqtype
== type
&&
823 (mp_irqs
[i
].dstapic
== mp_ioapics
[apic
].apicid
||
824 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) &&
825 mp_irqs
[i
].dstirq
== pin
)
832 * Find the pin to which IRQ[irq] (ISA) is connected
834 static int __init
find_isa_irq_pin(int irq
, int type
)
838 for (i
= 0; i
< mp_irq_entries
; i
++) {
839 int lbus
= mp_irqs
[i
].srcbus
;
841 if (test_bit(lbus
, mp_bus_not_pci
) &&
842 (mp_irqs
[i
].irqtype
== type
) &&
843 (mp_irqs
[i
].srcbusirq
== irq
))
845 return mp_irqs
[i
].dstirq
;
850 static int __init
find_isa_irq_apic(int irq
, int type
)
854 for (i
= 0; i
< mp_irq_entries
; i
++) {
855 int lbus
= mp_irqs
[i
].srcbus
;
857 if (test_bit(lbus
, mp_bus_not_pci
) &&
858 (mp_irqs
[i
].irqtype
== type
) &&
859 (mp_irqs
[i
].srcbusirq
== irq
))
862 if (i
< mp_irq_entries
) {
864 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
865 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
)
873 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
875 * EISA Edge/Level control register, ELCR
877 static int EISA_ELCR(unsigned int irq
)
879 if (irq
< NR_IRQS_LEGACY
) {
880 unsigned int port
= 0x4d0 + (irq
>> 3);
881 return (inb(port
) >> (irq
& 7)) & 1;
883 apic_printk(APIC_VERBOSE
, KERN_INFO
884 "Broken MPtable reports ISA irq %d\n", irq
);
890 /* ISA interrupts are always polarity zero edge triggered,
891 * when listed as conforming in the MP table. */
893 #define default_ISA_trigger(idx) (0)
894 #define default_ISA_polarity(idx) (0)
896 /* EISA interrupts are always polarity zero and can be edge or level
897 * trigger depending on the ELCR value. If an interrupt is listed as
898 * EISA conforming in the MP table, that means its trigger type must
899 * be read in from the ELCR */
901 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
902 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
904 /* PCI interrupts are always polarity one level triggered,
905 * when listed as conforming in the MP table. */
907 #define default_PCI_trigger(idx) (1)
908 #define default_PCI_polarity(idx) (1)
910 /* MCA interrupts are always polarity zero level triggered,
911 * when listed as conforming in the MP table. */
913 #define default_MCA_trigger(idx) (1)
914 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
916 static int MPBIOS_polarity(int idx
)
918 int bus
= mp_irqs
[idx
].srcbus
;
922 * Determine IRQ line polarity (high active or low active):
924 switch (mp_irqs
[idx
].irqflag
& 3)
926 case 0: /* conforms, ie. bus-type dependent polarity */
927 if (test_bit(bus
, mp_bus_not_pci
))
928 polarity
= default_ISA_polarity(idx
);
930 polarity
= default_PCI_polarity(idx
);
932 case 1: /* high active */
937 case 2: /* reserved */
939 printk(KERN_WARNING
"broken BIOS!!\n");
943 case 3: /* low active */
948 default: /* invalid */
950 printk(KERN_WARNING
"broken BIOS!!\n");
958 static int MPBIOS_trigger(int idx
)
960 int bus
= mp_irqs
[idx
].srcbus
;
964 * Determine IRQ trigger mode (edge or level sensitive):
966 switch ((mp_irqs
[idx
].irqflag
>>2) & 3)
968 case 0: /* conforms, ie. bus-type dependent */
969 if (test_bit(bus
, mp_bus_not_pci
))
970 trigger
= default_ISA_trigger(idx
);
972 trigger
= default_PCI_trigger(idx
);
973 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
974 switch (mp_bus_id_to_type
[bus
]) {
975 case MP_BUS_ISA
: /* ISA pin */
977 /* set before the switch */
980 case MP_BUS_EISA
: /* EISA pin */
982 trigger
= default_EISA_trigger(idx
);
985 case MP_BUS_PCI
: /* PCI pin */
987 /* set before the switch */
990 case MP_BUS_MCA
: /* MCA pin */
992 trigger
= default_MCA_trigger(idx
);
997 printk(KERN_WARNING
"broken BIOS!!\n");
1009 case 2: /* reserved */
1011 printk(KERN_WARNING
"broken BIOS!!\n");
1020 default: /* invalid */
1022 printk(KERN_WARNING
"broken BIOS!!\n");
1030 static inline int irq_polarity(int idx
)
1032 return MPBIOS_polarity(idx
);
1035 static inline int irq_trigger(int idx
)
1037 return MPBIOS_trigger(idx
);
1040 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
1041 static int pin_2_irq(int idx
, int apic
, int pin
)
1044 int bus
= mp_irqs
[idx
].srcbus
;
1047 * Debugging check, we are in big trouble if this message pops up!
1049 if (mp_irqs
[idx
].dstirq
!= pin
)
1050 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1052 if (test_bit(bus
, mp_bus_not_pci
)) {
1053 irq
= mp_irqs
[idx
].srcbusirq
;
1056 * PCI IRQs are mapped in order
1060 irq
+= nr_ioapic_registers
[i
++];
1063 * For MPS mode, so far only needed by ES7000 platform
1065 if (ioapic_renumber_irq
)
1066 irq
= ioapic_renumber_irq(apic
, irq
);
1069 #ifdef CONFIG_X86_32
1071 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1073 if ((pin
>= 16) && (pin
<= 23)) {
1074 if (pirq_entries
[pin
-16] != -1) {
1075 if (!pirq_entries
[pin
-16]) {
1076 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1077 "disabling PIRQ%d\n", pin
-16);
1079 irq
= pirq_entries
[pin
-16];
1080 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1081 "using PIRQ%d -> IRQ %d\n",
1092 * Find a specific PCI IRQ entry.
1093 * Not an __init, possibly needed by modules
1095 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
,
1096 struct io_apic_irq_attr
*irq_attr
)
1098 int apic
, i
, best_guess
= -1;
1100 apic_printk(APIC_DEBUG
,
1101 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1103 if (test_bit(bus
, mp_bus_not_pci
)) {
1104 apic_printk(APIC_VERBOSE
,
1105 "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1108 for (i
= 0; i
< mp_irq_entries
; i
++) {
1109 int lbus
= mp_irqs
[i
].srcbus
;
1111 for (apic
= 0; apic
< nr_ioapics
; apic
++)
1112 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
||
1113 mp_irqs
[i
].dstapic
== MP_APIC_ALL
)
1116 if (!test_bit(lbus
, mp_bus_not_pci
) &&
1117 !mp_irqs
[i
].irqtype
&&
1119 (slot
== ((mp_irqs
[i
].srcbusirq
>> 2) & 0x1f))) {
1120 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].dstirq
);
1122 if (!(apic
|| IO_APIC_IRQ(irq
)))
1125 if (pin
== (mp_irqs
[i
].srcbusirq
& 3)) {
1126 set_io_apic_irq_attr(irq_attr
, apic
,
1133 * Use the first all-but-pin matching entry as a
1134 * best-guess fuzzy result for broken mptables.
1136 if (best_guess
< 0) {
1137 set_io_apic_irq_attr(irq_attr
, apic
,
1147 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1149 void lock_vector_lock(void)
1151 /* Used to the online set of cpus does not change
1152 * during assign_irq_vector.
1154 spin_lock(&vector_lock
);
1157 void unlock_vector_lock(void)
1159 spin_unlock(&vector_lock
);
1163 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1166 * NOTE! The local APIC isn't very good at handling
1167 * multiple interrupts at the same interrupt level.
1168 * As the interrupt level is determined by taking the
1169 * vector number and shifting that right by 4, we
1170 * want to spread these out a bit so that they don't
1171 * all fall in the same interrupt level.
1173 * Also, we've got to be careful not to trash gate
1174 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1176 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1177 unsigned int old_vector
;
1179 cpumask_var_t tmp_mask
;
1181 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
1184 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1187 old_vector
= cfg
->vector
;
1189 cpumask_and(tmp_mask
, mask
, cpu_online_mask
);
1190 cpumask_and(tmp_mask
, cfg
->domain
, tmp_mask
);
1191 if (!cpumask_empty(tmp_mask
)) {
1192 free_cpumask_var(tmp_mask
);
1197 /* Only try and allocate irqs on cpus that are present */
1199 for_each_cpu_and(cpu
, mask
, cpu_online_mask
) {
1203 apic
->vector_allocation_domain(cpu
, tmp_mask
);
1205 vector
= current_vector
;
1206 offset
= current_offset
;
1209 if (vector
>= first_system_vector
) {
1210 /* If out of vectors on large boxen, must share them. */
1211 offset
= (offset
+ 1) % 8;
1212 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1214 if (unlikely(current_vector
== vector
))
1217 if (test_bit(vector
, used_vectors
))
1220 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1221 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1224 current_vector
= vector
;
1225 current_offset
= offset
;
1227 cfg
->move_in_progress
= 1;
1228 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1230 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1231 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1232 cfg
->vector
= vector
;
1233 cpumask_copy(cfg
->domain
, tmp_mask
);
1237 free_cpumask_var(tmp_mask
);
1242 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1245 unsigned long flags
;
1247 spin_lock_irqsave(&vector_lock
, flags
);
1248 err
= __assign_irq_vector(irq
, cfg
, mask
);
1249 spin_unlock_irqrestore(&vector_lock
, flags
);
1253 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1257 BUG_ON(!cfg
->vector
);
1259 vector
= cfg
->vector
;
1260 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1261 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1264 cpumask_clear(cfg
->domain
);
1266 if (likely(!cfg
->move_in_progress
))
1268 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1269 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
;
1271 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1273 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1277 cfg
->move_in_progress
= 0;
1280 void __setup_vector_irq(int cpu
)
1282 /* Initialize vector_irq on a new cpu */
1283 /* This function must be called with vector_lock held */
1285 struct irq_cfg
*cfg
;
1286 struct irq_desc
*desc
;
1288 /* Mark the inuse vectors */
1289 for_each_irq_desc(irq
, desc
) {
1290 cfg
= desc
->chip_data
;
1291 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1293 vector
= cfg
->vector
;
1294 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1296 /* Mark the free vectors */
1297 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1298 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1303 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1304 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1308 static struct irq_chip ioapic_chip
;
1309 static struct irq_chip ir_ioapic_chip
;
1311 #define IOAPIC_AUTO -1
1312 #define IOAPIC_EDGE 0
1313 #define IOAPIC_LEVEL 1
1315 #ifdef CONFIG_X86_32
1316 static inline int IO_APIC_irq_trigger(int irq
)
1320 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1321 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1322 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1323 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1324 return irq_trigger(idx
);
1328 * nonexistent IRQs are edge default
1333 static inline int IO_APIC_irq_trigger(int irq
)
1339 static void ioapic_register_intr(int irq
, struct irq_desc
*desc
, unsigned long trigger
)
1342 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1343 trigger
== IOAPIC_LEVEL
)
1344 desc
->status
|= IRQ_LEVEL
;
1346 desc
->status
&= ~IRQ_LEVEL
;
1348 if (irq_remapped(irq
)) {
1349 desc
->status
|= IRQ_MOVE_PCNTXT
;
1351 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1355 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1356 handle_edge_irq
, "edge");
1360 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1361 trigger
== IOAPIC_LEVEL
)
1362 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1366 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1367 handle_edge_irq
, "edge");
1370 int setup_ioapic_entry(int apic_id
, int irq
,
1371 struct IO_APIC_route_entry
*entry
,
1372 unsigned int destination
, int trigger
,
1373 int polarity
, int vector
, int pin
)
1376 * add it to the IO-APIC irq-routing table:
1378 memset(entry
,0,sizeof(*entry
));
1380 if (intr_remapping_enabled
) {
1381 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic_id
);
1383 struct IR_IO_APIC_route_entry
*ir_entry
=
1384 (struct IR_IO_APIC_route_entry
*) entry
;
1388 panic("No mapping iommu for ioapic %d\n", apic_id
);
1390 index
= alloc_irte(iommu
, irq
, 1);
1392 panic("Failed to allocate IRTE for ioapic %d\n", apic_id
);
1394 memset(&irte
, 0, sizeof(irte
));
1397 irte
.dst_mode
= apic
->irq_dest_mode
;
1399 * Trigger mode in the IRTE will always be edge, and the
1400 * actual level or edge trigger will be setup in the IO-APIC
1401 * RTE. This will help simplify level triggered irq migration.
1402 * For more details, see the comments above explainig IO-APIC
1403 * irq migration in the presence of interrupt-remapping.
1405 irte
.trigger_mode
= 0;
1406 irte
.dlvry_mode
= apic
->irq_delivery_mode
;
1407 irte
.vector
= vector
;
1408 irte
.dest_id
= IRTE_DEST(destination
);
1410 /* Set source-id of interrupt request */
1411 set_ioapic_sid(&irte
, apic_id
);
1413 modify_irte(irq
, &irte
);
1415 ir_entry
->index2
= (index
>> 15) & 0x1;
1417 ir_entry
->format
= 1;
1418 ir_entry
->index
= (index
& 0x7fff);
1420 * IO-APIC RTE will be configured with virtual vector.
1421 * irq handler will do the explicit EOI to the io-apic.
1423 ir_entry
->vector
= pin
;
1425 entry
->delivery_mode
= apic
->irq_delivery_mode
;
1426 entry
->dest_mode
= apic
->irq_dest_mode
;
1427 entry
->dest
= destination
;
1428 entry
->vector
= vector
;
1431 entry
->mask
= 0; /* enable IRQ */
1432 entry
->trigger
= trigger
;
1433 entry
->polarity
= polarity
;
1435 /* Mask level triggered irqs.
1436 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1443 static void setup_IO_APIC_irq(int apic_id
, int pin
, unsigned int irq
, struct irq_desc
*desc
,
1444 int trigger
, int polarity
)
1446 struct irq_cfg
*cfg
;
1447 struct IO_APIC_route_entry entry
;
1450 if (!IO_APIC_IRQ(irq
))
1453 cfg
= desc
->chip_data
;
1455 if (assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
1458 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
1460 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1461 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1462 "IRQ %d Mode:%i Active:%i)\n",
1463 apic_id
, mp_ioapics
[apic_id
].apicid
, pin
, cfg
->vector
,
1464 irq
, trigger
, polarity
);
1467 if (setup_ioapic_entry(mp_ioapics
[apic_id
].apicid
, irq
, &entry
,
1468 dest
, trigger
, polarity
, cfg
->vector
, pin
)) {
1469 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1470 mp_ioapics
[apic_id
].apicid
, pin
);
1471 __clear_irq_vector(irq
, cfg
);
1475 ioapic_register_intr(irq
, desc
, trigger
);
1476 if (irq
< NR_IRQS_LEGACY
)
1477 disable_8259A_irq(irq
);
1479 ioapic_write_entry(apic_id
, pin
, entry
);
1483 DECLARE_BITMAP(pin_programmed
, MP_MAX_IOAPIC_PIN
+ 1);
1484 } mp_ioapic_routing
[MAX_IO_APICS
];
1486 static void __init
setup_IO_APIC_irqs(void)
1488 int apic_id
= 0, pin
, idx
, irq
;
1490 struct irq_desc
*desc
;
1491 struct irq_cfg
*cfg
;
1492 int node
= cpu_to_node(boot_cpu_id
);
1494 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1497 if (!acpi_disabled
&& acpi_ioapic
) {
1498 apic_id
= mp_find_ioapic(0);
1504 for (pin
= 0; pin
< nr_ioapic_registers
[apic_id
]; pin
++) {
1505 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1509 apic_printk(APIC_VERBOSE
,
1510 KERN_DEBUG
" %d-%d",
1511 mp_ioapics
[apic_id
].apicid
, pin
);
1513 apic_printk(APIC_VERBOSE
, " %d-%d",
1514 mp_ioapics
[apic_id
].apicid
, pin
);
1518 apic_printk(APIC_VERBOSE
,
1519 " (apicid-pin) not connected\n");
1523 irq
= pin_2_irq(idx
, apic_id
, pin
);
1526 * Skip the timer IRQ if there's a quirk handler
1527 * installed and if it returns 1:
1529 if (apic
->multi_timer_check
&&
1530 apic
->multi_timer_check(apic_id
, irq
))
1533 desc
= irq_to_desc_alloc_node(irq
, node
);
1535 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
1538 cfg
= desc
->chip_data
;
1539 add_pin_to_irq_node(cfg
, node
, apic_id
, pin
);
1541 * don't mark it in pin_programmed, so later acpi could
1542 * set it correctly when irq < 16
1544 setup_IO_APIC_irq(apic_id
, pin
, irq
, desc
,
1545 irq_trigger(idx
), irq_polarity(idx
));
1549 apic_printk(APIC_VERBOSE
,
1550 " (apicid-pin) not connected\n");
1554 * Set up the timer pin, possibly with the 8259A-master behind.
1556 static void __init
setup_timer_IRQ0_pin(unsigned int apic_id
, unsigned int pin
,
1559 struct IO_APIC_route_entry entry
;
1561 if (intr_remapping_enabled
)
1564 memset(&entry
, 0, sizeof(entry
));
1567 * We use logical delivery to get the timer IRQ
1570 entry
.dest_mode
= apic
->irq_dest_mode
;
1571 entry
.mask
= 0; /* don't mask IRQ for edge */
1572 entry
.dest
= apic
->cpu_mask_to_apicid(apic
->target_cpus());
1573 entry
.delivery_mode
= apic
->irq_delivery_mode
;
1576 entry
.vector
= vector
;
1579 * The timer IRQ doesn't have to know that behind the
1580 * scene we may have a 8259A-master in AEOI mode ...
1582 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1585 * Add it to the IO-APIC irq-routing table:
1587 ioapic_write_entry(apic_id
, pin
, entry
);
1591 __apicdebuginit(void) print_IO_APIC(void)
1594 union IO_APIC_reg_00 reg_00
;
1595 union IO_APIC_reg_01 reg_01
;
1596 union IO_APIC_reg_02 reg_02
;
1597 union IO_APIC_reg_03 reg_03
;
1598 unsigned long flags
;
1599 struct irq_cfg
*cfg
;
1600 struct irq_desc
*desc
;
1603 if (apic_verbosity
== APIC_QUIET
)
1606 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1607 for (i
= 0; i
< nr_ioapics
; i
++)
1608 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1609 mp_ioapics
[i
].apicid
, nr_ioapic_registers
[i
]);
1612 * We are a bit conservative about what we expect. We have to
1613 * know about every hardware change ASAP.
1615 printk(KERN_INFO
"testing the IO APIC.......................\n");
1617 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1619 spin_lock_irqsave(&ioapic_lock
, flags
);
1620 reg_00
.raw
= io_apic_read(apic
, 0);
1621 reg_01
.raw
= io_apic_read(apic
, 1);
1622 if (reg_01
.bits
.version
>= 0x10)
1623 reg_02
.raw
= io_apic_read(apic
, 2);
1624 if (reg_01
.bits
.version
>= 0x20)
1625 reg_03
.raw
= io_apic_read(apic
, 3);
1626 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1629 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].apicid
);
1630 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1631 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1632 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1633 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1635 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1636 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1638 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1639 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1642 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1643 * but the value of reg_02 is read as the previous read register
1644 * value, so ignore it if reg_02 == reg_01.
1646 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1647 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1648 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1652 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1653 * or reg_03, but the value of reg_0[23] is read as the previous read
1654 * register value, so ignore it if reg_03 == reg_0[12].
1656 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1657 reg_03
.raw
!= reg_01
.raw
) {
1658 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1659 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1662 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1664 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1665 " Stat Dmod Deli Vect: \n");
1667 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1668 struct IO_APIC_route_entry entry
;
1670 entry
= ioapic_read_entry(apic
, i
);
1672 printk(KERN_DEBUG
" %02x %03X ",
1677 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1682 entry
.delivery_status
,
1684 entry
.delivery_mode
,
1689 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1690 for_each_irq_desc(irq
, desc
) {
1691 struct irq_pin_list
*entry
;
1693 cfg
= desc
->chip_data
;
1694 entry
= cfg
->irq_2_pin
;
1697 printk(KERN_DEBUG
"IRQ%d ", irq
);
1699 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1702 entry
= entry
->next
;
1707 printk(KERN_INFO
".................................... done.\n");
1712 __apicdebuginit(void) print_APIC_field(int base
)
1716 if (apic_verbosity
== APIC_QUIET
)
1721 for (i
= 0; i
< 8; i
++)
1722 printk(KERN_CONT
"%08x", apic_read(base
+ i
*0x10));
1724 printk(KERN_CONT
"\n");
1727 __apicdebuginit(void) print_local_APIC(void *dummy
)
1729 unsigned int i
, v
, ver
, maxlvt
;
1732 if (apic_verbosity
== APIC_QUIET
)
1735 printk(KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1736 smp_processor_id(), hard_smp_processor_id());
1737 v
= apic_read(APIC_ID
);
1738 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1739 v
= apic_read(APIC_LVR
);
1740 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1741 ver
= GET_APIC_VERSION(v
);
1742 maxlvt
= lapic_get_maxlvt();
1744 v
= apic_read(APIC_TASKPRI
);
1745 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1747 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1748 if (!APIC_XAPIC(ver
)) {
1749 v
= apic_read(APIC_ARBPRI
);
1750 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1751 v
& APIC_ARBPRI_MASK
);
1753 v
= apic_read(APIC_PROCPRI
);
1754 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1758 * Remote read supported only in the 82489DX and local APIC for
1759 * Pentium processors.
1761 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1762 v
= apic_read(APIC_RRR
);
1763 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1766 v
= apic_read(APIC_LDR
);
1767 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1768 if (!x2apic_enabled()) {
1769 v
= apic_read(APIC_DFR
);
1770 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1772 v
= apic_read(APIC_SPIV
);
1773 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1775 printk(KERN_DEBUG
"... APIC ISR field:\n");
1776 print_APIC_field(APIC_ISR
);
1777 printk(KERN_DEBUG
"... APIC TMR field:\n");
1778 print_APIC_field(APIC_TMR
);
1779 printk(KERN_DEBUG
"... APIC IRR field:\n");
1780 print_APIC_field(APIC_IRR
);
1782 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1783 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1784 apic_write(APIC_ESR
, 0);
1786 v
= apic_read(APIC_ESR
);
1787 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1790 icr
= apic_icr_read();
1791 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1792 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1794 v
= apic_read(APIC_LVTT
);
1795 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1797 if (maxlvt
> 3) { /* PC is LVT#4. */
1798 v
= apic_read(APIC_LVTPC
);
1799 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1801 v
= apic_read(APIC_LVT0
);
1802 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1803 v
= apic_read(APIC_LVT1
);
1804 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1806 if (maxlvt
> 2) { /* ERR is LVT#3. */
1807 v
= apic_read(APIC_LVTERR
);
1808 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1811 v
= apic_read(APIC_TMICT
);
1812 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1813 v
= apic_read(APIC_TMCCT
);
1814 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1815 v
= apic_read(APIC_TDCR
);
1816 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1818 if (boot_cpu_has(X86_FEATURE_EXTAPIC
)) {
1819 v
= apic_read(APIC_EFEAT
);
1820 maxlvt
= (v
>> 16) & 0xff;
1821 printk(KERN_DEBUG
"... APIC EFEAT: %08x\n", v
);
1822 v
= apic_read(APIC_ECTRL
);
1823 printk(KERN_DEBUG
"... APIC ECTRL: %08x\n", v
);
1824 for (i
= 0; i
< maxlvt
; i
++) {
1825 v
= apic_read(APIC_EILVTn(i
));
1826 printk(KERN_DEBUG
"... APIC EILVT%d: %08x\n", i
, v
);
1832 __apicdebuginit(void) print_all_local_APICs(void)
1837 for_each_online_cpu(cpu
)
1838 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1842 __apicdebuginit(void) print_PIC(void)
1845 unsigned long flags
;
1847 if (apic_verbosity
== APIC_QUIET
)
1850 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1852 spin_lock_irqsave(&i8259A_lock
, flags
);
1854 v
= inb(0xa1) << 8 | inb(0x21);
1855 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1857 v
= inb(0xa0) << 8 | inb(0x20);
1858 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1862 v
= inb(0xa0) << 8 | inb(0x20);
1866 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1868 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1870 v
= inb(0x4d1) << 8 | inb(0x4d0);
1871 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1874 __apicdebuginit(int) print_all_ICs(void)
1878 /* don't print out if apic is not there */
1879 if (!cpu_has_apic
|| disable_apic
)
1882 print_all_local_APICs();
1888 fs_initcall(print_all_ICs
);
1891 /* Where if anywhere is the i8259 connect in external int mode */
1892 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1894 void __init
enable_IO_APIC(void)
1896 union IO_APIC_reg_01 reg_01
;
1897 int i8259_apic
, i8259_pin
;
1899 unsigned long flags
;
1902 * The number of IO-APIC IRQ registers (== #pins):
1904 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1905 spin_lock_irqsave(&ioapic_lock
, flags
);
1906 reg_01
.raw
= io_apic_read(apic
, 1);
1907 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1908 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1910 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1912 /* See if any of the pins is in ExtINT mode */
1913 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1914 struct IO_APIC_route_entry entry
;
1915 entry
= ioapic_read_entry(apic
, pin
);
1917 /* If the interrupt line is enabled and in ExtInt mode
1918 * I have found the pin where the i8259 is connected.
1920 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1921 ioapic_i8259
.apic
= apic
;
1922 ioapic_i8259
.pin
= pin
;
1928 /* Look to see what if the MP table has reported the ExtINT */
1929 /* If we could not find the appropriate pin by looking at the ioapic
1930 * the i8259 probably is not connected the ioapic but give the
1931 * mptable a chance anyway.
1933 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1934 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1935 /* Trust the MP table if nothing is setup in the hardware */
1936 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1937 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1938 ioapic_i8259
.pin
= i8259_pin
;
1939 ioapic_i8259
.apic
= i8259_apic
;
1941 /* Complain if the MP table and the hardware disagree */
1942 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1943 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1945 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1949 * Do not trust the IO-APIC being empty at bootup
1955 * Not an __init, needed by the reboot code
1957 void disable_IO_APIC(void)
1960 * Clear the IO-APIC before rebooting:
1965 * If the i8259 is routed through an IOAPIC
1966 * Put that IOAPIC in virtual wire mode
1967 * so legacy interrupts can be delivered.
1969 * With interrupt-remapping, for now we will use virtual wire A mode,
1970 * as virtual wire B is little complex (need to configure both
1971 * IOAPIC RTE aswell as interrupt-remapping table entry).
1972 * As this gets called during crash dump, keep this simple for now.
1974 if (ioapic_i8259
.pin
!= -1 && !intr_remapping_enabled
) {
1975 struct IO_APIC_route_entry entry
;
1977 memset(&entry
, 0, sizeof(entry
));
1978 entry
.mask
= 0; /* Enabled */
1979 entry
.trigger
= 0; /* Edge */
1981 entry
.polarity
= 0; /* High */
1982 entry
.delivery_status
= 0;
1983 entry
.dest_mode
= 0; /* Physical */
1984 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1986 entry
.dest
= read_apic_id();
1989 * Add it to the IO-APIC irq-routing table:
1991 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1995 * Use virtual wire A mode when interrupt remapping is enabled.
1998 disconnect_bsp_APIC(!intr_remapping_enabled
&&
1999 ioapic_i8259
.pin
!= -1);
2002 #ifdef CONFIG_X86_32
2004 * function to set the IO-APIC physical IDs based on the
2005 * values stored in the MPC table.
2007 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2010 static void __init
setup_ioapic_ids_from_mpc(void)
2012 union IO_APIC_reg_00 reg_00
;
2013 physid_mask_t phys_id_present_map
;
2016 unsigned char old_id
;
2017 unsigned long flags
;
2019 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
2023 * Don't check I/O APIC IDs for xAPIC systems. They have
2024 * no meaning without the serial APIC bus.
2026 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2027 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2030 * This is broken; anything with a real cpu count has to
2031 * circumvent this idiocy regardless.
2033 phys_id_present_map
= apic
->ioapic_phys_id_map(phys_cpu_present_map
);
2036 * Set the IOAPIC ID to the value stored in the MPC table.
2038 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++) {
2040 /* Read the register 0 value */
2041 spin_lock_irqsave(&ioapic_lock
, flags
);
2042 reg_00
.raw
= io_apic_read(apic_id
, 0);
2043 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2045 old_id
= mp_ioapics
[apic_id
].apicid
;
2047 if (mp_ioapics
[apic_id
].apicid
>= get_physical_broadcast()) {
2048 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2049 apic_id
, mp_ioapics
[apic_id
].apicid
);
2050 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2052 mp_ioapics
[apic_id
].apicid
= reg_00
.bits
.ID
;
2056 * Sanity check, is the ID really free? Every APIC in a
2057 * system must have a unique ID or we get lots of nice
2058 * 'stuck on smp_invalidate_needed IPI wait' messages.
2060 if (apic
->check_apicid_used(phys_id_present_map
,
2061 mp_ioapics
[apic_id
].apicid
)) {
2062 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2063 apic_id
, mp_ioapics
[apic_id
].apicid
);
2064 for (i
= 0; i
< get_physical_broadcast(); i
++)
2065 if (!physid_isset(i
, phys_id_present_map
))
2067 if (i
>= get_physical_broadcast())
2068 panic("Max APIC ID exceeded!\n");
2069 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2071 physid_set(i
, phys_id_present_map
);
2072 mp_ioapics
[apic_id
].apicid
= i
;
2075 tmp
= apic
->apicid_to_cpu_present(mp_ioapics
[apic_id
].apicid
);
2076 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2077 "phys_id_present_map\n",
2078 mp_ioapics
[apic_id
].apicid
);
2079 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2084 * We need to adjust the IRQ routing table
2085 * if the ID changed.
2087 if (old_id
!= mp_ioapics
[apic_id
].apicid
)
2088 for (i
= 0; i
< mp_irq_entries
; i
++)
2089 if (mp_irqs
[i
].dstapic
== old_id
)
2091 = mp_ioapics
[apic_id
].apicid
;
2094 * Read the right value from the MPC table and
2095 * write it into the ID register.
2097 apic_printk(APIC_VERBOSE
, KERN_INFO
2098 "...changing IO-APIC physical APIC ID to %d ...",
2099 mp_ioapics
[apic_id
].apicid
);
2101 reg_00
.bits
.ID
= mp_ioapics
[apic_id
].apicid
;
2102 spin_lock_irqsave(&ioapic_lock
, flags
);
2103 io_apic_write(apic_id
, 0, reg_00
.raw
);
2104 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2109 spin_lock_irqsave(&ioapic_lock
, flags
);
2110 reg_00
.raw
= io_apic_read(apic_id
, 0);
2111 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2112 if (reg_00
.bits
.ID
!= mp_ioapics
[apic_id
].apicid
)
2113 printk("could not set ID!\n");
2115 apic_printk(APIC_VERBOSE
, " ok.\n");
2120 int no_timer_check __initdata
;
2122 static int __init
notimercheck(char *s
)
2127 __setup("no_timer_check", notimercheck
);
2130 * There is a nasty bug in some older SMP boards, their mptable lies
2131 * about the timer IRQ. We do the following to work around the situation:
2133 * - timer IRQ defaults to IO-APIC IRQ
2134 * - if this function detects that timer IRQs are defunct, then we fall
2135 * back to ISA timer IRQs
2137 static int __init
timer_irq_works(void)
2139 unsigned long t1
= jiffies
;
2140 unsigned long flags
;
2145 local_save_flags(flags
);
2147 /* Let ten ticks pass... */
2148 mdelay((10 * 1000) / HZ
);
2149 local_irq_restore(flags
);
2152 * Expect a few ticks at least, to be sure some possible
2153 * glue logic does not lock up after one or two first
2154 * ticks in a non-ExtINT mode. Also the local APIC
2155 * might have cached one ExtINT interrupt. Finally, at
2156 * least one tick may be lost due to delays.
2160 if (time_after(jiffies
, t1
+ 4))
2166 * In the SMP+IOAPIC case it might happen that there are an unspecified
2167 * number of pending IRQ events unhandled. These cases are very rare,
2168 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2169 * better to do it this way as thus we do not have to be aware of
2170 * 'pending' interrupts in the IRQ path, except at this point.
2173 * Edge triggered needs to resend any interrupt
2174 * that was delayed but this is now handled in the device
2179 * Starting up a edge-triggered IO-APIC interrupt is
2180 * nasty - we need to make sure that we get the edge.
2181 * If it is already asserted for some reason, we need
2182 * return 1 to indicate that is was pending.
2184 * This is not complete - we should be able to fake
2185 * an edge even if it isn't on the 8259A...
2188 static unsigned int startup_ioapic_irq(unsigned int irq
)
2190 int was_pending
= 0;
2191 unsigned long flags
;
2192 struct irq_cfg
*cfg
;
2194 spin_lock_irqsave(&ioapic_lock
, flags
);
2195 if (irq
< NR_IRQS_LEGACY
) {
2196 disable_8259A_irq(irq
);
2197 if (i8259A_irq_pending(irq
))
2201 __unmask_IO_APIC_irq(cfg
);
2202 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2207 #ifdef CONFIG_X86_64
2208 static int ioapic_retrigger_irq(unsigned int irq
)
2211 struct irq_cfg
*cfg
= irq_cfg(irq
);
2212 unsigned long flags
;
2214 spin_lock_irqsave(&vector_lock
, flags
);
2215 apic
->send_IPI_mask(cpumask_of(cpumask_first(cfg
->domain
)), cfg
->vector
);
2216 spin_unlock_irqrestore(&vector_lock
, flags
);
2221 static int ioapic_retrigger_irq(unsigned int irq
)
2223 apic
->send_IPI_self(irq_cfg(irq
)->vector
);
2230 * Level and edge triggered IO-APIC interrupts need different handling,
2231 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2232 * handled with the level-triggered descriptor, but that one has slightly
2233 * more overhead. Level-triggered interrupts cannot be handled with the
2234 * edge-triggered handler, without risking IRQ storms and other ugly
2239 static void send_cleanup_vector(struct irq_cfg
*cfg
)
2241 cpumask_var_t cleanup_mask
;
2243 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
2245 cfg
->move_cleanup_count
= 0;
2246 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
2247 cfg
->move_cleanup_count
++;
2248 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
2249 apic
->send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
2251 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
2252 cfg
->move_cleanup_count
= cpumask_weight(cleanup_mask
);
2253 apic
->send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2254 free_cpumask_var(cleanup_mask
);
2256 cfg
->move_in_progress
= 0;
2259 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
2262 struct irq_pin_list
*entry
;
2263 u8 vector
= cfg
->vector
;
2265 entry
= cfg
->irq_2_pin
;
2275 * With interrupt-remapping, destination information comes
2276 * from interrupt-remapping table entry.
2278 if (!irq_remapped(irq
))
2279 io_apic_write(apic
, 0x11 + pin
*2, dest
);
2280 reg
= io_apic_read(apic
, 0x10 + pin
*2);
2281 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
2283 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
2286 entry
= entry
->next
;
2291 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
);
2294 * Either sets desc->affinity to a valid value, and returns
2295 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
2296 * leaves desc->affinity untouched.
2299 set_desc_affinity(struct irq_desc
*desc
, const struct cpumask
*mask
)
2301 struct irq_cfg
*cfg
;
2304 if (!cpumask_intersects(mask
, cpu_online_mask
))
2308 cfg
= desc
->chip_data
;
2309 if (assign_irq_vector(irq
, cfg
, mask
))
2312 cpumask_copy(desc
->affinity
, mask
);
2314 return apic
->cpu_mask_to_apicid_and(desc
->affinity
, cfg
->domain
);
2318 set_ioapic_affinity_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2320 struct irq_cfg
*cfg
;
2321 unsigned long flags
;
2327 cfg
= desc
->chip_data
;
2329 spin_lock_irqsave(&ioapic_lock
, flags
);
2330 dest
= set_desc_affinity(desc
, mask
);
2331 if (dest
!= BAD_APICID
) {
2332 /* Only the high 8 bits are valid. */
2333 dest
= SET_APIC_LOGICAL_ID(dest
);
2334 __target_IO_APIC_irq(irq
, dest
, cfg
);
2337 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2343 set_ioapic_affinity_irq(unsigned int irq
, const struct cpumask
*mask
)
2345 struct irq_desc
*desc
;
2347 desc
= irq_to_desc(irq
);
2349 return set_ioapic_affinity_irq_desc(desc
, mask
);
2352 #ifdef CONFIG_INTR_REMAP
2355 * Migrate the IO-APIC irq in the presence of intr-remapping.
2357 * For both level and edge triggered, irq migration is a simple atomic
2358 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2360 * For level triggered, we eliminate the io-apic RTE modification (with the
2361 * updated vector information), by using a virtual vector (io-apic pin number).
2362 * Real vector that is used for interrupting cpu will be coming from
2363 * the interrupt-remapping table entry.
2366 migrate_ioapic_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2368 struct irq_cfg
*cfg
;
2374 if (!cpumask_intersects(mask
, cpu_online_mask
))
2378 if (get_irte(irq
, &irte
))
2381 cfg
= desc
->chip_data
;
2382 if (assign_irq_vector(irq
, cfg
, mask
))
2385 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, mask
);
2387 irte
.vector
= cfg
->vector
;
2388 irte
.dest_id
= IRTE_DEST(dest
);
2391 * Modified the IRTE and flushes the Interrupt entry cache.
2393 modify_irte(irq
, &irte
);
2395 if (cfg
->move_in_progress
)
2396 send_cleanup_vector(cfg
);
2398 cpumask_copy(desc
->affinity
, mask
);
2404 * Migrates the IRQ destination in the process context.
2406 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2407 const struct cpumask
*mask
)
2409 return migrate_ioapic_irq_desc(desc
, mask
);
2411 static int set_ir_ioapic_affinity_irq(unsigned int irq
,
2412 const struct cpumask
*mask
)
2414 struct irq_desc
*desc
= irq_to_desc(irq
);
2416 return set_ir_ioapic_affinity_irq_desc(desc
, mask
);
2419 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2420 const struct cpumask
*mask
)
2426 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2428 unsigned vector
, me
;
2434 me
= smp_processor_id();
2435 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2438 struct irq_desc
*desc
;
2439 struct irq_cfg
*cfg
;
2440 irq
= __get_cpu_var(vector_irq
)[vector
];
2445 desc
= irq_to_desc(irq
);
2450 spin_lock(&desc
->lock
);
2451 if (!cfg
->move_cleanup_count
)
2454 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2457 irr
= apic_read(APIC_IRR
+ (vector
/ 32 * 0x10));
2459 * Check if the vector that needs to be cleanedup is
2460 * registered at the cpu's IRR. If so, then this is not
2461 * the best time to clean it up. Lets clean it up in the
2462 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2465 if (irr
& (1 << (vector
% 32))) {
2466 apic
->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR
);
2469 __get_cpu_var(vector_irq
)[vector
] = -1;
2470 cfg
->move_cleanup_count
--;
2472 spin_unlock(&desc
->lock
);
2478 static void irq_complete_move(struct irq_desc
**descp
)
2480 struct irq_desc
*desc
= *descp
;
2481 struct irq_cfg
*cfg
= desc
->chip_data
;
2482 unsigned vector
, me
;
2484 if (likely(!cfg
->move_in_progress
))
2487 vector
= ~get_irq_regs()->orig_ax
;
2488 me
= smp_processor_id();
2490 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2491 send_cleanup_vector(cfg
);
2494 static inline void irq_complete_move(struct irq_desc
**descp
) {}
2497 static void ack_apic_edge(unsigned int irq
)
2499 struct irq_desc
*desc
= irq_to_desc(irq
);
2501 irq_complete_move(&desc
);
2502 move_native_irq(irq
);
2506 atomic_t irq_mis_count
;
2508 static void ack_apic_level(unsigned int irq
)
2510 struct irq_desc
*desc
= irq_to_desc(irq
);
2513 struct irq_cfg
*cfg
;
2514 int do_unmask_irq
= 0;
2516 irq_complete_move(&desc
);
2517 #ifdef CONFIG_GENERIC_PENDING_IRQ
2518 /* If we are moving the irq we need to mask it */
2519 if (unlikely(desc
->status
& IRQ_MOVE_PENDING
)) {
2521 mask_IO_APIC_irq_desc(desc
);
2526 * It appears there is an erratum which affects at least version 0x11
2527 * of I/O APIC (that's the 82093AA and cores integrated into various
2528 * chipsets). Under certain conditions a level-triggered interrupt is
2529 * erroneously delivered as edge-triggered one but the respective IRR
2530 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2531 * message but it will never arrive and further interrupts are blocked
2532 * from the source. The exact reason is so far unknown, but the
2533 * phenomenon was observed when two consecutive interrupt requests
2534 * from a given source get delivered to the same CPU and the source is
2535 * temporarily disabled in between.
2537 * A workaround is to simulate an EOI message manually. We achieve it
2538 * by setting the trigger mode to edge and then to level when the edge
2539 * trigger mode gets detected in the TMR of a local APIC for a
2540 * level-triggered interrupt. We mask the source for the time of the
2541 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2542 * The idea is from Manfred Spraul. --macro
2544 cfg
= desc
->chip_data
;
2546 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2549 * We must acknowledge the irq before we move it or the acknowledge will
2550 * not propagate properly.
2554 /* Now we can move and renable the irq */
2555 if (unlikely(do_unmask_irq
)) {
2556 /* Only migrate the irq if the ack has been received.
2558 * On rare occasions the broadcast level triggered ack gets
2559 * delayed going to ioapics, and if we reprogram the
2560 * vector while Remote IRR is still set the irq will never
2563 * To prevent this scenario we read the Remote IRR bit
2564 * of the ioapic. This has two effects.
2565 * - On any sane system the read of the ioapic will
2566 * flush writes (and acks) going to the ioapic from
2568 * - We get to see if the ACK has actually been delivered.
2570 * Based on failed experiments of reprogramming the
2571 * ioapic entry from outside of irq context starting
2572 * with masking the ioapic entry and then polling until
2573 * Remote IRR was clear before reprogramming the
2574 * ioapic I don't trust the Remote IRR bit to be
2575 * completey accurate.
2577 * However there appears to be no other way to plug
2578 * this race, so if the Remote IRR bit is not
2579 * accurate and is causing problems then it is a hardware bug
2580 * and you can go talk to the chipset vendor about it.
2582 cfg
= desc
->chip_data
;
2583 if (!io_apic_level_ack_pending(cfg
))
2584 move_masked_irq(irq
);
2585 unmask_IO_APIC_irq_desc(desc
);
2588 /* Tail end of version 0x11 I/O APIC bug workaround */
2589 if (!(v
& (1 << (i
& 0x1f)))) {
2590 atomic_inc(&irq_mis_count
);
2591 spin_lock(&ioapic_lock
);
2592 __mask_and_edge_IO_APIC_irq(cfg
);
2593 __unmask_and_level_IO_APIC_irq(cfg
);
2594 spin_unlock(&ioapic_lock
);
2598 #ifdef CONFIG_INTR_REMAP
2599 static void __eoi_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
)
2602 struct irq_pin_list
*entry
;
2604 entry
= cfg
->irq_2_pin
;
2612 io_apic_eoi(apic
, pin
);
2613 entry
= entry
->next
;
2618 eoi_ioapic_irq(struct irq_desc
*desc
)
2620 struct irq_cfg
*cfg
;
2621 unsigned long flags
;
2625 cfg
= desc
->chip_data
;
2627 spin_lock_irqsave(&ioapic_lock
, flags
);
2628 __eoi_ioapic_irq(irq
, cfg
);
2629 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2632 static void ir_ack_apic_edge(unsigned int irq
)
2637 static void ir_ack_apic_level(unsigned int irq
)
2639 struct irq_desc
*desc
= irq_to_desc(irq
);
2642 eoi_ioapic_irq(desc
);
2644 #endif /* CONFIG_INTR_REMAP */
2646 static struct irq_chip ioapic_chip __read_mostly
= {
2648 .startup
= startup_ioapic_irq
,
2649 .mask
= mask_IO_APIC_irq
,
2650 .unmask
= unmask_IO_APIC_irq
,
2651 .ack
= ack_apic_edge
,
2652 .eoi
= ack_apic_level
,
2654 .set_affinity
= set_ioapic_affinity_irq
,
2656 .retrigger
= ioapic_retrigger_irq
,
2659 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2660 .name
= "IR-IO-APIC",
2661 .startup
= startup_ioapic_irq
,
2662 .mask
= mask_IO_APIC_irq
,
2663 .unmask
= unmask_IO_APIC_irq
,
2664 #ifdef CONFIG_INTR_REMAP
2665 .ack
= ir_ack_apic_edge
,
2666 .eoi
= ir_ack_apic_level
,
2668 .set_affinity
= set_ir_ioapic_affinity_irq
,
2671 .retrigger
= ioapic_retrigger_irq
,
2674 static inline void init_IO_APIC_traps(void)
2677 struct irq_desc
*desc
;
2678 struct irq_cfg
*cfg
;
2681 * NOTE! The local APIC isn't very good at handling
2682 * multiple interrupts at the same interrupt level.
2683 * As the interrupt level is determined by taking the
2684 * vector number and shifting that right by 4, we
2685 * want to spread these out a bit so that they don't
2686 * all fall in the same interrupt level.
2688 * Also, we've got to be careful not to trash gate
2689 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2691 for_each_irq_desc(irq
, desc
) {
2692 cfg
= desc
->chip_data
;
2693 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2695 * Hmm.. We don't have an entry for this,
2696 * so default to an old-fashioned 8259
2697 * interrupt if we can..
2699 if (irq
< NR_IRQS_LEGACY
)
2700 make_8259A_irq(irq
);
2702 /* Strange. Oh, well.. */
2703 desc
->chip
= &no_irq_chip
;
2709 * The local APIC irq-chip implementation:
2712 static void mask_lapic_irq(unsigned int irq
)
2716 v
= apic_read(APIC_LVT0
);
2717 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2720 static void unmask_lapic_irq(unsigned int irq
)
2724 v
= apic_read(APIC_LVT0
);
2725 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2728 static void ack_lapic_irq(unsigned int irq
)
2733 static struct irq_chip lapic_chip __read_mostly
= {
2734 .name
= "local-APIC",
2735 .mask
= mask_lapic_irq
,
2736 .unmask
= unmask_lapic_irq
,
2737 .ack
= ack_lapic_irq
,
2740 static void lapic_register_intr(int irq
, struct irq_desc
*desc
)
2742 desc
->status
&= ~IRQ_LEVEL
;
2743 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2747 static void __init
setup_nmi(void)
2750 * Dirty trick to enable the NMI watchdog ...
2751 * We put the 8259A master into AEOI mode and
2752 * unmask on all local APICs LVT0 as NMI.
2754 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2755 * is from Maciej W. Rozycki - so we do not have to EOI from
2756 * the NMI handler or the timer interrupt.
2758 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2760 enable_NMI_through_LVT0();
2762 apic_printk(APIC_VERBOSE
, " done.\n");
2766 * This looks a bit hackish but it's about the only one way of sending
2767 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2768 * not support the ExtINT mode, unfortunately. We need to send these
2769 * cycles as some i82489DX-based boards have glue logic that keeps the
2770 * 8259A interrupt line asserted until INTA. --macro
2772 static inline void __init
unlock_ExtINT_logic(void)
2775 struct IO_APIC_route_entry entry0
, entry1
;
2776 unsigned char save_control
, save_freq_select
;
2778 pin
= find_isa_irq_pin(8, mp_INT
);
2783 apic
= find_isa_irq_apic(8, mp_INT
);
2789 entry0
= ioapic_read_entry(apic
, pin
);
2790 clear_IO_APIC_pin(apic
, pin
);
2792 memset(&entry1
, 0, sizeof(entry1
));
2794 entry1
.dest_mode
= 0; /* physical delivery */
2795 entry1
.mask
= 0; /* unmask IRQ now */
2796 entry1
.dest
= hard_smp_processor_id();
2797 entry1
.delivery_mode
= dest_ExtINT
;
2798 entry1
.polarity
= entry0
.polarity
;
2802 ioapic_write_entry(apic
, pin
, entry1
);
2804 save_control
= CMOS_READ(RTC_CONTROL
);
2805 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2806 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2808 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2813 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2817 CMOS_WRITE(save_control
, RTC_CONTROL
);
2818 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2819 clear_IO_APIC_pin(apic
, pin
);
2821 ioapic_write_entry(apic
, pin
, entry0
);
2824 static int disable_timer_pin_1 __initdata
;
2825 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2826 static int __init
disable_timer_pin_setup(char *arg
)
2828 disable_timer_pin_1
= 1;
2831 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2833 int timer_through_8259 __initdata
;
2836 * This code may look a bit paranoid, but it's supposed to cooperate with
2837 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2838 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2839 * fanatically on his truly buggy board.
2841 * FIXME: really need to revamp this for all platforms.
2843 static inline void __init
check_timer(void)
2845 struct irq_desc
*desc
= irq_to_desc(0);
2846 struct irq_cfg
*cfg
= desc
->chip_data
;
2847 int node
= cpu_to_node(boot_cpu_id
);
2848 int apic1
, pin1
, apic2
, pin2
;
2849 unsigned long flags
;
2852 local_irq_save(flags
);
2855 * get/set the timer IRQ vector:
2857 disable_8259A_irq(0);
2858 assign_irq_vector(0, cfg
, apic
->target_cpus());
2861 * As IRQ0 is to be enabled in the 8259A, the virtual
2862 * wire has to be disabled in the local APIC. Also
2863 * timer interrupts need to be acknowledged manually in
2864 * the 8259A for the i82489DX when using the NMI
2865 * watchdog as that APIC treats NMIs as level-triggered.
2866 * The AEOI mode will finish them in the 8259A
2869 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2871 #ifdef CONFIG_X86_32
2875 ver
= apic_read(APIC_LVR
);
2876 ver
= GET_APIC_VERSION(ver
);
2877 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2881 pin1
= find_isa_irq_pin(0, mp_INT
);
2882 apic1
= find_isa_irq_apic(0, mp_INT
);
2883 pin2
= ioapic_i8259
.pin
;
2884 apic2
= ioapic_i8259
.apic
;
2886 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2887 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2888 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2891 * Some BIOS writers are clueless and report the ExtINTA
2892 * I/O APIC input from the cascaded 8259A as the timer
2893 * interrupt input. So just in case, if only one pin
2894 * was found above, try it both directly and through the
2898 if (intr_remapping_enabled
)
2899 panic("BIOS bug: timer not connected to IO-APIC");
2903 } else if (pin2
== -1) {
2910 * Ok, does IRQ0 through the IOAPIC work?
2913 add_pin_to_irq_node(cfg
, node
, apic1
, pin1
);
2914 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2916 /* for edge trigger, setup_IO_APIC_irq already
2917 * leave it unmasked.
2918 * so only need to unmask if it is level-trigger
2919 * do we really have level trigger timer?
2922 idx
= find_irq_entry(apic1
, pin1
, mp_INT
);
2923 if (idx
!= -1 && irq_trigger(idx
))
2924 unmask_IO_APIC_irq_desc(desc
);
2926 if (timer_irq_works()) {
2927 if (nmi_watchdog
== NMI_IO_APIC
) {
2929 enable_8259A_irq(0);
2931 if (disable_timer_pin_1
> 0)
2932 clear_IO_APIC_pin(0, pin1
);
2935 if (intr_remapping_enabled
)
2936 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2937 local_irq_disable();
2938 clear_IO_APIC_pin(apic1
, pin1
);
2940 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2941 "8254 timer not connected to IO-APIC\n");
2943 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2944 "(IRQ0) through the 8259A ...\n");
2945 apic_printk(APIC_QUIET
, KERN_INFO
2946 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2948 * legacy devices should be connected to IO APIC #0
2950 replace_pin_at_irq_node(cfg
, node
, apic1
, pin1
, apic2
, pin2
);
2951 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2952 enable_8259A_irq(0);
2953 if (timer_irq_works()) {
2954 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2955 timer_through_8259
= 1;
2956 if (nmi_watchdog
== NMI_IO_APIC
) {
2957 disable_8259A_irq(0);
2959 enable_8259A_irq(0);
2964 * Cleanup, just in case ...
2966 local_irq_disable();
2967 disable_8259A_irq(0);
2968 clear_IO_APIC_pin(apic2
, pin2
);
2969 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2972 if (nmi_watchdog
== NMI_IO_APIC
) {
2973 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2974 "through the IO-APIC - disabling NMI Watchdog!\n");
2975 nmi_watchdog
= NMI_NONE
;
2977 #ifdef CONFIG_X86_32
2981 apic_printk(APIC_QUIET
, KERN_INFO
2982 "...trying to set up timer as Virtual Wire IRQ...\n");
2984 lapic_register_intr(0, desc
);
2985 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2986 enable_8259A_irq(0);
2988 if (timer_irq_works()) {
2989 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2992 local_irq_disable();
2993 disable_8259A_irq(0);
2994 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2995 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2997 apic_printk(APIC_QUIET
, KERN_INFO
2998 "...trying to set up timer as ExtINT IRQ...\n");
3002 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
3004 unlock_ExtINT_logic();
3006 if (timer_irq_works()) {
3007 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3010 local_irq_disable();
3011 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
3012 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3013 "report. Then try booting with the 'noapic' option.\n");
3015 local_irq_restore(flags
);
3019 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3020 * to devices. However there may be an I/O APIC pin available for
3021 * this interrupt regardless. The pin may be left unconnected, but
3022 * typically it will be reused as an ExtINT cascade interrupt for
3023 * the master 8259A. In the MPS case such a pin will normally be
3024 * reported as an ExtINT interrupt in the MP table. With ACPI
3025 * there is no provision for ExtINT interrupts, and in the absence
3026 * of an override it would be treated as an ordinary ISA I/O APIC
3027 * interrupt, that is edge-triggered and unmasked by default. We
3028 * used to do this, but it caused problems on some systems because
3029 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3030 * the same ExtINT cascade interrupt to drive the local APIC of the
3031 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3032 * the I/O APIC in all cases now. No actual device should request
3033 * it anyway. --macro
3035 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3037 void __init
setup_IO_APIC(void)
3041 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3044 io_apic_irqs
= ~PIC_IRQS
;
3046 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
3048 * Set up IO-APIC IRQ routing.
3050 #ifdef CONFIG_X86_32
3052 setup_ioapic_ids_from_mpc();
3055 setup_IO_APIC_irqs();
3056 init_IO_APIC_traps();
3061 * Called after all the initialization is done. If we didnt find any
3062 * APIC bugs then we can allow the modify fast path
3065 static int __init
io_apic_bug_finalize(void)
3067 if (sis_apic_bug
== -1)
3072 late_initcall(io_apic_bug_finalize
);
3074 struct sysfs_ioapic_data
{
3075 struct sys_device dev
;
3076 struct IO_APIC_route_entry entry
[0];
3078 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
3080 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
3082 struct IO_APIC_route_entry
*entry
;
3083 struct sysfs_ioapic_data
*data
;
3086 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3087 entry
= data
->entry
;
3088 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
3089 *entry
= ioapic_read_entry(dev
->id
, i
);
3094 static int ioapic_resume(struct sys_device
*dev
)
3096 struct IO_APIC_route_entry
*entry
;
3097 struct sysfs_ioapic_data
*data
;
3098 unsigned long flags
;
3099 union IO_APIC_reg_00 reg_00
;
3102 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3103 entry
= data
->entry
;
3105 spin_lock_irqsave(&ioapic_lock
, flags
);
3106 reg_00
.raw
= io_apic_read(dev
->id
, 0);
3107 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].apicid
) {
3108 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].apicid
;
3109 io_apic_write(dev
->id
, 0, reg_00
.raw
);
3111 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3112 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
3113 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
3118 static struct sysdev_class ioapic_sysdev_class
= {
3120 .suspend
= ioapic_suspend
,
3121 .resume
= ioapic_resume
,
3124 static int __init
ioapic_init_sysfs(void)
3126 struct sys_device
* dev
;
3129 error
= sysdev_class_register(&ioapic_sysdev_class
);
3133 for (i
= 0; i
< nr_ioapics
; i
++ ) {
3134 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
3135 * sizeof(struct IO_APIC_route_entry
);
3136 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
3137 if (!mp_ioapic_data
[i
]) {
3138 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3141 dev
= &mp_ioapic_data
[i
]->dev
;
3143 dev
->cls
= &ioapic_sysdev_class
;
3144 error
= sysdev_register(dev
);
3146 kfree(mp_ioapic_data
[i
]);
3147 mp_ioapic_data
[i
] = NULL
;
3148 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3156 device_initcall(ioapic_init_sysfs
);
3158 static int nr_irqs_gsi
= NR_IRQS_LEGACY
;
3160 * Dynamic irq allocate and deallocation
3162 unsigned int create_irq_nr(unsigned int irq_want
, int node
)
3164 /* Allocate an unused irq */
3167 unsigned long flags
;
3168 struct irq_cfg
*cfg_new
= NULL
;
3169 struct irq_desc
*desc_new
= NULL
;
3172 if (irq_want
< nr_irqs_gsi
)
3173 irq_want
= nr_irqs_gsi
;
3175 spin_lock_irqsave(&vector_lock
, flags
);
3176 for (new = irq_want
; new < nr_irqs
; new++) {
3177 desc_new
= irq_to_desc_alloc_node(new, node
);
3179 printk(KERN_INFO
"can not get irq_desc for %d\n", new);
3182 cfg_new
= desc_new
->chip_data
;
3184 if (cfg_new
->vector
!= 0)
3187 desc_new
= move_irq_desc(desc_new
, node
);
3189 if (__assign_irq_vector(new, cfg_new
, apic
->target_cpus()) == 0)
3193 spin_unlock_irqrestore(&vector_lock
, flags
);
3196 dynamic_irq_init(irq
);
3197 /* restore it, in case dynamic_irq_init clear it */
3199 desc_new
->chip_data
= cfg_new
;
3204 int create_irq(void)
3206 int node
= cpu_to_node(boot_cpu_id
);
3207 unsigned int irq_want
;
3210 irq_want
= nr_irqs_gsi
;
3211 irq
= create_irq_nr(irq_want
, node
);
3219 void destroy_irq(unsigned int irq
)
3221 unsigned long flags
;
3222 struct irq_cfg
*cfg
;
3223 struct irq_desc
*desc
;
3225 /* store it, in case dynamic_irq_cleanup clear it */
3226 desc
= irq_to_desc(irq
);
3227 cfg
= desc
->chip_data
;
3228 dynamic_irq_cleanup(irq
);
3229 /* connect back irq_cfg */
3231 desc
->chip_data
= cfg
;
3234 spin_lock_irqsave(&vector_lock
, flags
);
3235 __clear_irq_vector(irq
, cfg
);
3236 spin_unlock_irqrestore(&vector_lock
, flags
);
3240 * MSI message composition
3242 #ifdef CONFIG_PCI_MSI
3243 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
3245 struct irq_cfg
*cfg
;
3253 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3257 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
3259 if (irq_remapped(irq
)) {
3264 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3265 BUG_ON(ir_index
== -1);
3267 memset (&irte
, 0, sizeof(irte
));
3270 irte
.dst_mode
= apic
->irq_dest_mode
;
3271 irte
.trigger_mode
= 0; /* edge */
3272 irte
.dlvry_mode
= apic
->irq_delivery_mode
;
3273 irte
.vector
= cfg
->vector
;
3274 irte
.dest_id
= IRTE_DEST(dest
);
3276 /* Set source-id of interrupt request */
3277 set_msi_sid(&irte
, pdev
);
3279 modify_irte(irq
, &irte
);
3281 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3282 msg
->data
= sub_handle
;
3283 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3285 MSI_ADDR_IR_INDEX1(ir_index
) |
3286 MSI_ADDR_IR_INDEX2(ir_index
);
3288 if (x2apic_enabled())
3289 msg
->address_hi
= MSI_ADDR_BASE_HI
|
3290 MSI_ADDR_EXT_DEST_ID(dest
);
3292 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3296 ((apic
->irq_dest_mode
== 0) ?
3297 MSI_ADDR_DEST_MODE_PHYSICAL
:
3298 MSI_ADDR_DEST_MODE_LOGICAL
) |
3299 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3300 MSI_ADDR_REDIRECTION_CPU
:
3301 MSI_ADDR_REDIRECTION_LOWPRI
) |
3302 MSI_ADDR_DEST_ID(dest
);
3305 MSI_DATA_TRIGGER_EDGE
|
3306 MSI_DATA_LEVEL_ASSERT
|
3307 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3308 MSI_DATA_DELIVERY_FIXED
:
3309 MSI_DATA_DELIVERY_LOWPRI
) |
3310 MSI_DATA_VECTOR(cfg
->vector
);
3316 static int set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3318 struct irq_desc
*desc
= irq_to_desc(irq
);
3319 struct irq_cfg
*cfg
;
3323 dest
= set_desc_affinity(desc
, mask
);
3324 if (dest
== BAD_APICID
)
3327 cfg
= desc
->chip_data
;
3329 read_msi_msg_desc(desc
, &msg
);
3331 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3332 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3333 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3334 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3336 write_msi_msg_desc(desc
, &msg
);
3340 #ifdef CONFIG_INTR_REMAP
3342 * Migrate the MSI irq to another cpumask. This migration is
3343 * done in the process context using interrupt-remapping hardware.
3346 ir_set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3348 struct irq_desc
*desc
= irq_to_desc(irq
);
3349 struct irq_cfg
*cfg
= desc
->chip_data
;
3353 if (get_irte(irq
, &irte
))
3356 dest
= set_desc_affinity(desc
, mask
);
3357 if (dest
== BAD_APICID
)
3360 irte
.vector
= cfg
->vector
;
3361 irte
.dest_id
= IRTE_DEST(dest
);
3364 * atomically update the IRTE with the new destination and vector.
3366 modify_irte(irq
, &irte
);
3369 * After this point, all the interrupts will start arriving
3370 * at the new destination. So, time to cleanup the previous
3371 * vector allocation.
3373 if (cfg
->move_in_progress
)
3374 send_cleanup_vector(cfg
);
3380 #endif /* CONFIG_SMP */
3383 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3384 * which implement the MSI or MSI-X Capability Structure.
3386 static struct irq_chip msi_chip
= {
3388 .unmask
= unmask_msi_irq
,
3389 .mask
= mask_msi_irq
,
3390 .ack
= ack_apic_edge
,
3392 .set_affinity
= set_msi_irq_affinity
,
3394 .retrigger
= ioapic_retrigger_irq
,
3397 static struct irq_chip msi_ir_chip
= {
3398 .name
= "IR-PCI-MSI",
3399 .unmask
= unmask_msi_irq
,
3400 .mask
= mask_msi_irq
,
3401 #ifdef CONFIG_INTR_REMAP
3402 .ack
= ir_ack_apic_edge
,
3404 .set_affinity
= ir_set_msi_irq_affinity
,
3407 .retrigger
= ioapic_retrigger_irq
,
3411 * Map the PCI dev to the corresponding remapping hardware unit
3412 * and allocate 'nvec' consecutive interrupt-remapping table entries
3415 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3417 struct intel_iommu
*iommu
;
3420 iommu
= map_dev_to_ir(dev
);
3423 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3427 index
= alloc_irte(iommu
, irq
, nvec
);
3430 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3437 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
, int irq
)
3442 ret
= msi_compose_msg(dev
, irq
, &msg
);
3446 set_irq_msi(irq
, msidesc
);
3447 write_msi_msg(irq
, &msg
);
3449 if (irq_remapped(irq
)) {
3450 struct irq_desc
*desc
= irq_to_desc(irq
);
3452 * irq migration in process context
3454 desc
->status
|= IRQ_MOVE_PCNTXT
;
3455 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
3457 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
3459 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3464 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3467 int ret
, sub_handle
;
3468 struct msi_desc
*msidesc
;
3469 unsigned int irq_want
;
3470 struct intel_iommu
*iommu
= NULL
;
3474 /* x86 doesn't support multiple MSI yet */
3475 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
3478 node
= dev_to_node(&dev
->dev
);
3479 irq_want
= nr_irqs_gsi
;
3481 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3482 irq
= create_irq_nr(irq_want
, node
);
3486 if (!intr_remapping_enabled
)
3491 * allocate the consecutive block of IRTE's
3494 index
= msi_alloc_irte(dev
, irq
, nvec
);
3500 iommu
= map_dev_to_ir(dev
);
3506 * setup the mapping between the irq and the IRTE
3507 * base index, the sub_handle pointing to the
3508 * appropriate interrupt remap table entry.
3510 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3513 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3525 void arch_teardown_msi_irq(unsigned int irq
)
3530 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3532 static int dmar_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3534 struct irq_desc
*desc
= irq_to_desc(irq
);
3535 struct irq_cfg
*cfg
;
3539 dest
= set_desc_affinity(desc
, mask
);
3540 if (dest
== BAD_APICID
)
3543 cfg
= desc
->chip_data
;
3545 dmar_msi_read(irq
, &msg
);
3547 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3548 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3549 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3550 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3552 dmar_msi_write(irq
, &msg
);
3557 #endif /* CONFIG_SMP */
3559 static struct irq_chip dmar_msi_type
= {
3561 .unmask
= dmar_msi_unmask
,
3562 .mask
= dmar_msi_mask
,
3563 .ack
= ack_apic_edge
,
3565 .set_affinity
= dmar_msi_set_affinity
,
3567 .retrigger
= ioapic_retrigger_irq
,
3570 int arch_setup_dmar_msi(unsigned int irq
)
3575 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3578 dmar_msi_write(irq
, &msg
);
3579 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3585 #ifdef CONFIG_HPET_TIMER
3588 static int hpet_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3590 struct irq_desc
*desc
= irq_to_desc(irq
);
3591 struct irq_cfg
*cfg
;
3595 dest
= set_desc_affinity(desc
, mask
);
3596 if (dest
== BAD_APICID
)
3599 cfg
= desc
->chip_data
;
3601 hpet_msi_read(irq
, &msg
);
3603 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3604 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3605 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3606 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3608 hpet_msi_write(irq
, &msg
);
3613 #endif /* CONFIG_SMP */
3615 static struct irq_chip hpet_msi_type
= {
3617 .unmask
= hpet_msi_unmask
,
3618 .mask
= hpet_msi_mask
,
3619 .ack
= ack_apic_edge
,
3621 .set_affinity
= hpet_msi_set_affinity
,
3623 .retrigger
= ioapic_retrigger_irq
,
3626 int arch_setup_hpet_msi(unsigned int irq
)
3630 struct irq_desc
*desc
= irq_to_desc(irq
);
3632 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3636 hpet_msi_write(irq
, &msg
);
3637 desc
->status
|= IRQ_MOVE_PCNTXT
;
3638 set_irq_chip_and_handler_name(irq
, &hpet_msi_type
, handle_edge_irq
,
3645 #endif /* CONFIG_PCI_MSI */
3647 * Hypertransport interrupt support
3649 #ifdef CONFIG_HT_IRQ
3653 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3655 struct ht_irq_msg msg
;
3656 fetch_ht_irq_msg(irq
, &msg
);
3658 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3659 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3661 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3662 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3664 write_ht_irq_msg(irq
, &msg
);
3667 static int set_ht_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3669 struct irq_desc
*desc
= irq_to_desc(irq
);
3670 struct irq_cfg
*cfg
;
3673 dest
= set_desc_affinity(desc
, mask
);
3674 if (dest
== BAD_APICID
)
3677 cfg
= desc
->chip_data
;
3679 target_ht_irq(irq
, dest
, cfg
->vector
);
3686 static struct irq_chip ht_irq_chip
= {
3688 .mask
= mask_ht_irq
,
3689 .unmask
= unmask_ht_irq
,
3690 .ack
= ack_apic_edge
,
3692 .set_affinity
= set_ht_irq_affinity
,
3694 .retrigger
= ioapic_retrigger_irq
,
3697 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3699 struct irq_cfg
*cfg
;
3706 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3708 struct ht_irq_msg msg
;
3711 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
3712 apic
->target_cpus());
3714 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3718 HT_IRQ_LOW_DEST_ID(dest
) |
3719 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3720 ((apic
->irq_dest_mode
== 0) ?
3721 HT_IRQ_LOW_DM_PHYSICAL
:
3722 HT_IRQ_LOW_DM_LOGICAL
) |
3723 HT_IRQ_LOW_RQEOI_EDGE
|
3724 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3725 HT_IRQ_LOW_MT_FIXED
:
3726 HT_IRQ_LOW_MT_ARBITRATED
) |
3727 HT_IRQ_LOW_IRQ_MASKED
;
3729 write_ht_irq_msg(irq
, &msg
);
3731 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3732 handle_edge_irq
, "edge");
3734 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3738 #endif /* CONFIG_HT_IRQ */
3740 #ifdef CONFIG_X86_UV
3742 * Re-target the irq to the specified CPU and enable the specified MMR located
3743 * on the specified blade to allow the sending of MSIs to the specified CPU.
3745 int arch_enable_uv_irq(char *irq_name
, unsigned int irq
, int cpu
, int mmr_blade
,
3746 unsigned long mmr_offset
)
3748 const struct cpumask
*eligible_cpu
= cpumask_of(cpu
);
3749 struct irq_cfg
*cfg
;
3751 unsigned long mmr_value
;
3752 struct uv_IO_APIC_route_entry
*entry
;
3753 unsigned long flags
;
3756 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3760 err
= assign_irq_vector(irq
, cfg
, eligible_cpu
);
3764 spin_lock_irqsave(&vector_lock
, flags
);
3765 set_irq_chip_and_handler_name(irq
, &uv_irq_chip
, handle_percpu_irq
,
3767 spin_unlock_irqrestore(&vector_lock
, flags
);
3770 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3771 entry
->vector
= cfg
->vector
;
3772 entry
->delivery_mode
= apic
->irq_delivery_mode
;
3773 entry
->dest_mode
= apic
->irq_dest_mode
;
3774 entry
->polarity
= 0;
3777 entry
->dest
= apic
->cpu_mask_to_apicid(eligible_cpu
);
3779 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3780 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3786 * Disable the specified MMR located on the specified blade so that MSIs are
3787 * longer allowed to be sent.
3789 void arch_disable_uv_irq(int mmr_blade
, unsigned long mmr_offset
)
3791 unsigned long mmr_value
;
3792 struct uv_IO_APIC_route_entry
*entry
;
3795 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3798 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3801 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3802 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3804 #endif /* CONFIG_X86_64 */
3806 int __init
io_apic_get_redir_entries (int ioapic
)
3808 union IO_APIC_reg_01 reg_01
;
3809 unsigned long flags
;
3811 spin_lock_irqsave(&ioapic_lock
, flags
);
3812 reg_01
.raw
= io_apic_read(ioapic
, 1);
3813 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3815 return reg_01
.bits
.entries
;
3818 void __init
probe_nr_irqs_gsi(void)
3822 nr
= acpi_probe_gsi();
3823 if (nr
> nr_irqs_gsi
) {
3826 /* for acpi=off or acpi is not compiled in */
3830 for (idx
= 0; idx
< nr_ioapics
; idx
++)
3831 nr
+= io_apic_get_redir_entries(idx
) + 1;
3833 if (nr
> nr_irqs_gsi
)
3837 printk(KERN_DEBUG
"nr_irqs_gsi: %d\n", nr_irqs_gsi
);
3840 #ifdef CONFIG_SPARSE_IRQ
3841 int __init
arch_probe_nr_irqs(void)
3845 if (nr_irqs
> (NR_VECTORS
* nr_cpu_ids
))
3846 nr_irqs
= NR_VECTORS
* nr_cpu_ids
;
3848 nr
= nr_irqs_gsi
+ 8 * nr_cpu_ids
;
3849 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3851 * for MSI and HT dyn irq
3853 nr
+= nr_irqs_gsi
* 16;
3862 static int __io_apic_set_pci_routing(struct device
*dev
, int irq
,
3863 struct io_apic_irq_attr
*irq_attr
)
3865 struct irq_desc
*desc
;
3866 struct irq_cfg
*cfg
;
3869 int trigger
, polarity
;
3871 ioapic
= irq_attr
->ioapic
;
3872 if (!IO_APIC_IRQ(irq
)) {
3873 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3879 node
= dev_to_node(dev
);
3881 node
= cpu_to_node(boot_cpu_id
);
3883 desc
= irq_to_desc_alloc_node(irq
, node
);
3885 printk(KERN_INFO
"can not get irq_desc %d\n", irq
);
3889 pin
= irq_attr
->ioapic_pin
;
3890 trigger
= irq_attr
->trigger
;
3891 polarity
= irq_attr
->polarity
;
3894 * IRQs < 16 are already in the irq_2_pin[] map
3896 if (irq
>= NR_IRQS_LEGACY
) {
3897 cfg
= desc
->chip_data
;
3898 add_pin_to_irq_node(cfg
, node
, ioapic
, pin
);
3901 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
, trigger
, polarity
);
3906 int io_apic_set_pci_routing(struct device
*dev
, int irq
,
3907 struct io_apic_irq_attr
*irq_attr
)
3911 * Avoid pin reprogramming. PRTs typically include entries
3912 * with redundant pin->gsi mappings (but unique PCI devices);
3913 * we only program the IOAPIC on the first.
3915 ioapic
= irq_attr
->ioapic
;
3916 pin
= irq_attr
->ioapic_pin
;
3917 if (test_bit(pin
, mp_ioapic_routing
[ioapic
].pin_programmed
)) {
3918 pr_debug("Pin %d-%d already programmed\n",
3919 mp_ioapics
[ioapic
].apicid
, pin
);
3922 set_bit(pin
, mp_ioapic_routing
[ioapic
].pin_programmed
);
3924 return __io_apic_set_pci_routing(dev
, irq
, irq_attr
);
3927 /* --------------------------------------------------------------------------
3928 ACPI-based IOAPIC Configuration
3929 -------------------------------------------------------------------------- */
3933 #ifdef CONFIG_X86_32
3934 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3936 union IO_APIC_reg_00 reg_00
;
3937 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3939 unsigned long flags
;
3943 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3944 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3945 * supports up to 16 on one shared APIC bus.
3947 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3948 * advantage of new APIC bus architecture.
3951 if (physids_empty(apic_id_map
))
3952 apic_id_map
= apic
->ioapic_phys_id_map(phys_cpu_present_map
);
3954 spin_lock_irqsave(&ioapic_lock
, flags
);
3955 reg_00
.raw
= io_apic_read(ioapic
, 0);
3956 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3958 if (apic_id
>= get_physical_broadcast()) {
3959 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3960 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3961 apic_id
= reg_00
.bits
.ID
;
3965 * Every APIC in a system must have a unique ID or we get lots of nice
3966 * 'stuck on smp_invalidate_needed IPI wait' messages.
3968 if (apic
->check_apicid_used(apic_id_map
, apic_id
)) {
3970 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3971 if (!apic
->check_apicid_used(apic_id_map
, i
))
3975 if (i
== get_physical_broadcast())
3976 panic("Max apic_id exceeded!\n");
3978 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3979 "trying %d\n", ioapic
, apic_id
, i
);
3984 tmp
= apic
->apicid_to_cpu_present(apic_id
);
3985 physids_or(apic_id_map
, apic_id_map
, tmp
);
3987 if (reg_00
.bits
.ID
!= apic_id
) {
3988 reg_00
.bits
.ID
= apic_id
;
3990 spin_lock_irqsave(&ioapic_lock
, flags
);
3991 io_apic_write(ioapic
, 0, reg_00
.raw
);
3992 reg_00
.raw
= io_apic_read(ioapic
, 0);
3993 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3996 if (reg_00
.bits
.ID
!= apic_id
) {
3997 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
4002 apic_printk(APIC_VERBOSE
, KERN_INFO
4003 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
4009 int __init
io_apic_get_version(int ioapic
)
4011 union IO_APIC_reg_01 reg_01
;
4012 unsigned long flags
;
4014 spin_lock_irqsave(&ioapic_lock
, flags
);
4015 reg_01
.raw
= io_apic_read(ioapic
, 1);
4016 spin_unlock_irqrestore(&ioapic_lock
, flags
);
4018 return reg_01
.bits
.version
;
4021 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
4025 if (skip_ioapic_setup
)
4028 for (i
= 0; i
< mp_irq_entries
; i
++)
4029 if (mp_irqs
[i
].irqtype
== mp_INT
&&
4030 mp_irqs
[i
].srcbusirq
== bus_irq
)
4032 if (i
>= mp_irq_entries
)
4035 *trigger
= irq_trigger(i
);
4036 *polarity
= irq_polarity(i
);
4040 #endif /* CONFIG_ACPI */
4043 * This function currently is only a helper for the i386 smp boot process where
4044 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4045 * so mask in all cases should simply be apic->target_cpus()
4048 void __init
setup_ioapic_dest(void)
4050 int pin
, ioapic
= 0, irq
, irq_entry
;
4051 struct irq_desc
*desc
;
4052 const struct cpumask
*mask
;
4054 if (skip_ioapic_setup
== 1)
4058 if (!acpi_disabled
&& acpi_ioapic
) {
4059 ioapic
= mp_find_ioapic(0);
4065 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
4066 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
4067 if (irq_entry
== -1)
4069 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
4071 desc
= irq_to_desc(irq
);
4074 * Honour affinities which have been set in early boot
4077 (IRQ_NO_BALANCING
| IRQ_AFFINITY_SET
))
4078 mask
= desc
->affinity
;
4080 mask
= apic
->target_cpus();
4082 if (intr_remapping_enabled
)
4083 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
4085 set_ioapic_affinity_irq_desc(desc
, mask
);
4091 #define IOAPIC_RESOURCE_NAME_SIZE 11
4093 static struct resource
*ioapic_resources
;
4095 static struct resource
* __init
ioapic_setup_resources(void)
4098 struct resource
*res
;
4102 if (nr_ioapics
<= 0)
4105 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
4108 mem
= alloc_bootmem(n
);
4112 mem
+= sizeof(struct resource
) * nr_ioapics
;
4114 for (i
= 0; i
< nr_ioapics
; i
++) {
4116 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
4117 sprintf(mem
, "IOAPIC %u", i
);
4118 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
4122 ioapic_resources
= res
;
4127 void __init
ioapic_init_mappings(void)
4129 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
4130 struct resource
*ioapic_res
;
4133 ioapic_res
= ioapic_setup_resources();
4134 for (i
= 0; i
< nr_ioapics
; i
++) {
4135 if (smp_found_config
) {
4136 ioapic_phys
= mp_ioapics
[i
].apicaddr
;
4137 #ifdef CONFIG_X86_32
4140 "WARNING: bogus zero IO-APIC "
4141 "address found in MPTABLE, "
4142 "disabling IO/APIC support!\n");
4143 smp_found_config
= 0;
4144 skip_ioapic_setup
= 1;
4145 goto fake_ioapic_page
;
4149 #ifdef CONFIG_X86_32
4152 ioapic_phys
= (unsigned long)
4153 alloc_bootmem_pages(PAGE_SIZE
);
4154 ioapic_phys
= __pa(ioapic_phys
);
4156 set_fixmap_nocache(idx
, ioapic_phys
);
4157 apic_printk(APIC_VERBOSE
,
4158 "mapped IOAPIC to %08lx (%08lx)\n",
4159 __fix_to_virt(idx
), ioapic_phys
);
4162 if (ioapic_res
!= NULL
) {
4163 ioapic_res
->start
= ioapic_phys
;
4164 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
4170 static int __init
ioapic_insert_resources(void)
4173 struct resource
*r
= ioapic_resources
;
4176 if (nr_ioapics
> 0) {
4178 "IO APIC resources couldn't be allocated.\n");
4184 for (i
= 0; i
< nr_ioapics
; i
++) {
4185 insert_resource(&iomem_resource
, r
);
4192 /* Insert the IO APIC resources after PCI initialization has occured to handle
4193 * IO APICS that are mapped in on a BAR in PCI space. */
4194 late_initcall(ioapic_insert_resources
);