drivers/staging/fbtft/fb_s6d02a1.c

   1 /*
   2  * FB driver for the S6D02A1 LCD Controller
   3  *
   4  * Based on fb_st7735r.c by Noralf Tronnes
   5  * Init code from UTFT library by Henning Karlsen
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/init.h>
  25
  26 #include "fbtft.h"
  27
  28 #define DRVNAME "fb_s6d02a1"
  29
  30 static int default_init_sequence[] = {
  31
  32         -1, 0xf0, 0x5a, 0x5a,
  33
  34         -1, 0xfc, 0x5a, 0x5a,
  35
  36         -1, 0xfa, 0x02, 0x1f, 0x00, 0x10, 0x22, 0x30, 0x38, 0x3A, 0x3A, 0x3A, 0x3A, 0x3A, 0x3d, 0x02, 0x01,
  37
  38         -1, 0xfb, 0x21, 0x00, 0x02, 0x04, 0x07, 0x0a, 0x0b, 0x0c, 0x0c, 0x16, 0x1e, 0x30, 0x3f, 0x01, 0x02,
  39
  40         /* power setting sequence */
  41         -1, 0xfd, 0x00, 0x00, 0x00, 0x17, 0x10, 0x00, 0x01, 0x01, 0x00, 0x1f, 0x1f,
  42
  43         -1, 0xf4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x07, 0x00, 0x3C, 0x36, 0x00, 0x3C, 0x36, 0x00,
  44
  45         -1, 0xf5, 0x00, 0x70, 0x66, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6d, 0x66, 0x06,
  46
  47         -1, 0xf6, 0x02, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x02, 0x00, 0x06, 0x01, 0x00,
  48
  49         -1, 0xf2, 0x00, 0x01, 0x03, 0x08, 0x08, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x04, 0x08, 0x08,
  50
  51         -1, 0xf8, 0x11,
  52
  53         -1, 0xf7, 0xc8, 0x20, 0x00, 0x00,
  54
  55         -1, 0xf3, 0x00, 0x00,
  56
  57         -1, 0x11,
  58         -2, 50,
  59
  60         -1, 0xf3, 0x00, 0x01,
  61         -2, 50,
  62         -1, 0xf3, 0x00, 0x03,
  63         -2, 50,
  64         -1, 0xf3, 0x00, 0x07,
  65         -2, 50,
  66         -1, 0xf3, 0x00, 0x0f,
  67         -2, 50,
  68
  69         -1, 0xf4, 0x00, 0x04, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x07, 0x00, 0x3C, 0x36, 0x00, 0x3C, 0x36, 0x00,
  70         -2, 50,
  71
  72         -1, 0xf3, 0x00, 0x1f,
  73         -2, 50,
  74         -1, 0xf3, 0x00, 0x7f,
  75         -2, 50,
  76
  77         -1, 0xf3, 0x00, 0xff,
  78         -2, 50,
  79
  80         -1, 0xfd, 0x00, 0x00, 0x00, 0x17, 0x10, 0x00, 0x00, 0x01, 0x00, 0x16, 0x16,
  81
  82         -1, 0xf4, 0x00, 0x09, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x07, 0x00, 0x3C, 0x36, 0x00, 0x3C, 0x36, 0x00,
  83
  84         /* initializing sequence */
  85
  86         -1, 0x36, 0x08,
  87
  88         -1, 0x35, 0x00,
  89
  90         -1, 0x3a, 0x05,
  91
  92         /* gamma setting sequence */
  93         -1, 0x26, 0x01, /* preset gamma curves, possible values 0x01, 0x02, 0x04, 0x08 */
  94
  95         -2, 150,
  96         -1, 0x29,
  97         -1, 0x2c,
  98         /* end marker */
  99         -3
 100
 101 };
 102
 103 static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
 104 {
 105         fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
 106                 "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
 107
 108         /* Column address */
 109         write_reg(par, 0x2A, xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF);
 110
 111         /* Row adress */
 112         write_reg(par, 0x2B, ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF);
 113
 114         /* Memory write */
 115         write_reg(par, 0x2C);
 116 }
 117
 118 #define MY (1 << 7)
 119 #define MX (1 << 6)
 120 #define MV (1 << 5)
 121 static int set_var(struct fbtft_par *par)
 122 {
 123         fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
 124
 125         /* MADCTL - Memory data access control
 126              RGB/BGR:
 127                 1. Mode selection pin SRGB
 128                         RGB H/W pin for color filter setting: 0=RGB, 1=BGR
 129                 2. MADCTL RGB bit
 130                         RGB-BGR ORDER color filter panel: 0=RGB, 1=BGR */
 131         switch (par->info->var.rotate) {
 132         case 0:
 133                 write_reg(par, 0x36, MX | MY | (par->bgr << 3));
 134                 break;
 135         case 270:
 136                 write_reg(par, 0x36, MY | MV | (par->bgr << 3));
 137                 break;
 138         case 180:
 139                 write_reg(par, 0x36, (par->bgr << 3));
 140                 break;
 141         case 90:
 142                 write_reg(par, 0x36, MX | MV | (par->bgr << 3));
 143                 break;
 144         }
 145
 146         return 0;
 147 }
 148
 149 static struct fbtft_display display = {
 150         .regwidth = 8,
 151         .width = 128,
 152         .height = 160,
 153         .init_sequence = default_init_sequence,
 154         .fbtftops = {
 155                 .set_addr_win = set_addr_win,
 156                 .set_var = set_var,
 157         },
 158 };
 159 FBTFT_REGISTER_DRIVER(DRVNAME, "samsung,s6d02a1", &display);
 160
 161 MODULE_ALIAS("spi:" DRVNAME);
 162 MODULE_ALIAS("platform:" DRVNAME);
 163 MODULE_ALIAS("spi:s6d02a1");
 164 MODULE_ALIAS("platform:s6d02a1");
 165
 166 MODULE_DESCRIPTION("FB driver for the S6D02A1 LCD Controller");
 167 MODULE_AUTHOR("WOLFGANG BUENING");
 168 MODULE_LICENSE("GPL");