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serial: sh-sci: fix hardware RX trigger level setting
[linux-2.6/btrfs-unstable.git] / drivers / tty / serial / sh-sci.c
blob9a47cc4f16a2798f7c0a084d44621d371a2f59a9
1 /*
2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Copyright (C) 2015 Glider bvba
6 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 *
8 * based off of the old drivers/char/sh-sci.c by:
9 *
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15 * Removed SH7300 support (Jul 2007).
16 *
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details.
20 */
21 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #define SUPPORT_SYSRQ
23 #endif
24
25 #undef DEBUG
26
27 #include <linux/clk.h>
28 #include <linux/console.h>
29 #include <linux/ctype.h>
30 #include <linux/cpufreq.h>
31 #include <linux/delay.h>
32 #include <linux/dmaengine.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/err.h>
35 #include <linux/errno.h>
36 #include <linux/init.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/major.h>
40 #include <linux/module.h>
41 #include <linux/mm.h>
42 #include <linux/of.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
55
56 #ifdef CONFIG_SUPERH
57 #include <asm/sh_bios.h>
58 #endif
59
60 #include "serial_mctrl_gpio.h"
61 #include "sh-sci.h"
62
63 /* Offsets into the sci_port->irqs array */
64 enum {
65 SCIx_ERI_IRQ,
66 SCIx_RXI_IRQ,
67 SCIx_TXI_IRQ,
68 SCIx_BRI_IRQ,
69 SCIx_NR_IRQS,
70
71 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
72 };
73
74 #define SCIx_IRQ_IS_MUXED(port) \
75 ((port)->irqs[SCIx_ERI_IRQ] == \
76 (port)->irqs[SCIx_RXI_IRQ]) || \
77 ((port)->irqs[SCIx_ERI_IRQ] && \
78 ((port)->irqs[SCIx_RXI_IRQ] < 0))
79
80 enum SCI_CLKS {
81 SCI_FCK, /* Functional Clock */
82 SCI_SCK, /* Optional External Clock */
83 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
84 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
85 SCI_NUM_CLKS
86 };
87
88 /* Bit x set means sampling rate x + 1 is supported */
89 #define SCI_SR(x) BIT((x) - 1)
90 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
91
92 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
93 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
94 SCI_SR(19) | SCI_SR(27)
95
96 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
97 #define max_sr(_port) fls((_port)->sampling_rate_mask)
98
99 /* Iterate over all supported sampling rates, from high to low */
100 #define for_each_sr(_sr, _port) \
101 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
102 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
103
104 struct plat_sci_reg {
105 u8 offset, size;
106 };
107
108 struct sci_port_params {
109 const struct plat_sci_reg regs[SCIx_NR_REGS];
110 unsigned int fifosize;
111 unsigned int overrun_reg;
112 unsigned int overrun_mask;
113 unsigned int sampling_rate_mask;
114 unsigned int error_mask;
115 unsigned int error_clear;
116 };
117
118 struct sci_port {
119 struct uart_port port;
120
121 /* Platform configuration */
122 const struct sci_port_params *params;
123 const struct plat_sci_port *cfg;
124 unsigned int sampling_rate_mask;
125 resource_size_t reg_size;
126 struct mctrl_gpios *gpios;
127
128 /* Clocks */
129 struct clk *clks[SCI_NUM_CLKS];
130 unsigned long clk_rates[SCI_NUM_CLKS];
131
132 int irqs[SCIx_NR_IRQS];
133 char *irqstr[SCIx_NR_IRQS];
134
135 struct dma_chan *chan_tx;
136 struct dma_chan *chan_rx;
137
138 #ifdef CONFIG_SERIAL_SH_SCI_DMA
139 dma_cookie_t cookie_tx;
140 dma_cookie_t cookie_rx[2];
141 dma_cookie_t active_rx;
142 dma_addr_t tx_dma_addr;
143 unsigned int tx_dma_len;
144 struct scatterlist sg_rx[2];
145 void *rx_buf[2];
146 size_t buf_len_rx;
147 struct work_struct work_tx;
148 struct timer_list rx_timer;
149 unsigned int rx_timeout;
150 #endif
151 unsigned int rx_frame;
152 int rx_trigger;
153 struct timer_list rx_fifo_timer;
154 int rx_fifo_timeout;
155
156 bool has_rtscts;
157 bool autorts;
158 };
159
160 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
161
162 static struct sci_port sci_ports[SCI_NPORTS];
163 static struct uart_driver sci_uart_driver;
164
165 static inline struct sci_port *
166 to_sci_port(struct uart_port *uart)
167 {
168 return container_of(uart, struct sci_port, port);
169 }
170
171 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
172 /*
173 * Common SCI definitions, dependent on the port's regshift
174 * value.
175 */
176 [SCIx_SCI_REGTYPE] = {
177 .regs = {
178 [SCSMR] = { 0x00, 8 },
179 [SCBRR] = { 0x01, 8 },
180 [SCSCR] = { 0x02, 8 },
181 [SCxTDR] = { 0x03, 8 },
182 [SCxSR] = { 0x04, 8 },
183 [SCxRDR] = { 0x05, 8 },
184 },
185 .fifosize = 1,
186 .overrun_reg = SCxSR,
187 .overrun_mask = SCI_ORER,
188 .sampling_rate_mask = SCI_SR(32),
189 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
190 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
191 },
192
193 /*
194 * Common definitions for legacy IrDA ports.
195 */
196 [SCIx_IRDA_REGTYPE] = {
197 .regs = {
198 [SCSMR] = { 0x00, 8 },
199 [SCBRR] = { 0x02, 8 },
200 [SCSCR] = { 0x04, 8 },
201 [SCxTDR] = { 0x06, 8 },
202 [SCxSR] = { 0x08, 16 },
203 [SCxRDR] = { 0x0a, 8 },
204 [SCFCR] = { 0x0c, 8 },
205 [SCFDR] = { 0x0e, 16 },
206 },
207 .fifosize = 1,
208 .overrun_reg = SCxSR,
209 .overrun_mask = SCI_ORER,
210 .sampling_rate_mask = SCI_SR(32),
211 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
212 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
213 },
214
215 /*
216 * Common SCIFA definitions.
217 */
218 [SCIx_SCIFA_REGTYPE] = {
219 .regs = {
220 [SCSMR] = { 0x00, 16 },
221 [SCBRR] = { 0x04, 8 },
222 [SCSCR] = { 0x08, 16 },
223 [SCxTDR] = { 0x20, 8 },
224 [SCxSR] = { 0x14, 16 },
225 [SCxRDR] = { 0x24, 8 },
226 [SCFCR] = { 0x18, 16 },
227 [SCFDR] = { 0x1c, 16 },
228 [SCPCR] = { 0x30, 16 },
229 [SCPDR] = { 0x34, 16 },
230 },
231 .fifosize = 64,
232 .overrun_reg = SCxSR,
233 .overrun_mask = SCIFA_ORER,
234 .sampling_rate_mask = SCI_SR_SCIFAB,
235 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
236 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
237 },
238
239 /*
240 * Common SCIFB definitions.
241 */
242 [SCIx_SCIFB_REGTYPE] = {
243 .regs = {
244 [SCSMR] = { 0x00, 16 },
245 [SCBRR] = { 0x04, 8 },
246 [SCSCR] = { 0x08, 16 },
247 [SCxTDR] = { 0x40, 8 },
248 [SCxSR] = { 0x14, 16 },
249 [SCxRDR] = { 0x60, 8 },
250 [SCFCR] = { 0x18, 16 },
251 [SCTFDR] = { 0x38, 16 },
252 [SCRFDR] = { 0x3c, 16 },
253 [SCPCR] = { 0x30, 16 },
254 [SCPDR] = { 0x34, 16 },
255 },
256 .fifosize = 256,
257 .overrun_reg = SCxSR,
258 .overrun_mask = SCIFA_ORER,
259 .sampling_rate_mask = SCI_SR_SCIFAB,
260 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
261 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
262 },
263
264 /*
265 * Common SH-2(A) SCIF definitions for ports with FIFO data
266 * count registers.
267 */
268 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
269 .regs = {
270 [SCSMR] = { 0x00, 16 },
271 [SCBRR] = { 0x04, 8 },
272 [SCSCR] = { 0x08, 16 },
273 [SCxTDR] = { 0x0c, 8 },
274 [SCxSR] = { 0x10, 16 },
275 [SCxRDR] = { 0x14, 8 },
276 [SCFCR] = { 0x18, 16 },
277 [SCFDR] = { 0x1c, 16 },
278 [SCSPTR] = { 0x20, 16 },
279 [SCLSR] = { 0x24, 16 },
280 },
281 .fifosize = 16,
282 .overrun_reg = SCLSR,
283 .overrun_mask = SCLSR_ORER,
284 .sampling_rate_mask = SCI_SR(32),
285 .error_mask = SCIF_DEFAULT_ERROR_MASK,
286 .error_clear = SCIF_ERROR_CLEAR,
287 },
288
289 /*
290 * Common SH-3 SCIF definitions.
291 */
292 [SCIx_SH3_SCIF_REGTYPE] = {
293 .regs = {
294 [SCSMR] = { 0x00, 8 },
295 [SCBRR] = { 0x02, 8 },
296 [SCSCR] = { 0x04, 8 },
297 [SCxTDR] = { 0x06, 8 },
298 [SCxSR] = { 0x08, 16 },
299 [SCxRDR] = { 0x0a, 8 },
300 [SCFCR] = { 0x0c, 8 },
301 [SCFDR] = { 0x0e, 16 },
302 },
303 .fifosize = 16,
304 .overrun_reg = SCLSR,
305 .overrun_mask = SCLSR_ORER,
306 .sampling_rate_mask = SCI_SR(32),
307 .error_mask = SCIF_DEFAULT_ERROR_MASK,
308 .error_clear = SCIF_ERROR_CLEAR,
309 },
310
311 /*
312 * Common SH-4(A) SCIF(B) definitions.
313 */
314 [SCIx_SH4_SCIF_REGTYPE] = {
315 .regs = {
316 [SCSMR] = { 0x00, 16 },
317 [SCBRR] = { 0x04, 8 },
318 [SCSCR] = { 0x08, 16 },
319 [SCxTDR] = { 0x0c, 8 },
320 [SCxSR] = { 0x10, 16 },
321 [SCxRDR] = { 0x14, 8 },
322 [SCFCR] = { 0x18, 16 },
323 [SCFDR] = { 0x1c, 16 },
324 [SCSPTR] = { 0x20, 16 },
325 [SCLSR] = { 0x24, 16 },
326 },
327 .fifosize = 16,
328 .overrun_reg = SCLSR,
329 .overrun_mask = SCLSR_ORER,
330 .sampling_rate_mask = SCI_SR(32),
331 .error_mask = SCIF_DEFAULT_ERROR_MASK,
332 .error_clear = SCIF_ERROR_CLEAR,
333 },
334
335 /*
336 * Common SCIF definitions for ports with a Baud Rate Generator for
337 * External Clock (BRG).
338 */
339 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
340 .regs = {
341 [SCSMR] = { 0x00, 16 },
342 [SCBRR] = { 0x04, 8 },
343 [SCSCR] = { 0x08, 16 },
344 [SCxTDR] = { 0x0c, 8 },
345 [SCxSR] = { 0x10, 16 },
346 [SCxRDR] = { 0x14, 8 },
347 [SCFCR] = { 0x18, 16 },
348 [SCFDR] = { 0x1c, 16 },
349 [SCSPTR] = { 0x20, 16 },
350 [SCLSR] = { 0x24, 16 },
351 [SCDL] = { 0x30, 16 },
352 [SCCKS] = { 0x34, 16 },
353 },
354 .fifosize = 16,
355 .overrun_reg = SCLSR,
356 .overrun_mask = SCLSR_ORER,
357 .sampling_rate_mask = SCI_SR(32),
358 .error_mask = SCIF_DEFAULT_ERROR_MASK,
359 .error_clear = SCIF_ERROR_CLEAR,
360 },
361
362 /*
363 * Common HSCIF definitions.
364 */
365 [SCIx_HSCIF_REGTYPE] = {
366 .regs = {
367 [SCSMR] = { 0x00, 16 },
368 [SCBRR] = { 0x04, 8 },
369 [SCSCR] = { 0x08, 16 },
370 [SCxTDR] = { 0x0c, 8 },
371 [SCxSR] = { 0x10, 16 },
372 [SCxRDR] = { 0x14, 8 },
373 [SCFCR] = { 0x18, 16 },
374 [SCFDR] = { 0x1c, 16 },
375 [SCSPTR] = { 0x20, 16 },
376 [SCLSR] = { 0x24, 16 },
377 [HSSRR] = { 0x40, 16 },
378 [SCDL] = { 0x30, 16 },
379 [SCCKS] = { 0x34, 16 },
380 [HSRTRGR] = { 0x54, 16 },
381 [HSTTRGR] = { 0x58, 16 },
382 },
383 .fifosize = 128,
384 .overrun_reg = SCLSR,
385 .overrun_mask = SCLSR_ORER,
386 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
387 .error_mask = SCIF_DEFAULT_ERROR_MASK,
388 .error_clear = SCIF_ERROR_CLEAR,
389 },
390
391 /*
392 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
393 * register.
394 */
395 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
396 .regs = {
397 [SCSMR] = { 0x00, 16 },
398 [SCBRR] = { 0x04, 8 },
399 [SCSCR] = { 0x08, 16 },
400 [SCxTDR] = { 0x0c, 8 },
401 [SCxSR] = { 0x10, 16 },
402 [SCxRDR] = { 0x14, 8 },
403 [SCFCR] = { 0x18, 16 },
404 [SCFDR] = { 0x1c, 16 },
405 [SCLSR] = { 0x24, 16 },
406 },
407 .fifosize = 16,
408 .overrun_reg = SCLSR,
409 .overrun_mask = SCLSR_ORER,
410 .sampling_rate_mask = SCI_SR(32),
411 .error_mask = SCIF_DEFAULT_ERROR_MASK,
412 .error_clear = SCIF_ERROR_CLEAR,
413 },
414
415 /*
416 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
417 * count registers.
418 */
419 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
420 .regs = {
421 [SCSMR] = { 0x00, 16 },
422 [SCBRR] = { 0x04, 8 },
423 [SCSCR] = { 0x08, 16 },
424 [SCxTDR] = { 0x0c, 8 },
425 [SCxSR] = { 0x10, 16 },
426 [SCxRDR] = { 0x14, 8 },
427 [SCFCR] = { 0x18, 16 },
428 [SCFDR] = { 0x1c, 16 },
429 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
430 [SCRFDR] = { 0x20, 16 },
431 [SCSPTR] = { 0x24, 16 },
432 [SCLSR] = { 0x28, 16 },
433 },
434 .fifosize = 16,
435 .overrun_reg = SCLSR,
436 .overrun_mask = SCLSR_ORER,
437 .sampling_rate_mask = SCI_SR(32),
438 .error_mask = SCIF_DEFAULT_ERROR_MASK,
439 .error_clear = SCIF_ERROR_CLEAR,
440 },
441
442 /*
443 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
444 * registers.
445 */
446 [SCIx_SH7705_SCIF_REGTYPE] = {
447 .regs = {
448 [SCSMR] = { 0x00, 16 },
449 [SCBRR] = { 0x04, 8 },
450 [SCSCR] = { 0x08, 16 },
451 [SCxTDR] = { 0x20, 8 },
452 [SCxSR] = { 0x14, 16 },
453 [SCxRDR] = { 0x24, 8 },
454 [SCFCR] = { 0x18, 16 },
455 [SCFDR] = { 0x1c, 16 },
456 },
457 .fifosize = 64,
458 .overrun_reg = SCxSR,
459 .overrun_mask = SCIFA_ORER,
460 .sampling_rate_mask = SCI_SR(16),
461 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
462 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
463 },
464 };
465
466 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
467
468 /*
469 * The "offset" here is rather misleading, in that it refers to an enum
470 * value relative to the port mapping rather than the fixed offset
471 * itself, which needs to be manually retrieved from the platform's
472 * register map for the given port.
473 */
474 static unsigned int sci_serial_in(struct uart_port *p, int offset)
475 {
476 const struct plat_sci_reg *reg = sci_getreg(p, offset);
477
478 if (reg->size == 8)
479 return ioread8(p->membase + (reg->offset << p->regshift));
480 else if (reg->size == 16)
481 return ioread16(p->membase + (reg->offset << p->regshift));
482 else
483 WARN(1, "Invalid register access\n");
484
485 return 0;
486 }
487
488 static void sci_serial_out(struct uart_port *p, int offset, int value)
489 {
490 const struct plat_sci_reg *reg = sci_getreg(p, offset);
491
492 if (reg->size == 8)
493 iowrite8(value, p->membase + (reg->offset << p->regshift));
494 else if (reg->size == 16)
495 iowrite16(value, p->membase + (reg->offset << p->regshift));
496 else
497 WARN(1, "Invalid register access\n");
498 }
499
500 static void sci_port_enable(struct sci_port *sci_port)
501 {
502 unsigned int i;
503
504 if (!sci_port->port.dev)
505 return;
506
507 pm_runtime_get_sync(sci_port->port.dev);
508
509 for (i = 0; i < SCI_NUM_CLKS; i++) {
510 clk_prepare_enable(sci_port->clks[i]);
511 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
512 }
513 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
514 }
515
516 static void sci_port_disable(struct sci_port *sci_port)
517 {
518 unsigned int i;
519
520 if (!sci_port->port.dev)
521 return;
522
523 for (i = SCI_NUM_CLKS; i-- > 0; )
524 clk_disable_unprepare(sci_port->clks[i]);
525
526 pm_runtime_put_sync(sci_port->port.dev);
527 }
528
529 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
530 {
531 /*
532 * Not all ports (such as SCIFA) will support REIE. Rather than
533 * special-casing the port type, we check the port initialization
534 * IRQ enable mask to see whether the IRQ is desired at all. If
535 * it's unset, it's logically inferred that there's no point in
536 * testing for it.
537 */
538 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
539 }
540
541 static void sci_start_tx(struct uart_port *port)
542 {
543 struct sci_port *s = to_sci_port(port);
544 unsigned short ctrl;
545
546 #ifdef CONFIG_SERIAL_SH_SCI_DMA
547 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
548 u16 new, scr = serial_port_in(port, SCSCR);
549 if (s->chan_tx)
550 new = scr | SCSCR_TDRQE;
551 else
552 new = scr & ~SCSCR_TDRQE;
553 if (new != scr)
554 serial_port_out(port, SCSCR, new);
555 }
556
557 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
558 dma_submit_error(s->cookie_tx)) {
559 s->cookie_tx = 0;
560 schedule_work(&s->work_tx);
561 }
562 #endif
563
564 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
565 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
566 ctrl = serial_port_in(port, SCSCR);
567 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
568 }
569 }
570
571 static void sci_stop_tx(struct uart_port *port)
572 {
573 unsigned short ctrl;
574
575 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
576 ctrl = serial_port_in(port, SCSCR);
577
578 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
579 ctrl &= ~SCSCR_TDRQE;
580
581 ctrl &= ~SCSCR_TIE;
582
583 serial_port_out(port, SCSCR, ctrl);
584 }
585
586 static void sci_start_rx(struct uart_port *port)
587 {
588 unsigned short ctrl;
589
590 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
591
592 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
593 ctrl &= ~SCSCR_RDRQE;
594
595 serial_port_out(port, SCSCR, ctrl);
596 }
597
598 static void sci_stop_rx(struct uart_port *port)
599 {
600 unsigned short ctrl;
601
602 ctrl = serial_port_in(port, SCSCR);
603
604 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
605 ctrl &= ~SCSCR_RDRQE;
606
607 ctrl &= ~port_rx_irq_mask(port);
608
609 serial_port_out(port, SCSCR, ctrl);
610 }
611
612 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
613 {
614 if (port->type == PORT_SCI) {
615 /* Just store the mask */
616 serial_port_out(port, SCxSR, mask);
617 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
618 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
619 /* Only clear the status bits we want to clear */
620 serial_port_out(port, SCxSR,
621 serial_port_in(port, SCxSR) & mask);
622 } else {
623 /* Store the mask, clear parity/framing errors */
624 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
625 }
626 }
627
628 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
629 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
630
631 #ifdef CONFIG_CONSOLE_POLL
632 static int sci_poll_get_char(struct uart_port *port)
633 {
634 unsigned short status;
635 int c;
636
637 do {
638 status = serial_port_in(port, SCxSR);
639 if (status & SCxSR_ERRORS(port)) {
640 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
641 continue;
642 }
643 break;
644 } while (1);
645
646 if (!(status & SCxSR_RDxF(port)))
647 return NO_POLL_CHAR;
648
649 c = serial_port_in(port, SCxRDR);
650
651 /* Dummy read */
652 serial_port_in(port, SCxSR);
653 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
654
655 return c;
656 }
657 #endif
658
659 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
660 {
661 unsigned short status;
662
663 do {
664 status = serial_port_in(port, SCxSR);
665 } while (!(status & SCxSR_TDxE(port)));
666
667 serial_port_out(port, SCxTDR, c);
668 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
669 }
670 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
671 CONFIG_SERIAL_SH_SCI_EARLYCON */
672
673 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
674 {
675 struct sci_port *s = to_sci_port(port);
676
677 /*
678 * Use port-specific handler if provided.
679 */
680 if (s->cfg->ops && s->cfg->ops->init_pins) {
681 s->cfg->ops->init_pins(port, cflag);
682 return;
683 }
684
685 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
686 u16 ctrl = serial_port_in(port, SCPCR);
687
688 /* Enable RXD and TXD pin functions */
689 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
690 if (to_sci_port(port)->has_rtscts) {
691 /* RTS# is output, driven 1 */
692 ctrl |= SCPCR_RTSC;
693 serial_port_out(port, SCPDR,
694 serial_port_in(port, SCPDR) | SCPDR_RTSD);
695 /* Enable CTS# pin function */
696 ctrl &= ~SCPCR_CTSC;
697 }
698 serial_port_out(port, SCPCR, ctrl);
699 } else if (sci_getreg(port, SCSPTR)->size) {
700 u16 status = serial_port_in(port, SCSPTR);
701
702 /* RTS# is output, driven 1 */
703 status |= SCSPTR_RTSIO | SCSPTR_RTSDT;
704 /* CTS# and SCK are inputs */
705 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
706 serial_port_out(port, SCSPTR, status);
707 }
708 }
709
710 static int sci_txfill(struct uart_port *port)
711 {
712 struct sci_port *s = to_sci_port(port);
713 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
714 const struct plat_sci_reg *reg;
715
716 reg = sci_getreg(port, SCTFDR);
717 if (reg->size)
718 return serial_port_in(port, SCTFDR) & fifo_mask;
719
720 reg = sci_getreg(port, SCFDR);
721 if (reg->size)
722 return serial_port_in(port, SCFDR) >> 8;
723
724 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
725 }
726
727 static int sci_txroom(struct uart_port *port)
728 {
729 return port->fifosize - sci_txfill(port);
730 }
731
732 static int sci_rxfill(struct uart_port *port)
733 {
734 struct sci_port *s = to_sci_port(port);
735 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
736 const struct plat_sci_reg *reg;
737
738 reg = sci_getreg(port, SCRFDR);
739 if (reg->size)
740 return serial_port_in(port, SCRFDR) & fifo_mask;
741
742 reg = sci_getreg(port, SCFDR);
743 if (reg->size)
744 return serial_port_in(port, SCFDR) & fifo_mask;
745
746 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
747 }
748
749 /* ********************************************************************** *
750 * the interrupt related routines *
751 * ********************************************************************** */
752
753 static void sci_transmit_chars(struct uart_port *port)
754 {
755 struct circ_buf *xmit = &port->state->xmit;
756 unsigned int stopped = uart_tx_stopped(port);
757 unsigned short status;
758 unsigned short ctrl;
759 int count;
760
761 status = serial_port_in(port, SCxSR);
762 if (!(status & SCxSR_TDxE(port))) {
763 ctrl = serial_port_in(port, SCSCR);
764 if (uart_circ_empty(xmit))
765 ctrl &= ~SCSCR_TIE;
766 else
767 ctrl |= SCSCR_TIE;
768 serial_port_out(port, SCSCR, ctrl);
769 return;
770 }
771
772 count = sci_txroom(port);
773
774 do {
775 unsigned char c;
776
777 if (port->x_char) {
778 c = port->x_char;
779 port->x_char = 0;
780 } else if (!uart_circ_empty(xmit) && !stopped) {
781 c = xmit->buf[xmit->tail];
782 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
783 } else {
784 break;
785 }
786
787 serial_port_out(port, SCxTDR, c);
788
789 port->icount.tx++;
790 } while (--count > 0);
791
792 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
793
794 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
795 uart_write_wakeup(port);
796 if (uart_circ_empty(xmit)) {
797 sci_stop_tx(port);
798 } else {
799 ctrl = serial_port_in(port, SCSCR);
800
801 if (port->type != PORT_SCI) {
802 serial_port_in(port, SCxSR); /* Dummy read */
803 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
804 }
805
806 ctrl |= SCSCR_TIE;
807 serial_port_out(port, SCSCR, ctrl);
808 }
809 }
810
811 /* On SH3, SCIF may read end-of-break as a space->mark char */
812 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
813
814 static void sci_receive_chars(struct uart_port *port)
815 {
816 struct tty_port *tport = &port->state->port;
817 int i, count, copied = 0;
818 unsigned short status;
819 unsigned char flag;
820
821 status = serial_port_in(port, SCxSR);
822 if (!(status & SCxSR_RDxF(port)))
823 return;
824
825 while (1) {
826 /* Don't copy more bytes than there is room for in the buffer */
827 count = tty_buffer_request_room(tport, sci_rxfill(port));
828
829 /* If for any reason we can't copy more data, we're done! */
830 if (count == 0)
831 break;
832
833 if (port->type == PORT_SCI) {
834 char c = serial_port_in(port, SCxRDR);
835 if (uart_handle_sysrq_char(port, c))
836 count = 0;
837 else
838 tty_insert_flip_char(tport, c, TTY_NORMAL);
839 } else {
840 for (i = 0; i < count; i++) {
841 char c = serial_port_in(port, SCxRDR);
842
843 status = serial_port_in(port, SCxSR);
844 if (uart_handle_sysrq_char(port, c)) {
845 count--; i--;
846 continue;
847 }
848
849 /* Store data and status */
850 if (status & SCxSR_FER(port)) {
851 flag = TTY_FRAME;
852 port->icount.frame++;
853 dev_notice(port->dev, "frame error\n");
854 } else if (status & SCxSR_PER(port)) {
855 flag = TTY_PARITY;
856 port->icount.parity++;
857 dev_notice(port->dev, "parity error\n");
858 } else
859 flag = TTY_NORMAL;
860
861 tty_insert_flip_char(tport, c, flag);
862 }
863 }
864
865 serial_port_in(port, SCxSR); /* dummy read */
866 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
867
868 copied += count;
869 port->icount.rx += count;
870 }
871
872 if (copied) {
873 /* Tell the rest of the system the news. New characters! */
874 tty_flip_buffer_push(tport);
875 } else {
876 serial_port_in(port, SCxSR); /* dummy read */
877 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
878 }
879 }
880
881 static int sci_handle_errors(struct uart_port *port)
882 {
883 int copied = 0;
884 unsigned short status = serial_port_in(port, SCxSR);
885 struct tty_port *tport = &port->state->port;
886 struct sci_port *s = to_sci_port(port);
887
888 /* Handle overruns */
889 if (status & s->params->overrun_mask) {
890 port->icount.overrun++;
891
892 /* overrun error */
893 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
894 copied++;
895
896 dev_notice(port->dev, "overrun error\n");
897 }
898
899 if (status & SCxSR_FER(port)) {
900 /* frame error */
901 port->icount.frame++;
902
903 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
904 copied++;
905
906 dev_notice(port->dev, "frame error\n");
907 }
908
909 if (status & SCxSR_PER(port)) {
910 /* parity error */
911 port->icount.parity++;
912
913 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
914 copied++;
915
916 dev_notice(port->dev, "parity error\n");
917 }
918
919 if (copied)
920 tty_flip_buffer_push(tport);
921
922 return copied;
923 }
924
925 static int sci_handle_fifo_overrun(struct uart_port *port)
926 {
927 struct tty_port *tport = &port->state->port;
928 struct sci_port *s = to_sci_port(port);
929 const struct plat_sci_reg *reg;
930 int copied = 0;
931 u16 status;
932
933 reg = sci_getreg(port, s->params->overrun_reg);
934 if (!reg->size)
935 return 0;
936
937 status = serial_port_in(port, s->params->overrun_reg);
938 if (status & s->params->overrun_mask) {
939 status &= ~s->params->overrun_mask;
940 serial_port_out(port, s->params->overrun_reg, status);
941
942 port->icount.overrun++;
943
944 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
945 tty_flip_buffer_push(tport);
946
947 dev_dbg(port->dev, "overrun error\n");
948 copied++;
949 }
950
951 return copied;
952 }
953
954 static int sci_handle_breaks(struct uart_port *port)
955 {
956 int copied = 0;
957 unsigned short status = serial_port_in(port, SCxSR);
958 struct tty_port *tport = &port->state->port;
959
960 if (uart_handle_break(port))
961 return 0;
962
963 if (status & SCxSR_BRK(port)) {
964 port->icount.brk++;
965
966 /* Notify of BREAK */
967 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
968 copied++;
969
970 dev_dbg(port->dev, "BREAK detected\n");
971 }
972
973 if (copied)
974 tty_flip_buffer_push(tport);
975
976 copied += sci_handle_fifo_overrun(port);
977
978 return copied;
979 }
980
981 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
982 {
983 unsigned int bits;
984
985 if (rx_trig < 1)
986 rx_trig = 1;
987 if (rx_trig >= port->fifosize)
988 rx_trig = port->fifosize;
989
990 /* HSCIF can be set to an arbitrary level. */
991 if (sci_getreg(port, HSRTRGR)->size) {
992 serial_port_out(port, HSRTRGR, rx_trig);
993 return rx_trig;
994 }
995
996 switch (port->type) {
997 case PORT_SCIF:
998 if (rx_trig < 4) {
999 bits = 0;
1000 rx_trig = 1;
1001 } else if (rx_trig < 8) {
1002 bits = SCFCR_RTRG0;
1003 rx_trig = 4;
1004 } else if (rx_trig < 14) {
1005 bits = SCFCR_RTRG1;
1006 rx_trig = 8;
1007 } else {
1008 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1009 rx_trig = 14;
1010 }
1011 break;
1012 case PORT_SCIFA:
1013 case PORT_SCIFB:
1014 if (rx_trig < 16) {
1015 bits = 0;
1016 rx_trig = 1;
1017 } else if (rx_trig < 32) {
1018 bits = SCFCR_RTRG0;
1019 rx_trig = 16;
1020 } else if (rx_trig < 48) {
1021 bits = SCFCR_RTRG1;
1022 rx_trig = 32;
1023 } else {
1024 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1025 rx_trig = 48;
1026 }
1027 break;
1028 default:
1029 WARN(1, "unknown FIFO configuration");
1030 return 1;
1031 }
1032
1033 serial_port_out(port, SCFCR,
1034 (serial_port_in(port, SCFCR) &
1035 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1036
1037 return rx_trig;
1038 }
1039
1040 static int scif_rtrg_enabled(struct uart_port *port)
1041 {
1042 if (sci_getreg(port, HSRTRGR)->size)
1043 return serial_port_in(port, HSRTRGR) != 0;
1044 else
1045 return (serial_port_in(port, SCFCR) &
1046 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1047 }
1048
1049 static void rx_fifo_timer_fn(unsigned long arg)
1050 {
1051 struct sci_port *s = (struct sci_port *)arg;
1052 struct uart_port *port = &s->port;
1053
1054 dev_dbg(port->dev, "Rx timed out\n");
1055 scif_set_rtrg(port, 1);
1056 }
1057
1058 static ssize_t rx_trigger_show(struct device *dev,
1059 struct device_attribute *attr,
1060 char *buf)
1061 {
1062 struct uart_port *port = dev_get_drvdata(dev);
1063 struct sci_port *sci = to_sci_port(port);
1064
1065 return sprintf(buf, "%d\n", sci->rx_trigger);
1066 }
1067
1068 static ssize_t rx_trigger_store(struct device *dev,
1069 struct device_attribute *attr,
1070 const char *buf,
1071 size_t count)
1072 {
1073 struct uart_port *port = dev_get_drvdata(dev);
1074 struct sci_port *sci = to_sci_port(port);
1075 long r;
1076
1077 if (kstrtol(buf, 0, &r) == -EINVAL)
1078 return -EINVAL;
1079
1080 sci->rx_trigger = scif_set_rtrg(port, r);
1081 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1082 scif_set_rtrg(port, 1);
1083
1084 return count;
1085 }
1086
1087 static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store);
1088
1089 static ssize_t rx_fifo_timeout_show(struct device *dev,
1090 struct device_attribute *attr,
1091 char *buf)
1092 {
1093 struct uart_port *port = dev_get_drvdata(dev);
1094 struct sci_port *sci = to_sci_port(port);
1095
1096 return sprintf(buf, "%d\n", sci->rx_fifo_timeout);
1097 }
1098
1099 static ssize_t rx_fifo_timeout_store(struct device *dev,
1100 struct device_attribute *attr,
1101 const char *buf,
1102 size_t count)
1103 {
1104 struct uart_port *port = dev_get_drvdata(dev);
1105 struct sci_port *sci = to_sci_port(port);
1106 long r;
1107
1108 if (kstrtol(buf, 0, &r) == -EINVAL)
1109 return -EINVAL;
1110 sci->rx_fifo_timeout = r;
1111 scif_set_rtrg(port, 1);
1112 if (r > 0)
1113 setup_timer(&sci->rx_fifo_timer, rx_fifo_timer_fn,
1114 (unsigned long)sci);
1115 return count;
1116 }
1117
1118 static DEVICE_ATTR(rx_fifo_timeout, 0644, rx_fifo_timeout_show, rx_fifo_timeout_store);
1119
1120
1121 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1122 static void sci_dma_tx_complete(void *arg)
1123 {
1124 struct sci_port *s = arg;
1125 struct uart_port *port = &s->port;
1126 struct circ_buf *xmit = &port->state->xmit;
1127 unsigned long flags;
1128
1129 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1130
1131 spin_lock_irqsave(&port->lock, flags);
1132
1133 xmit->tail += s->tx_dma_len;
1134 xmit->tail &= UART_XMIT_SIZE - 1;
1135
1136 port->icount.tx += s->tx_dma_len;
1137
1138 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1139 uart_write_wakeup(port);
1140
1141 if (!uart_circ_empty(xmit)) {
1142 s->cookie_tx = 0;
1143 schedule_work(&s->work_tx);
1144 } else {
1145 s->cookie_tx = -EINVAL;
1146 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1147 u16 ctrl = serial_port_in(port, SCSCR);
1148 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1149 }
1150 }
1151
1152 spin_unlock_irqrestore(&port->lock, flags);
1153 }
1154
1155 /* Locking: called with port lock held */
1156 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1157 {
1158 struct uart_port *port = &s->port;
1159 struct tty_port *tport = &port->state->port;
1160 int copied;
1161
1162 copied = tty_insert_flip_string(tport, buf, count);
1163 if (copied < count)
1164 port->icount.buf_overrun++;
1165
1166 port->icount.rx += copied;
1167
1168 return copied;
1169 }
1170
1171 static int sci_dma_rx_find_active(struct sci_port *s)
1172 {
1173 unsigned int i;
1174
1175 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1176 if (s->active_rx == s->cookie_rx[i])
1177 return i;
1178
1179 return -1;
1180 }
1181
1182 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1183 {
1184 struct dma_chan *chan = s->chan_rx;
1185 struct uart_port *port = &s->port;
1186 unsigned long flags;
1187
1188 spin_lock_irqsave(&port->lock, flags);
1189 s->chan_rx = NULL;
1190 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1191 spin_unlock_irqrestore(&port->lock, flags);
1192 dmaengine_terminate_all(chan);
1193 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1194 sg_dma_address(&s->sg_rx[0]));
1195 dma_release_channel(chan);
1196 if (enable_pio)
1197 sci_start_rx(port);
1198 }
1199
1200 static void sci_dma_rx_complete(void *arg)
1201 {
1202 struct sci_port *s = arg;
1203 struct dma_chan *chan = s->chan_rx;
1204 struct uart_port *port = &s->port;
1205 struct dma_async_tx_descriptor *desc;
1206 unsigned long flags;
1207 int active, count = 0;
1208
1209 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1210 s->active_rx);
1211
1212 spin_lock_irqsave(&port->lock, flags);
1213
1214 active = sci_dma_rx_find_active(s);
1215 if (active >= 0)
1216 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1217
1218 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1219
1220 if (count)
1221 tty_flip_buffer_push(&port->state->port);
1222
1223 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1224 DMA_DEV_TO_MEM,
1225 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1226 if (!desc)
1227 goto fail;
1228
1229 desc->callback = sci_dma_rx_complete;
1230 desc->callback_param = s;
1231 s->cookie_rx[active] = dmaengine_submit(desc);
1232 if (dma_submit_error(s->cookie_rx[active]))
1233 goto fail;
1234
1235 s->active_rx = s->cookie_rx[!active];
1236
1237 dma_async_issue_pending(chan);
1238
1239 spin_unlock_irqrestore(&port->lock, flags);
1240 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1241 __func__, s->cookie_rx[active], active, s->active_rx);
1242 return;
1243
1244 fail:
1245 spin_unlock_irqrestore(&port->lock, flags);
1246 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1247 sci_rx_dma_release(s, true);
1248 }
1249
1250 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1251 {
1252 struct dma_chan *chan = s->chan_tx;
1253 struct uart_port *port = &s->port;
1254 unsigned long flags;
1255
1256 spin_lock_irqsave(&port->lock, flags);
1257 s->chan_tx = NULL;
1258 s->cookie_tx = -EINVAL;
1259 spin_unlock_irqrestore(&port->lock, flags);
1260 dmaengine_terminate_all(chan);
1261 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1262 DMA_TO_DEVICE);
1263 dma_release_channel(chan);
1264 if (enable_pio)
1265 sci_start_tx(port);
1266 }
1267
1268 static void sci_submit_rx(struct sci_port *s)
1269 {
1270 struct dma_chan *chan = s->chan_rx;
1271 int i;
1272
1273 for (i = 0; i < 2; i++) {
1274 struct scatterlist *sg = &s->sg_rx[i];
1275 struct dma_async_tx_descriptor *desc;
1276
1277 desc = dmaengine_prep_slave_sg(chan,
1278 sg, 1, DMA_DEV_TO_MEM,
1279 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1280 if (!desc)
1281 goto fail;
1282
1283 desc->callback = sci_dma_rx_complete;
1284 desc->callback_param = s;
1285 s->cookie_rx[i] = dmaengine_submit(desc);
1286 if (dma_submit_error(s->cookie_rx[i]))
1287 goto fail;
1288
1289 }
1290
1291 s->active_rx = s->cookie_rx[0];
1292
1293 dma_async_issue_pending(chan);
1294 return;
1295
1296 fail:
1297 if (i)
1298 dmaengine_terminate_all(chan);
1299 for (i = 0; i < 2; i++)
1300 s->cookie_rx[i] = -EINVAL;
1301 s->active_rx = -EINVAL;
1302 sci_rx_dma_release(s, true);
1303 }
1304
1305 static void work_fn_tx(struct work_struct *work)
1306 {
1307 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1308 struct dma_async_tx_descriptor *desc;
1309 struct dma_chan *chan = s->chan_tx;
1310 struct uart_port *port = &s->port;
1311 struct circ_buf *xmit = &port->state->xmit;
1312 dma_addr_t buf;
1313
1314 /*
1315 * DMA is idle now.
1316 * Port xmit buffer is already mapped, and it is one page... Just adjust
1317 * offsets and lengths. Since it is a circular buffer, we have to
1318 * transmit till the end, and then the rest. Take the port lock to get a
1319 * consistent xmit buffer state.
1320 */
1321 spin_lock_irq(&port->lock);
1322 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1323 s->tx_dma_len = min_t(unsigned int,
1324 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1325 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1326 spin_unlock_irq(&port->lock);
1327
1328 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1329 DMA_MEM_TO_DEV,
1330 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1331 if (!desc) {
1332 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1333 /* switch to PIO */
1334 sci_tx_dma_release(s, true);
1335 return;
1336 }
1337
1338 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1339 DMA_TO_DEVICE);
1340
1341 spin_lock_irq(&port->lock);
1342 desc->callback = sci_dma_tx_complete;
1343 desc->callback_param = s;
1344 spin_unlock_irq(&port->lock);
1345 s->cookie_tx = dmaengine_submit(desc);
1346 if (dma_submit_error(s->cookie_tx)) {
1347 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1348 /* switch to PIO */
1349 sci_tx_dma_release(s, true);
1350 return;
1351 }
1352
1353 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1354 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1355
1356 dma_async_issue_pending(chan);
1357 }
1358
1359 static void rx_timer_fn(unsigned long arg)
1360 {
1361 struct sci_port *s = (struct sci_port *)arg;
1362 struct dma_chan *chan = s->chan_rx;
1363 struct uart_port *port = &s->port;
1364 struct dma_tx_state state;
1365 enum dma_status status;
1366 unsigned long flags;
1367 unsigned int read;
1368 int active, count;
1369 u16 scr;
1370
1371 dev_dbg(port->dev, "DMA Rx timed out\n");
1372
1373 spin_lock_irqsave(&port->lock, flags);
1374
1375 active = sci_dma_rx_find_active(s);
1376 if (active < 0) {
1377 spin_unlock_irqrestore(&port->lock, flags);
1378 return;
1379 }
1380
1381 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1382 if (status == DMA_COMPLETE) {
1383 spin_unlock_irqrestore(&port->lock, flags);
1384 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1385 s->active_rx, active);
1386
1387 /* Let packet complete handler take care of the packet */
1388 return;
1389 }
1390
1391 dmaengine_pause(chan);
1392
1393 /*
1394 * sometimes DMA transfer doesn't stop even if it is stopped and
1395 * data keeps on coming until transaction is complete so check
1396 * for DMA_COMPLETE again
1397 * Let packet complete handler take care of the packet
1398 */
1399 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1400 if (status == DMA_COMPLETE) {
1401 spin_unlock_irqrestore(&port->lock, flags);
1402 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1403 return;
1404 }
1405
1406 /* Handle incomplete DMA receive */
1407 dmaengine_terminate_all(s->chan_rx);
1408 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1409
1410 if (read) {
1411 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1412 if (count)
1413 tty_flip_buffer_push(&port->state->port);
1414 }
1415
1416 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1417 sci_submit_rx(s);
1418
1419 /* Direct new serial port interrupts back to CPU */
1420 scr = serial_port_in(port, SCSCR);
1421 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1422 scr &= ~SCSCR_RDRQE;
1423 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1424 }
1425 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1426
1427 spin_unlock_irqrestore(&port->lock, flags);
1428 }
1429
1430 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1431 enum dma_transfer_direction dir)
1432 {
1433 struct dma_chan *chan;
1434 struct dma_slave_config cfg;
1435 int ret;
1436
1437 chan = dma_request_slave_channel(port->dev,
1438 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1439 if (!chan) {
1440 dev_warn(port->dev,
1441 "dma_request_slave_channel_compat failed\n");
1442 return NULL;
1443 }
1444
1445 memset(&cfg, 0, sizeof(cfg));
1446 cfg.direction = dir;
1447 if (dir == DMA_MEM_TO_DEV) {
1448 cfg.dst_addr = port->mapbase +
1449 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1450 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1451 } else {
1452 cfg.src_addr = port->mapbase +
1453 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1454 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1455 }
1456
1457 ret = dmaengine_slave_config(chan, &cfg);
1458 if (ret) {
1459 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1460 dma_release_channel(chan);
1461 return NULL;
1462 }
1463
1464 return chan;
1465 }
1466
1467 static void sci_request_dma(struct uart_port *port)
1468 {
1469 struct sci_port *s = to_sci_port(port);
1470 struct dma_chan *chan;
1471
1472 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1473
1474 if (!port->dev->of_node)
1475 return;
1476
1477 s->cookie_tx = -EINVAL;
1478 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1479 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1480 if (chan) {
1481 s->chan_tx = chan;
1482 /* UART circular tx buffer is an aligned page. */
1483 s->tx_dma_addr = dma_map_single(chan->device->dev,
1484 port->state->xmit.buf,
1485 UART_XMIT_SIZE,
1486 DMA_TO_DEVICE);
1487 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1488 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1489 dma_release_channel(chan);
1490 s->chan_tx = NULL;
1491 } else {
1492 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1493 __func__, UART_XMIT_SIZE,
1494 port->state->xmit.buf, &s->tx_dma_addr);
1495 }
1496
1497 INIT_WORK(&s->work_tx, work_fn_tx);
1498 }
1499
1500 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1501 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1502 if (chan) {
1503 unsigned int i;
1504 dma_addr_t dma;
1505 void *buf;
1506
1507 s->chan_rx = chan;
1508
1509 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1510 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1511 &dma, GFP_KERNEL);
1512 if (!buf) {
1513 dev_warn(port->dev,
1514 "Failed to allocate Rx dma buffer, using PIO\n");
1515 dma_release_channel(chan);
1516 s->chan_rx = NULL;
1517 return;
1518 }
1519
1520 for (i = 0; i < 2; i++) {
1521 struct scatterlist *sg = &s->sg_rx[i];
1522
1523 sg_init_table(sg, 1);
1524 s->rx_buf[i] = buf;
1525 sg_dma_address(sg) = dma;
1526 sg_dma_len(sg) = s->buf_len_rx;
1527
1528 buf += s->buf_len_rx;
1529 dma += s->buf_len_rx;
1530 }
1531
1532 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1533
1534 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1535 sci_submit_rx(s);
1536 }
1537 }
1538
1539 static void sci_free_dma(struct uart_port *port)
1540 {
1541 struct sci_port *s = to_sci_port(port);
1542
1543 if (s->chan_tx)
1544 sci_tx_dma_release(s, false);
1545 if (s->chan_rx)
1546 sci_rx_dma_release(s, false);
1547 }
1548 #else
1549 static inline void sci_request_dma(struct uart_port *port)
1550 {
1551 }
1552
1553 static inline void sci_free_dma(struct uart_port *port)
1554 {
1555 }
1556 #endif
1557
1558 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1559 {
1560 struct uart_port *port = ptr;
1561 struct sci_port *s = to_sci_port(port);
1562
1563 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1564 if (s->chan_rx) {
1565 u16 scr = serial_port_in(port, SCSCR);
1566 u16 ssr = serial_port_in(port, SCxSR);
1567
1568 /* Disable future Rx interrupts */
1569 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1570 disable_irq_nosync(irq);
1571 scr |= SCSCR_RDRQE;
1572 } else {
1573 scr &= ~SCSCR_RIE;
1574 sci_submit_rx(s);
1575 }
1576 serial_port_out(port, SCSCR, scr);
1577 /* Clear current interrupt */
1578 serial_port_out(port, SCxSR,
1579 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1580 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1581 jiffies, s->rx_timeout);
1582 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1583
1584 return IRQ_HANDLED;
1585 }
1586 #endif
1587
1588 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1589 if (!scif_rtrg_enabled(port))
1590 scif_set_rtrg(port, s->rx_trigger);
1591
1592 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1593 s->rx_frame * s->rx_fifo_timeout, 1000));
1594 }
1595
1596 /* I think sci_receive_chars has to be called irrespective
1597 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1598 * to be disabled?
1599 */
1600 sci_receive_chars(ptr);
1601
1602 return IRQ_HANDLED;
1603 }
1604
1605 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1606 {
1607 struct uart_port *port = ptr;
1608 unsigned long flags;
1609
1610 spin_lock_irqsave(&port->lock, flags);
1611 sci_transmit_chars(port);
1612 spin_unlock_irqrestore(&port->lock, flags);
1613
1614 return IRQ_HANDLED;
1615 }
1616
1617 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1618 {
1619 struct uart_port *port = ptr;
1620 struct sci_port *s = to_sci_port(port);
1621
1622 /* Handle errors */
1623 if (port->type == PORT_SCI) {
1624 if (sci_handle_errors(port)) {
1625 /* discard character in rx buffer */
1626 serial_port_in(port, SCxSR);
1627 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1628 }
1629 } else {
1630 sci_handle_fifo_overrun(port);
1631 if (!s->chan_rx)
1632 sci_receive_chars(ptr);
1633 }
1634
1635 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1636
1637 /* Kick the transmission */
1638 if (!s->chan_tx)
1639 sci_tx_interrupt(irq, ptr);
1640
1641 return IRQ_HANDLED;
1642 }
1643
1644 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1645 {
1646 struct uart_port *port = ptr;
1647
1648 /* Handle BREAKs */
1649 sci_handle_breaks(port);
1650 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1651
1652 return IRQ_HANDLED;
1653 }
1654
1655 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1656 {
1657 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1658 struct uart_port *port = ptr;
1659 struct sci_port *s = to_sci_port(port);
1660 irqreturn_t ret = IRQ_NONE;
1661
1662 ssr_status = serial_port_in(port, SCxSR);
1663 scr_status = serial_port_in(port, SCSCR);
1664 if (s->params->overrun_reg == SCxSR)
1665 orer_status = ssr_status;
1666 else if (sci_getreg(port, s->params->overrun_reg)->size)
1667 orer_status = serial_port_in(port, s->params->overrun_reg);
1668
1669 err_enabled = scr_status & port_rx_irq_mask(port);
1670
1671 /* Tx Interrupt */
1672 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1673 !s->chan_tx)
1674 ret = sci_tx_interrupt(irq, ptr);
1675
1676 /*
1677 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1678 * DR flags
1679 */
1680 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1681 (scr_status & SCSCR_RIE))
1682 ret = sci_rx_interrupt(irq, ptr);
1683
1684 /* Error Interrupt */
1685 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1686 ret = sci_er_interrupt(irq, ptr);
1687
1688 /* Break Interrupt */
1689 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1690 ret = sci_br_interrupt(irq, ptr);
1691
1692 /* Overrun Interrupt */
1693 if (orer_status & s->params->overrun_mask) {
1694 sci_handle_fifo_overrun(port);
1695 ret = IRQ_HANDLED;
1696 }
1697
1698 return ret;
1699 }
1700
1701 static const struct sci_irq_desc {
1702 const char *desc;
1703 irq_handler_t handler;
1704 } sci_irq_desc[] = {
1705 /*
1706 * Split out handlers, the default case.
1707 */
1708 [SCIx_ERI_IRQ] = {
1709 .desc = "rx err",
1710 .handler = sci_er_interrupt,
1711 },
1712
1713 [SCIx_RXI_IRQ] = {
1714 .desc = "rx full",
1715 .handler = sci_rx_interrupt,
1716 },
1717
1718 [SCIx_TXI_IRQ] = {
1719 .desc = "tx empty",
1720 .handler = sci_tx_interrupt,
1721 },
1722
1723 [SCIx_BRI_IRQ] = {
1724 .desc = "break",
1725 .handler = sci_br_interrupt,
1726 },
1727
1728 /*
1729 * Special muxed handler.
1730 */
1731 [SCIx_MUX_IRQ] = {
1732 .desc = "mux",
1733 .handler = sci_mpxed_interrupt,
1734 },
1735 };
1736
1737 static int sci_request_irq(struct sci_port *port)
1738 {
1739 struct uart_port *up = &port->port;
1740 int i, j, ret = 0;
1741
1742 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1743 const struct sci_irq_desc *desc;
1744 int irq;
1745
1746 if (SCIx_IRQ_IS_MUXED(port)) {
1747 i = SCIx_MUX_IRQ;
1748 irq = up->irq;
1749 } else {
1750 irq = port->irqs[i];
1751
1752 /*
1753 * Certain port types won't support all of the
1754 * available interrupt sources.
1755 */
1756 if (unlikely(irq < 0))
1757 continue;
1758 }
1759
1760 desc = sci_irq_desc + i;
1761 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1762 dev_name(up->dev), desc->desc);
1763 if (!port->irqstr[j]) {
1764 ret = -ENOMEM;
1765 goto out_nomem;
1766 }
1767
1768 ret = request_irq(irq, desc->handler, up->irqflags,
1769 port->irqstr[j], port);
1770 if (unlikely(ret)) {
1771 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1772 goto out_noirq;
1773 }
1774 }
1775
1776 return 0;
1777
1778 out_noirq:
1779 while (--i >= 0)
1780 free_irq(port->irqs[i], port);
1781
1782 out_nomem:
1783 while (--j >= 0)
1784 kfree(port->irqstr[j]);
1785
1786 return ret;
1787 }
1788
1789 static void sci_free_irq(struct sci_port *port)
1790 {
1791 int i;
1792
1793 /*
1794 * Intentionally in reverse order so we iterate over the muxed
1795 * IRQ first.
1796 */
1797 for (i = 0; i < SCIx_NR_IRQS; i++) {
1798 int irq = port->irqs[i];
1799
1800 /*
1801 * Certain port types won't support all of the available
1802 * interrupt sources.
1803 */
1804 if (unlikely(irq < 0))
1805 continue;
1806
1807 free_irq(port->irqs[i], port);
1808 kfree(port->irqstr[i]);
1809
1810 if (SCIx_IRQ_IS_MUXED(port)) {
1811 /* If there's only one IRQ, we're done. */
1812 return;
1813 }
1814 }
1815 }
1816
1817 static unsigned int sci_tx_empty(struct uart_port *port)
1818 {
1819 unsigned short status = serial_port_in(port, SCxSR);
1820 unsigned short in_tx_fifo = sci_txfill(port);
1821
1822 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1823 }
1824
1825 static void sci_set_rts(struct uart_port *port, bool state)
1826 {
1827 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1828 u16 data = serial_port_in(port, SCPDR);
1829
1830 /* Active low */
1831 if (state)
1832 data &= ~SCPDR_RTSD;
1833 else
1834 data |= SCPDR_RTSD;
1835 serial_port_out(port, SCPDR, data);
1836
1837 /* RTS# is output */
1838 serial_port_out(port, SCPCR,
1839 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1840 } else if (sci_getreg(port, SCSPTR)->size) {
1841 u16 ctrl = serial_port_in(port, SCSPTR);
1842
1843 /* Active low */
1844 if (state)
1845 ctrl &= ~SCSPTR_RTSDT;
1846 else
1847 ctrl |= SCSPTR_RTSDT;
1848 serial_port_out(port, SCSPTR, ctrl);
1849 }
1850 }
1851
1852 static bool sci_get_cts(struct uart_port *port)
1853 {
1854 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1855 /* Active low */
1856 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
1857 } else if (sci_getreg(port, SCSPTR)->size) {
1858 /* Active low */
1859 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
1860 }
1861
1862 return true;
1863 }
1864
1865 /*
1866 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1867 * CTS/RTS is supported in hardware by at least one port and controlled
1868 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1869 * handled via the ->init_pins() op, which is a bit of a one-way street,
1870 * lacking any ability to defer pin control -- this will later be
1871 * converted over to the GPIO framework).
1872 *
1873 * Other modes (such as loopback) are supported generically on certain
1874 * port types, but not others. For these it's sufficient to test for the
1875 * existence of the support register and simply ignore the port type.
1876 */
1877 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1878 {
1879 struct sci_port *s = to_sci_port(port);
1880
1881 if (mctrl & TIOCM_LOOP) {
1882 const struct plat_sci_reg *reg;
1883
1884 /*
1885 * Standard loopback mode for SCFCR ports.
1886 */
1887 reg = sci_getreg(port, SCFCR);
1888 if (reg->size)
1889 serial_port_out(port, SCFCR,
1890 serial_port_in(port, SCFCR) |
1891 SCFCR_LOOP);
1892 }
1893
1894 mctrl_gpio_set(s->gpios, mctrl);
1895
1896 if (!s->has_rtscts)
1897 return;
1898
1899 if (!(mctrl & TIOCM_RTS)) {
1900 /* Disable Auto RTS */
1901 serial_port_out(port, SCFCR,
1902 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
1903
1904 /* Clear RTS */
1905 sci_set_rts(port, 0);
1906 } else if (s->autorts) {
1907 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1908 /* Enable RTS# pin function */
1909 serial_port_out(port, SCPCR,
1910 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
1911 }
1912
1913 /* Enable Auto RTS */
1914 serial_port_out(port, SCFCR,
1915 serial_port_in(port, SCFCR) | SCFCR_MCE);
1916 } else {
1917 /* Set RTS */
1918 sci_set_rts(port, 1);
1919 }
1920 }
1921
1922 static unsigned int sci_get_mctrl(struct uart_port *port)
1923 {
1924 struct sci_port *s = to_sci_port(port);
1925 struct mctrl_gpios *gpios = s->gpios;
1926 unsigned int mctrl = 0;
1927
1928 mctrl_gpio_get(gpios, &mctrl);
1929
1930 /*
1931 * CTS/RTS is handled in hardware when supported, while nothing
1932 * else is wired up.
1933 */
1934 if (s->autorts) {
1935 if (sci_get_cts(port))
1936 mctrl |= TIOCM_CTS;
1937 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
1938 mctrl |= TIOCM_CTS;
1939 }
1940 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
1941 mctrl |= TIOCM_DSR;
1942 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
1943 mctrl |= TIOCM_CAR;
1944
1945 return mctrl;
1946 }
1947
1948 static void sci_enable_ms(struct uart_port *port)
1949 {
1950 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
1951 }
1952
1953 static void sci_break_ctl(struct uart_port *port, int break_state)
1954 {
1955 unsigned short scscr, scsptr;
1956
1957 /* check wheter the port has SCSPTR */
1958 if (!sci_getreg(port, SCSPTR)->size) {
1959 /*
1960 * Not supported by hardware. Most parts couple break and rx
1961 * interrupts together, with break detection always enabled.
1962 */
1963 return;
1964 }
1965
1966 scsptr = serial_port_in(port, SCSPTR);
1967 scscr = serial_port_in(port, SCSCR);
1968
1969 if (break_state == -1) {
1970 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1971 scscr &= ~SCSCR_TE;
1972 } else {
1973 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1974 scscr |= SCSCR_TE;
1975 }
1976
1977 serial_port_out(port, SCSPTR, scsptr);
1978 serial_port_out(port, SCSCR, scscr);
1979 }
1980
1981 static int sci_startup(struct uart_port *port)
1982 {
1983 struct sci_port *s = to_sci_port(port);
1984 int ret;
1985
1986 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1987
1988 ret = sci_request_irq(s);
1989 if (unlikely(ret < 0))
1990 return ret;
1991
1992 sci_request_dma(port);
1993
1994 return 0;
1995 }
1996
1997 static void sci_shutdown(struct uart_port *port)
1998 {
1999 struct sci_port *s = to_sci_port(port);
2000 unsigned long flags;
2001 u16 scr;
2002
2003 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2004
2005 s->autorts = false;
2006 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2007
2008 spin_lock_irqsave(&port->lock, flags);
2009 sci_stop_rx(port);
2010 sci_stop_tx(port);
2011 /* Stop RX and TX, disable related interrupts, keep clock source */
2012 scr = serial_port_in(port, SCSCR);
2013 serial_port_out(port, SCSCR, scr & (SCSCR_CKE1 | SCSCR_CKE0));
2014 spin_unlock_irqrestore(&port->lock, flags);
2015
2016 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2017 if (s->chan_rx) {
2018 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2019 port->line);
2020 del_timer_sync(&s->rx_timer);
2021 }
2022 #endif
2023
2024 sci_free_dma(port);
2025 sci_free_irq(s);
2026 }
2027
2028 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2029 unsigned int *srr)
2030 {
2031 unsigned long freq = s->clk_rates[SCI_SCK];
2032 int err, min_err = INT_MAX;
2033 unsigned int sr;
2034
2035 if (s->port.type != PORT_HSCIF)
2036 freq *= 2;
2037
2038 for_each_sr(sr, s) {
2039 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2040 if (abs(err) >= abs(min_err))
2041 continue;
2042
2043 min_err = err;
2044 *srr = sr - 1;
2045
2046 if (!err)
2047 break;
2048 }
2049
2050 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2051 *srr + 1);
2052 return min_err;
2053 }
2054
2055 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2056 unsigned long freq, unsigned int *dlr,
2057 unsigned int *srr)
2058 {
2059 int err, min_err = INT_MAX;
2060 unsigned int sr, dl;
2061
2062 if (s->port.type != PORT_HSCIF)
2063 freq *= 2;
2064
2065 for_each_sr(sr, s) {
2066 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2067 dl = clamp(dl, 1U, 65535U);
2068
2069 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2070 if (abs(err) >= abs(min_err))
2071 continue;
2072
2073 min_err = err;
2074 *dlr = dl;
2075 *srr = sr - 1;
2076
2077 if (!err)
2078 break;
2079 }
2080
2081 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2082 min_err, *dlr, *srr + 1);
2083 return min_err;
2084 }
2085
2086 /* calculate sample rate, BRR, and clock select */
2087 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2088 unsigned int *brr, unsigned int *srr,
2089 unsigned int *cks)
2090 {
2091 unsigned long freq = s->clk_rates[SCI_FCK];
2092 unsigned int sr, br, prediv, scrate, c;
2093 int err, min_err = INT_MAX;
2094
2095 if (s->port.type != PORT_HSCIF)
2096 freq *= 2;
2097
2098 /*
2099 * Find the combination of sample rate and clock select with the
2100 * smallest deviation from the desired baud rate.
2101 * Prefer high sample rates to maximise the receive margin.
2102 *
2103 * M: Receive margin (%)
2104 * N: Ratio of bit rate to clock (N = sampling rate)
2105 * D: Clock duty (D = 0 to 1.0)
2106 * L: Frame length (L = 9 to 12)
2107 * F: Absolute value of clock frequency deviation
2108 *
2109 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2110 * (|D - 0.5| / N * (1 + F))|
2111 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2112 */
2113 for_each_sr(sr, s) {
2114 for (c = 0; c <= 3; c++) {
2115 /* integerized formulas from HSCIF documentation */
2116 prediv = sr * (1 << (2 * c + 1));
2117
2118 /*
2119 * We need to calculate:
2120 *
2121 * br = freq / (prediv * bps) clamped to [1..256]
2122 * err = freq / (br * prediv) - bps
2123 *
2124 * Watch out for overflow when calculating the desired
2125 * sampling clock rate!
2126 */
2127 if (bps > UINT_MAX / prediv)
2128 break;
2129
2130 scrate = prediv * bps;
2131 br = DIV_ROUND_CLOSEST(freq, scrate);
2132 br = clamp(br, 1U, 256U);
2133
2134 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2135 if (abs(err) >= abs(min_err))
2136 continue;
2137
2138 min_err = err;
2139 *brr = br - 1;
2140 *srr = sr - 1;
2141 *cks = c;
2142
2143 if (!err)
2144 goto found;
2145 }
2146 }
2147
2148 found:
2149 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2150 min_err, *brr, *srr + 1, *cks);
2151 return min_err;
2152 }
2153
2154 static void sci_reset(struct uart_port *port)
2155 {
2156 const struct plat_sci_reg *reg;
2157 unsigned int status;
2158 struct sci_port *s = to_sci_port(port);
2159
2160 do {
2161 status = serial_port_in(port, SCxSR);
2162 } while (!(status & SCxSR_TEND(port)));
2163
2164 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
2165
2166 reg = sci_getreg(port, SCFCR);
2167 if (reg->size)
2168 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2169
2170 sci_clear_SCxSR(port,
2171 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2172 SCxSR_BREAK_CLEAR(port));
2173 if (sci_getreg(port, SCLSR)->size) {
2174 status = serial_port_in(port, SCLSR);
2175 status &= ~(SCLSR_TO | SCLSR_ORER);
2176 serial_port_out(port, SCLSR, status);
2177 }
2178
2179 if (s->rx_trigger > 1) {
2180 if (s->rx_fifo_timeout) {
2181 scif_set_rtrg(port, 1);
2182 setup_timer(&s->rx_fifo_timer, rx_fifo_timer_fn,
2183 (unsigned long)s);
2184 } else {
2185 if (port->type == PORT_SCIFA ||
2186 port->type == PORT_SCIFB)
2187 scif_set_rtrg(port, 1);
2188 else
2189 scif_set_rtrg(port, s->rx_trigger);
2190 }
2191 }
2192 }
2193
2194 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2195 struct ktermios *old)
2196 {
2197 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2198 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2199 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2200 struct sci_port *s = to_sci_port(port);
2201 const struct plat_sci_reg *reg;
2202 int min_err = INT_MAX, err;
2203 unsigned long max_freq = 0;
2204 int best_clk = -1;
2205
2206 if ((termios->c_cflag & CSIZE) == CS7)
2207 smr_val |= SCSMR_CHR;
2208 if (termios->c_cflag & PARENB)
2209 smr_val |= SCSMR_PE;
2210 if (termios->c_cflag & PARODD)
2211 smr_val |= SCSMR_PE | SCSMR_ODD;
2212 if (termios->c_cflag & CSTOPB)
2213 smr_val |= SCSMR_STOP;
2214
2215 /*
2216 * earlyprintk comes here early on with port->uartclk set to zero.
2217 * the clock framework is not up and running at this point so here
2218 * we assume that 115200 is the maximum baud rate. please note that
2219 * the baud rate is not programmed during earlyprintk - it is assumed
2220 * that the previous boot loader has enabled required clocks and
2221 * setup the baud rate generator hardware for us already.
2222 */
2223 if (!port->uartclk) {
2224 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2225 goto done;
2226 }
2227
2228 for (i = 0; i < SCI_NUM_CLKS; i++)
2229 max_freq = max(max_freq, s->clk_rates[i]);
2230
2231 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2232 if (!baud)
2233 goto done;
2234
2235 /*
2236 * There can be multiple sources for the sampling clock. Find the one
2237 * that gives us the smallest deviation from the desired baud rate.
2238 */
2239
2240 /* Optional Undivided External Clock */
2241 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2242 port->type != PORT_SCIFB) {
2243 err = sci_sck_calc(s, baud, &srr1);
2244 if (abs(err) < abs(min_err)) {
2245 best_clk = SCI_SCK;
2246 scr_val = SCSCR_CKE1;
2247 sccks = SCCKS_CKS;
2248 min_err = err;
2249 srr = srr1;
2250 if (!err)
2251 goto done;
2252 }
2253 }
2254
2255 /* Optional BRG Frequency Divided External Clock */
2256 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2257 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2258 &srr1);
2259 if (abs(err) < abs(min_err)) {
2260 best_clk = SCI_SCIF_CLK;
2261 scr_val = SCSCR_CKE1;
2262 sccks = 0;
2263 min_err = err;
2264 dl = dl1;
2265 srr = srr1;
2266 if (!err)
2267 goto done;
2268 }
2269 }
2270
2271 /* Optional BRG Frequency Divided Internal Clock */
2272 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2273 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2274 &srr1);
2275 if (abs(err) < abs(min_err)) {
2276 best_clk = SCI_BRG_INT;
2277 scr_val = SCSCR_CKE1;
2278 sccks = SCCKS_XIN;
2279 min_err = err;
2280 dl = dl1;
2281 srr = srr1;
2282 if (!min_err)
2283 goto done;
2284 }
2285 }
2286
2287 /* Divided Functional Clock using standard Bit Rate Register */
2288 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2289 if (abs(err) < abs(min_err)) {
2290 best_clk = SCI_FCK;
2291 scr_val = 0;
2292 min_err = err;
2293 brr = brr1;
2294 srr = srr1;
2295 cks = cks1;
2296 }
2297
2298 done:
2299 if (best_clk >= 0)
2300 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2301 s->clks[best_clk], baud, min_err);
2302
2303 sci_port_enable(s);
2304
2305 /*
2306 * Program the optional External Baud Rate Generator (BRG) first.
2307 * It controls the mux to select (H)SCK or frequency divided clock.
2308 */
2309 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2310 serial_port_out(port, SCDL, dl);
2311 serial_port_out(port, SCCKS, sccks);
2312 }
2313
2314 sci_reset(port);
2315
2316 uart_update_timeout(port, termios->c_cflag, baud);
2317
2318 if (best_clk >= 0) {
2319 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2320 switch (srr + 1) {
2321 case 5: smr_val |= SCSMR_SRC_5; break;
2322 case 7: smr_val |= SCSMR_SRC_7; break;
2323 case 11: smr_val |= SCSMR_SRC_11; break;
2324 case 13: smr_val |= SCSMR_SRC_13; break;
2325 case 16: smr_val |= SCSMR_SRC_16; break;
2326 case 17: smr_val |= SCSMR_SRC_17; break;
2327 case 19: smr_val |= SCSMR_SRC_19; break;
2328 case 27: smr_val |= SCSMR_SRC_27; break;
2329 }
2330 smr_val |= cks;
2331 dev_dbg(port->dev,
2332 "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n",
2333 scr_val, smr_val, brr, sccks, dl, srr);
2334 serial_port_out(port, SCSCR, scr_val);
2335 serial_port_out(port, SCSMR, smr_val);
2336 serial_port_out(port, SCBRR, brr);
2337 if (sci_getreg(port, HSSRR)->size)
2338 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
2339
2340 /* Wait one bit interval */
2341 udelay((1000000 + (baud - 1)) / baud);
2342 } else {
2343 /* Don't touch the bit rate configuration */
2344 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2345 smr_val |= serial_port_in(port, SCSMR) &
2346 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2347 dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
2348 serial_port_out(port, SCSCR, scr_val);
2349 serial_port_out(port, SCSMR, smr_val);
2350 }
2351
2352 sci_init_pins(port, termios->c_cflag);
2353
2354 port->status &= ~UPSTAT_AUTOCTS;
2355 s->autorts = false;
2356 reg = sci_getreg(port, SCFCR);
2357 if (reg->size) {
2358 unsigned short ctrl = serial_port_in(port, SCFCR);
2359
2360 if ((port->flags & UPF_HARD_FLOW) &&
2361 (termios->c_cflag & CRTSCTS)) {
2362 /* There is no CTS interrupt to restart the hardware */
2363 port->status |= UPSTAT_AUTOCTS;
2364 /* MCE is enabled when RTS is raised */
2365 s->autorts = true;
2366 }
2367
2368 /*
2369 * As we've done a sci_reset() above, ensure we don't
2370 * interfere with the FIFOs while toggling MCE. As the
2371 * reset values could still be set, simply mask them out.
2372 */
2373 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2374
2375 serial_port_out(port, SCFCR, ctrl);
2376 }
2377
2378 scr_val |= SCSCR_RE | SCSCR_TE |
2379 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2380 dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
2381 serial_port_out(port, SCSCR, scr_val);
2382 if ((srr + 1 == 5) &&
2383 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2384 /*
2385 * In asynchronous mode, when the sampling rate is 1/5, first
2386 * received data may become invalid on some SCIFA and SCIFB.
2387 * To avoid this problem wait more than 1 serial data time (1
2388 * bit time x serial data number) after setting SCSCR.RE = 1.
2389 */
2390 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2391 }
2392
2393 /*
2394 * Calculate delay for 2 DMA buffers (4 FIFO).
2395 * See serial_core.c::uart_update_timeout().
2396 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2397 * function calculates 1 jiffie for the data plus 5 jiffies for the
2398 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2399 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2400 * value obtained by this formula is too small. Therefore, if the value
2401 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2402 */
2403 /* byte size and parity */
2404 switch (termios->c_cflag & CSIZE) {
2405 case CS5:
2406 bits = 7;
2407 break;
2408 case CS6:
2409 bits = 8;
2410 break;
2411 case CS7:
2412 bits = 9;
2413 break;
2414 default:
2415 bits = 10;
2416 break;
2417 }
2418
2419 if (termios->c_cflag & CSTOPB)
2420 bits++;
2421 if (termios->c_cflag & PARENB)
2422 bits++;
2423
2424 s->rx_frame = (100 * bits * HZ) / (baud / 10);
2425 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2426 s->rx_timeout = DIV_ROUND_UP(s->buf_len_rx * 2 * s->rx_frame, 1000);
2427 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2428 s->rx_timeout * 1000 / HZ, port->timeout);
2429 if (s->rx_timeout < msecs_to_jiffies(20))
2430 s->rx_timeout = msecs_to_jiffies(20);
2431 #endif
2432
2433 if ((termios->c_cflag & CREAD) != 0)
2434 sci_start_rx(port);
2435
2436 sci_port_disable(s);
2437
2438 if (UART_ENABLE_MS(port, termios->c_cflag))
2439 sci_enable_ms(port);
2440 }
2441
2442 static void sci_pm(struct uart_port *port, unsigned int state,
2443 unsigned int oldstate)
2444 {
2445 struct sci_port *sci_port = to_sci_port(port);
2446
2447 switch (state) {
2448 case UART_PM_STATE_OFF:
2449 sci_port_disable(sci_port);
2450 break;
2451 default:
2452 sci_port_enable(sci_port);
2453 break;
2454 }
2455 }
2456
2457 static const char *sci_type(struct uart_port *port)
2458 {
2459 switch (port->type) {
2460 case PORT_IRDA:
2461 return "irda";
2462 case PORT_SCI:
2463 return "sci";
2464 case PORT_SCIF:
2465 return "scif";
2466 case PORT_SCIFA:
2467 return "scifa";
2468 case PORT_SCIFB:
2469 return "scifb";
2470 case PORT_HSCIF:
2471 return "hscif";
2472 }
2473
2474 return NULL;
2475 }
2476
2477 static int sci_remap_port(struct uart_port *port)
2478 {
2479 struct sci_port *sport = to_sci_port(port);
2480
2481 /*
2482 * Nothing to do if there's already an established membase.
2483 */
2484 if (port->membase)
2485 return 0;
2486
2487 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2488 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2489 if (unlikely(!port->membase)) {
2490 dev_err(port->dev, "can't remap port#%d\n", port->line);
2491 return -ENXIO;
2492 }
2493 } else {
2494 /*
2495 * For the simple (and majority of) cases where we don't
2496 * need to do any remapping, just cast the cookie
2497 * directly.
2498 */
2499 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2500 }
2501
2502 return 0;
2503 }
2504
2505 static void sci_release_port(struct uart_port *port)
2506 {
2507 struct sci_port *sport = to_sci_port(port);
2508
2509 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2510 iounmap(port->membase);
2511 port->membase = NULL;
2512 }
2513
2514 release_mem_region(port->mapbase, sport->reg_size);
2515 }
2516
2517 static int sci_request_port(struct uart_port *port)
2518 {
2519 struct resource *res;
2520 struct sci_port *sport = to_sci_port(port);
2521 int ret;
2522
2523 res = request_mem_region(port->mapbase, sport->reg_size,
2524 dev_name(port->dev));
2525 if (unlikely(res == NULL)) {
2526 dev_err(port->dev, "request_mem_region failed.");
2527 return -EBUSY;
2528 }
2529
2530 ret = sci_remap_port(port);
2531 if (unlikely(ret != 0)) {
2532 release_resource(res);
2533 return ret;
2534 }
2535
2536 return 0;
2537 }
2538
2539 static void sci_config_port(struct uart_port *port, int flags)
2540 {
2541 if (flags & UART_CONFIG_TYPE) {
2542 struct sci_port *sport = to_sci_port(port);
2543
2544 port->type = sport->cfg->type;
2545 sci_request_port(port);
2546 }
2547 }
2548
2549 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2550 {
2551 if (ser->baud_base < 2400)
2552 /* No paper tape reader for Mitch.. */
2553 return -EINVAL;
2554
2555 return 0;
2556 }
2557
2558 static const struct uart_ops sci_uart_ops = {
2559 .tx_empty = sci_tx_empty,
2560 .set_mctrl = sci_set_mctrl,
2561 .get_mctrl = sci_get_mctrl,
2562 .start_tx = sci_start_tx,
2563 .stop_tx = sci_stop_tx,
2564 .stop_rx = sci_stop_rx,
2565 .enable_ms = sci_enable_ms,
2566 .break_ctl = sci_break_ctl,
2567 .startup = sci_startup,
2568 .shutdown = sci_shutdown,
2569 .set_termios = sci_set_termios,
2570 .pm = sci_pm,
2571 .type = sci_type,
2572 .release_port = sci_release_port,
2573 .request_port = sci_request_port,
2574 .config_port = sci_config_port,
2575 .verify_port = sci_verify_port,
2576 #ifdef CONFIG_CONSOLE_POLL
2577 .poll_get_char = sci_poll_get_char,
2578 .poll_put_char = sci_poll_put_char,
2579 #endif
2580 };
2581
2582 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2583 {
2584 const char *clk_names[] = {
2585 [SCI_FCK] = "fck",
2586 [SCI_SCK] = "sck",
2587 [SCI_BRG_INT] = "brg_int",
2588 [SCI_SCIF_CLK] = "scif_clk",
2589 };
2590 struct clk *clk;
2591 unsigned int i;
2592
2593 if (sci_port->cfg->type == PORT_HSCIF)
2594 clk_names[SCI_SCK] = "hsck";
2595
2596 for (i = 0; i < SCI_NUM_CLKS; i++) {
2597 clk = devm_clk_get(dev, clk_names[i]);
2598 if (PTR_ERR(clk) == -EPROBE_DEFER)
2599 return -EPROBE_DEFER;
2600
2601 if (IS_ERR(clk) && i == SCI_FCK) {
2602 /*
2603 * "fck" used to be called "sci_ick", and we need to
2604 * maintain DT backward compatibility.
2605 */
2606 clk = devm_clk_get(dev, "sci_ick");
2607 if (PTR_ERR(clk) == -EPROBE_DEFER)
2608 return -EPROBE_DEFER;
2609
2610 if (!IS_ERR(clk))
2611 goto found;
2612
2613 /*
2614 * Not all SH platforms declare a clock lookup entry
2615 * for SCI devices, in which case we need to get the
2616 * global "peripheral_clk" clock.
2617 */
2618 clk = devm_clk_get(dev, "peripheral_clk");
2619 if (!IS_ERR(clk))
2620 goto found;
2621
2622 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2623 PTR_ERR(clk));
2624 return PTR_ERR(clk);
2625 }
2626
2627 found:
2628 if (IS_ERR(clk))
2629 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2630 PTR_ERR(clk));
2631 else
2632 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2633 clk, clk);
2634 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2635 }
2636 return 0;
2637 }
2638
2639 static const struct sci_port_params *
2640 sci_probe_regmap(const struct plat_sci_port *cfg)
2641 {
2642 unsigned int regtype;
2643
2644 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2645 return &sci_port_params[cfg->regtype];
2646
2647 switch (cfg->type) {
2648 case PORT_SCI:
2649 regtype = SCIx_SCI_REGTYPE;
2650 break;
2651 case PORT_IRDA:
2652 regtype = SCIx_IRDA_REGTYPE;
2653 break;
2654 case PORT_SCIFA:
2655 regtype = SCIx_SCIFA_REGTYPE;
2656 break;
2657 case PORT_SCIFB:
2658 regtype = SCIx_SCIFB_REGTYPE;
2659 break;
2660 case PORT_SCIF:
2661 /*
2662 * The SH-4 is a bit of a misnomer here, although that's
2663 * where this particular port layout originated. This
2664 * configuration (or some slight variation thereof)
2665 * remains the dominant model for all SCIFs.
2666 */
2667 regtype = SCIx_SH4_SCIF_REGTYPE;
2668 break;
2669 case PORT_HSCIF:
2670 regtype = SCIx_HSCIF_REGTYPE;
2671 break;
2672 default:
2673 pr_err("Can't probe register map for given port\n");
2674 return NULL;
2675 }
2676
2677 return &sci_port_params[regtype];
2678 }
2679
2680 static int sci_init_single(struct platform_device *dev,
2681 struct sci_port *sci_port, unsigned int index,
2682 const struct plat_sci_port *p, bool early)
2683 {
2684 struct uart_port *port = &sci_port->port;
2685 const struct resource *res;
2686 unsigned int i;
2687 int ret;
2688
2689 sci_port->cfg = p;
2690
2691 port->ops = &sci_uart_ops;
2692 port->iotype = UPIO_MEM;
2693 port->line = index;
2694
2695 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2696 if (res == NULL)
2697 return -ENOMEM;
2698
2699 port->mapbase = res->start;
2700 sci_port->reg_size = resource_size(res);
2701
2702 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2703 sci_port->irqs[i] = platform_get_irq(dev, i);
2704
2705 /* The SCI generates several interrupts. They can be muxed together or
2706 * connected to different interrupt lines. In the muxed case only one
2707 * interrupt resource is specified. In the non-muxed case three or four
2708 * interrupt resources are specified, as the BRI interrupt is optional.
2709 */
2710 if (sci_port->irqs[0] < 0)
2711 return -ENXIO;
2712
2713 if (sci_port->irqs[1] < 0) {
2714 sci_port->irqs[1] = sci_port->irqs[0];
2715 sci_port->irqs[2] = sci_port->irqs[0];
2716 sci_port->irqs[3] = sci_port->irqs[0];
2717 }
2718
2719 sci_port->params = sci_probe_regmap(p);
2720 if (unlikely(sci_port->params == NULL))
2721 return -EINVAL;
2722
2723 switch (p->type) {
2724 case PORT_SCIFB:
2725 sci_port->rx_trigger = 48;
2726 break;
2727 case PORT_HSCIF:
2728 sci_port->rx_trigger = 64;
2729 break;
2730 case PORT_SCIFA:
2731 sci_port->rx_trigger = 32;
2732 break;
2733 case PORT_SCIF:
2734 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2735 /* RX triggering not implemented for this IP */
2736 sci_port->rx_trigger = 1;
2737 else
2738 sci_port->rx_trigger = 8;
2739 break;
2740 default:
2741 sci_port->rx_trigger = 1;
2742 break;
2743 }
2744
2745 sci_port->rx_fifo_timeout = 0;
2746
2747 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2748 * match the SoC datasheet, this should be investigated. Let platform
2749 * data override the sampling rate for now.
2750 */
2751 sci_port->sampling_rate_mask = p->sampling_rate
2752 ? SCI_SR(p->sampling_rate)
2753 : sci_port->params->sampling_rate_mask;
2754
2755 if (!early) {
2756 ret = sci_init_clocks(sci_port, &dev->dev);
2757 if (ret < 0)
2758 return ret;
2759
2760 port->dev = &dev->dev;
2761
2762 pm_runtime_enable(&dev->dev);
2763 }
2764
2765 port->type = p->type;
2766 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2767 port->fifosize = sci_port->params->fifosize;
2768
2769 if (port->type == PORT_SCI) {
2770 if (sci_port->reg_size >= 0x20)
2771 port->regshift = 2;
2772 else
2773 port->regshift = 1;
2774 }
2775
2776 /*
2777 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2778 * for the multi-IRQ ports, which is where we are primarily
2779 * concerned with the shutdown path synchronization.
2780 *
2781 * For the muxed case there's nothing more to do.
2782 */
2783 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2784 port->irqflags = 0;
2785
2786 port->serial_in = sci_serial_in;
2787 port->serial_out = sci_serial_out;
2788
2789 return 0;
2790 }
2791
2792 static void sci_cleanup_single(struct sci_port *port)
2793 {
2794 pm_runtime_disable(port->port.dev);
2795 }
2796
2797 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2798 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2799 static void serial_console_putchar(struct uart_port *port, int ch)
2800 {
2801 sci_poll_put_char(port, ch);
2802 }
2803
2804 /*
2805 * Print a string to the serial port trying not to disturb
2806 * any possible real use of the port...
2807 */
2808 static void serial_console_write(struct console *co, const char *s,
2809 unsigned count)
2810 {
2811 struct sci_port *sci_port = &sci_ports[co->index];
2812 struct uart_port *port = &sci_port->port;
2813 unsigned short bits, ctrl, ctrl_temp;
2814 unsigned long flags;
2815 int locked = 1;
2816
2817 local_irq_save(flags);
2818 #if defined(SUPPORT_SYSRQ)
2819 if (port->sysrq)
2820 locked = 0;
2821 else
2822 #endif
2823 if (oops_in_progress)
2824 locked = spin_trylock(&port->lock);
2825 else
2826 spin_lock(&port->lock);
2827
2828 /* first save SCSCR then disable interrupts, keep clock source */
2829 ctrl = serial_port_in(port, SCSCR);
2830 ctrl_temp = SCSCR_RE | SCSCR_TE |
2831 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2832 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2833 serial_port_out(port, SCSCR, ctrl_temp);
2834
2835 uart_console_write(port, s, count, serial_console_putchar);
2836
2837 /* wait until fifo is empty and last bit has been transmitted */
2838 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2839 while ((serial_port_in(port, SCxSR) & bits) != bits)
2840 cpu_relax();
2841
2842 /* restore the SCSCR */
2843 serial_port_out(port, SCSCR, ctrl);
2844
2845 if (locked)
2846 spin_unlock(&port->lock);
2847 local_irq_restore(flags);
2848 }
2849
2850 static int serial_console_setup(struct console *co, char *options)
2851 {
2852 struct sci_port *sci_port;
2853 struct uart_port *port;
2854 int baud = 115200;
2855 int bits = 8;
2856 int parity = 'n';
2857 int flow = 'n';
2858 int ret;
2859
2860 /*
2861 * Refuse to handle any bogus ports.
2862 */
2863 if (co->index < 0 || co->index >= SCI_NPORTS)
2864 return -ENODEV;
2865
2866 sci_port = &sci_ports[co->index];
2867 port = &sci_port->port;
2868
2869 /*
2870 * Refuse to handle uninitialized ports.
2871 */
2872 if (!port->ops)
2873 return -ENODEV;
2874
2875 ret = sci_remap_port(port);
2876 if (unlikely(ret != 0))
2877 return ret;
2878
2879 if (options)
2880 uart_parse_options(options, &baud, &parity, &bits, &flow);
2881
2882 return uart_set_options(port, co, baud, parity, bits, flow);
2883 }
2884
2885 static struct console serial_console = {
2886 .name = "ttySC",
2887 .device = uart_console_device,
2888 .write = serial_console_write,
2889 .setup = serial_console_setup,
2890 .flags = CON_PRINTBUFFER,
2891 .index = -1,
2892 .data = &sci_uart_driver,
2893 };
2894
2895 static struct console early_serial_console = {
2896 .name = "early_ttySC",
2897 .write = serial_console_write,
2898 .flags = CON_PRINTBUFFER,
2899 .index = -1,
2900 };
2901
2902 static char early_serial_buf[32];
2903
2904 static int sci_probe_earlyprintk(struct platform_device *pdev)
2905 {
2906 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2907
2908 if (early_serial_console.data)
2909 return -EEXIST;
2910
2911 early_serial_console.index = pdev->id;
2912
2913 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2914
2915 serial_console_setup(&early_serial_console, early_serial_buf);
2916
2917 if (!strstr(early_serial_buf, "keep"))
2918 early_serial_console.flags |= CON_BOOT;
2919
2920 register_console(&early_serial_console);
2921 return 0;
2922 }
2923
2924 #define SCI_CONSOLE (&serial_console)
2925
2926 #else
2927 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2928 {
2929 return -EINVAL;
2930 }
2931
2932 #define SCI_CONSOLE NULL
2933
2934 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
2935
2936 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2937
2938 static struct uart_driver sci_uart_driver = {
2939 .owner = THIS_MODULE,
2940 .driver_name = "sci",
2941 .dev_name = "ttySC",
2942 .major = SCI_MAJOR,
2943 .minor = SCI_MINOR_START,
2944 .nr = SCI_NPORTS,
2945 .cons = SCI_CONSOLE,
2946 };
2947
2948 static int sci_remove(struct platform_device *dev)
2949 {
2950 struct sci_port *port = platform_get_drvdata(dev);
2951
2952 uart_remove_one_port(&sci_uart_driver, &port->port);
2953
2954 sci_cleanup_single(port);
2955
2956 if (port->port.fifosize > 1) {
2957 sysfs_remove_file(&dev->dev.kobj,
2958 &dev_attr_rx_fifo_trigger.attr);
2959 }
2960 if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB) {
2961 sysfs_remove_file(&dev->dev.kobj,
2962 &dev_attr_rx_fifo_timeout.attr);
2963 }
2964
2965 return 0;
2966 }
2967
2968
2969 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
2970 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
2971 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
2972
2973 static const struct of_device_id of_sci_match[] = {
2974 /* SoC-specific types */
2975 {
2976 .compatible = "renesas,scif-r7s72100",
2977 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
2978 },
2979 /* Family-specific types */
2980 {
2981 .compatible = "renesas,rcar-gen1-scif",
2982 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2983 }, {
2984 .compatible = "renesas,rcar-gen2-scif",
2985 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2986 }, {
2987 .compatible = "renesas,rcar-gen3-scif",
2988 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2989 },
2990 /* Generic types */
2991 {
2992 .compatible = "renesas,scif",
2993 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
2994 }, {
2995 .compatible = "renesas,scifa",
2996 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
2997 }, {
2998 .compatible = "renesas,scifb",
2999 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3000 }, {
3001 .compatible = "renesas,hscif",
3002 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3003 }, {
3004 .compatible = "renesas,sci",
3005 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3006 }, {
3007 /* Terminator */
3008 },
3009 };
3010 MODULE_DEVICE_TABLE(of, of_sci_match);
3011
3012 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3013 unsigned int *dev_id)
3014 {
3015 struct device_node *np = pdev->dev.of_node;
3016 const struct of_device_id *match;
3017 struct plat_sci_port *p;
3018 struct sci_port *sp;
3019 int id;
3020
3021 if (!IS_ENABLED(CONFIG_OF) || !np)
3022 return NULL;
3023
3024 match = of_match_node(of_sci_match, np);
3025 if (!match)
3026 return NULL;
3027
3028 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3029 if (!p)
3030 return NULL;
3031
3032 /* Get the line number from the aliases node. */
3033 id = of_alias_get_id(np, "serial");
3034 if (id < 0) {
3035 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3036 return NULL;
3037 }
3038
3039 sp = &sci_ports[id];
3040 *dev_id = id;
3041
3042 p->type = SCI_OF_TYPE(match->data);
3043 p->regtype = SCI_OF_REGTYPE(match->data);
3044
3045 if (of_find_property(np, "uart-has-rtscts", NULL))
3046 sp->has_rtscts = true;
3047
3048 return p;
3049 }
3050
3051 static int sci_probe_single(struct platform_device *dev,
3052 unsigned int index,
3053 struct plat_sci_port *p,
3054 struct sci_port *sciport)
3055 {
3056 int ret;
3057
3058 /* Sanity check */
3059 if (unlikely(index >= SCI_NPORTS)) {
3060 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3061 index+1, SCI_NPORTS);
3062 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3063 return -EINVAL;
3064 }
3065
3066 ret = sci_init_single(dev, sciport, index, p, false);
3067 if (ret)
3068 return ret;
3069
3070 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3071 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3072 return PTR_ERR(sciport->gpios);
3073
3074 if (sciport->has_rtscts) {
3075 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3076 UART_GPIO_CTS)) ||
3077 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3078 UART_GPIO_RTS))) {
3079 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3080 return -EINVAL;
3081 }
3082 sciport->port.flags |= UPF_HARD_FLOW;
3083 }
3084
3085 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3086 if (ret) {
3087 sci_cleanup_single(sciport);
3088 return ret;
3089 }
3090
3091 return 0;
3092 }
3093
3094 static int sci_probe(struct platform_device *dev)
3095 {
3096 struct plat_sci_port *p;
3097 struct sci_port *sp;
3098 unsigned int dev_id;
3099 int ret;
3100
3101 /*
3102 * If we've come here via earlyprintk initialization, head off to
3103 * the special early probe. We don't have sufficient device state
3104 * to make it beyond this yet.
3105 */
3106 if (is_early_platform_device(dev))
3107 return sci_probe_earlyprintk(dev);
3108
3109 if (dev->dev.of_node) {
3110 p = sci_parse_dt(dev, &dev_id);
3111 if (p == NULL)
3112 return -EINVAL;
3113 } else {
3114 p = dev->dev.platform_data;
3115 if (p == NULL) {
3116 dev_err(&dev->dev, "no platform data supplied\n");
3117 return -EINVAL;
3118 }
3119
3120 dev_id = dev->id;
3121 }
3122
3123 sp = &sci_ports[dev_id];
3124 platform_set_drvdata(dev, sp);
3125
3126 ret = sci_probe_single(dev, dev_id, p, sp);
3127 if (ret)
3128 return ret;
3129
3130 if (sp->port.fifosize > 1) {
3131 ret = sysfs_create_file(&dev->dev.kobj,
3132 &dev_attr_rx_fifo_trigger.attr);
3133 if (ret)
3134 return ret;
3135 }
3136 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB) {
3137 ret = sysfs_create_file(&dev->dev.kobj,
3138 &dev_attr_rx_fifo_timeout.attr);
3139 if (ret) {
3140 if (sp->port.fifosize > 1) {
3141 sysfs_remove_file(&dev->dev.kobj,
3142 &dev_attr_rx_fifo_trigger.attr);
3143 }
3144 return ret;
3145 }
3146 }
3147
3148 #ifdef CONFIG_SH_STANDARD_BIOS
3149 sh_bios_gdb_detach();
3150 #endif
3151
3152 return 0;
3153 }
3154
3155 static __maybe_unused int sci_suspend(struct device *dev)
3156 {
3157 struct sci_port *sport = dev_get_drvdata(dev);
3158
3159 if (sport)
3160 uart_suspend_port(&sci_uart_driver, &sport->port);
3161
3162 return 0;
3163 }
3164
3165 static __maybe_unused int sci_resume(struct device *dev)
3166 {
3167 struct sci_port *sport = dev_get_drvdata(dev);
3168
3169 if (sport)
3170 uart_resume_port(&sci_uart_driver, &sport->port);
3171
3172 return 0;
3173 }
3174
3175 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3176
3177 static struct platform_driver sci_driver = {
3178 .probe = sci_probe,
3179 .remove = sci_remove,
3180 .driver = {
3181 .name = "sh-sci",
3182 .pm = &sci_dev_pm_ops,
3183 .of_match_table = of_match_ptr(of_sci_match),
3184 },
3185 };
3186
3187 static int __init sci_init(void)
3188 {
3189 int ret;
3190
3191 pr_info("%s\n", banner);
3192
3193 ret = uart_register_driver(&sci_uart_driver);
3194 if (likely(ret == 0)) {
3195 ret = platform_driver_register(&sci_driver);
3196 if (unlikely(ret))
3197 uart_unregister_driver(&sci_uart_driver);
3198 }
3199
3200 return ret;
3201 }
3202
3203 static void __exit sci_exit(void)
3204 {
3205 platform_driver_unregister(&sci_driver);
3206 uart_unregister_driver(&sci_uart_driver);
3207 }
3208
3209 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3210 early_platform_init_buffer("earlyprintk", &sci_driver,
3211 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3212 #endif
3213 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3214 static struct __init plat_sci_port port_cfg;
3215
3216 static int __init early_console_setup(struct earlycon_device *device,
3217 int type)
3218 {
3219 if (!device->port.membase)
3220 return -ENODEV;
3221
3222 device->port.serial_in = sci_serial_in;
3223 device->port.serial_out = sci_serial_out;
3224 device->port.type = type;
3225 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3226 port_cfg.type = type;
3227 sci_ports[0].cfg = &port_cfg;
3228 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3229 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3230 sci_serial_out(&sci_ports[0].port, SCSCR,
3231 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3232
3233 device->con->write = serial_console_write;
3234 return 0;
3235 }
3236 static int __init sci_early_console_setup(struct earlycon_device *device,
3237 const char *opt)
3238 {
3239 return early_console_setup(device, PORT_SCI);
3240 }
3241 static int __init scif_early_console_setup(struct earlycon_device *device,
3242 const char *opt)
3243 {
3244 return early_console_setup(device, PORT_SCIF);
3245 }
3246 static int __init scifa_early_console_setup(struct earlycon_device *device,
3247 const char *opt)
3248 {
3249 return early_console_setup(device, PORT_SCIFA);
3250 }
3251 static int __init scifb_early_console_setup(struct earlycon_device *device,
3252 const char *opt)
3253 {
3254 return early_console_setup(device, PORT_SCIFB);
3255 }
3256 static int __init hscif_early_console_setup(struct earlycon_device *device,
3257 const char *opt)
3258 {
3259 return early_console_setup(device, PORT_HSCIF);
3260 }
3261
3262 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3263 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3264 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3265 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3266 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3267 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3268
3269 module_init(sci_init);
3270 module_exit(sci_exit);
3271
3272 MODULE_LICENSE("GPL");
3273 MODULE_ALIAS("platform:sh-sci");
3274 MODULE_AUTHOR("Paul Mundt");
3275 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
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