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dt3155: fix CodingStyle issues
[linux-2.6/btrfs-unstable.git] / drivers / media / pci / dt3155 / dt3155.c
blob89d0dc705e4a7a497b01638cab673aafe940ec67
1 /***************************************************************************
2 * Copyright (C) 2006-2010 by Marin Mitov *
3 * mitov@issp.bas.bg *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 ***************************************************************************/
16
17 #include <linux/module.h>
18 #include <linux/version.h>
19 #include <linux/stringify.h>
20 #include <linux/delay.h>
21 #include <linux/kthread.h>
22 #include <linux/slab.h>
23 #include <media/v4l2-dev.h>
24 #include <media/v4l2-ioctl.h>
25 #include <media/v4l2-common.h>
26 #include <media/videobuf2-dma-contig.h>
27
28 #include "dt3155.h"
29
30 #define DT3155_DEVICE_ID 0x1223
31
32 /**
33 * read_i2c_reg - reads an internal i2c register
34 *
35 * @addr: dt3155 mmio base address
36 * @index: index (internal address) of register to read
37 * @data: pointer to byte the read data will be placed in
38 *
39 * returns: zero on success or error code
40 *
41 * This function starts reading the specified (by index) register
42 * and busy waits for the process to finish. The result is placed
43 * in a byte pointed by data.
44 */
45 static int read_i2c_reg(void __iomem *addr, u8 index, u8 *data)
46 {
47 u32 tmp = index;
48
49 iowrite32((tmp << 17) | IIC_READ, addr + IIC_CSR2);
50 mmiowb();
51 udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */
52 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
53 return -EIO; /* error: NEW_CYCLE not cleared */
54 tmp = ioread32(addr + IIC_CSR1);
55 if (tmp & DIRECT_ABORT) {
56 /* reset DIRECT_ABORT bit */
57 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
58 return -EIO; /* error: DIRECT_ABORT set */
59 }
60 *data = tmp >> 24;
61 return 0;
62 }
63
64 /**
65 * write_i2c_reg - writes to an internal i2c register
66 *
67 * @addr: dt3155 mmio base address
68 * @index: index (internal address) of register to read
69 * @data: data to be written
70 *
71 * returns: zero on success or error code
72 *
73 * This function starts writing the specified (by index) register
74 * and busy waits for the process to finish.
75 */
76 static int write_i2c_reg(void __iomem *addr, u8 index, u8 data)
77 {
78 u32 tmp = index;
79
80 iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2);
81 mmiowb();
82 udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
83 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
84 return -EIO; /* error: NEW_CYCLE not cleared */
85 if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
86 /* reset DIRECT_ABORT bit */
87 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
88 return -EIO; /* error: DIRECT_ABORT set */
89 }
90 return 0;
91 }
92
93 /**
94 * write_i2c_reg_nowait - writes to an internal i2c register
95 *
96 * @addr: dt3155 mmio base address
97 * @index: index (internal address) of register to read
98 * @data: data to be written
99 *
100 * This function starts writing the specified (by index) register
101 * and then returns.
102 */
103 static void write_i2c_reg_nowait(void __iomem *addr, u8 index, u8 data)
104 {
105 u32 tmp = index;
106
107 iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2);
108 mmiowb();
109 }
110
111 /**
112 * wait_i2c_reg - waits the read/write to finish
113 *
114 * @addr: dt3155 mmio base address
115 *
116 * returns: zero on success or error code
117 *
118 * This function waits reading/writing to finish.
119 */
120 static int wait_i2c_reg(void __iomem *addr)
121 {
122 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
123 udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
124 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
125 return -EIO; /* error: NEW_CYCLE not cleared */
126 if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
127 /* reset DIRECT_ABORT bit */
128 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
129 return -EIO; /* error: DIRECT_ABORT set */
130 }
131 return 0;
132 }
133
134 static int
135 dt3155_queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt,
136 unsigned int *nbuffers, unsigned int *num_planes,
137 unsigned int sizes[], void *alloc_ctxs[])
138
139 {
140 struct dt3155_priv *pd = vb2_get_drv_priv(vq);
141 unsigned size = pd->width * pd->height;
142
143 if (vq->num_buffers + *nbuffers < 2)
144 *nbuffers = 2 - vq->num_buffers;
145 if (fmt && fmt->fmt.pix.sizeimage < size)
146 return -EINVAL;
147 *num_planes = 1;
148 sizes[0] = fmt ? fmt->fmt.pix.sizeimage : size;
149 alloc_ctxs[0] = pd->alloc_ctx;
150 return 0;
151 }
152
153 static int dt3155_buf_prepare(struct vb2_buffer *vb)
154 {
155 struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
156
157 vb2_set_plane_payload(vb, 0, pd->width * pd->height);
158 return 0;
159 }
160
161 static int dt3155_start_streaming(struct vb2_queue *q, unsigned count)
162 {
163 struct dt3155_priv *pd = vb2_get_drv_priv(q);
164 struct vb2_buffer *vb = pd->curr_buf;
165 dma_addr_t dma_addr;
166
167 pd->sequence = 0;
168 dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
169 iowrite32(dma_addr, pd->regs + EVEN_DMA_START);
170 iowrite32(dma_addr + pd->width, pd->regs + ODD_DMA_START);
171 iowrite32(pd->width, pd->regs + EVEN_DMA_STRIDE);
172 iowrite32(pd->width, pd->regs + ODD_DMA_STRIDE);
173 /* enable interrupts, clear all irq flags */
174 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
175 FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
176 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
177 FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD,
178 pd->regs + CSR1);
179 wait_i2c_reg(pd->regs);
180 write_i2c_reg(pd->regs, CONFIG, pd->config);
181 write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);
182 write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);
183
184 /* start the board */
185 write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD);
186 return 0;
187 }
188
189 static void dt3155_stop_streaming(struct vb2_queue *q)
190 {
191 struct dt3155_priv *pd = vb2_get_drv_priv(q);
192 struct vb2_buffer *vb;
193
194 spin_lock_irq(&pd->lock);
195 /* stop the board */
196 write_i2c_reg_nowait(pd->regs, CSR2, pd->csr2);
197 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
198 FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1);
199 /* disable interrupts, clear all irq flags */
200 iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
201 spin_unlock_irq(&pd->lock);
202
203 /*
204 * It is not clear whether the DMA stops at once or whether it
205 * will finish the current frame or field first. To be on the
206 * safe side we wait a bit.
207 */
208 msleep(45);
209
210 spin_lock_irq(&pd->lock);
211 if (pd->curr_buf) {
212 vb2_buffer_done(pd->curr_buf, VB2_BUF_STATE_ERROR);
213 pd->curr_buf = NULL;
214 }
215
216 while (!list_empty(&pd->dmaq)) {
217 vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry);
218 list_del(&vb->done_entry);
219 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
220 }
221 spin_unlock_irq(&pd->lock);
222 }
223
224 static void dt3155_buf_queue(struct vb2_buffer *vb)
225 {
226 struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
227
228 /* pd->vidq.streaming = 1 when dt3155_buf_queue() is invoked */
229 spin_lock_irq(&pd->lock);
230 if (pd->curr_buf)
231 list_add_tail(&vb->done_entry, &pd->dmaq);
232 else
233 pd->curr_buf = vb;
234 spin_unlock_irq(&pd->lock);
235 }
236
237 static const struct vb2_ops q_ops = {
238 .queue_setup = dt3155_queue_setup,
239 .wait_prepare = vb2_ops_wait_prepare,
240 .wait_finish = vb2_ops_wait_finish,
241 .buf_prepare = dt3155_buf_prepare,
242 .start_streaming = dt3155_start_streaming,
243 .stop_streaming = dt3155_stop_streaming,
244 .buf_queue = dt3155_buf_queue,
245 };
246
247 static irqreturn_t dt3155_irq_handler_even(int irq, void *dev_id)
248 {
249 struct dt3155_priv *ipd = dev_id;
250 struct vb2_buffer *ivb;
251 dma_addr_t dma_addr;
252 u32 tmp;
253
254 tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD);
255 if (!tmp)
256 return IRQ_NONE; /* not our irq */
257 if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) {
258 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START,
259 ipd->regs + INT_CSR);
260 return IRQ_HANDLED; /* start of field irq */
261 }
262 tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD);
263 if (tmp) {
264 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
265 FLD_DN_ODD | FLD_DN_EVEN |
266 CAP_CONT_EVEN | CAP_CONT_ODD,
267 ipd->regs + CSR1);
268 mmiowb();
269 }
270
271 spin_lock(&ipd->lock);
272 if (ipd->curr_buf && !list_empty(&ipd->dmaq)) {
273 v4l2_get_timestamp(&ipd->curr_buf->v4l2_buf.timestamp);
274 ipd->curr_buf->v4l2_buf.sequence = ipd->sequence++;
275 ipd->curr_buf->v4l2_buf.field = V4L2_FIELD_NONE;
276 vb2_buffer_done(ipd->curr_buf, VB2_BUF_STATE_DONE);
277
278 ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), done_entry);
279 list_del(&ivb->done_entry);
280 ipd->curr_buf = ivb;
281 dma_addr = vb2_dma_contig_plane_dma_addr(ivb, 0);
282 iowrite32(dma_addr, ipd->regs + EVEN_DMA_START);
283 iowrite32(dma_addr + ipd->width, ipd->regs + ODD_DMA_START);
284 iowrite32(ipd->width, ipd->regs + EVEN_DMA_STRIDE);
285 iowrite32(ipd->width, ipd->regs + ODD_DMA_STRIDE);
286 mmiowb();
287 }
288
289 /* enable interrupts, clear all irq flags */
290 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
291 FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
292 spin_unlock(&ipd->lock);
293 return IRQ_HANDLED;
294 }
295
296 static const struct v4l2_file_operations dt3155_fops = {
297 .owner = THIS_MODULE,
298 .open = v4l2_fh_open,
299 .release = vb2_fop_release,
300 .unlocked_ioctl = video_ioctl2,
301 .read = vb2_fop_read,
302 .mmap = vb2_fop_mmap,
303 .poll = vb2_fop_poll
304 };
305
306 static int dt3155_querycap(struct file *filp, void *p,
307 struct v4l2_capability *cap)
308 {
309 struct dt3155_priv *pd = video_drvdata(filp);
310
311 strcpy(cap->driver, DT3155_NAME);
312 strcpy(cap->card, DT3155_NAME " frame grabber");
313 sprintf(cap->bus_info, "PCI:%s", pci_name(pd->pdev));
314 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE |
315 V4L2_CAP_STREAMING | V4L2_CAP_READWRITE;
316 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
317 return 0;
318 }
319
320 static int dt3155_enum_fmt_vid_cap(struct file *filp,
321 void *p, struct v4l2_fmtdesc *f)
322 {
323 if (f->index)
324 return -EINVAL;
325 f->pixelformat = V4L2_PIX_FMT_GREY;
326 strcpy(f->description, "8-bit Greyscale");
327 return 0;
328 }
329
330 static int dt3155_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
331 {
332 struct dt3155_priv *pd = video_drvdata(filp);
333
334 f->fmt.pix.width = pd->width;
335 f->fmt.pix.height = pd->height;
336 f->fmt.pix.pixelformat = V4L2_PIX_FMT_GREY;
337 f->fmt.pix.field = V4L2_FIELD_NONE;
338 f->fmt.pix.bytesperline = f->fmt.pix.width;
339 f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height;
340 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
341 return 0;
342 }
343
344 static int dt3155_g_std(struct file *filp, void *p, v4l2_std_id *norm)
345 {
346 struct dt3155_priv *pd = video_drvdata(filp);
347
348 *norm = pd->std;
349 return 0;
350 }
351
352 static int dt3155_s_std(struct file *filp, void *p, v4l2_std_id norm)
353 {
354 struct dt3155_priv *pd = video_drvdata(filp);
355
356 if (pd->std == norm)
357 return 0;
358 if (vb2_is_busy(&pd->vidq))
359 return -EBUSY;
360 pd->std = norm;
361 if (pd->std & V4L2_STD_525_60) {
362 pd->csr2 = VT_60HZ;
363 pd->width = 640;
364 pd->height = 480;
365 } else {
366 pd->csr2 = VT_50HZ;
367 pd->width = 768;
368 pd->height = 576;
369 }
370 return 0;
371 }
372
373 static int dt3155_enum_input(struct file *filp, void *p,
374 struct v4l2_input *input)
375 {
376 if (input->index > 3)
377 return -EINVAL;
378 if (input->index)
379 snprintf(input->name, sizeof(input->name), "VID%d",
380 input->index);
381 else
382 strlcpy(input->name, "J2/VID0", sizeof(input->name));
383 input->type = V4L2_INPUT_TYPE_CAMERA;
384 input->std = V4L2_STD_ALL;
385 input->status = 0;
386 return 0;
387 }
388
389 static int dt3155_g_input(struct file *filp, void *p, unsigned int *i)
390 {
391 struct dt3155_priv *pd = video_drvdata(filp);
392
393 *i = pd->input;
394 return 0;
395 }
396
397 static int dt3155_s_input(struct file *filp, void *p, unsigned int i)
398 {
399 struct dt3155_priv *pd = video_drvdata(filp);
400
401 if (i > 3)
402 return -EINVAL;
403 pd->input = i;
404 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
405 write_i2c_reg(pd->regs, AD_CMD, (i << 6) | (i << 4) | SYNC_LVL_3);
406 return 0;
407 }
408
409 static const struct v4l2_ioctl_ops dt3155_ioctl_ops = {
410 .vidioc_querycap = dt3155_querycap,
411 .vidioc_enum_fmt_vid_cap = dt3155_enum_fmt_vid_cap,
412 .vidioc_try_fmt_vid_cap = dt3155_fmt_vid_cap,
413 .vidioc_g_fmt_vid_cap = dt3155_fmt_vid_cap,
414 .vidioc_s_fmt_vid_cap = dt3155_fmt_vid_cap,
415 .vidioc_reqbufs = vb2_ioctl_reqbufs,
416 .vidioc_create_bufs = vb2_ioctl_create_bufs,
417 .vidioc_querybuf = vb2_ioctl_querybuf,
418 .vidioc_expbuf = vb2_ioctl_expbuf,
419 .vidioc_qbuf = vb2_ioctl_qbuf,
420 .vidioc_dqbuf = vb2_ioctl_dqbuf,
421 .vidioc_streamon = vb2_ioctl_streamon,
422 .vidioc_streamoff = vb2_ioctl_streamoff,
423 .vidioc_g_std = dt3155_g_std,
424 .vidioc_s_std = dt3155_s_std,
425 .vidioc_enum_input = dt3155_enum_input,
426 .vidioc_g_input = dt3155_g_input,
427 .vidioc_s_input = dt3155_s_input,
428 };
429
430 static int dt3155_init_board(struct dt3155_priv *pd)
431 {
432 struct pci_dev *pdev = pd->pdev;
433 int i;
434 u8 tmp = 0;
435
436 pci_set_master(pdev); /* dt3155 needs it */
437
438 /* resetting the adapter */
439 iowrite32(ADDR_ERR_ODD | ADDR_ERR_EVEN | FLD_CRPT_ODD | FLD_CRPT_EVEN |
440 FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1);
441 mmiowb();
442 msleep(20);
443
444 /* initializing adapter registers */
445 iowrite32(FIFO_EN | SRST, pd->regs + CSR1);
446 mmiowb();
447 iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT);
448 iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT);
449 iowrite32(0x00000020, pd->regs + FIFO_TRIGER);
450 iowrite32(0x00000103, pd->regs + XFER_MODE);
451 iowrite32(0, pd->regs + RETRY_WAIT_CNT);
452 iowrite32(0, pd->regs + INT_CSR);
453 iowrite32(1, pd->regs + EVEN_FLD_MASK);
454 iowrite32(1, pd->regs + ODD_FLD_MASK);
455 iowrite32(0, pd->regs + MASK_LENGTH);
456 iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT);
457 iowrite32(0x01010101, pd->regs + IIC_CLK_DUR);
458 mmiowb();
459
460 /* verifying that we have a DT3155 board (not just a SAA7116 chip) */
461 read_i2c_reg(pd->regs, DT_ID, &tmp);
462 if (tmp != DT3155_ID)
463 return -ENODEV;
464
465 /* initialize AD LUT */
466 write_i2c_reg(pd->regs, AD_ADDR, 0);
467 for (i = 0; i < 256; i++)
468 write_i2c_reg(pd->regs, AD_LUT, i);
469
470 /* initialize ADC references */
471 /* FIXME: pos_ref & neg_ref depend on VT_50HZ */
472 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
473 write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
474 write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF);
475 write_i2c_reg(pd->regs, AD_CMD, 34);
476 write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF);
477 write_i2c_reg(pd->regs, AD_CMD, 0);
478
479 /* initialize PM LUT */
480 write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM);
481 for (i = 0; i < 256; i++) {
482 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
483 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
484 }
485 write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL);
486 for (i = 0; i < 256; i++) {
487 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
488 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
489 }
490 write_i2c_reg(pd->regs, CONFIG, pd->config); /* ACQ_MODE_EVEN */
491
492 /* select channel 1 for input and set sync level */
493 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
494 write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
495
496 /* disable all irqs, clear all irq flags */
497 iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD,
498 pd->regs + INT_CSR);
499
500 return 0;
501 }
502
503 static struct video_device dt3155_vdev = {
504 .name = DT3155_NAME,
505 .fops = &dt3155_fops,
506 .ioctl_ops = &dt3155_ioctl_ops,
507 .minor = -1,
508 .release = video_device_release_empty,
509 .tvnorms = V4L2_STD_ALL,
510 };
511
512 static int dt3155_probe(struct pci_dev *pdev, const struct pci_device_id *id)
513 {
514 int err;
515 struct dt3155_priv *pd;
516
517 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
518 if (err)
519 return -ENODEV;
520 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
521 if (!pd)
522 return -ENOMEM;
523
524 err = v4l2_device_register(&pdev->dev, &pd->v4l2_dev);
525 if (err)
526 return err;
527 pd->vdev = dt3155_vdev;
528 pd->vdev.v4l2_dev = &pd->v4l2_dev;
529 video_set_drvdata(&pd->vdev, pd); /* for use in video_fops */
530 pd->pdev = pdev;
531 pd->std = V4L2_STD_625_50;
532 pd->csr2 = VT_50HZ;
533 pd->width = 768;
534 pd->height = 576;
535 INIT_LIST_HEAD(&pd->dmaq);
536 mutex_init(&pd->mux);
537 pd->vdev.lock = &pd->mux; /* for locking v4l2_file_operations */
538 pd->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
539 pd->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
540 pd->vidq.io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
541 pd->vidq.ops = &q_ops;
542 pd->vidq.mem_ops = &vb2_dma_contig_memops;
543 pd->vidq.drv_priv = pd;
544 pd->vidq.min_buffers_needed = 2;
545 pd->vidq.gfp_flags = GFP_DMA32;
546 pd->vidq.lock = &pd->mux; /* for locking v4l2_file_operations */
547 pd->vdev.queue = &pd->vidq;
548 err = vb2_queue_init(&pd->vidq);
549 if (err < 0)
550 goto err_v4l2_dev_unreg;
551 pd->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
552 if (IS_ERR(pd->alloc_ctx)) {
553 dev_err(&pdev->dev, "Can't allocate buffer context");
554 err = PTR_ERR(pd->alloc_ctx);
555 goto err_v4l2_dev_unreg;
556 }
557 spin_lock_init(&pd->lock);
558 pd->config = ACQ_MODE_EVEN;
559 err = pci_enable_device(pdev);
560 if (err)
561 goto err_free_ctx;
562 err = pci_request_region(pdev, 0, pci_name(pdev));
563 if (err)
564 goto err_pci_disable;
565 pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0));
566 if (!pd->regs) {
567 err = -ENOMEM;
568 goto err_free_reg;
569 }
570 err = dt3155_init_board(pd);
571 if (err)
572 goto err_iounmap;
573 err = request_irq(pd->pdev->irq, dt3155_irq_handler_even,
574 IRQF_SHARED, DT3155_NAME, pd);
575 if (err)
576 goto err_iounmap;
577 err = video_register_device(&pd->vdev, VFL_TYPE_GRABBER, -1);
578 if (err)
579 goto err_free_irq;
580 dev_info(&pdev->dev, "/dev/video%i is ready\n", pd->vdev.minor);
581 return 0; /* success */
582
583 err_free_irq:
584 free_irq(pd->pdev->irq, pd);
585 err_iounmap:
586 pci_iounmap(pdev, pd->regs);
587 err_free_reg:
588 pci_release_region(pdev, 0);
589 err_pci_disable:
590 pci_disable_device(pdev);
591 err_free_ctx:
592 vb2_dma_contig_cleanup_ctx(pd->alloc_ctx);
593 err_v4l2_dev_unreg:
594 v4l2_device_unregister(&pd->v4l2_dev);
595 return err;
596 }
597
598 static void dt3155_remove(struct pci_dev *pdev)
599 {
600 struct v4l2_device *v4l2_dev = pci_get_drvdata(pdev);
601 struct dt3155_priv *pd = container_of(v4l2_dev, struct dt3155_priv,
602 v4l2_dev);
603
604 video_unregister_device(&pd->vdev);
605 free_irq(pd->pdev->irq, pd);
606 vb2_queue_release(&pd->vidq);
607 v4l2_device_unregister(&pd->v4l2_dev);
608 pci_iounmap(pdev, pd->regs);
609 pci_release_region(pdev, 0);
610 pci_disable_device(pdev);
611 vb2_dma_contig_cleanup_ctx(pd->alloc_ctx);
612 }
613
614 static const struct pci_device_id pci_ids[] = {
615 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, DT3155_DEVICE_ID) },
616 { 0, /* zero marks the end */ },
617 };
618 MODULE_DEVICE_TABLE(pci, pci_ids);
619
620 static struct pci_driver pci_driver = {
621 .name = DT3155_NAME,
622 .id_table = pci_ids,
623 .probe = dt3155_probe,
624 .remove = dt3155_remove,
625 };
626
627 module_pci_driver(pci_driver);
628
629 MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber");
630 MODULE_AUTHOR("Marin Mitov <mitov@issp.bas.bg>");
631 MODULE_VERSION(DT3155_VERSION);
632 MODULE_LICENSE("GPL");
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