arch/mips/include/asm/pci.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  */
   6 #ifndef _ASM_PCI_H
   7 #define _ASM_PCI_H
   8
   9 #include <linux/mm.h>
  10
  11 #ifdef __KERNEL__
  12
  13 /*
  14  * This file essentially defines the interface between board
  15  * specific PCI code and MIPS common PCI code.  Should potentially put
  16  * into include/asm/pci.h file.
  17  */
  18
  19 #include <linux/ioport.h>
  20 #include <linux/of.h>
  21
  22 /*
  23  * Each pci channel is a top-level PCI bus seem by CPU.  A machine  with
  24  * multiple PCI channels may have multiple PCI host controllers or a
  25  * single controller supporting multiple channels.
  26  */
  27 struct pci_controller {
  28         struct pci_controller *next;
  29         struct pci_bus *bus;
  30         struct device_node *of_node;
  31
  32         struct pci_ops *pci_ops;
  33         struct resource *mem_resource;
  34         unsigned long mem_offset;
  35         struct resource *io_resource;
  36         unsigned long io_offset;
  37         unsigned long io_map_base;
  38
  39         unsigned int index;
  40         /* For compatibility with current (as of July 2003) pciutils
  41            and XFree86. Eventually will be removed. */
  42         unsigned int need_domain_info;
  43
  44         int iommu;
  45
  46         /* Optional access methods for reading/writing the bus number
  47            of the PCI controller */
  48         int (*get_busno)(void);
  49         void (*set_busno)(int busno);
  50 };
  51
  52 /*
  53  * Used by boards to register their PCI busses before the actual scanning.
  54  */
  55 extern void register_pci_controller(struct pci_controller *hose);
  56
  57 /*
  58  * board supplied pci irq fixup routine
  59  */
  60 extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
  61
  62
  63 /* Can be used to override the logic in pci_scan_bus for skipping
  64    already-configured bus numbers - to be used for buggy BIOSes
  65    or architectures with incomplete PCI setup by the loader */
  66
  67 extern unsigned int pcibios_assign_all_busses(void);
  68
  69 extern unsigned long PCIBIOS_MIN_IO;
  70 extern unsigned long PCIBIOS_MIN_MEM;
  71
  72 #define PCIBIOS_MIN_CARDBUS_IO  0x4000
  73
  74 extern void pcibios_set_master(struct pci_dev *dev);
  75
  76 static inline void pcibios_penalize_isa_irq(int irq, int active)
  77 {
  78         /* We don't do dynamic PCI IRQ allocation */
  79 }
  80
  81 #define HAVE_PCI_MMAP
  82
  83 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
  84         enum pci_mmap_state mmap_state, int write_combine);
  85
  86 #define HAVE_ARCH_PCI_RESOURCE_TO_USER
  87
  88 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
  89                 const struct resource *rsrc, resource_size_t *start,
  90                 resource_size_t *end)
  91 {
  92         phys_t size = resource_size(rsrc);
  93
  94         *start = fixup_bigphys_addr(rsrc->start, size);
  95         *end = rsrc->start + size;
  96 }
  97
  98 /*
  99  * Dynamic DMA mapping stuff.
 100  * MIPS has everything mapped statically.
 101  */
 102
 103 #include <linux/types.h>
 104 #include <linux/slab.h>
 105 #include <asm/scatterlist.h>
 106 #include <linux/string.h>
 107 #include <asm/io.h>
 108 #include <asm-generic/pci-bridge.h>
 109
 110 struct pci_dev;
 111
 112 /*
 113  * The PCI address space does equal the physical memory address space.  The
 114  * networking and block device layers use this boolean for bounce buffer
 115  * decisions.  This is set if any hose does not have an IOMMU.
 116  */
 117 extern unsigned int PCI_DMA_BUS_IS_PHYS;
 118
 119 #ifdef CONFIG_PCI
 120 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 121                                         enum pci_dma_burst_strategy *strat,
 122                                         unsigned long *strategy_parameter)
 123 {
 124         *strat = PCI_DMA_BURST_INFINITY;
 125         *strategy_parameter = ~0UL;
 126 }
 127 #endif
 128
 129 #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
 130
 131 static inline int pci_proc_domain(struct pci_bus *bus)
 132 {
 133         struct pci_controller *hose = bus->sysdata;
 134         return hose->need_domain_info;
 135 }
 136
 137 #endif /* __KERNEL__ */
 138
 139 /* implement the pci_ DMA API in terms of the generic device dma_ one */
 140 #include <asm-generic/pci-dma-compat.h>
 141
 142 /* Do platform specific device initialization at pci_enable_device() time */
 143 extern int pcibios_plat_dev_init(struct pci_dev *dev);
 144
 145 /* Chances are this interrupt is wired PC-style ...  */
 146 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 147 {
 148         return channel ? 15 : 14;
 149 }
 150
 151 extern char * (*pcibios_plat_setup)(char *str);
 152
 153 #ifdef CONFIG_OF
 154 /* this function parses memory ranges from a device node */
 155 extern void pci_load_of_ranges(struct pci_controller *hose,
 156                                struct device_node *node);
 157 #else
 158 static inline void pci_load_of_ranges(struct pci_controller *hose,
 159                                       struct device_node *node) {}
 160 #endif
 161
 162 #endif /* _ASM_PCI_H */