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USB: f_mass_storage: fix crash on bind() error
[linux-2.6/btrfs-unstable.git] / drivers / spi / dw_spi.c
blob8ed38f1d6c18d36daab177affb9fb1e015cd2c07
1 /*
2 * dw_spi.c - Designware SPI core controller driver (refer pxa2xx_spi.c)
3 *
4 * Copyright (c) 2009, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 */
19
20 #include <linux/dma-mapping.h>
21 #include <linux/interrupt.h>
22 #include <linux/highmem.h>
23 #include <linux/delay.h>
24
25 #include <linux/spi/dw_spi.h>
26 #include <linux/spi/spi.h>
27
28 #ifdef CONFIG_DEBUG_FS
29 #include <linux/debugfs.h>
30 #endif
31
32 #define START_STATE ((void *)0)
33 #define RUNNING_STATE ((void *)1)
34 #define DONE_STATE ((void *)2)
35 #define ERROR_STATE ((void *)-1)
36
37 #define QUEUE_RUNNING 0
38 #define QUEUE_STOPPED 1
39
40 #define MRST_SPI_DEASSERT 0
41 #define MRST_SPI_ASSERT 1
42
43 /* Slave spi_dev related */
44 struct chip_data {
45 u16 cr0;
46 u8 cs; /* chip select pin */
47 u8 n_bytes; /* current is a 1/2/4 byte op */
48 u8 tmode; /* TR/TO/RO/EEPROM */
49 u8 type; /* SPI/SSP/MicroWire */
50
51 u8 poll_mode; /* 1 means use poll mode */
52
53 u32 dma_width;
54 u32 rx_threshold;
55 u32 tx_threshold;
56 u8 enable_dma;
57 u8 bits_per_word;
58 u16 clk_div; /* baud rate divider */
59 u32 speed_hz; /* baud rate */
60 int (*write)(struct dw_spi *dws);
61 int (*read)(struct dw_spi *dws);
62 void (*cs_control)(u32 command);
63 };
64
65 #ifdef CONFIG_DEBUG_FS
66 static int spi_show_regs_open(struct inode *inode, struct file *file)
67 {
68 file->private_data = inode->i_private;
69 return 0;
70 }
71
72 #define SPI_REGS_BUFSIZE 1024
73 static ssize_t spi_show_regs(struct file *file, char __user *user_buf,
74 size_t count, loff_t *ppos)
75 {
76 struct dw_spi *dws;
77 char *buf;
78 u32 len = 0;
79 ssize_t ret;
80
81 dws = file->private_data;
82
83 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
84 if (!buf)
85 return 0;
86
87 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
88 "MRST SPI0 registers:\n");
89 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
90 "=================================\n");
91 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
92 "CTRL0: \t\t0x%08x\n", dw_readl(dws, ctrl0));
93 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
94 "CTRL1: \t\t0x%08x\n", dw_readl(dws, ctrl1));
95 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
96 "SSIENR: \t0x%08x\n", dw_readl(dws, ssienr));
97 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
98 "SER: \t\t0x%08x\n", dw_readl(dws, ser));
99 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
100 "BAUDR: \t\t0x%08x\n", dw_readl(dws, baudr));
101 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
102 "TXFTLR: \t0x%08x\n", dw_readl(dws, txfltr));
103 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
104 "RXFTLR: \t0x%08x\n", dw_readl(dws, rxfltr));
105 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
106 "TXFLR: \t\t0x%08x\n", dw_readl(dws, txflr));
107 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
108 "RXFLR: \t\t0x%08x\n", dw_readl(dws, rxflr));
109 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
110 "SR: \t\t0x%08x\n", dw_readl(dws, sr));
111 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
112 "IMR: \t\t0x%08x\n", dw_readl(dws, imr));
113 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
114 "ISR: \t\t0x%08x\n", dw_readl(dws, isr));
115 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
116 "DMACR: \t\t0x%08x\n", dw_readl(dws, dmacr));
117 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
118 "DMATDLR: \t0x%08x\n", dw_readl(dws, dmatdlr));
119 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
120 "DMARDLR: \t0x%08x\n", dw_readl(dws, dmardlr));
121 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
122 "=================================\n");
123
124 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
125 kfree(buf);
126 return ret;
127 }
128
129 static const struct file_operations mrst_spi_regs_ops = {
130 .owner = THIS_MODULE,
131 .open = spi_show_regs_open,
132 .read = spi_show_regs,
133 };
134
135 static int mrst_spi_debugfs_init(struct dw_spi *dws)
136 {
137 dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
138 if (!dws->debugfs)
139 return -ENOMEM;
140
141 debugfs_create_file("registers", S_IFREG | S_IRUGO,
142 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
143 return 0;
144 }
145
146 static void mrst_spi_debugfs_remove(struct dw_spi *dws)
147 {
148 if (dws->debugfs)
149 debugfs_remove_recursive(dws->debugfs);
150 }
151
152 #else
153 static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
154 {
155 return 0;
156 }
157
158 static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
159 {
160 }
161 #endif /* CONFIG_DEBUG_FS */
162
163 static void wait_till_not_busy(struct dw_spi *dws)
164 {
165 unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);
166
167 while (time_before(jiffies, end)) {
168 if (!(dw_readw(dws, sr) & SR_BUSY))
169 return;
170 }
171 dev_err(&dws->master->dev,
172 "DW SPI: Status keeps busy for 1000us after a read/write!\n");
173 }
174
175 static void flush(struct dw_spi *dws)
176 {
177 while (dw_readw(dws, sr) & SR_RF_NOT_EMPT)
178 dw_readw(dws, dr);
179
180 wait_till_not_busy(dws);
181 }
182
183 static void null_cs_control(u32 command)
184 {
185 }
186
187 static int null_writer(struct dw_spi *dws)
188 {
189 u8 n_bytes = dws->n_bytes;
190
191 if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
192 || (dws->tx == dws->tx_end))
193 return 0;
194 dw_writew(dws, dr, 0);
195 dws->tx += n_bytes;
196
197 wait_till_not_busy(dws);
198 return 1;
199 }
200
201 static int null_reader(struct dw_spi *dws)
202 {
203 u8 n_bytes = dws->n_bytes;
204
205 while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
206 && (dws->rx < dws->rx_end)) {
207 dw_readw(dws, dr);
208 dws->rx += n_bytes;
209 }
210 wait_till_not_busy(dws);
211 return dws->rx == dws->rx_end;
212 }
213
214 static int u8_writer(struct dw_spi *dws)
215 {
216 if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
217 || (dws->tx == dws->tx_end))
218 return 0;
219
220 dw_writew(dws, dr, *(u8 *)(dws->tx));
221 ++dws->tx;
222
223 wait_till_not_busy(dws);
224 return 1;
225 }
226
227 static int u8_reader(struct dw_spi *dws)
228 {
229 while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
230 && (dws->rx < dws->rx_end)) {
231 *(u8 *)(dws->rx) = dw_readw(dws, dr);
232 ++dws->rx;
233 }
234
235 wait_till_not_busy(dws);
236 return dws->rx == dws->rx_end;
237 }
238
239 static int u16_writer(struct dw_spi *dws)
240 {
241 if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
242 || (dws->tx == dws->tx_end))
243 return 0;
244
245 dw_writew(dws, dr, *(u16 *)(dws->tx));
246 dws->tx += 2;
247
248 wait_till_not_busy(dws);
249 return 1;
250 }
251
252 static int u16_reader(struct dw_spi *dws)
253 {
254 u16 temp;
255
256 while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
257 && (dws->rx < dws->rx_end)) {
258 temp = dw_readw(dws, dr);
259 *(u16 *)(dws->rx) = temp;
260 dws->rx += 2;
261 }
262
263 wait_till_not_busy(dws);
264 return dws->rx == dws->rx_end;
265 }
266
267 static void *next_transfer(struct dw_spi *dws)
268 {
269 struct spi_message *msg = dws->cur_msg;
270 struct spi_transfer *trans = dws->cur_transfer;
271
272 /* Move to next transfer */
273 if (trans->transfer_list.next != &msg->transfers) {
274 dws->cur_transfer =
275 list_entry(trans->transfer_list.next,
276 struct spi_transfer,
277 transfer_list);
278 return RUNNING_STATE;
279 } else
280 return DONE_STATE;
281 }
282
283 /*
284 * Note: first step is the protocol driver prepares
285 * a dma-capable memory, and this func just need translate
286 * the virt addr to physical
287 */
288 static int map_dma_buffers(struct dw_spi *dws)
289 {
290 if (!dws->cur_msg->is_dma_mapped || !dws->dma_inited
291 || !dws->cur_chip->enable_dma)
292 return 0;
293
294 if (dws->cur_transfer->tx_dma)
295 dws->tx_dma = dws->cur_transfer->tx_dma;
296
297 if (dws->cur_transfer->rx_dma)
298 dws->rx_dma = dws->cur_transfer->rx_dma;
299
300 return 1;
301 }
302
303 /* Caller already set message->status; dma and pio irqs are blocked */
304 static void giveback(struct dw_spi *dws)
305 {
306 struct spi_transfer *last_transfer;
307 unsigned long flags;
308 struct spi_message *msg;
309
310 spin_lock_irqsave(&dws->lock, flags);
311 msg = dws->cur_msg;
312 dws->cur_msg = NULL;
313 dws->cur_transfer = NULL;
314 dws->prev_chip = dws->cur_chip;
315 dws->cur_chip = NULL;
316 dws->dma_mapped = 0;
317 queue_work(dws->workqueue, &dws->pump_messages);
318 spin_unlock_irqrestore(&dws->lock, flags);
319
320 last_transfer = list_entry(msg->transfers.prev,
321 struct spi_transfer,
322 transfer_list);
323
324 if (!last_transfer->cs_change)
325 dws->cs_control(MRST_SPI_DEASSERT);
326
327 msg->state = NULL;
328 if (msg->complete)
329 msg->complete(msg->context);
330 }
331
332 static void int_error_stop(struct dw_spi *dws, const char *msg)
333 {
334 /* Stop and reset hw */
335 flush(dws);
336 spi_enable_chip(dws, 0);
337
338 dev_err(&dws->master->dev, "%s\n", msg);
339 dws->cur_msg->state = ERROR_STATE;
340 tasklet_schedule(&dws->pump_transfers);
341 }
342
343 static void transfer_complete(struct dw_spi *dws)
344 {
345 /* Update total byte transfered return count actual bytes read */
346 dws->cur_msg->actual_length += dws->len;
347
348 /* Move to next transfer */
349 dws->cur_msg->state = next_transfer(dws);
350
351 /* Handle end of message */
352 if (dws->cur_msg->state == DONE_STATE) {
353 dws->cur_msg->status = 0;
354 giveback(dws);
355 } else
356 tasklet_schedule(&dws->pump_transfers);
357 }
358
359 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
360 {
361 u16 irq_status, irq_mask = 0x3f;
362 u32 int_level = dws->fifo_len / 2;
363 u32 left;
364
365 irq_status = dw_readw(dws, isr) & irq_mask;
366 /* Error handling */
367 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
368 dw_readw(dws, txoicr);
369 dw_readw(dws, rxoicr);
370 dw_readw(dws, rxuicr);
371 int_error_stop(dws, "interrupt_transfer: fifo overrun");
372 return IRQ_HANDLED;
373 }
374
375 if (irq_status & SPI_INT_TXEI) {
376 spi_mask_intr(dws, SPI_INT_TXEI);
377
378 left = (dws->tx_end - dws->tx) / dws->n_bytes;
379 left = (left > int_level) ? int_level : left;
380
381 while (left--)
382 dws->write(dws);
383 dws->read(dws);
384
385 /* Re-enable the IRQ if there is still data left to tx */
386 if (dws->tx_end > dws->tx)
387 spi_umask_intr(dws, SPI_INT_TXEI);
388 else
389 transfer_complete(dws);
390 }
391
392 return IRQ_HANDLED;
393 }
394
395 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
396 {
397 struct dw_spi *dws = dev_id;
398
399 if (!dws->cur_msg) {
400 spi_mask_intr(dws, SPI_INT_TXEI);
401 /* Never fail */
402 return IRQ_HANDLED;
403 }
404
405 return dws->transfer_handler(dws);
406 }
407
408 /* Must be called inside pump_transfers() */
409 static void poll_transfer(struct dw_spi *dws)
410 {
411 while (dws->write(dws))
412 dws->read(dws);
413
414 transfer_complete(dws);
415 }
416
417 static void dma_transfer(struct dw_spi *dws, int cs_change)
418 {
419 }
420
421 static void pump_transfers(unsigned long data)
422 {
423 struct dw_spi *dws = (struct dw_spi *)data;
424 struct spi_message *message = NULL;
425 struct spi_transfer *transfer = NULL;
426 struct spi_transfer *previous = NULL;
427 struct spi_device *spi = NULL;
428 struct chip_data *chip = NULL;
429 u8 bits = 0;
430 u8 imask = 0;
431 u8 cs_change = 0;
432 u16 txint_level = 0;
433 u16 clk_div = 0;
434 u32 speed = 0;
435 u32 cr0 = 0;
436
437 /* Get current state information */
438 message = dws->cur_msg;
439 transfer = dws->cur_transfer;
440 chip = dws->cur_chip;
441 spi = message->spi;
442
443 if (unlikely(!chip->clk_div))
444 chip->clk_div = dws->max_freq / chip->speed_hz;
445
446 if (message->state == ERROR_STATE) {
447 message->status = -EIO;
448 goto early_exit;
449 }
450
451 /* Handle end of message */
452 if (message->state == DONE_STATE) {
453 message->status = 0;
454 goto early_exit;
455 }
456
457 /* Delay if requested at end of transfer*/
458 if (message->state == RUNNING_STATE) {
459 previous = list_entry(transfer->transfer_list.prev,
460 struct spi_transfer,
461 transfer_list);
462 if (previous->delay_usecs)
463 udelay(previous->delay_usecs);
464 }
465
466 dws->n_bytes = chip->n_bytes;
467 dws->dma_width = chip->dma_width;
468 dws->cs_control = chip->cs_control;
469
470 dws->rx_dma = transfer->rx_dma;
471 dws->tx_dma = transfer->tx_dma;
472 dws->tx = (void *)transfer->tx_buf;
473 dws->tx_end = dws->tx + transfer->len;
474 dws->rx = transfer->rx_buf;
475 dws->rx_end = dws->rx + transfer->len;
476 dws->write = dws->tx ? chip->write : null_writer;
477 dws->read = dws->rx ? chip->read : null_reader;
478 dws->cs_change = transfer->cs_change;
479 dws->len = dws->cur_transfer->len;
480 if (chip != dws->prev_chip)
481 cs_change = 1;
482
483 cr0 = chip->cr0;
484
485 /* Handle per transfer options for bpw and speed */
486 if (transfer->speed_hz) {
487 speed = chip->speed_hz;
488
489 if (transfer->speed_hz != speed) {
490 speed = transfer->speed_hz;
491 if (speed > dws->max_freq) {
492 printk(KERN_ERR "MRST SPI0: unsupported"
493 "freq: %dHz\n", speed);
494 message->status = -EIO;
495 goto early_exit;
496 }
497
498 /* clk_div doesn't support odd number */
499 clk_div = dws->max_freq / speed;
500 clk_div = (clk_div + 1) & 0xfffe;
501
502 chip->speed_hz = speed;
503 chip->clk_div = clk_div;
504 }
505 }
506 if (transfer->bits_per_word) {
507 bits = transfer->bits_per_word;
508
509 switch (bits) {
510 case 8:
511 dws->n_bytes = 1;
512 dws->dma_width = 1;
513 dws->read = (dws->read != null_reader) ?
514 u8_reader : null_reader;
515 dws->write = (dws->write != null_writer) ?
516 u8_writer : null_writer;
517 break;
518 case 16:
519 dws->n_bytes = 2;
520 dws->dma_width = 2;
521 dws->read = (dws->read != null_reader) ?
522 u16_reader : null_reader;
523 dws->write = (dws->write != null_writer) ?
524 u16_writer : null_writer;
525 break;
526 default:
527 printk(KERN_ERR "MRST SPI0: unsupported bits:"
528 "%db\n", bits);
529 message->status = -EIO;
530 goto early_exit;
531 }
532
533 cr0 = (bits - 1)
534 | (chip->type << SPI_FRF_OFFSET)
535 | (spi->mode << SPI_MODE_OFFSET)
536 | (chip->tmode << SPI_TMOD_OFFSET);
537 }
538 message->state = RUNNING_STATE;
539
540 /*
541 * Adjust transfer mode if necessary. Requires platform dependent
542 * chipselect mechanism.
543 */
544 if (dws->cs_control) {
545 if (dws->rx && dws->tx)
546 chip->tmode = 0x00;
547 else if (dws->rx)
548 chip->tmode = 0x02;
549 else
550 chip->tmode = 0x01;
551
552 cr0 &= ~(0x3 << SPI_MODE_OFFSET);
553 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
554 }
555
556 /* Check if current transfer is a DMA transaction */
557 dws->dma_mapped = map_dma_buffers(dws);
558
559 /*
560 * Interrupt mode
561 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
562 */
563 if (!dws->dma_mapped && !chip->poll_mode) {
564 int templen = dws->len / dws->n_bytes;
565 txint_level = dws->fifo_len / 2;
566 txint_level = (templen > txint_level) ? txint_level : templen;
567
568 imask |= SPI_INT_TXEI;
569 dws->transfer_handler = interrupt_transfer;
570 }
571
572 /*
573 * Reprogram registers only if
574 * 1. chip select changes
575 * 2. clk_div is changed
576 * 3. control value changes
577 */
578 if (dw_readw(dws, ctrl0) != cr0 || cs_change || clk_div || imask) {
579 spi_enable_chip(dws, 0);
580
581 if (dw_readw(dws, ctrl0) != cr0)
582 dw_writew(dws, ctrl0, cr0);
583
584 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
585 spi_chip_sel(dws, spi->chip_select);
586
587 /* Set the interrupt mask, for poll mode just diable all int */
588 spi_mask_intr(dws, 0xff);
589 if (imask)
590 spi_umask_intr(dws, imask);
591 if (txint_level)
592 dw_writew(dws, txfltr, txint_level);
593
594 spi_enable_chip(dws, 1);
595 if (cs_change)
596 dws->prev_chip = chip;
597 }
598
599 if (dws->dma_mapped)
600 dma_transfer(dws, cs_change);
601
602 if (chip->poll_mode)
603 poll_transfer(dws);
604
605 return;
606
607 early_exit:
608 giveback(dws);
609 return;
610 }
611
612 static void pump_messages(struct work_struct *work)
613 {
614 struct dw_spi *dws =
615 container_of(work, struct dw_spi, pump_messages);
616 unsigned long flags;
617
618 /* Lock queue and check for queue work */
619 spin_lock_irqsave(&dws->lock, flags);
620 if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
621 dws->busy = 0;
622 spin_unlock_irqrestore(&dws->lock, flags);
623 return;
624 }
625
626 /* Make sure we are not already running a message */
627 if (dws->cur_msg) {
628 spin_unlock_irqrestore(&dws->lock, flags);
629 return;
630 }
631
632 /* Extract head of queue */
633 dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
634 list_del_init(&dws->cur_msg->queue);
635
636 /* Initial message state*/
637 dws->cur_msg->state = START_STATE;
638 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
639 struct spi_transfer,
640 transfer_list);
641 dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
642
643 /* Mark as busy and launch transfers */
644 tasklet_schedule(&dws->pump_transfers);
645
646 dws->busy = 1;
647 spin_unlock_irqrestore(&dws->lock, flags);
648 }
649
650 /* spi_device use this to queue in their spi_msg */
651 static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
652 {
653 struct dw_spi *dws = spi_master_get_devdata(spi->master);
654 unsigned long flags;
655
656 spin_lock_irqsave(&dws->lock, flags);
657
658 if (dws->run == QUEUE_STOPPED) {
659 spin_unlock_irqrestore(&dws->lock, flags);
660 return -ESHUTDOWN;
661 }
662
663 msg->actual_length = 0;
664 msg->status = -EINPROGRESS;
665 msg->state = START_STATE;
666
667 list_add_tail(&msg->queue, &dws->queue);
668
669 if (dws->run == QUEUE_RUNNING && !dws->busy) {
670
671 if (dws->cur_transfer || dws->cur_msg)
672 queue_work(dws->workqueue,
673 &dws->pump_messages);
674 else {
675 /* If no other data transaction in air, just go */
676 spin_unlock_irqrestore(&dws->lock, flags);
677 pump_messages(&dws->pump_messages);
678 return 0;
679 }
680 }
681
682 spin_unlock_irqrestore(&dws->lock, flags);
683 return 0;
684 }
685
686 /* This may be called twice for each spi dev */
687 static int dw_spi_setup(struct spi_device *spi)
688 {
689 struct dw_spi_chip *chip_info = NULL;
690 struct chip_data *chip;
691
692 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
693 return -EINVAL;
694
695 /* Only alloc on first setup */
696 chip = spi_get_ctldata(spi);
697 if (!chip) {
698 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
699 if (!chip)
700 return -ENOMEM;
701
702 chip->cs_control = null_cs_control;
703 chip->enable_dma = 0;
704 }
705
706 /*
707 * Protocol drivers may change the chip settings, so...
708 * if chip_info exists, use it
709 */
710 chip_info = spi->controller_data;
711
712 /* chip_info doesn't always exist */
713 if (chip_info) {
714 if (chip_info->cs_control)
715 chip->cs_control = chip_info->cs_control;
716
717 chip->poll_mode = chip_info->poll_mode;
718 chip->type = chip_info->type;
719
720 chip->rx_threshold = 0;
721 chip->tx_threshold = 0;
722
723 chip->enable_dma = chip_info->enable_dma;
724 }
725
726 if (spi->bits_per_word <= 8) {
727 chip->n_bytes = 1;
728 chip->dma_width = 1;
729 chip->read = u8_reader;
730 chip->write = u8_writer;
731 } else if (spi->bits_per_word <= 16) {
732 chip->n_bytes = 2;
733 chip->dma_width = 2;
734 chip->read = u16_reader;
735 chip->write = u16_writer;
736 } else {
737 /* Never take >16b case for MRST SPIC */
738 dev_err(&spi->dev, "invalid wordsize\n");
739 return -EINVAL;
740 }
741 chip->bits_per_word = spi->bits_per_word;
742
743 if (!spi->max_speed_hz) {
744 dev_err(&spi->dev, "No max speed HZ parameter\n");
745 return -EINVAL;
746 }
747 chip->speed_hz = spi->max_speed_hz;
748
749 chip->tmode = 0; /* Tx & Rx */
750 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
751 chip->cr0 = (chip->bits_per_word - 1)
752 | (chip->type << SPI_FRF_OFFSET)
753 | (spi->mode << SPI_MODE_OFFSET)
754 | (chip->tmode << SPI_TMOD_OFFSET);
755
756 spi_set_ctldata(spi, chip);
757 return 0;
758 }
759
760 static void dw_spi_cleanup(struct spi_device *spi)
761 {
762 struct chip_data *chip = spi_get_ctldata(spi);
763 kfree(chip);
764 }
765
766 static int __devinit init_queue(struct dw_spi *dws)
767 {
768 INIT_LIST_HEAD(&dws->queue);
769 spin_lock_init(&dws->lock);
770
771 dws->run = QUEUE_STOPPED;
772 dws->busy = 0;
773
774 tasklet_init(&dws->pump_transfers,
775 pump_transfers, (unsigned long)dws);
776
777 INIT_WORK(&dws->pump_messages, pump_messages);
778 dws->workqueue = create_singlethread_workqueue(
779 dev_name(dws->master->dev.parent));
780 if (dws->workqueue == NULL)
781 return -EBUSY;
782
783 return 0;
784 }
785
786 static int start_queue(struct dw_spi *dws)
787 {
788 unsigned long flags;
789
790 spin_lock_irqsave(&dws->lock, flags);
791
792 if (dws->run == QUEUE_RUNNING || dws->busy) {
793 spin_unlock_irqrestore(&dws->lock, flags);
794 return -EBUSY;
795 }
796
797 dws->run = QUEUE_RUNNING;
798 dws->cur_msg = NULL;
799 dws->cur_transfer = NULL;
800 dws->cur_chip = NULL;
801 dws->prev_chip = NULL;
802 spin_unlock_irqrestore(&dws->lock, flags);
803
804 queue_work(dws->workqueue, &dws->pump_messages);
805
806 return 0;
807 }
808
809 static int stop_queue(struct dw_spi *dws)
810 {
811 unsigned long flags;
812 unsigned limit = 50;
813 int status = 0;
814
815 spin_lock_irqsave(&dws->lock, flags);
816 dws->run = QUEUE_STOPPED;
817 while (!list_empty(&dws->queue) && dws->busy && limit--) {
818 spin_unlock_irqrestore(&dws->lock, flags);
819 msleep(10);
820 spin_lock_irqsave(&dws->lock, flags);
821 }
822
823 if (!list_empty(&dws->queue) || dws->busy)
824 status = -EBUSY;
825 spin_unlock_irqrestore(&dws->lock, flags);
826
827 return status;
828 }
829
830 static int destroy_queue(struct dw_spi *dws)
831 {
832 int status;
833
834 status = stop_queue(dws);
835 if (status != 0)
836 return status;
837 destroy_workqueue(dws->workqueue);
838 return 0;
839 }
840
841 /* Restart the controller, disable all interrupts, clean rx fifo */
842 static void spi_hw_init(struct dw_spi *dws)
843 {
844 spi_enable_chip(dws, 0);
845 spi_mask_intr(dws, 0xff);
846 spi_enable_chip(dws, 1);
847 flush(dws);
848
849 /*
850 * Try to detect the FIFO depth if not set by interface driver,
851 * the depth could be from 2 to 256 from HW spec
852 */
853 if (!dws->fifo_len) {
854 u32 fifo;
855 for (fifo = 2; fifo <= 257; fifo++) {
856 dw_writew(dws, txfltr, fifo);
857 if (fifo != dw_readw(dws, txfltr))
858 break;
859 }
860
861 dws->fifo_len = (fifo == 257) ? 0 : fifo;
862 dw_writew(dws, txfltr, 0);
863 }
864 }
865
866 int __devinit dw_spi_add_host(struct dw_spi *dws)
867 {
868 struct spi_master *master;
869 int ret;
870
871 BUG_ON(dws == NULL);
872
873 master = spi_alloc_master(dws->parent_dev, 0);
874 if (!master) {
875 ret = -ENOMEM;
876 goto exit;
877 }
878
879 dws->master = master;
880 dws->type = SSI_MOTO_SPI;
881 dws->prev_chip = NULL;
882 dws->dma_inited = 0;
883 dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
884
885 ret = request_irq(dws->irq, dw_spi_irq, 0,
886 "dw_spi", dws);
887 if (ret < 0) {
888 dev_err(&master->dev, "can not get IRQ\n");
889 goto err_free_master;
890 }
891
892 master->mode_bits = SPI_CPOL | SPI_CPHA;
893 master->bus_num = dws->bus_num;
894 master->num_chipselect = dws->num_cs;
895 master->cleanup = dw_spi_cleanup;
896 master->setup = dw_spi_setup;
897 master->transfer = dw_spi_transfer;
898
899 dws->dma_inited = 0;
900
901 /* Basic HW init */
902 spi_hw_init(dws);
903
904 /* Initial and start queue */
905 ret = init_queue(dws);
906 if (ret) {
907 dev_err(&master->dev, "problem initializing queue\n");
908 goto err_diable_hw;
909 }
910 ret = start_queue(dws);
911 if (ret) {
912 dev_err(&master->dev, "problem starting queue\n");
913 goto err_diable_hw;
914 }
915
916 spi_master_set_devdata(master, dws);
917 ret = spi_register_master(master);
918 if (ret) {
919 dev_err(&master->dev, "problem registering spi master\n");
920 goto err_queue_alloc;
921 }
922
923 mrst_spi_debugfs_init(dws);
924 return 0;
925
926 err_queue_alloc:
927 destroy_queue(dws);
928 err_diable_hw:
929 spi_enable_chip(dws, 0);
930 free_irq(dws->irq, dws);
931 err_free_master:
932 spi_master_put(master);
933 exit:
934 return ret;
935 }
936 EXPORT_SYMBOL(dw_spi_add_host);
937
938 void __devexit dw_spi_remove_host(struct dw_spi *dws)
939 {
940 int status = 0;
941
942 if (!dws)
943 return;
944 mrst_spi_debugfs_remove(dws);
945
946 /* Remove the queue */
947 status = destroy_queue(dws);
948 if (status != 0)
949 dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "
950 "complete, message memory not freed\n");
951
952 spi_enable_chip(dws, 0);
953 /* Disable clk */
954 spi_set_clk(dws, 0);
955 free_irq(dws->irq, dws);
956
957 /* Disconnect from the SPI framework */
958 spi_unregister_master(dws->master);
959 }
960 EXPORT_SYMBOL(dw_spi_remove_host);
961
962 int dw_spi_suspend_host(struct dw_spi *dws)
963 {
964 int ret = 0;
965
966 ret = stop_queue(dws);
967 if (ret)
968 return ret;
969 spi_enable_chip(dws, 0);
970 spi_set_clk(dws, 0);
971 return ret;
972 }
973 EXPORT_SYMBOL(dw_spi_suspend_host);
974
975 int dw_spi_resume_host(struct dw_spi *dws)
976 {
977 int ret;
978
979 spi_hw_init(dws);
980 ret = start_queue(dws);
981 if (ret)
982 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
983 return ret;
984 }
985 EXPORT_SYMBOL(dw_spi_resume_host);
986
987 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
988 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
989 MODULE_LICENSE("GPL v2");
(deprecated) Btrfs devel tree