arch/arm/mach-omap2/pm44xx.c

   1 /*
   2  * OMAP4+ Power Management Routines
   3  *
   4  * Copyright (C) 2010-2013 Texas Instruments, Inc.
   5  * Rajendra Nayak <rnayak@ti.com>
   6  * Santosh Shilimkar <santosh.shilimkar@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/pm.h>
  14 #include <linux/suspend.h>
  15 #include <linux/module.h>
  16 #include <linux/list.h>
  17 #include <linux/err.h>
  18 #include <linux/slab.h>
  19 #include <asm/system_misc.h>
  20
  21 #include "soc.h"
  22 #include "common.h"
  23 #include "clockdomain.h"
  24 #include "powerdomain.h"
  25 #include "pm.h"
  26
  27 u16 pm44xx_errata;
  28
  29 struct power_state {
  30         struct powerdomain *pwrdm;
  31         u32 next_state;
  32         u32 next_logic_state;
  33 #ifdef CONFIG_SUSPEND
  34         u32 saved_state;
  35         u32 saved_logic_state;
  36 #endif
  37         struct list_head node;
  38 };
  39
  40 static u32 cpu_suspend_state = PWRDM_POWER_OFF;
  41
  42 static LIST_HEAD(pwrst_list);
  43
  44 #ifdef CONFIG_SUSPEND
  45 static int omap4_pm_suspend(void)
  46 {
  47         struct power_state *pwrst;
  48         int state, ret = 0;
  49         u32 cpu_id = smp_processor_id();
  50
  51         /* Save current powerdomain state */
  52         list_for_each_entry(pwrst, &pwrst_list, node) {
  53                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
  54                 pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
  55         }
  56
  57         /* Set targeted power domain states by suspend */
  58         list_for_each_entry(pwrst, &pwrst_list, node) {
  59                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
  60                 pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->next_logic_state);
  61         }
  62
  63         /*
  64          * For MPUSS to hit power domain retention(CSWR or OSWR),
  65          * CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
  66          * since CPU power domain CSWR is not supported by hardware
  67          * Only master CPU follows suspend path. All other CPUs follow
  68          * CPU hotplug path in system wide suspend. On OMAP4, CPU power
  69          * domain CSWR is not supported by hardware.
  70          * More details can be found in OMAP4430 TRM section 4.3.4.2.
  71          */
  72         omap4_enter_lowpower(cpu_id, cpu_suspend_state);
  73
  74         /* Restore next powerdomain state */
  75         list_for_each_entry(pwrst, &pwrst_list, node) {
  76                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
  77                 if (state > pwrst->next_state) {
  78                         pr_info("Powerdomain (%s) didn't enter target state %d\n",
  79                                 pwrst->pwrdm->name, pwrst->next_state);
  80                         ret = -1;
  81                 }
  82                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
  83                 pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
  84         }
  85         if (ret) {
  86                 pr_crit("Could not enter target state in pm_suspend\n");
  87                 /*
  88                  * OMAP4 chip PM currently works only with certain (newer)
  89                  * versions of bootloaders. This is due to missing code in the
  90                  * kernel to properly reset and initialize some devices.
  91                  * Warn the user about the bootloader version being one of the
  92                  * possible causes.
  93                  * http://www.spinics.net/lists/arm-kernel/msg218641.html
  94                  */
  95                 pr_warn("A possible cause could be an old bootloader - try u-boot >= v2012.07\n");
  96         } else {
  97                 pr_info("Successfully put all powerdomains to target state\n");
  98         }
  99
 100         return 0;
 101 }
 102 #else
 103 #define omap4_pm_suspend NULL
 104 #endif /* CONFIG_SUSPEND */
 105
 106 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 107 {
 108         struct power_state *pwrst;
 109
 110         if (!pwrdm->pwrsts)
 111                 return 0;
 112
 113         /*
 114          * Skip CPU0 and CPU1 power domains. CPU1 is programmed
 115          * through hotplug path and CPU0 explicitly programmed
 116          * further down in the code path
 117          */
 118         if (!strncmp(pwrdm->name, "cpu", 3)) {
 119                 if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
 120                         cpu_suspend_state = PWRDM_POWER_RET;
 121                 return 0;
 122         }
 123
 124         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 125         if (!pwrst)
 126                 return -ENOMEM;
 127
 128         pwrst->pwrdm = pwrdm;
 129         pwrst->next_state = pwrdm_get_valid_lp_state(pwrdm, false,
 130                                                      PWRDM_POWER_RET);
 131         pwrst->next_logic_state = pwrdm_get_valid_lp_state(pwrdm, true,
 132                                                            PWRDM_POWER_OFF);
 133
 134         list_add(&pwrst->node, &pwrst_list);
 135
 136         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 137 }
 138
 139 /**
 140  * omap_default_idle - OMAP4 default ilde routine.'
 141  *
 142  * Implements OMAP4 memory, IO ordering requirements which can't be addressed
 143  * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPU_IDLE and
 144  * by secondary CPU with CONFIG_CPU_IDLE.
 145  */
 146 static void omap_default_idle(void)
 147 {
 148         omap_do_wfi();
 149 }
 150
 151 /**
 152  * omap4_init_static_deps - Add OMAP4 static dependencies
 153  *
 154  * Add needed static clockdomain dependencies on OMAP4 devices.
 155  * Return: 0 on success or 'err' on failures
 156  */
 157 static inline int omap4_init_static_deps(void)
 158 {
 159         struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
 160         struct clockdomain *ducati_clkdm, *l3_2_clkdm;
 161         int ret = 0;
 162
 163         if (omap_rev() == OMAP4430_REV_ES1_0) {
 164                 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
 165                 return -ENODEV;
 166         }
 167
 168         pr_err("Power Management for TI OMAP4.\n");
 169         /*
 170          * OMAP4 chip PM currently works only with certain (newer)
 171          * versions of bootloaders. This is due to missing code in the
 172          * kernel to properly reset and initialize some devices.
 173          * http://www.spinics.net/lists/arm-kernel/msg218641.html
 174          */
 175         pr_warn("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n");
 176
 177         ret = pwrdm_for_each(pwrdms_setup, NULL);
 178         if (ret) {
 179                 pr_err("Failed to setup powerdomains\n");
 180                 return ret;
 181         }
 182
 183         /*
 184          * The dynamic dependency between MPUSS -> MEMIF and
 185          * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
 186          * expected. The hardware recommendation is to enable static
 187          * dependencies for these to avoid system lock ups or random crashes.
 188          * The L4 wakeup depedency is added to workaround the OCP sync hardware
 189          * BUG with 32K synctimer which lead to incorrect timer value read
 190          * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
 191          * are part of L4 wakeup clockdomain.
 192          */
 193         mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
 194         emif_clkdm = clkdm_lookup("l3_emif_clkdm");
 195         l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
 196         l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
 197         ducati_clkdm = clkdm_lookup("ducati_clkdm");
 198         if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
 199                 (!l3_2_clkdm) || (!ducati_clkdm))
 200                 return -EINVAL;
 201
 202         ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
 203         ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
 204         ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
 205         ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
 206         ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
 207         if (ret) {
 208                 pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n");
 209                 return -EINVAL;
 210         }
 211
 212         return ret;
 213 }
 214
 215 /**
 216  * omap5_dra7_init_static_deps - Init static clkdm dependencies on OMAP5 and
 217  *                               DRA7
 218  *
 219  * The dynamic dependency between MPUSS -> EMIF is broken and has
 220  * not worked as expected. The hardware recommendation is to
 221  * enable static dependencies for these to avoid system
 222  * lock ups or random crashes.
 223  */
 224 static inline int omap5_dra7_init_static_deps(void)
 225 {
 226         struct clockdomain *mpuss_clkdm, *emif_clkdm;
 227         int ret;
 228
 229         mpuss_clkdm = clkdm_lookup("mpu_clkdm");
 230         emif_clkdm = clkdm_lookup("emif_clkdm");
 231         if (!mpuss_clkdm || !emif_clkdm)
 232                 return -EINVAL;
 233
 234         ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
 235         if (ret)
 236                 pr_err("Failed to add MPUSS -> EMIF wakeup dependency\n");
 237
 238         return ret;
 239 }
 240
 241 /**
 242  * omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices
 243  *
 244  * Initializes basic stuff for power management functionality.
 245  */
 246 int __init omap4_pm_init_early(void)
 247 {
 248         if (cpu_is_omap446x())
 249                 pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
 250
 251         if (soc_is_omap54xx() || soc_is_dra7xx())
 252                 pm44xx_errata |= PM_OMAP4_CPU_OSWR_DISABLE;
 253
 254         return 0;
 255 }
 256
 257 /**
 258  * omap4_pm_init - Init routine for OMAP4+ devices
 259  *
 260  * Initializes all powerdomain and clockdomain target states
 261  * and all PRCM settings.
 262  * Return: Returns the error code returned by called functions.
 263  */
 264 int __init omap4_pm_init(void)
 265 {
 266         int ret = 0;
 267
 268         if (omap_rev() == OMAP4430_REV_ES1_0) {
 269                 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
 270                 return -ENODEV;
 271         }
 272
 273         pr_info("Power Management for TI OMAP4+ devices.\n");
 274
 275         ret = pwrdm_for_each(pwrdms_setup, NULL);
 276         if (ret) {
 277                 pr_err("Failed to setup powerdomains.\n");
 278                 goto err2;
 279         }
 280
 281         if (cpu_is_omap44xx())
 282                 ret = omap4_init_static_deps();
 283         else if (soc_is_omap54xx() || soc_is_dra7xx())
 284                 ret = omap5_dra7_init_static_deps();
 285
 286         if (ret) {
 287                 pr_err("Failed to initialise static dependencies.\n");
 288                 goto err2;
 289         }
 290
 291         ret = omap4_mpuss_init();
 292         if (ret) {
 293                 pr_err("Failed to initialise OMAP4 MPUSS\n");
 294                 goto err2;
 295         }
 296
 297         (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
 298
 299         omap_common_suspend_init(omap4_pm_suspend);
 300
 301         /* Overwrite the default cpu_do_idle() */
 302         arm_pm_idle = omap_default_idle;
 303
 304         if (cpu_is_omap44xx())
 305                 omap4_idle_init();
 306
 307 err2:
 308         return ret;
 309 }