2 * Part of Intel(R) Manageability Engine Interface Linux driver
4 * Copyright (c) 2003 - 2008 Intel Corp.
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8 * modification, are permitted provided that the following conditions
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16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
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19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
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41 #ifndef _HECI_DATA_STRUCTURES_H_
42 #define _HECI_DATA_STRUCTURES_H_
44 #include <linux/spinlock.h>
45 #include <linux/list.h>
46 #include <linux/pci.h>
47 #include <linux/timer.h>
48 #include <linux/interrupt.h>
49 #include <linux/workqueue.h>
50 #include <linux/module.h>
51 #include <linux/aio.h>
52 #include <linux/types.h>
55 * error code definition
57 #define ESLOTS_OVERFLOW 1
58 #define ECORRUPTED_MESSAGE_HEADER 1000
59 #define ECOMPLETE_MESSAGE 1001
61 #define HECI_FC_MESSAGE_RESERVED_LENGTH 5
64 * Number of queue lists used by this driver
66 #define HECI_IO_LISTS_NUMBER 7
69 * Maximum transmission unit (MTU) of heci messages
71 #define IAMTHIF_MTU 4160
79 /* H_CB_WW - Host Circular Buffer (CB) Write Window register */
81 /* H_CSR - Host Control Status register */
83 /* ME_CB_RW - ME Circular Buffer Read Window register (read only) */
85 /* ME_CSR_HA - ME Control Status Host Access register (read only) */
89 /* register bits of H_CSR (Host Control Status register) */
90 /* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
91 #define H_CBD 0xFF000000
92 /* Host Circular Buffer Write Pointer */
93 #define H_CBWP 0x00FF0000
94 /* Host Circular Buffer Read Pointer */
95 #define H_CBRP 0x0000FF00
97 #define H_RST 0x00000010
99 #define H_RDY 0x00000008
100 /* Host Interrupt Generate */
101 #define H_IG 0x00000004
102 /* Host Interrupt Status */
103 #define H_IS 0x00000002
104 /* Host Interrupt Enable */
105 #define H_IE 0x00000001
108 /* register bits of ME_CSR_HA (ME Control Status Host Access register) */
109 /* ME CB (Circular Buffer) Depth HRA (Host Read Access)
110 * - host read only access to ME_CBD */
111 #define ME_CBD_HRA 0xFF000000
112 /* ME CB Write Pointer HRA - host read only access to ME_CBWP */
113 #define ME_CBWP_HRA 0x00FF0000
114 /* ME CB Read Pointer HRA - host read only access to ME_CBRP */
115 #define ME_CBRP_HRA 0x0000FF00
116 /* ME Reset HRA - host read only access to ME_RST */
117 #define ME_RST_HRA 0x00000010
118 /* ME Ready HRA - host read only access to ME_RDY */
119 #define ME_RDY_HRA 0x00000008
120 /* ME Interrupt Generate HRA - host read only access to ME_IG */
121 #define ME_IG_HRA 0x00000004
122 /* ME Interrupt Status HRA - host read only access to ME_IS */
123 #define ME_IS_HRA 0x00000002
124 /* ME Interrupt Enable HRA - host read only access to ME_IE */
125 #define ME_IE_HRA 0x00000001
127 #define HECI_MINORS_BASE 1
128 #define HECI_MINORS_COUNT 1
130 #define HECI_MINOR_NUMBER 1
131 #define HECI_MAX_OPEN_HANDLE_COUNT 253
134 * debug kernel print macro define
136 extern int heci_debug
;
138 #define DBG(format, arg...) do { \
140 printk(KERN_INFO "heci: %s: " format, __func__, ## arg); \
145 * time to wait HECI become ready after init
147 #define HECI_INTEROP_TIMEOUT (HZ * 7)
150 * watch dog definition
152 #define HECI_WATCHDOG_DATA_SIZE 16
153 #define HECI_START_WD_DATA_SIZE 20
154 #define HECI_WD_PARAMS_SIZE 4
155 #define HECI_WD_STATE_INDEPENDENCE_MSG_SENT (1 << 0)
157 #define HECI_WD_HOST_CLIENT_ID 1
158 #define HECI_IAMTHIF_HOST_CLIENT_ID 2
169 HECI_FILE_INITIALIZING
= 0,
170 HECI_FILE_CONNECTING
,
172 HECI_FILE_DISCONNECTING
,
173 HECI_FILE_DISCONNECTED
176 /* HECI device states */
178 HECI_INITIALIZING
= 0,
182 HECI_RECOVERING_FROM_RESET
,
187 enum iamthif_states
{
189 HECI_IAMTHIF_WRITING
,
190 HECI_IAMTHIF_FLOW_CONTROL
,
191 HECI_IAMTHIF_READING
,
192 HECI_IAMTHIF_READ_COMPLETE
195 enum heci_file_transaction_states
{
205 enum heci_cb_major_types
{
213 /* HECI user data struct */
214 struct heci_message_data
{
217 } __attribute__((packed
));
219 #define HECI_CONNECT_TIMEOUT 3 /* at least 2 seconds */
221 #define IAMTHIF_STALL_TIMER 12 /* seconds */
222 #define IAMTHIF_READ_TIMER 15 /* seconds */
224 struct heci_cb_private
{
225 struct list_head cb_list
;
226 enum heci_cb_major_types major_file_operations
;
228 struct heci_message_data request_buffer
;
229 struct heci_message_data response_buffer
;
230 unsigned long information
;
231 unsigned long read_time
;
232 struct file
*file_object
;
235 /* Private file struct */
236 struct heci_file_private
{
237 struct list_head link
;
239 enum file_state state
;
240 wait_queue_head_t tx_wait
;
241 wait_queue_head_t rx_wait
;
242 wait_queue_head_t wait
;
243 spinlock_t file_lock
; /* file lock */
244 spinlock_t read_io_lock
; /* read lock */
245 spinlock_t write_io_lock
; /* write lock */
248 /* ID of client connected */
251 __u8 flow_ctrl_creds
;
253 enum heci_file_transaction_states reading_state
;
254 enum heci_file_transaction_states writing_state
;
256 struct heci_cb_private
*read_cb
;
259 struct io_heci_list
{
260 struct heci_cb_private heci_cb
;
262 struct iamt_heci_device
*device_extension
;
265 struct heci_driver_version
{
270 } __attribute__((packed
));
274 __u32 max_msg_length
;
275 __u8 protocol_version
;
276 } __attribute__((packed
));
279 * HECI BUS Interface Section
281 struct heci_msg_hdr
{
286 __u32 msg_complete
:1;
287 } __attribute__((packed
));
293 } __attribute__((packed
));
296 struct heci_bus_message
{
298 __u8 command_specific_data
[];
299 } __attribute__((packed
));
304 } __attribute__((packed
));
306 struct hbm_host_version_request
{
309 struct hbm_version host_version
;
310 } __attribute__((packed
));
312 struct hbm_host_version_response
{
314 int host_version_supported
;
315 struct hbm_version me_max_version
;
316 } __attribute__((packed
));
318 struct hbm_host_stop_request
{
322 } __attribute__((packed
));
324 struct hbm_host_stop_response
{
327 } __attribute__((packed
));
329 struct hbm_me_stop_request
{
333 } __attribute__((packed
));
335 struct hbm_host_enum_request
{
338 } __attribute__((packed
));
340 struct hbm_host_enum_response
{
343 __u8 valid_addresses
[32];
344 } __attribute__((packed
));
346 struct heci_client_properties
{
347 struct guid protocol_name
;
348 __u8 protocol_version
;
349 __u8 max_number_of_connections
;
351 __u8 single_recv_buf
;
352 __u32 max_msg_length
;
353 } __attribute__((packed
));
355 struct hbm_props_request
{
359 } __attribute__((packed
));
362 struct hbm_props_response
{
367 struct heci_client_properties client_properties
;
368 } __attribute__((packed
));
370 struct hbm_client_connect_request
{
375 } __attribute__((packed
));
377 struct hbm_client_connect_response
{
382 } __attribute__((packed
));
384 struct hbm_client_disconnect_request
{
389 } __attribute__((packed
));
391 struct hbm_flow_control
{
395 __u8 reserved
[HECI_FC_MESSAGE_RESERVED_LENGTH
];
396 } __attribute__((packed
));
398 struct heci_me_client
{
399 struct heci_client_properties props
;
401 __u8 flow_ctrl_creds
;
402 } __attribute__((packed
));
404 /* private device struct */
405 struct iamt_heci_device
{
406 struct pci_dev
*pdev
; /* pointer to pci device struct */
410 /* array of pointers to aio lists */
411 struct io_heci_list
*io_list_array
[HECI_IO_LISTS_NUMBER
];
412 struct io_heci_list read_list
; /* driver read queue */
413 struct io_heci_list write_list
; /* driver write queue */
414 struct io_heci_list write_waiting_list
; /* write waiting queue */
415 struct io_heci_list ctrl_wr_list
; /* managed write IOCTL list */
416 struct io_heci_list ctrl_rd_list
; /* managed read IOCTL list */
417 struct io_heci_list pthi_cmd_list
; /* PTHI list for cmd waiting */
419 /* driver managed PTHI list for reading completed pthi cmd data */
420 struct io_heci_list pthi_read_complete_list
;
424 struct list_head file_list
;
428 unsigned int mem_base
;
429 unsigned int mem_length
;
430 void __iomem
*mem_addr
;
432 * lock for the device
434 spinlock_t device_lock
; /* device lock*/
435 struct work_struct work
;
438 struct task_struct
*reinit_tsk
;
440 struct timer_list wd_timer
;
442 * hw states of host and fw(ME)
447 * waiting queue for receive message from FW
449 wait_queue_head_t wait_recvd_msg
;
450 wait_queue_head_t wait_stop_wd
;
454 enum heci_states heci_state
;
457 __u32 extra_write_index
;
458 __u32 rd_msg_buf
[128]; /* used for control messages */
459 __u32 wr_msg_buf
[128]; /* used for control messages */
460 __u32 ext_msg_buf
[8]; /* for control responses */
463 struct hbm_version version
;
465 int host_buffer_is_empty
;
466 struct heci_file_private wd_file_ext
;
467 struct heci_me_client
*me_clients
; /* Note: memory has to be allocated*/
468 __u8 heci_me_clients
[32]; /* list of existing clients */
469 __u8 num_heci_me_clients
;
470 __u8 heci_host_clients
[32]; /* list of existing clients */
471 __u8 current_host_client_id
;
475 __u16 wd_timeout
; /* seconds ((wd_data[1] << 8) + wd_data[0]) */
476 unsigned char wd_data
[HECI_START_WD_DATA_SIZE
];
479 __u16 wd_due_counter
;
481 int wd_bypass
; /* if 1, don't refresh watchdog ME client */
483 struct file
*iamthif_file_object
;
484 struct heci_file_private iamthif_file_ext
;
486 int iamthif_canceled
;
488 __u32 iamthif_stall_timer
;
489 unsigned char iamthif_msg_buf
[IAMTHIF_MTU
];
490 __u32 iamthif_msg_buf_size
;
491 __u32 iamthif_msg_buf_index
;
492 int iamthif_flow_control_pending
;
493 enum iamthif_states iamthif_state
;
495 struct heci_cb_private
*iamthif_current_cb
;
498 long open_handle_count
;
503 * read_heci_register - Read a byte from the heci device
505 * @dev: the device structure
506 * @offset: offset from which to read the data
508 * returns the byte read.
510 static inline __u32
read_heci_register(struct iamt_heci_device
*dev
,
511 unsigned long offset
)
513 return readl(dev
->mem_addr
+ offset
);
517 * write_heci_register - Write 4 bytes to the heci device
519 * @dev: the device structure
520 * @offset: offset from which to write the data
521 * @value: the byte to write
523 static inline void write_heci_register(struct iamt_heci_device
*dev
,
524 unsigned long offset
, __u32 value
)
526 writel(value
, dev
->mem_addr
+ offset
);
529 #endif /* _HECI_DATA_STRUCTURES_H_ */