2 * hcd.c - DesignWare HS OTG Controller host-mode routines
4 * Copyright (C) 2004-2013 Synopsys, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * This file contains the core HCD code, and implements the Linux hc_driver
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/spinlock.h>
44 #include <linux/interrupt.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/delay.h>
48 #include <linux/slab.h>
49 #include <linux/usb.h>
51 #include <linux/usb/hcd.h>
52 #include <linux/usb/ch11.h>
58 * dwc2_dump_channel_info() - Prints the state of a host channel
60 * @hsotg: Programming view of DWC_otg controller
61 * @chan: Pointer to the channel to dump
63 * Must be called with interrupt disabled and spinlock held
65 * NOTE: This function will be removed once the peripheral controller code
66 * is integrated and the driver is stable
68 static void dwc2_dump_channel_info(struct dwc2_hsotg
*hsotg
,
69 struct dwc2_host_chan
*chan
)
72 int num_channels
= hsotg
->core_params
->host_channels
;
83 hcchar
= dwc2_readl(hsotg
->regs
+ HCCHAR(chan
->hc_num
));
84 hcsplt
= dwc2_readl(hsotg
->regs
+ HCSPLT(chan
->hc_num
));
85 hctsiz
= dwc2_readl(hsotg
->regs
+ HCTSIZ(chan
->hc_num
));
86 hc_dma
= dwc2_readl(hsotg
->regs
+ HCDMA(chan
->hc_num
));
88 dev_dbg(hsotg
->dev
, " Assigned to channel %p:\n", chan
);
89 dev_dbg(hsotg
->dev
, " hcchar 0x%08x, hcsplt 0x%08x\n",
91 dev_dbg(hsotg
->dev
, " hctsiz 0x%08x, hc_dma 0x%08x\n",
93 dev_dbg(hsotg
->dev
, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
94 chan
->dev_addr
, chan
->ep_num
, chan
->ep_is_in
);
95 dev_dbg(hsotg
->dev
, " ep_type: %d\n", chan
->ep_type
);
96 dev_dbg(hsotg
->dev
, " max_packet: %d\n", chan
->max_packet
);
97 dev_dbg(hsotg
->dev
, " data_pid_start: %d\n", chan
->data_pid_start
);
98 dev_dbg(hsotg
->dev
, " xfer_started: %d\n", chan
->xfer_started
);
99 dev_dbg(hsotg
->dev
, " halt_status: %d\n", chan
->halt_status
);
100 dev_dbg(hsotg
->dev
, " xfer_buf: %p\n", chan
->xfer_buf
);
101 dev_dbg(hsotg
->dev
, " xfer_dma: %08lx\n",
102 (unsigned long)chan
->xfer_dma
);
103 dev_dbg(hsotg
->dev
, " xfer_len: %d\n", chan
->xfer_len
);
104 dev_dbg(hsotg
->dev
, " qh: %p\n", chan
->qh
);
105 dev_dbg(hsotg
->dev
, " NP inactive sched:\n");
106 list_for_each_entry(qh
, &hsotg
->non_periodic_sched_inactive
,
108 dev_dbg(hsotg
->dev
, " %p\n", qh
);
109 dev_dbg(hsotg
->dev
, " NP active sched:\n");
110 list_for_each_entry(qh
, &hsotg
->non_periodic_sched_active
,
112 dev_dbg(hsotg
->dev
, " %p\n", qh
);
113 dev_dbg(hsotg
->dev
, " Channels:\n");
114 for (i
= 0; i
< num_channels
; i
++) {
115 struct dwc2_host_chan
*chan
= hsotg
->hc_ptr_array
[i
];
117 dev_dbg(hsotg
->dev
, " %2d: %p\n", i
, chan
);
119 #endif /* VERBOSE_DEBUG */
123 * Processes all the URBs in a single list of QHs. Completes them with
124 * -ETIMEDOUT and frees the QTD.
126 * Must be called with interrupt disabled and spinlock held
128 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg
*hsotg
,
129 struct list_head
*qh_list
)
131 struct dwc2_qh
*qh
, *qh_tmp
;
132 struct dwc2_qtd
*qtd
, *qtd_tmp
;
134 list_for_each_entry_safe(qh
, qh_tmp
, qh_list
, qh_list_entry
) {
135 list_for_each_entry_safe(qtd
, qtd_tmp
, &qh
->qtd_list
,
137 dwc2_host_complete(hsotg
, qtd
, -ECONNRESET
);
138 dwc2_hcd_qtd_unlink_and_free(hsotg
, qtd
, qh
);
143 static void dwc2_qh_list_free(struct dwc2_hsotg
*hsotg
,
144 struct list_head
*qh_list
)
146 struct dwc2_qtd
*qtd
, *qtd_tmp
;
147 struct dwc2_qh
*qh
, *qh_tmp
;
151 /* The list hasn't been initialized yet */
154 spin_lock_irqsave(&hsotg
->lock
, flags
);
156 /* Ensure there are no QTDs or URBs left */
157 dwc2_kill_urbs_in_qh_list(hsotg
, qh_list
);
159 list_for_each_entry_safe(qh
, qh_tmp
, qh_list
, qh_list_entry
) {
160 dwc2_hcd_qh_unlink(hsotg
, qh
);
162 /* Free each QTD in the QH's QTD list */
163 list_for_each_entry_safe(qtd
, qtd_tmp
, &qh
->qtd_list
,
165 dwc2_hcd_qtd_unlink_and_free(hsotg
, qtd
, qh
);
167 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
168 dwc2_hcd_qh_free(hsotg
, qh
);
169 spin_lock_irqsave(&hsotg
->lock
, flags
);
172 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
176 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
177 * and periodic schedules. The QTD associated with each URB is removed from
178 * the schedule and freed. This function may be called when a disconnect is
179 * detected or when the HCD is being stopped.
181 * Must be called with interrupt disabled and spinlock held
183 static void dwc2_kill_all_urbs(struct dwc2_hsotg
*hsotg
)
185 dwc2_kill_urbs_in_qh_list(hsotg
, &hsotg
->non_periodic_sched_inactive
);
186 dwc2_kill_urbs_in_qh_list(hsotg
, &hsotg
->non_periodic_sched_active
);
187 dwc2_kill_urbs_in_qh_list(hsotg
, &hsotg
->periodic_sched_inactive
);
188 dwc2_kill_urbs_in_qh_list(hsotg
, &hsotg
->periodic_sched_ready
);
189 dwc2_kill_urbs_in_qh_list(hsotg
, &hsotg
->periodic_sched_assigned
);
190 dwc2_kill_urbs_in_qh_list(hsotg
, &hsotg
->periodic_sched_queued
);
194 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
196 * @hsotg: Pointer to struct dwc2_hsotg
198 void dwc2_hcd_start(struct dwc2_hsotg
*hsotg
)
202 if (hsotg
->op_state
== OTG_STATE_B_HOST
) {
204 * Reset the port. During a HNP mode switch the reset
205 * needs to occur within 1ms and have a duration of at
208 hprt0
= dwc2_read_hprt0(hsotg
);
210 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
213 queue_delayed_work(hsotg
->wq_otg
, &hsotg
->start_work
,
214 msecs_to_jiffies(50));
217 /* Must be called with interrupt disabled and spinlock held */
218 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg
*hsotg
)
220 int num_channels
= hsotg
->core_params
->host_channels
;
221 struct dwc2_host_chan
*channel
;
225 if (hsotg
->core_params
->dma_enable
<= 0) {
226 /* Flush out any channel requests in slave mode */
227 for (i
= 0; i
< num_channels
; i
++) {
228 channel
= hsotg
->hc_ptr_array
[i
];
229 if (!list_empty(&channel
->hc_list_entry
))
231 hcchar
= dwc2_readl(hsotg
->regs
+ HCCHAR(i
));
232 if (hcchar
& HCCHAR_CHENA
) {
233 hcchar
&= ~(HCCHAR_CHENA
| HCCHAR_EPDIR
);
234 hcchar
|= HCCHAR_CHDIS
;
235 dwc2_writel(hcchar
, hsotg
->regs
+ HCCHAR(i
));
240 for (i
= 0; i
< num_channels
; i
++) {
241 channel
= hsotg
->hc_ptr_array
[i
];
242 if (!list_empty(&channel
->hc_list_entry
))
244 hcchar
= dwc2_readl(hsotg
->regs
+ HCCHAR(i
));
245 if (hcchar
& HCCHAR_CHENA
) {
246 /* Halt the channel */
247 hcchar
|= HCCHAR_CHDIS
;
248 dwc2_writel(hcchar
, hsotg
->regs
+ HCCHAR(i
));
251 dwc2_hc_cleanup(hsotg
, channel
);
252 list_add_tail(&channel
->hc_list_entry
, &hsotg
->free_hc_list
);
254 * Added for Descriptor DMA to prevent channel double cleanup in
255 * release_channel_ddma(), which is called from ep_disable when
260 /* All channels have been freed, mark them available */
261 if (hsotg
->core_params
->uframe_sched
> 0) {
262 hsotg
->available_host_channels
=
263 hsotg
->core_params
->host_channels
;
265 hsotg
->non_periodic_channels
= 0;
266 hsotg
->periodic_channels
= 0;
271 * dwc2_hcd_connect() - Handles connect of the HCD
273 * @hsotg: Pointer to struct dwc2_hsotg
275 * Must be called with interrupt disabled and spinlock held
277 void dwc2_hcd_connect(struct dwc2_hsotg
*hsotg
)
279 if (hsotg
->lx_state
!= DWC2_L0
)
280 usb_hcd_resume_root_hub(hsotg
->priv
);
282 hsotg
->flags
.b
.port_connect_status_change
= 1;
283 hsotg
->flags
.b
.port_connect_status
= 1;
287 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
289 * @hsotg: Pointer to struct dwc2_hsotg
290 * @force: If true, we won't try to reconnect even if we see device connected.
292 * Must be called with interrupt disabled and spinlock held
294 void dwc2_hcd_disconnect(struct dwc2_hsotg
*hsotg
, bool force
)
299 /* Set status flags for the hub driver */
300 hsotg
->flags
.b
.port_connect_status_change
= 1;
301 hsotg
->flags
.b
.port_connect_status
= 0;
304 * Shutdown any transfers in process by clearing the Tx FIFO Empty
305 * interrupt mask and status bits and disabling subsequent host
306 * channel interrupts.
308 intr
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
309 intr
&= ~(GINTSTS_NPTXFEMP
| GINTSTS_PTXFEMP
| GINTSTS_HCHINT
);
310 dwc2_writel(intr
, hsotg
->regs
+ GINTMSK
);
311 intr
= GINTSTS_NPTXFEMP
| GINTSTS_PTXFEMP
| GINTSTS_HCHINT
;
312 dwc2_writel(intr
, hsotg
->regs
+ GINTSTS
);
315 * Turn off the vbus power only if the core has transitioned to device
316 * mode. If still in host mode, need to keep power on to detect a
319 if (dwc2_is_device_mode(hsotg
)) {
320 if (hsotg
->op_state
!= OTG_STATE_A_SUSPEND
) {
321 dev_dbg(hsotg
->dev
, "Disconnect: PortPower off\n");
322 dwc2_writel(0, hsotg
->regs
+ HPRT0
);
325 dwc2_disable_host_interrupts(hsotg
);
328 /* Respond with an error status to all URBs in the schedule */
329 dwc2_kill_all_urbs(hsotg
);
331 if (dwc2_is_host_mode(hsotg
))
332 /* Clean up any host channels that were in use */
333 dwc2_hcd_cleanup_channels(hsotg
);
335 dwc2_host_disconnect(hsotg
);
338 * Add an extra check here to see if we're actually connected but
339 * we don't have a detection interrupt pending. This can happen if:
340 * 1. hardware sees connect
341 * 2. hardware sees disconnect
342 * 3. hardware sees connect
343 * 4. dwc2_port_intr() - clears connect interrupt
344 * 5. dwc2_handle_common_intr() - calls here
346 * Without the extra check here we will end calling disconnect
347 * and won't get any future interrupts to handle the connect.
350 hprt0
= dwc2_readl(hsotg
->regs
+ HPRT0
);
351 if (!(hprt0
& HPRT0_CONNDET
) && (hprt0
& HPRT0_CONNSTS
))
352 dwc2_hcd_connect(hsotg
);
357 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
359 * @hsotg: Pointer to struct dwc2_hsotg
361 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg
*hsotg
)
363 if (hsotg
->bus_suspended
) {
364 hsotg
->flags
.b
.port_suspend_change
= 1;
365 usb_hcd_resume_root_hub(hsotg
->priv
);
368 if (hsotg
->lx_state
== DWC2_L1
)
369 hsotg
->flags
.b
.port_l1_change
= 1;
373 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
375 * @hsotg: Pointer to struct dwc2_hsotg
377 * Must be called with interrupt disabled and spinlock held
379 void dwc2_hcd_stop(struct dwc2_hsotg
*hsotg
)
381 dev_dbg(hsotg
->dev
, "DWC OTG HCD STOP\n");
384 * The root hub should be disconnected before this function is called.
385 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
386 * and the QH lists (via ..._hcd_endpoint_disable).
389 /* Turn off all host-specific interrupts */
390 dwc2_disable_host_interrupts(hsotg
);
392 /* Turn off the vbus power */
393 dev_dbg(hsotg
->dev
, "PortPower off\n");
394 dwc2_writel(0, hsotg
->regs
+ HPRT0
);
397 /* Caller must hold driver lock */
398 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg
*hsotg
,
399 struct dwc2_hcd_urb
*urb
, struct dwc2_qh
*qh
,
400 struct dwc2_qtd
*qtd
)
406 if (!hsotg
->flags
.b
.port_connect_status
) {
407 /* No longer connected */
408 dev_err(hsotg
->dev
, "Not connected\n");
412 dev_speed
= dwc2_host_get_speed(hsotg
, urb
->priv
);
414 /* Some configurations cannot support LS traffic on a FS root port */
415 if ((dev_speed
== USB_SPEED_LOW
) &&
416 (hsotg
->hw_params
.fs_phy_type
== GHWCFG2_FS_PHY_TYPE_DEDICATED
) &&
417 (hsotg
->hw_params
.hs_phy_type
== GHWCFG2_HS_PHY_TYPE_UTMI
)) {
418 u32 hprt0
= dwc2_readl(hsotg
->regs
+ HPRT0
);
419 u32 prtspd
= (hprt0
& HPRT0_SPD_MASK
) >> HPRT0_SPD_SHIFT
;
421 if (prtspd
== HPRT0_SPD_FULL_SPEED
)
428 dwc2_hcd_qtd_init(qtd
, urb
);
429 retval
= dwc2_hcd_qtd_add(hsotg
, qtd
, qh
);
432 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
437 intr_mask
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
438 if (!(intr_mask
& GINTSTS_SOF
)) {
439 enum dwc2_transaction_type tr_type
;
441 if (qtd
->qh
->ep_type
== USB_ENDPOINT_XFER_BULK
&&
442 !(qtd
->urb
->flags
& URB_GIVEBACK_ASAP
))
444 * Do not schedule SG transactions until qtd has
445 * URB_GIVEBACK_ASAP set
449 tr_type
= dwc2_hcd_select_transactions(hsotg
);
450 if (tr_type
!= DWC2_TRANSACTION_NONE
)
451 dwc2_hcd_queue_transactions(hsotg
, tr_type
);
457 /* Must be called with interrupt disabled and spinlock held */
458 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg
*hsotg
,
459 struct dwc2_hcd_urb
*urb
)
462 struct dwc2_qtd
*urb_qtd
;
466 dev_dbg(hsotg
->dev
, "## Urb QTD is NULL ##\n");
472 dev_dbg(hsotg
->dev
, "## Urb QTD QH is NULL ##\n");
478 if (urb_qtd
->in_process
&& qh
->channel
) {
479 dwc2_dump_channel_info(hsotg
, qh
->channel
);
481 /* The QTD is in process (it has been assigned to a channel) */
482 if (hsotg
->flags
.b
.port_connect_status
)
484 * If still connected (i.e. in host mode), halt the
485 * channel so it can be used for other transfers. If
486 * no longer connected, the host registers can't be
487 * written to halt the channel since the core is in
490 dwc2_hc_halt(hsotg
, qh
->channel
,
491 DWC2_HC_XFER_URB_DEQUEUE
);
495 * Free the QTD and clean up the associated QH. Leave the QH in the
496 * schedule if it has any remaining QTDs.
498 if (hsotg
->core_params
->dma_desc_enable
<= 0) {
499 u8 in_process
= urb_qtd
->in_process
;
501 dwc2_hcd_qtd_unlink_and_free(hsotg
, urb_qtd
, qh
);
503 dwc2_hcd_qh_deactivate(hsotg
, qh
, 0);
505 } else if (list_empty(&qh
->qtd_list
)) {
506 dwc2_hcd_qh_unlink(hsotg
, qh
);
509 dwc2_hcd_qtd_unlink_and_free(hsotg
, urb_qtd
, qh
);
515 /* Must NOT be called with interrupt disabled or spinlock held */
516 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg
*hsotg
,
517 struct usb_host_endpoint
*ep
, int retry
)
519 struct dwc2_qtd
*qtd
, *qtd_tmp
;
524 spin_lock_irqsave(&hsotg
->lock
, flags
);
532 while (!list_empty(&qh
->qtd_list
) && retry
--) {
535 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
540 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
541 usleep_range(20000, 40000);
542 spin_lock_irqsave(&hsotg
->lock
, flags
);
550 dwc2_hcd_qh_unlink(hsotg
, qh
);
552 /* Free each QTD in the QH's QTD list */
553 list_for_each_entry_safe(qtd
, qtd_tmp
, &qh
->qtd_list
, qtd_list_entry
)
554 dwc2_hcd_qtd_unlink_and_free(hsotg
, qtd
, qh
);
557 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
558 dwc2_hcd_qh_free(hsotg
, qh
);
564 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
569 /* Must be called with interrupt disabled and spinlock held */
570 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg
*hsotg
,
571 struct usb_host_endpoint
*ep
)
573 struct dwc2_qh
*qh
= ep
->hcpriv
;
578 qh
->data_toggle
= DWC2_HC_PID_DATA0
;
584 * Initializes dynamic portions of the DWC_otg HCD state
586 * Must be called with interrupt disabled and spinlock held
588 static void dwc2_hcd_reinit(struct dwc2_hsotg
*hsotg
)
590 struct dwc2_host_chan
*chan
, *chan_tmp
;
594 hsotg
->flags
.d32
= 0;
595 hsotg
->non_periodic_qh_ptr
= &hsotg
->non_periodic_sched_active
;
597 if (hsotg
->core_params
->uframe_sched
> 0) {
598 hsotg
->available_host_channels
=
599 hsotg
->core_params
->host_channels
;
601 hsotg
->non_periodic_channels
= 0;
602 hsotg
->periodic_channels
= 0;
606 * Put all channels in the free channel list and clean up channel
609 list_for_each_entry_safe(chan
, chan_tmp
, &hsotg
->free_hc_list
,
611 list_del_init(&chan
->hc_list_entry
);
613 num_channels
= hsotg
->core_params
->host_channels
;
614 for (i
= 0; i
< num_channels
; i
++) {
615 chan
= hsotg
->hc_ptr_array
[i
];
616 list_add_tail(&chan
->hc_list_entry
, &hsotg
->free_hc_list
);
617 dwc2_hc_cleanup(hsotg
, chan
);
620 /* Initialize the DWC core for host mode operation */
621 dwc2_core_host_init(hsotg
);
624 static void dwc2_hc_init_split(struct dwc2_hsotg
*hsotg
,
625 struct dwc2_host_chan
*chan
,
626 struct dwc2_qtd
*qtd
, struct dwc2_hcd_urb
*urb
)
628 int hub_addr
, hub_port
;
631 chan
->xact_pos
= qtd
->isoc_split_pos
;
632 chan
->complete_split
= qtd
->complete_split
;
633 dwc2_host_hub_info(hsotg
, urb
->priv
, &hub_addr
, &hub_port
);
634 chan
->hub_addr
= (u8
)hub_addr
;
635 chan
->hub_port
= (u8
)hub_port
;
638 static void *dwc2_hc_init_xfer(struct dwc2_hsotg
*hsotg
,
639 struct dwc2_host_chan
*chan
,
640 struct dwc2_qtd
*qtd
, void *bufptr
)
642 struct dwc2_hcd_urb
*urb
= qtd
->urb
;
643 struct dwc2_hcd_iso_packet_desc
*frame_desc
;
645 switch (dwc2_hcd_get_pipe_type(&urb
->pipe_info
)) {
646 case USB_ENDPOINT_XFER_CONTROL
:
647 chan
->ep_type
= USB_ENDPOINT_XFER_CONTROL
;
649 switch (qtd
->control_phase
) {
650 case DWC2_CONTROL_SETUP
:
651 dev_vdbg(hsotg
->dev
, " Control setup transaction\n");
654 chan
->data_pid_start
= DWC2_HC_PID_SETUP
;
655 if (hsotg
->core_params
->dma_enable
> 0)
656 chan
->xfer_dma
= urb
->setup_dma
;
658 chan
->xfer_buf
= urb
->setup_packet
;
663 case DWC2_CONTROL_DATA
:
664 dev_vdbg(hsotg
->dev
, " Control data transaction\n");
665 chan
->data_pid_start
= qtd
->data_toggle
;
668 case DWC2_CONTROL_STATUS
:
670 * Direction is opposite of data direction or IN if no
673 dev_vdbg(hsotg
->dev
, " Control status transaction\n");
674 if (urb
->length
== 0)
678 dwc2_hcd_is_pipe_out(&urb
->pipe_info
);
681 chan
->data_pid_start
= DWC2_HC_PID_DATA1
;
683 if (hsotg
->core_params
->dma_enable
> 0)
684 chan
->xfer_dma
= hsotg
->status_buf_dma
;
686 chan
->xfer_buf
= hsotg
->status_buf
;
692 case USB_ENDPOINT_XFER_BULK
:
693 chan
->ep_type
= USB_ENDPOINT_XFER_BULK
;
696 case USB_ENDPOINT_XFER_INT
:
697 chan
->ep_type
= USB_ENDPOINT_XFER_INT
;
700 case USB_ENDPOINT_XFER_ISOC
:
701 chan
->ep_type
= USB_ENDPOINT_XFER_ISOC
;
702 if (hsotg
->core_params
->dma_desc_enable
> 0)
705 frame_desc
= &urb
->iso_descs
[qtd
->isoc_frame_index
];
706 frame_desc
->status
= 0;
708 if (hsotg
->core_params
->dma_enable
> 0) {
709 chan
->xfer_dma
= urb
->dma
;
710 chan
->xfer_dma
+= frame_desc
->offset
+
711 qtd
->isoc_split_offset
;
713 chan
->xfer_buf
= urb
->buf
;
714 chan
->xfer_buf
+= frame_desc
->offset
+
715 qtd
->isoc_split_offset
;
718 chan
->xfer_len
= frame_desc
->length
- qtd
->isoc_split_offset
;
720 /* For non-dword aligned buffers */
721 if (hsotg
->core_params
->dma_enable
> 0 &&
722 (chan
->xfer_dma
& 0x3))
723 bufptr
= (u8
*)urb
->buf
+ frame_desc
->offset
+
724 qtd
->isoc_split_offset
;
728 if (chan
->xact_pos
== DWC2_HCSPLT_XACTPOS_ALL
) {
729 if (chan
->xfer_len
<= 188)
730 chan
->xact_pos
= DWC2_HCSPLT_XACTPOS_ALL
;
732 chan
->xact_pos
= DWC2_HCSPLT_XACTPOS_BEGIN
;
740 static int dwc2_hc_setup_align_buf(struct dwc2_hsotg
*hsotg
, struct dwc2_qh
*qh
,
741 struct dwc2_host_chan
*chan
,
742 struct dwc2_hcd_urb
*urb
, void *bufptr
)
748 if (!qh
->dw_align_buf
) {
749 if (chan
->ep_type
!= USB_ENDPOINT_XFER_ISOC
)
750 buf_size
= hsotg
->core_params
->max_transfer_size
;
752 /* 3072 = 3 max-size Isoc packets */
755 qh
->dw_align_buf
= kmalloc(buf_size
, GFP_ATOMIC
| GFP_DMA
);
756 if (!qh
->dw_align_buf
)
758 qh
->dw_align_buf_size
= buf_size
;
761 if (chan
->xfer_len
) {
762 dev_vdbg(hsotg
->dev
, "%s(): non-aligned buffer\n", __func__
);
766 if (usb_urb
->transfer_flags
&
767 (URB_SETUP_MAP_SINGLE
| URB_DMA_MAP_SG
|
768 URB_DMA_MAP_PAGE
| URB_DMA_MAP_SINGLE
)) {
769 hcd
= dwc2_hsotg_to_hcd(hsotg
);
770 usb_hcd_unmap_urb_for_dma(hcd
, usb_urb
);
773 memcpy(qh
->dw_align_buf
, bufptr
,
776 dev_warn(hsotg
->dev
, "no URB in dwc2_urb\n");
780 qh
->dw_align_buf_dma
= dma_map_single(hsotg
->dev
,
781 qh
->dw_align_buf
, qh
->dw_align_buf_size
,
782 chan
->ep_is_in
? DMA_FROM_DEVICE
: DMA_TO_DEVICE
);
783 if (dma_mapping_error(hsotg
->dev
, qh
->dw_align_buf_dma
)) {
784 dev_err(hsotg
->dev
, "can't map align_buf\n");
789 chan
->align_buf
= qh
->dw_align_buf_dma
;
794 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
795 * channel and initializes the host channel to perform the transactions. The
796 * host channel is removed from the free list.
798 * @hsotg: The HCD state structure
799 * @qh: Transactions from the first QTD for this QH are selected and assigned
800 * to a free host channel
802 static int dwc2_assign_and_init_hc(struct dwc2_hsotg
*hsotg
, struct dwc2_qh
*qh
)
804 struct dwc2_host_chan
*chan
;
805 struct dwc2_hcd_urb
*urb
;
806 struct dwc2_qtd
*qtd
;
810 dev_vdbg(hsotg
->dev
, "%s(%p,%p)\n", __func__
, hsotg
, qh
);
812 if (list_empty(&qh
->qtd_list
)) {
813 dev_dbg(hsotg
->dev
, "No QTDs in QH list\n");
817 if (list_empty(&hsotg
->free_hc_list
)) {
818 dev_dbg(hsotg
->dev
, "No free channel to assign\n");
822 chan
= list_first_entry(&hsotg
->free_hc_list
, struct dwc2_host_chan
,
825 /* Remove host channel from free list */
826 list_del_init(&chan
->hc_list_entry
);
828 qtd
= list_first_entry(&qh
->qtd_list
, struct dwc2_qtd
, qtd_list_entry
);
834 * Use usb_pipedevice to determine device address. This address is
835 * 0 before the SET_ADDRESS command and the correct address afterward.
837 chan
->dev_addr
= dwc2_hcd_get_dev_addr(&urb
->pipe_info
);
838 chan
->ep_num
= dwc2_hcd_get_ep_num(&urb
->pipe_info
);
839 chan
->speed
= qh
->dev_speed
;
840 chan
->max_packet
= dwc2_max_packet(qh
->maxp
);
842 chan
->xfer_started
= 0;
843 chan
->halt_status
= DWC2_HC_XFER_NO_HALT_STATUS
;
844 chan
->error_state
= (qtd
->error_count
> 0);
845 chan
->halt_on_queue
= 0;
846 chan
->halt_pending
= 0;
850 * The following values may be modified in the transfer type section
851 * below. The xfer_len value may be reduced when the transfer is
852 * started to accommodate the max widths of the XferSize and PktCnt
853 * fields in the HCTSIZn register.
856 chan
->ep_is_in
= (dwc2_hcd_is_pipe_in(&urb
->pipe_info
) != 0);
860 chan
->do_ping
= qh
->ping_state
;
862 chan
->data_pid_start
= qh
->data_toggle
;
863 chan
->multi_count
= 1;
865 if (urb
->actual_length
> urb
->length
&&
866 !dwc2_hcd_is_pipe_in(&urb
->pipe_info
))
867 urb
->actual_length
= urb
->length
;
869 if (hsotg
->core_params
->dma_enable
> 0) {
870 chan
->xfer_dma
= urb
->dma
+ urb
->actual_length
;
872 /* For non-dword aligned case */
873 if (hsotg
->core_params
->dma_desc_enable
<= 0 &&
874 (chan
->xfer_dma
& 0x3))
875 bufptr
= (u8
*)urb
->buf
+ urb
->actual_length
;
877 chan
->xfer_buf
= (u8
*)urb
->buf
+ urb
->actual_length
;
880 chan
->xfer_len
= urb
->length
- urb
->actual_length
;
881 chan
->xfer_count
= 0;
883 /* Set the split attributes if required */
885 dwc2_hc_init_split(hsotg
, chan
, qtd
, urb
);
889 /* Set the transfer attributes */
890 bufptr
= dwc2_hc_init_xfer(hsotg
, chan
, qtd
, bufptr
);
892 /* Non DWORD-aligned buffer case */
894 dev_vdbg(hsotg
->dev
, "Non-aligned buffer\n");
895 if (dwc2_hc_setup_align_buf(hsotg
, qh
, chan
, urb
, bufptr
)) {
897 "%s: Failed to allocate memory to handle non-dword aligned buffer\n",
899 /* Add channel back to free list */
901 chan
->multi_count
= 0;
902 list_add_tail(&chan
->hc_list_entry
,
903 &hsotg
->free_hc_list
);
912 if (chan
->ep_type
== USB_ENDPOINT_XFER_INT
||
913 chan
->ep_type
== USB_ENDPOINT_XFER_ISOC
)
915 * This value may be modified when the transfer is started
916 * to reflect the actual transfer length
918 chan
->multi_count
= dwc2_hb_mult(qh
->maxp
);
920 if (hsotg
->core_params
->dma_desc_enable
> 0) {
921 chan
->desc_list_addr
= qh
->desc_list_dma
;
922 chan
->desc_list_sz
= qh
->desc_list_sz
;
925 dwc2_hc_init(hsotg
, chan
);
932 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
933 * schedule and assigns them to available host channels. Called from the HCD
934 * interrupt handler functions.
936 * @hsotg: The HCD state structure
938 * Return: The types of new transactions that were assigned to host channels
940 enum dwc2_transaction_type
dwc2_hcd_select_transactions(
941 struct dwc2_hsotg
*hsotg
)
943 enum dwc2_transaction_type ret_val
= DWC2_TRANSACTION_NONE
;
944 struct list_head
*qh_ptr
;
948 #ifdef DWC2_DEBUG_SOF
949 dev_vdbg(hsotg
->dev
, " Select Transactions\n");
952 /* Process entries in the periodic ready list */
953 qh_ptr
= hsotg
->periodic_sched_ready
.next
;
954 while (qh_ptr
!= &hsotg
->periodic_sched_ready
) {
955 if (list_empty(&hsotg
->free_hc_list
))
957 if (hsotg
->core_params
->uframe_sched
> 0) {
958 if (hsotg
->available_host_channels
<= 1)
960 hsotg
->available_host_channels
--;
962 qh
= list_entry(qh_ptr
, struct dwc2_qh
, qh_list_entry
);
963 if (dwc2_assign_and_init_hc(hsotg
, qh
))
967 * Move the QH from the periodic ready schedule to the
968 * periodic assigned schedule
970 qh_ptr
= qh_ptr
->next
;
971 list_move(&qh
->qh_list_entry
, &hsotg
->periodic_sched_assigned
);
972 ret_val
= DWC2_TRANSACTION_PERIODIC
;
976 * Process entries in the inactive portion of the non-periodic
977 * schedule. Some free host channels may not be used if they are
978 * reserved for periodic transfers.
980 num_channels
= hsotg
->core_params
->host_channels
;
981 qh_ptr
= hsotg
->non_periodic_sched_inactive
.next
;
982 while (qh_ptr
!= &hsotg
->non_periodic_sched_inactive
) {
983 if (hsotg
->core_params
->uframe_sched
<= 0 &&
984 hsotg
->non_periodic_channels
>= num_channels
-
985 hsotg
->periodic_channels
)
987 if (list_empty(&hsotg
->free_hc_list
))
989 qh
= list_entry(qh_ptr
, struct dwc2_qh
, qh_list_entry
);
990 if (hsotg
->core_params
->uframe_sched
> 0) {
991 if (hsotg
->available_host_channels
< 1)
993 hsotg
->available_host_channels
--;
996 if (dwc2_assign_and_init_hc(hsotg
, qh
))
1000 * Move the QH from the non-periodic inactive schedule to the
1001 * non-periodic active schedule
1003 qh_ptr
= qh_ptr
->next
;
1004 list_move(&qh
->qh_list_entry
,
1005 &hsotg
->non_periodic_sched_active
);
1007 if (ret_val
== DWC2_TRANSACTION_NONE
)
1008 ret_val
= DWC2_TRANSACTION_NON_PERIODIC
;
1010 ret_val
= DWC2_TRANSACTION_ALL
;
1012 if (hsotg
->core_params
->uframe_sched
<= 0)
1013 hsotg
->non_periodic_channels
++;
1020 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
1021 * a host channel associated with either a periodic or non-periodic transfer
1023 * @hsotg: The HCD state structure
1024 * @chan: Host channel descriptor associated with either a periodic or
1025 * non-periodic transfer
1026 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
1027 * for periodic transfers or the non-periodic Tx FIFO
1028 * for non-periodic transfers
1030 * Return: 1 if a request is queued and more requests may be needed to
1031 * complete the transfer, 0 if no more requests are required for this
1032 * transfer, -1 if there is insufficient space in the Tx FIFO
1034 * This function assumes that there is space available in the appropriate
1035 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
1036 * it checks whether space is available in the appropriate Tx FIFO.
1038 * Must be called with interrupt disabled and spinlock held
1040 static int dwc2_queue_transaction(struct dwc2_hsotg
*hsotg
,
1041 struct dwc2_host_chan
*chan
,
1042 u16 fifo_dwords_avail
)
1046 if (hsotg
->core_params
->dma_enable
> 0) {
1047 if (hsotg
->core_params
->dma_desc_enable
> 0) {
1048 if (!chan
->xfer_started
||
1049 chan
->ep_type
== USB_ENDPOINT_XFER_ISOC
) {
1050 dwc2_hcd_start_xfer_ddma(hsotg
, chan
->qh
);
1051 chan
->qh
->ping_state
= 0;
1053 } else if (!chan
->xfer_started
) {
1054 dwc2_hc_start_transfer(hsotg
, chan
);
1055 chan
->qh
->ping_state
= 0;
1057 } else if (chan
->halt_pending
) {
1058 /* Don't queue a request if the channel has been halted */
1059 } else if (chan
->halt_on_queue
) {
1060 dwc2_hc_halt(hsotg
, chan
, chan
->halt_status
);
1061 } else if (chan
->do_ping
) {
1062 if (!chan
->xfer_started
)
1063 dwc2_hc_start_transfer(hsotg
, chan
);
1064 } else if (!chan
->ep_is_in
||
1065 chan
->data_pid_start
== DWC2_HC_PID_SETUP
) {
1066 if ((fifo_dwords_avail
* 4) >= chan
->max_packet
) {
1067 if (!chan
->xfer_started
) {
1068 dwc2_hc_start_transfer(hsotg
, chan
);
1071 retval
= dwc2_hc_continue_transfer(hsotg
, chan
);
1077 if (!chan
->xfer_started
) {
1078 dwc2_hc_start_transfer(hsotg
, chan
);
1081 retval
= dwc2_hc_continue_transfer(hsotg
, chan
);
1089 * Processes periodic channels for the next frame and queues transactions for
1090 * these channels to the DWC_otg controller. After queueing transactions, the
1091 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1092 * to queue as Periodic Tx FIFO or request queue space becomes available.
1093 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1095 * Must be called with interrupt disabled and spinlock held
1097 static void dwc2_process_periodic_channels(struct dwc2_hsotg
*hsotg
)
1099 struct list_head
*qh_ptr
;
1105 int no_queue_space
= 0;
1106 int no_fifo_space
= 0;
1110 dev_vdbg(hsotg
->dev
, "Queue periodic transactions\n");
1112 tx_status
= dwc2_readl(hsotg
->regs
+ HPTXSTS
);
1113 qspcavail
= (tx_status
& TXSTS_QSPCAVAIL_MASK
) >>
1114 TXSTS_QSPCAVAIL_SHIFT
;
1115 fspcavail
= (tx_status
& TXSTS_FSPCAVAIL_MASK
) >>
1116 TXSTS_FSPCAVAIL_SHIFT
;
1119 dev_vdbg(hsotg
->dev
, " P Tx Req Queue Space Avail (before queue): %d\n",
1121 dev_vdbg(hsotg
->dev
, " P Tx FIFO Space Avail (before queue): %d\n",
1125 qh_ptr
= hsotg
->periodic_sched_assigned
.next
;
1126 while (qh_ptr
!= &hsotg
->periodic_sched_assigned
) {
1127 tx_status
= dwc2_readl(hsotg
->regs
+ HPTXSTS
);
1128 qspcavail
= (tx_status
& TXSTS_QSPCAVAIL_MASK
) >>
1129 TXSTS_QSPCAVAIL_SHIFT
;
1130 if (qspcavail
== 0) {
1135 qh
= list_entry(qh_ptr
, struct dwc2_qh
, qh_list_entry
);
1137 qh_ptr
= qh_ptr
->next
;
1141 /* Make sure EP's TT buffer is clean before queueing qtds */
1142 if (qh
->tt_buffer_dirty
) {
1143 qh_ptr
= qh_ptr
->next
;
1148 * Set a flag if we're queuing high-bandwidth in slave mode.
1149 * The flag prevents any halts to get into the request queue in
1150 * the middle of multiple high-bandwidth packets getting queued.
1152 if (hsotg
->core_params
->dma_enable
<= 0 &&
1153 qh
->channel
->multi_count
> 1)
1154 hsotg
->queuing_high_bandwidth
= 1;
1156 fspcavail
= (tx_status
& TXSTS_FSPCAVAIL_MASK
) >>
1157 TXSTS_FSPCAVAIL_SHIFT
;
1158 status
= dwc2_queue_transaction(hsotg
, qh
->channel
, fspcavail
);
1165 * In Slave mode, stay on the current transfer until there is
1166 * nothing more to do or the high-bandwidth request count is
1167 * reached. In DMA mode, only need to queue one request. The
1168 * controller automatically handles multiple packets for
1169 * high-bandwidth transfers.
1171 if (hsotg
->core_params
->dma_enable
> 0 || status
== 0 ||
1172 qh
->channel
->requests
== qh
->channel
->multi_count
) {
1173 qh_ptr
= qh_ptr
->next
;
1175 * Move the QH from the periodic assigned schedule to
1176 * the periodic queued schedule
1178 list_move(&qh
->qh_list_entry
,
1179 &hsotg
->periodic_sched_queued
);
1181 /* done queuing high bandwidth */
1182 hsotg
->queuing_high_bandwidth
= 0;
1186 if (hsotg
->core_params
->dma_enable
<= 0) {
1187 tx_status
= dwc2_readl(hsotg
->regs
+ HPTXSTS
);
1188 qspcavail
= (tx_status
& TXSTS_QSPCAVAIL_MASK
) >>
1189 TXSTS_QSPCAVAIL_SHIFT
;
1190 fspcavail
= (tx_status
& TXSTS_FSPCAVAIL_MASK
) >>
1191 TXSTS_FSPCAVAIL_SHIFT
;
1193 dev_vdbg(hsotg
->dev
,
1194 " P Tx Req Queue Space Avail (after queue): %d\n",
1196 dev_vdbg(hsotg
->dev
,
1197 " P Tx FIFO Space Avail (after queue): %d\n",
1201 if (!list_empty(&hsotg
->periodic_sched_assigned
) ||
1202 no_queue_space
|| no_fifo_space
) {
1204 * May need to queue more transactions as the request
1205 * queue or Tx FIFO empties. Enable the periodic Tx
1206 * FIFO empty interrupt. (Always use the half-empty
1207 * level to ensure that new requests are loaded as
1208 * soon as possible.)
1210 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
1211 gintmsk
|= GINTSTS_PTXFEMP
;
1212 dwc2_writel(gintmsk
, hsotg
->regs
+ GINTMSK
);
1215 * Disable the Tx FIFO empty interrupt since there are
1216 * no more transactions that need to be queued right
1217 * now. This function is called from interrupt
1218 * handlers to queue more transactions as transfer
1221 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
1222 gintmsk
&= ~GINTSTS_PTXFEMP
;
1223 dwc2_writel(gintmsk
, hsotg
->regs
+ GINTMSK
);
1229 * Processes active non-periodic channels and queues transactions for these
1230 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1231 * FIFO Empty interrupt is enabled if there are more transactions to queue as
1232 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1233 * FIFO Empty interrupt is disabled.
1235 * Must be called with interrupt disabled and spinlock held
1237 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg
*hsotg
)
1239 struct list_head
*orig_qh_ptr
;
1246 int no_queue_space
= 0;
1247 int no_fifo_space
= 0;
1250 dev_vdbg(hsotg
->dev
, "Queue non-periodic transactions\n");
1252 tx_status
= dwc2_readl(hsotg
->regs
+ GNPTXSTS
);
1253 qspcavail
= (tx_status
& TXSTS_QSPCAVAIL_MASK
) >>
1254 TXSTS_QSPCAVAIL_SHIFT
;
1255 fspcavail
= (tx_status
& TXSTS_FSPCAVAIL_MASK
) >>
1256 TXSTS_FSPCAVAIL_SHIFT
;
1257 dev_vdbg(hsotg
->dev
, " NP Tx Req Queue Space Avail (before queue): %d\n",
1259 dev_vdbg(hsotg
->dev
, " NP Tx FIFO Space Avail (before queue): %d\n",
1263 * Keep track of the starting point. Skip over the start-of-list
1266 if (hsotg
->non_periodic_qh_ptr
== &hsotg
->non_periodic_sched_active
)
1267 hsotg
->non_periodic_qh_ptr
= hsotg
->non_periodic_qh_ptr
->next
;
1268 orig_qh_ptr
= hsotg
->non_periodic_qh_ptr
;
1271 * Process once through the active list or until no more space is
1272 * available in the request queue or the Tx FIFO
1275 tx_status
= dwc2_readl(hsotg
->regs
+ GNPTXSTS
);
1276 qspcavail
= (tx_status
& TXSTS_QSPCAVAIL_MASK
) >>
1277 TXSTS_QSPCAVAIL_SHIFT
;
1278 if (hsotg
->core_params
->dma_enable
<= 0 && qspcavail
== 0) {
1283 qh
= list_entry(hsotg
->non_periodic_qh_ptr
, struct dwc2_qh
,
1288 /* Make sure EP's TT buffer is clean before queueing qtds */
1289 if (qh
->tt_buffer_dirty
)
1292 fspcavail
= (tx_status
& TXSTS_FSPCAVAIL_MASK
) >>
1293 TXSTS_FSPCAVAIL_SHIFT
;
1294 status
= dwc2_queue_transaction(hsotg
, qh
->channel
, fspcavail
);
1298 } else if (status
< 0) {
1303 /* Advance to next QH, skipping start-of-list entry */
1304 hsotg
->non_periodic_qh_ptr
= hsotg
->non_periodic_qh_ptr
->next
;
1305 if (hsotg
->non_periodic_qh_ptr
==
1306 &hsotg
->non_periodic_sched_active
)
1307 hsotg
->non_periodic_qh_ptr
=
1308 hsotg
->non_periodic_qh_ptr
->next
;
1309 } while (hsotg
->non_periodic_qh_ptr
!= orig_qh_ptr
);
1311 if (hsotg
->core_params
->dma_enable
<= 0) {
1312 tx_status
= dwc2_readl(hsotg
->regs
+ GNPTXSTS
);
1313 qspcavail
= (tx_status
& TXSTS_QSPCAVAIL_MASK
) >>
1314 TXSTS_QSPCAVAIL_SHIFT
;
1315 fspcavail
= (tx_status
& TXSTS_FSPCAVAIL_MASK
) >>
1316 TXSTS_FSPCAVAIL_SHIFT
;
1317 dev_vdbg(hsotg
->dev
,
1318 " NP Tx Req Queue Space Avail (after queue): %d\n",
1320 dev_vdbg(hsotg
->dev
,
1321 " NP Tx FIFO Space Avail (after queue): %d\n",
1324 if (more_to_do
|| no_queue_space
|| no_fifo_space
) {
1326 * May need to queue more transactions as the request
1327 * queue or Tx FIFO empties. Enable the non-periodic
1328 * Tx FIFO empty interrupt. (Always use the half-empty
1329 * level to ensure that new requests are loaded as
1330 * soon as possible.)
1332 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
1333 gintmsk
|= GINTSTS_NPTXFEMP
;
1334 dwc2_writel(gintmsk
, hsotg
->regs
+ GINTMSK
);
1337 * Disable the Tx FIFO empty interrupt since there are
1338 * no more transactions that need to be queued right
1339 * now. This function is called from interrupt
1340 * handlers to queue more transactions as transfer
1343 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
1344 gintmsk
&= ~GINTSTS_NPTXFEMP
;
1345 dwc2_writel(gintmsk
, hsotg
->regs
+ GINTMSK
);
1351 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
1352 * and queues transactions for these channels to the DWC_otg controller. Called
1353 * from the HCD interrupt handler functions.
1355 * @hsotg: The HCD state structure
1356 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
1359 * Must be called with interrupt disabled and spinlock held
1361 void dwc2_hcd_queue_transactions(struct dwc2_hsotg
*hsotg
,
1362 enum dwc2_transaction_type tr_type
)
1364 #ifdef DWC2_DEBUG_SOF
1365 dev_vdbg(hsotg
->dev
, "Queue Transactions\n");
1367 /* Process host channels associated with periodic transfers */
1368 if ((tr_type
== DWC2_TRANSACTION_PERIODIC
||
1369 tr_type
== DWC2_TRANSACTION_ALL
) &&
1370 !list_empty(&hsotg
->periodic_sched_assigned
))
1371 dwc2_process_periodic_channels(hsotg
);
1373 /* Process host channels associated with non-periodic transfers */
1374 if (tr_type
== DWC2_TRANSACTION_NON_PERIODIC
||
1375 tr_type
== DWC2_TRANSACTION_ALL
) {
1376 if (!list_empty(&hsotg
->non_periodic_sched_active
)) {
1377 dwc2_process_non_periodic_channels(hsotg
);
1380 * Ensure NP Tx FIFO empty interrupt is disabled when
1381 * there are no non-periodic transfers to process
1383 u32 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
1385 gintmsk
&= ~GINTSTS_NPTXFEMP
;
1386 dwc2_writel(gintmsk
, hsotg
->regs
+ GINTMSK
);
1391 static void dwc2_conn_id_status_change(struct work_struct
*work
)
1393 struct dwc2_hsotg
*hsotg
= container_of(work
, struct dwc2_hsotg
,
1397 unsigned long flags
;
1399 dev_dbg(hsotg
->dev
, "%s()\n", __func__
);
1401 gotgctl
= dwc2_readl(hsotg
->regs
+ GOTGCTL
);
1402 dev_dbg(hsotg
->dev
, "gotgctl=%0x\n", gotgctl
);
1403 dev_dbg(hsotg
->dev
, "gotgctl.b.conidsts=%d\n",
1404 !!(gotgctl
& GOTGCTL_CONID_B
));
1406 /* B-Device connector (Device Mode) */
1407 if (gotgctl
& GOTGCTL_CONID_B
) {
1408 /* Wait for switch to device mode */
1409 dev_dbg(hsotg
->dev
, "connId B\n");
1410 while (!dwc2_is_device_mode(hsotg
)) {
1411 dev_info(hsotg
->dev
,
1412 "Waiting for Peripheral Mode, Mode=%s\n",
1413 dwc2_is_host_mode(hsotg
) ? "Host" :
1415 usleep_range(20000, 40000);
1421 "Connection id status change timed out\n");
1422 hsotg
->op_state
= OTG_STATE_B_PERIPHERAL
;
1423 dwc2_core_init(hsotg
, false);
1424 dwc2_enable_global_interrupts(hsotg
);
1425 spin_lock_irqsave(&hsotg
->lock
, flags
);
1426 dwc2_hsotg_core_init_disconnected(hsotg
, false);
1427 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
1428 dwc2_hsotg_core_connect(hsotg
);
1430 /* A-Device connector (Host Mode) */
1431 dev_dbg(hsotg
->dev
, "connId A\n");
1432 while (!dwc2_is_host_mode(hsotg
)) {
1433 dev_info(hsotg
->dev
, "Waiting for Host Mode, Mode=%s\n",
1434 dwc2_is_host_mode(hsotg
) ?
1435 "Host" : "Peripheral");
1436 usleep_range(20000, 40000);
1442 "Connection id status change timed out\n");
1443 hsotg
->op_state
= OTG_STATE_A_HOST
;
1445 /* Initialize the Core for Host mode */
1446 dwc2_core_init(hsotg
, false);
1447 dwc2_enable_global_interrupts(hsotg
);
1448 dwc2_hcd_start(hsotg
);
1452 static void dwc2_wakeup_detected(unsigned long data
)
1454 struct dwc2_hsotg
*hsotg
= (struct dwc2_hsotg
*)data
;
1457 dev_dbg(hsotg
->dev
, "%s()\n", __func__
);
1460 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
1461 * so that OPT tests pass with all PHYs.)
1463 hprt0
= dwc2_read_hprt0(hsotg
);
1464 dev_dbg(hsotg
->dev
, "Resume: HPRT0=%0x\n", hprt0
);
1465 hprt0
&= ~HPRT0_RES
;
1466 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
1467 dev_dbg(hsotg
->dev
, "Clear Resume: HPRT0=%0x\n",
1468 dwc2_readl(hsotg
->regs
+ HPRT0
));
1470 dwc2_hcd_rem_wakeup(hsotg
);
1471 hsotg
->bus_suspended
= 0;
1473 /* Change to L0 state */
1474 hsotg
->lx_state
= DWC2_L0
;
1477 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg
*hsotg
)
1479 struct usb_hcd
*hcd
= dwc2_hsotg_to_hcd(hsotg
);
1481 return hcd
->self
.b_hnp_enable
;
1484 /* Must NOT be called with interrupt disabled or spinlock held */
1485 static void dwc2_port_suspend(struct dwc2_hsotg
*hsotg
, u16 windex
)
1487 unsigned long flags
;
1492 dev_dbg(hsotg
->dev
, "%s()\n", __func__
);
1494 spin_lock_irqsave(&hsotg
->lock
, flags
);
1496 if (windex
== hsotg
->otg_port
&& dwc2_host_is_b_hnp_enabled(hsotg
)) {
1497 gotgctl
= dwc2_readl(hsotg
->regs
+ GOTGCTL
);
1498 gotgctl
|= GOTGCTL_HSTSETHNPEN
;
1499 dwc2_writel(gotgctl
, hsotg
->regs
+ GOTGCTL
);
1500 hsotg
->op_state
= OTG_STATE_A_SUSPEND
;
1503 hprt0
= dwc2_read_hprt0(hsotg
);
1504 hprt0
|= HPRT0_SUSP
;
1505 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
1507 hsotg
->bus_suspended
= 1;
1510 * If hibernation is supported, Phy clock will be suspended
1511 * after registers are backuped.
1513 if (!hsotg
->core_params
->hibernation
) {
1514 /* Suspend the Phy Clock */
1515 pcgctl
= dwc2_readl(hsotg
->regs
+ PCGCTL
);
1516 pcgctl
|= PCGCTL_STOPPCLK
;
1517 dwc2_writel(pcgctl
, hsotg
->regs
+ PCGCTL
);
1521 /* For HNP the bus must be suspended for at least 200ms */
1522 if (dwc2_host_is_b_hnp_enabled(hsotg
)) {
1523 pcgctl
= dwc2_readl(hsotg
->regs
+ PCGCTL
);
1524 pcgctl
&= ~PCGCTL_STOPPCLK
;
1525 dwc2_writel(pcgctl
, hsotg
->regs
+ PCGCTL
);
1527 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
1529 usleep_range(200000, 250000);
1531 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
1535 /* Must NOT be called with interrupt disabled or spinlock held */
1536 static void dwc2_port_resume(struct dwc2_hsotg
*hsotg
)
1538 unsigned long flags
;
1542 spin_lock_irqsave(&hsotg
->lock
, flags
);
1545 * If hibernation is supported, Phy clock is already resumed
1546 * after registers restore.
1548 if (!hsotg
->core_params
->hibernation
) {
1549 pcgctl
= dwc2_readl(hsotg
->regs
+ PCGCTL
);
1550 pcgctl
&= ~PCGCTL_STOPPCLK
;
1551 dwc2_writel(pcgctl
, hsotg
->regs
+ PCGCTL
);
1552 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
1553 usleep_range(20000, 40000);
1554 spin_lock_irqsave(&hsotg
->lock
, flags
);
1557 hprt0
= dwc2_read_hprt0(hsotg
);
1559 hprt0
&= ~HPRT0_SUSP
;
1560 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
1561 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
1563 msleep(USB_RESUME_TIMEOUT
);
1565 spin_lock_irqsave(&hsotg
->lock
, flags
);
1566 hprt0
= dwc2_read_hprt0(hsotg
);
1567 hprt0
&= ~(HPRT0_RES
| HPRT0_SUSP
);
1568 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
1569 hsotg
->bus_suspended
= 0;
1570 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
1573 /* Handles hub class-specific requests */
1574 static int dwc2_hcd_hub_control(struct dwc2_hsotg
*hsotg
, u16 typereq
,
1575 u16 wvalue
, u16 windex
, char *buf
, u16 wlength
)
1577 struct usb_hub_descriptor
*hub_desc
;
1585 case ClearHubFeature
:
1586 dev_dbg(hsotg
->dev
, "ClearHubFeature %1xh\n", wvalue
);
1589 case C_HUB_LOCAL_POWER
:
1590 case C_HUB_OVER_CURRENT
:
1591 /* Nothing required here */
1597 "ClearHubFeature request %1xh unknown\n",
1602 case ClearPortFeature
:
1603 if (wvalue
!= USB_PORT_FEAT_L1
)
1604 if (!windex
|| windex
> 1)
1607 case USB_PORT_FEAT_ENABLE
:
1609 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
1610 hprt0
= dwc2_read_hprt0(hsotg
);
1612 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
1615 case USB_PORT_FEAT_SUSPEND
:
1617 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
1619 if (hsotg
->bus_suspended
)
1620 dwc2_port_resume(hsotg
);
1623 case USB_PORT_FEAT_POWER
:
1625 "ClearPortFeature USB_PORT_FEAT_POWER\n");
1626 hprt0
= dwc2_read_hprt0(hsotg
);
1627 hprt0
&= ~HPRT0_PWR
;
1628 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
1631 case USB_PORT_FEAT_INDICATOR
:
1633 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
1634 /* Port indicator not supported */
1637 case USB_PORT_FEAT_C_CONNECTION
:
1639 * Clears driver's internal Connect Status Change flag
1642 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
1643 hsotg
->flags
.b
.port_connect_status_change
= 0;
1646 case USB_PORT_FEAT_C_RESET
:
1647 /* Clears driver's internal Port Reset Change flag */
1649 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
1650 hsotg
->flags
.b
.port_reset_change
= 0;
1653 case USB_PORT_FEAT_C_ENABLE
:
1655 * Clears the driver's internal Port Enable/Disable
1659 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
1660 hsotg
->flags
.b
.port_enable_change
= 0;
1663 case USB_PORT_FEAT_C_SUSPEND
:
1665 * Clears the driver's internal Port Suspend Change
1666 * flag, which is set when resume signaling on the host
1670 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
1671 hsotg
->flags
.b
.port_suspend_change
= 0;
1674 case USB_PORT_FEAT_C_PORT_L1
:
1676 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
1677 hsotg
->flags
.b
.port_l1_change
= 0;
1680 case USB_PORT_FEAT_C_OVER_CURRENT
:
1682 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
1683 hsotg
->flags
.b
.port_over_current_change
= 0;
1689 "ClearPortFeature request %1xh unknown or unsupported\n",
1694 case GetHubDescriptor
:
1695 dev_dbg(hsotg
->dev
, "GetHubDescriptor\n");
1696 hub_desc
= (struct usb_hub_descriptor
*)buf
;
1697 hub_desc
->bDescLength
= 9;
1698 hub_desc
->bDescriptorType
= USB_DT_HUB
;
1699 hub_desc
->bNbrPorts
= 1;
1700 hub_desc
->wHubCharacteristics
=
1701 cpu_to_le16(HUB_CHAR_COMMON_LPSM
|
1702 HUB_CHAR_INDV_PORT_OCPM
);
1703 hub_desc
->bPwrOn2PwrGood
= 1;
1704 hub_desc
->bHubContrCurrent
= 0;
1705 hub_desc
->u
.hs
.DeviceRemovable
[0] = 0;
1706 hub_desc
->u
.hs
.DeviceRemovable
[1] = 0xff;
1710 dev_dbg(hsotg
->dev
, "GetHubStatus\n");
1715 dev_vdbg(hsotg
->dev
,
1716 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex
,
1718 if (!windex
|| windex
> 1)
1722 if (hsotg
->flags
.b
.port_connect_status_change
)
1723 port_status
|= USB_PORT_STAT_C_CONNECTION
<< 16;
1724 if (hsotg
->flags
.b
.port_enable_change
)
1725 port_status
|= USB_PORT_STAT_C_ENABLE
<< 16;
1726 if (hsotg
->flags
.b
.port_suspend_change
)
1727 port_status
|= USB_PORT_STAT_C_SUSPEND
<< 16;
1728 if (hsotg
->flags
.b
.port_l1_change
)
1729 port_status
|= USB_PORT_STAT_C_L1
<< 16;
1730 if (hsotg
->flags
.b
.port_reset_change
)
1731 port_status
|= USB_PORT_STAT_C_RESET
<< 16;
1732 if (hsotg
->flags
.b
.port_over_current_change
) {
1733 dev_warn(hsotg
->dev
, "Overcurrent change detected\n");
1734 port_status
|= USB_PORT_STAT_C_OVERCURRENT
<< 16;
1737 if (!hsotg
->flags
.b
.port_connect_status
) {
1739 * The port is disconnected, which means the core is
1740 * either in device mode or it soon will be. Just
1741 * return 0's for the remainder of the port status
1742 * since the port register can't be read if the core
1743 * is in device mode.
1745 *(__le32
*)buf
= cpu_to_le32(port_status
);
1749 hprt0
= dwc2_readl(hsotg
->regs
+ HPRT0
);
1750 dev_vdbg(hsotg
->dev
, " HPRT0: 0x%08x\n", hprt0
);
1752 if (hprt0
& HPRT0_CONNSTS
)
1753 port_status
|= USB_PORT_STAT_CONNECTION
;
1754 if (hprt0
& HPRT0_ENA
)
1755 port_status
|= USB_PORT_STAT_ENABLE
;
1756 if (hprt0
& HPRT0_SUSP
)
1757 port_status
|= USB_PORT_STAT_SUSPEND
;
1758 if (hprt0
& HPRT0_OVRCURRACT
)
1759 port_status
|= USB_PORT_STAT_OVERCURRENT
;
1760 if (hprt0
& HPRT0_RST
)
1761 port_status
|= USB_PORT_STAT_RESET
;
1762 if (hprt0
& HPRT0_PWR
)
1763 port_status
|= USB_PORT_STAT_POWER
;
1765 speed
= (hprt0
& HPRT0_SPD_MASK
) >> HPRT0_SPD_SHIFT
;
1766 if (speed
== HPRT0_SPD_HIGH_SPEED
)
1767 port_status
|= USB_PORT_STAT_HIGH_SPEED
;
1768 else if (speed
== HPRT0_SPD_LOW_SPEED
)
1769 port_status
|= USB_PORT_STAT_LOW_SPEED
;
1771 if (hprt0
& HPRT0_TSTCTL_MASK
)
1772 port_status
|= USB_PORT_STAT_TEST
;
1773 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
1775 if (hsotg
->core_params
->dma_desc_fs_enable
) {
1777 * Enable descriptor DMA only if a full speed
1778 * device is connected.
1780 if (hsotg
->new_connection
&&
1782 (USB_PORT_STAT_CONNECTION
|
1783 USB_PORT_STAT_HIGH_SPEED
|
1784 USB_PORT_STAT_LOW_SPEED
)) ==
1785 USB_PORT_STAT_CONNECTION
)) {
1788 dev_info(hsotg
->dev
, "Enabling descriptor DMA mode\n");
1789 hsotg
->core_params
->dma_desc_enable
= 1;
1790 hcfg
= dwc2_readl(hsotg
->regs
+ HCFG
);
1791 hcfg
|= HCFG_DESCDMA
;
1792 dwc2_writel(hcfg
, hsotg
->regs
+ HCFG
);
1793 hsotg
->new_connection
= false;
1797 dev_vdbg(hsotg
->dev
, "port_status=%08x\n", port_status
);
1798 *(__le32
*)buf
= cpu_to_le32(port_status
);
1802 dev_dbg(hsotg
->dev
, "SetHubFeature\n");
1803 /* No HUB features supported */
1806 case SetPortFeature
:
1807 dev_dbg(hsotg
->dev
, "SetPortFeature\n");
1808 if (wvalue
!= USB_PORT_FEAT_TEST
&& (!windex
|| windex
> 1))
1811 if (!hsotg
->flags
.b
.port_connect_status
) {
1813 * The port is disconnected, which means the core is
1814 * either in device mode or it soon will be. Just
1815 * return without doing anything since the port
1816 * register can't be written if the core is in device
1823 case USB_PORT_FEAT_SUSPEND
:
1825 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
1826 if (windex
!= hsotg
->otg_port
)
1828 dwc2_port_suspend(hsotg
, windex
);
1831 case USB_PORT_FEAT_POWER
:
1833 "SetPortFeature - USB_PORT_FEAT_POWER\n");
1834 hprt0
= dwc2_read_hprt0(hsotg
);
1836 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
1839 case USB_PORT_FEAT_RESET
:
1840 hprt0
= dwc2_read_hprt0(hsotg
);
1842 "SetPortFeature - USB_PORT_FEAT_RESET\n");
1843 pcgctl
= dwc2_readl(hsotg
->regs
+ PCGCTL
);
1844 pcgctl
&= ~(PCGCTL_ENBL_SLEEP_GATING
| PCGCTL_STOPPCLK
);
1845 dwc2_writel(pcgctl
, hsotg
->regs
+ PCGCTL
);
1846 /* ??? Original driver does this */
1847 dwc2_writel(0, hsotg
->regs
+ PCGCTL
);
1849 hprt0
= dwc2_read_hprt0(hsotg
);
1850 /* Clear suspend bit if resetting from suspend state */
1851 hprt0
&= ~HPRT0_SUSP
;
1854 * When B-Host the Port reset bit is set in the Start
1855 * HCD Callback function, so that the reset is started
1856 * within 1ms of the HNP success interrupt
1858 if (!dwc2_hcd_is_b_host(hsotg
)) {
1859 hprt0
|= HPRT0_PWR
| HPRT0_RST
;
1861 "In host mode, hprt0=%08x\n", hprt0
);
1862 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
1865 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
1866 usleep_range(50000, 70000);
1867 hprt0
&= ~HPRT0_RST
;
1868 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
1869 hsotg
->lx_state
= DWC2_L0
; /* Now back to On state */
1872 case USB_PORT_FEAT_INDICATOR
:
1874 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
1878 case USB_PORT_FEAT_TEST
:
1879 hprt0
= dwc2_read_hprt0(hsotg
);
1881 "SetPortFeature - USB_PORT_FEAT_TEST\n");
1882 hprt0
&= ~HPRT0_TSTCTL_MASK
;
1883 hprt0
|= (windex
>> 8) << HPRT0_TSTCTL_SHIFT
;
1884 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
1890 "SetPortFeature %1xh unknown or unsupported\n",
1900 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
1901 typereq
, windex
, wvalue
);
1908 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg
*hsotg
, int port
)
1915 retval
= (hsotg
->flags
.b
.port_connect_status_change
||
1916 hsotg
->flags
.b
.port_reset_change
||
1917 hsotg
->flags
.b
.port_enable_change
||
1918 hsotg
->flags
.b
.port_suspend_change
||
1919 hsotg
->flags
.b
.port_over_current_change
);
1923 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
1924 dev_dbg(hsotg
->dev
, " port_connect_status_change: %d\n",
1925 hsotg
->flags
.b
.port_connect_status_change
);
1926 dev_dbg(hsotg
->dev
, " port_reset_change: %d\n",
1927 hsotg
->flags
.b
.port_reset_change
);
1928 dev_dbg(hsotg
->dev
, " port_enable_change: %d\n",
1929 hsotg
->flags
.b
.port_enable_change
);
1930 dev_dbg(hsotg
->dev
, " port_suspend_change: %d\n",
1931 hsotg
->flags
.b
.port_suspend_change
);
1932 dev_dbg(hsotg
->dev
, " port_over_current_change: %d\n",
1933 hsotg
->flags
.b
.port_over_current_change
);
1939 int dwc2_hcd_get_frame_number(struct dwc2_hsotg
*hsotg
)
1941 u32 hfnum
= dwc2_readl(hsotg
->regs
+ HFNUM
);
1943 #ifdef DWC2_DEBUG_SOF
1944 dev_vdbg(hsotg
->dev
, "DWC OTG HCD GET FRAME NUMBER %d\n",
1945 (hfnum
& HFNUM_FRNUM_MASK
) >> HFNUM_FRNUM_SHIFT
);
1947 return (hfnum
& HFNUM_FRNUM_MASK
) >> HFNUM_FRNUM_SHIFT
;
1950 int dwc2_hcd_is_b_host(struct dwc2_hsotg
*hsotg
)
1952 return hsotg
->op_state
== OTG_STATE_B_HOST
;
1955 static struct dwc2_hcd_urb
*dwc2_hcd_urb_alloc(struct dwc2_hsotg
*hsotg
,
1959 struct dwc2_hcd_urb
*urb
;
1960 u32 size
= sizeof(*urb
) + iso_desc_count
*
1961 sizeof(struct dwc2_hcd_iso_packet_desc
);
1963 urb
= kzalloc(size
, mem_flags
);
1965 urb
->packet_count
= iso_desc_count
;
1969 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg
*hsotg
,
1970 struct dwc2_hcd_urb
*urb
, u8 dev_addr
,
1971 u8 ep_num
, u8 ep_type
, u8 ep_dir
, u16 mps
)
1974 ep_type
== USB_ENDPOINT_XFER_BULK
||
1975 ep_type
== USB_ENDPOINT_XFER_CONTROL
)
1976 dev_vdbg(hsotg
->dev
,
1977 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
1978 dev_addr
, ep_num
, ep_dir
, ep_type
, mps
);
1979 urb
->pipe_info
.dev_addr
= dev_addr
;
1980 urb
->pipe_info
.ep_num
= ep_num
;
1981 urb
->pipe_info
.pipe_type
= ep_type
;
1982 urb
->pipe_info
.pipe_dir
= ep_dir
;
1983 urb
->pipe_info
.mps
= mps
;
1987 * NOTE: This function will be removed once the peripheral controller code
1988 * is integrated and the driver is stable
1990 void dwc2_hcd_dump_state(struct dwc2_hsotg
*hsotg
)
1993 struct dwc2_host_chan
*chan
;
1994 struct dwc2_hcd_urb
*urb
;
1995 struct dwc2_qtd
*qtd
;
2001 num_channels
= hsotg
->core_params
->host_channels
;
2002 dev_dbg(hsotg
->dev
, "\n");
2004 "************************************************************\n");
2005 dev_dbg(hsotg
->dev
, "HCD State:\n");
2006 dev_dbg(hsotg
->dev
, " Num channels: %d\n", num_channels
);
2008 for (i
= 0; i
< num_channels
; i
++) {
2009 chan
= hsotg
->hc_ptr_array
[i
];
2010 dev_dbg(hsotg
->dev
, " Channel %d:\n", i
);
2012 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
2013 chan
->dev_addr
, chan
->ep_num
, chan
->ep_is_in
);
2014 dev_dbg(hsotg
->dev
, " speed: %d\n", chan
->speed
);
2015 dev_dbg(hsotg
->dev
, " ep_type: %d\n", chan
->ep_type
);
2016 dev_dbg(hsotg
->dev
, " max_packet: %d\n", chan
->max_packet
);
2017 dev_dbg(hsotg
->dev
, " data_pid_start: %d\n",
2018 chan
->data_pid_start
);
2019 dev_dbg(hsotg
->dev
, " multi_count: %d\n", chan
->multi_count
);
2020 dev_dbg(hsotg
->dev
, " xfer_started: %d\n",
2021 chan
->xfer_started
);
2022 dev_dbg(hsotg
->dev
, " xfer_buf: %p\n", chan
->xfer_buf
);
2023 dev_dbg(hsotg
->dev
, " xfer_dma: %08lx\n",
2024 (unsigned long)chan
->xfer_dma
);
2025 dev_dbg(hsotg
->dev
, " xfer_len: %d\n", chan
->xfer_len
);
2026 dev_dbg(hsotg
->dev
, " xfer_count: %d\n", chan
->xfer_count
);
2027 dev_dbg(hsotg
->dev
, " halt_on_queue: %d\n",
2028 chan
->halt_on_queue
);
2029 dev_dbg(hsotg
->dev
, " halt_pending: %d\n",
2030 chan
->halt_pending
);
2031 dev_dbg(hsotg
->dev
, " halt_status: %d\n", chan
->halt_status
);
2032 dev_dbg(hsotg
->dev
, " do_split: %d\n", chan
->do_split
);
2033 dev_dbg(hsotg
->dev
, " complete_split: %d\n",
2034 chan
->complete_split
);
2035 dev_dbg(hsotg
->dev
, " hub_addr: %d\n", chan
->hub_addr
);
2036 dev_dbg(hsotg
->dev
, " hub_port: %d\n", chan
->hub_port
);
2037 dev_dbg(hsotg
->dev
, " xact_pos: %d\n", chan
->xact_pos
);
2038 dev_dbg(hsotg
->dev
, " requests: %d\n", chan
->requests
);
2039 dev_dbg(hsotg
->dev
, " qh: %p\n", chan
->qh
);
2041 if (chan
->xfer_started
) {
2042 u32 hfnum
, hcchar
, hctsiz
, hcint
, hcintmsk
;
2044 hfnum
= dwc2_readl(hsotg
->regs
+ HFNUM
);
2045 hcchar
= dwc2_readl(hsotg
->regs
+ HCCHAR(i
));
2046 hctsiz
= dwc2_readl(hsotg
->regs
+ HCTSIZ(i
));
2047 hcint
= dwc2_readl(hsotg
->regs
+ HCINT(i
));
2048 hcintmsk
= dwc2_readl(hsotg
->regs
+ HCINTMSK(i
));
2049 dev_dbg(hsotg
->dev
, " hfnum: 0x%08x\n", hfnum
);
2050 dev_dbg(hsotg
->dev
, " hcchar: 0x%08x\n", hcchar
);
2051 dev_dbg(hsotg
->dev
, " hctsiz: 0x%08x\n", hctsiz
);
2052 dev_dbg(hsotg
->dev
, " hcint: 0x%08x\n", hcint
);
2053 dev_dbg(hsotg
->dev
, " hcintmsk: 0x%08x\n", hcintmsk
);
2056 if (!(chan
->xfer_started
&& chan
->qh
))
2059 list_for_each_entry(qtd
, &chan
->qh
->qtd_list
, qtd_list_entry
) {
2060 if (!qtd
->in_process
)
2063 dev_dbg(hsotg
->dev
, " URB Info:\n");
2064 dev_dbg(hsotg
->dev
, " qtd: %p, urb: %p\n",
2068 " Dev: %d, EP: %d %s\n",
2069 dwc2_hcd_get_dev_addr(&urb
->pipe_info
),
2070 dwc2_hcd_get_ep_num(&urb
->pipe_info
),
2071 dwc2_hcd_is_pipe_in(&urb
->pipe_info
) ?
2074 " Max packet size: %d\n",
2075 dwc2_hcd_get_mps(&urb
->pipe_info
));
2077 " transfer_buffer: %p\n",
2080 " transfer_dma: %08lx\n",
2081 (unsigned long)urb
->dma
);
2083 " transfer_buffer_length: %d\n",
2085 dev_dbg(hsotg
->dev
, " actual_length: %d\n",
2086 urb
->actual_length
);
2091 dev_dbg(hsotg
->dev
, " non_periodic_channels: %d\n",
2092 hsotg
->non_periodic_channels
);
2093 dev_dbg(hsotg
->dev
, " periodic_channels: %d\n",
2094 hsotg
->periodic_channels
);
2095 dev_dbg(hsotg
->dev
, " periodic_usecs: %d\n", hsotg
->periodic_usecs
);
2096 np_tx_status
= dwc2_readl(hsotg
->regs
+ GNPTXSTS
);
2097 dev_dbg(hsotg
->dev
, " NP Tx Req Queue Space Avail: %d\n",
2098 (np_tx_status
& TXSTS_QSPCAVAIL_MASK
) >> TXSTS_QSPCAVAIL_SHIFT
);
2099 dev_dbg(hsotg
->dev
, " NP Tx FIFO Space Avail: %d\n",
2100 (np_tx_status
& TXSTS_FSPCAVAIL_MASK
) >> TXSTS_FSPCAVAIL_SHIFT
);
2101 p_tx_status
= dwc2_readl(hsotg
->regs
+ HPTXSTS
);
2102 dev_dbg(hsotg
->dev
, " P Tx Req Queue Space Avail: %d\n",
2103 (p_tx_status
& TXSTS_QSPCAVAIL_MASK
) >> TXSTS_QSPCAVAIL_SHIFT
);
2104 dev_dbg(hsotg
->dev
, " P Tx FIFO Space Avail: %d\n",
2105 (p_tx_status
& TXSTS_FSPCAVAIL_MASK
) >> TXSTS_FSPCAVAIL_SHIFT
);
2106 dwc2_hcd_dump_frrem(hsotg
);
2107 dwc2_dump_global_registers(hsotg
);
2108 dwc2_dump_host_registers(hsotg
);
2110 "************************************************************\n");
2111 dev_dbg(hsotg
->dev
, "\n");
2116 * NOTE: This function will be removed once the peripheral controller code
2117 * is integrated and the driver is stable
2119 void dwc2_hcd_dump_frrem(struct dwc2_hsotg
*hsotg
)
2121 #ifdef DWC2_DUMP_FRREM
2122 dev_dbg(hsotg
->dev
, "Frame remaining at SOF:\n");
2123 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
2124 hsotg
->frrem_samples
, hsotg
->frrem_accum
,
2125 hsotg
->frrem_samples
> 0 ?
2126 hsotg
->frrem_accum
/ hsotg
->frrem_samples
: 0);
2127 dev_dbg(hsotg
->dev
, "\n");
2128 dev_dbg(hsotg
->dev
, "Frame remaining at start_transfer (uframe 7):\n");
2129 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
2130 hsotg
->hfnum_7_samples
,
2131 hsotg
->hfnum_7_frrem_accum
,
2132 hsotg
->hfnum_7_samples
> 0 ?
2133 hsotg
->hfnum_7_frrem_accum
/ hsotg
->hfnum_7_samples
: 0);
2134 dev_dbg(hsotg
->dev
, "Frame remaining at start_transfer (uframe 0):\n");
2135 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
2136 hsotg
->hfnum_0_samples
,
2137 hsotg
->hfnum_0_frrem_accum
,
2138 hsotg
->hfnum_0_samples
> 0 ?
2139 hsotg
->hfnum_0_frrem_accum
/ hsotg
->hfnum_0_samples
: 0);
2140 dev_dbg(hsotg
->dev
, "Frame remaining at start_transfer (uframe 1-6):\n");
2141 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
2142 hsotg
->hfnum_other_samples
,
2143 hsotg
->hfnum_other_frrem_accum
,
2144 hsotg
->hfnum_other_samples
> 0 ?
2145 hsotg
->hfnum_other_frrem_accum
/ hsotg
->hfnum_other_samples
:
2147 dev_dbg(hsotg
->dev
, "\n");
2148 dev_dbg(hsotg
->dev
, "Frame remaining at sample point A (uframe 7):\n");
2149 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
2150 hsotg
->hfnum_7_samples_a
, hsotg
->hfnum_7_frrem_accum_a
,
2151 hsotg
->hfnum_7_samples_a
> 0 ?
2152 hsotg
->hfnum_7_frrem_accum_a
/ hsotg
->hfnum_7_samples_a
: 0);
2153 dev_dbg(hsotg
->dev
, "Frame remaining at sample point A (uframe 0):\n");
2154 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
2155 hsotg
->hfnum_0_samples_a
, hsotg
->hfnum_0_frrem_accum_a
,
2156 hsotg
->hfnum_0_samples_a
> 0 ?
2157 hsotg
->hfnum_0_frrem_accum_a
/ hsotg
->hfnum_0_samples_a
: 0);
2158 dev_dbg(hsotg
->dev
, "Frame remaining at sample point A (uframe 1-6):\n");
2159 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
2160 hsotg
->hfnum_other_samples_a
, hsotg
->hfnum_other_frrem_accum_a
,
2161 hsotg
->hfnum_other_samples_a
> 0 ?
2162 hsotg
->hfnum_other_frrem_accum_a
/ hsotg
->hfnum_other_samples_a
2164 dev_dbg(hsotg
->dev
, "\n");
2165 dev_dbg(hsotg
->dev
, "Frame remaining at sample point B (uframe 7):\n");
2166 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
2167 hsotg
->hfnum_7_samples_b
, hsotg
->hfnum_7_frrem_accum_b
,
2168 hsotg
->hfnum_7_samples_b
> 0 ?
2169 hsotg
->hfnum_7_frrem_accum_b
/ hsotg
->hfnum_7_samples_b
: 0);
2170 dev_dbg(hsotg
->dev
, "Frame remaining at sample point B (uframe 0):\n");
2171 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
2172 hsotg
->hfnum_0_samples_b
, hsotg
->hfnum_0_frrem_accum_b
,
2173 (hsotg
->hfnum_0_samples_b
> 0) ?
2174 hsotg
->hfnum_0_frrem_accum_b
/ hsotg
->hfnum_0_samples_b
: 0);
2175 dev_dbg(hsotg
->dev
, "Frame remaining at sample point B (uframe 1-6):\n");
2176 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
2177 hsotg
->hfnum_other_samples_b
, hsotg
->hfnum_other_frrem_accum_b
,
2178 (hsotg
->hfnum_other_samples_b
> 0) ?
2179 hsotg
->hfnum_other_frrem_accum_b
/ hsotg
->hfnum_other_samples_b
2184 struct wrapper_priv_data
{
2185 struct dwc2_hsotg
*hsotg
;
2188 /* Gets the dwc2_hsotg from a usb_hcd */
2189 static struct dwc2_hsotg
*dwc2_hcd_to_hsotg(struct usb_hcd
*hcd
)
2191 struct wrapper_priv_data
*p
;
2193 p
= (struct wrapper_priv_data
*) &hcd
->hcd_priv
;
2197 static int _dwc2_hcd_start(struct usb_hcd
*hcd
);
2199 void dwc2_host_start(struct dwc2_hsotg
*hsotg
)
2201 struct usb_hcd
*hcd
= dwc2_hsotg_to_hcd(hsotg
);
2203 hcd
->self
.is_b_host
= dwc2_hcd_is_b_host(hsotg
);
2204 _dwc2_hcd_start(hcd
);
2207 void dwc2_host_disconnect(struct dwc2_hsotg
*hsotg
)
2209 struct usb_hcd
*hcd
= dwc2_hsotg_to_hcd(hsotg
);
2211 hcd
->self
.is_b_host
= 0;
2214 void dwc2_host_hub_info(struct dwc2_hsotg
*hsotg
, void *context
, int *hub_addr
,
2217 struct urb
*urb
= context
;
2220 *hub_addr
= urb
->dev
->tt
->hub
->devnum
;
2223 *hub_port
= urb
->dev
->ttport
;
2226 int dwc2_host_get_speed(struct dwc2_hsotg
*hsotg
, void *context
)
2228 struct urb
*urb
= context
;
2230 return urb
->dev
->speed
;
2233 static void dwc2_allocate_bus_bandwidth(struct usb_hcd
*hcd
, u16 bw
,
2236 struct usb_bus
*bus
= hcd_to_bus(hcd
);
2239 bus
->bandwidth_allocated
+= bw
/ urb
->interval
;
2240 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
)
2241 bus
->bandwidth_isoc_reqs
++;
2243 bus
->bandwidth_int_reqs
++;
2246 static void dwc2_free_bus_bandwidth(struct usb_hcd
*hcd
, u16 bw
,
2249 struct usb_bus
*bus
= hcd_to_bus(hcd
);
2252 bus
->bandwidth_allocated
-= bw
/ urb
->interval
;
2253 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
)
2254 bus
->bandwidth_isoc_reqs
--;
2256 bus
->bandwidth_int_reqs
--;
2260 * Sets the final status of an URB and returns it to the upper layer. Any
2261 * required cleanup of the URB is performed.
2263 * Must be called with interrupt disabled and spinlock held
2265 void dwc2_host_complete(struct dwc2_hsotg
*hsotg
, struct dwc2_qtd
*qtd
,
2272 dev_dbg(hsotg
->dev
, "## %s: qtd is NULL ##\n", __func__
);
2277 dev_dbg(hsotg
->dev
, "## %s: qtd->urb is NULL ##\n", __func__
);
2281 urb
= qtd
->urb
->priv
;
2283 dev_dbg(hsotg
->dev
, "## %s: urb->priv is NULL ##\n", __func__
);
2287 urb
->actual_length
= dwc2_hcd_urb_get_actual_length(qtd
->urb
);
2290 dev_vdbg(hsotg
->dev
,
2291 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
2292 __func__
, urb
, usb_pipedevice(urb
->pipe
),
2293 usb_pipeendpoint(urb
->pipe
),
2294 usb_pipein(urb
->pipe
) ? "IN" : "OUT", status
,
2295 urb
->actual_length
);
2298 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
2299 urb
->error_count
= dwc2_hcd_urb_get_error_count(qtd
->urb
);
2300 for (i
= 0; i
< urb
->number_of_packets
; ++i
) {
2301 urb
->iso_frame_desc
[i
].actual_length
=
2302 dwc2_hcd_urb_get_iso_desc_actual_length(
2304 urb
->iso_frame_desc
[i
].status
=
2305 dwc2_hcd_urb_get_iso_desc_status(qtd
->urb
, i
);
2309 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
&& dbg_perio()) {
2310 for (i
= 0; i
< urb
->number_of_packets
; i
++)
2311 dev_vdbg(hsotg
->dev
, " ISO Desc %d status %d\n",
2312 i
, urb
->iso_frame_desc
[i
].status
);
2315 urb
->status
= status
;
2317 if ((urb
->transfer_flags
& URB_SHORT_NOT_OK
) &&
2318 urb
->actual_length
< urb
->transfer_buffer_length
)
2319 urb
->status
= -EREMOTEIO
;
2322 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
||
2323 usb_pipetype(urb
->pipe
) == PIPE_INTERRUPT
) {
2324 struct usb_host_endpoint
*ep
= urb
->ep
;
2327 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg
),
2328 dwc2_hcd_get_ep_bandwidth(hsotg
, ep
),
2332 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg
), urb
);
2337 spin_unlock(&hsotg
->lock
);
2338 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg
), urb
, status
);
2339 spin_lock(&hsotg
->lock
);
2343 * Work queue function for starting the HCD when A-Cable is connected
2345 static void dwc2_hcd_start_func(struct work_struct
*work
)
2347 struct dwc2_hsotg
*hsotg
= container_of(work
, struct dwc2_hsotg
,
2350 dev_dbg(hsotg
->dev
, "%s() %p\n", __func__
, hsotg
);
2351 dwc2_host_start(hsotg
);
2355 * Reset work queue function
2357 static void dwc2_hcd_reset_func(struct work_struct
*work
)
2359 struct dwc2_hsotg
*hsotg
= container_of(work
, struct dwc2_hsotg
,
2361 unsigned long flags
;
2364 dev_dbg(hsotg
->dev
, "USB RESET function called\n");
2366 spin_lock_irqsave(&hsotg
->lock
, flags
);
2368 hprt0
= dwc2_read_hprt0(hsotg
);
2369 hprt0
&= ~HPRT0_RST
;
2370 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
2371 hsotg
->flags
.b
.port_reset_change
= 1;
2373 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2377 * =========================================================================
2378 * Linux HC Driver Functions
2379 * =========================================================================
2383 * Initializes the DWC_otg controller and its root hub and prepares it for host
2384 * mode operation. Activates the root port. Returns 0 on success and a negative
2385 * error code on failure.
2387 static int _dwc2_hcd_start(struct usb_hcd
*hcd
)
2389 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
2390 struct usb_bus
*bus
= hcd_to_bus(hcd
);
2391 unsigned long flags
;
2393 dev_dbg(hsotg
->dev
, "DWC OTG HCD START\n");
2395 spin_lock_irqsave(&hsotg
->lock
, flags
);
2396 hsotg
->lx_state
= DWC2_L0
;
2397 hcd
->state
= HC_STATE_RUNNING
;
2398 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
2400 if (dwc2_is_device_mode(hsotg
)) {
2401 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2402 return 0; /* why 0 ?? */
2405 dwc2_hcd_reinit(hsotg
);
2407 /* Initialize and connect root hub if one is not already attached */
2408 if (bus
->root_hub
) {
2409 dev_dbg(hsotg
->dev
, "DWC OTG HCD Has Root Hub\n");
2410 /* Inform the HUB driver to resume */
2411 usb_hcd_resume_root_hub(hcd
);
2414 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2419 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
2422 static void _dwc2_hcd_stop(struct usb_hcd
*hcd
)
2424 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
2425 unsigned long flags
;
2427 /* Turn off all host-specific interrupts */
2428 dwc2_disable_host_interrupts(hsotg
);
2430 /* Wait for interrupt processing to finish */
2431 synchronize_irq(hcd
->irq
);
2433 spin_lock_irqsave(&hsotg
->lock
, flags
);
2434 /* Ensure hcd is disconnected */
2435 dwc2_hcd_disconnect(hsotg
, true);
2436 dwc2_hcd_stop(hsotg
);
2437 hsotg
->lx_state
= DWC2_L3
;
2438 hcd
->state
= HC_STATE_HALT
;
2439 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
2440 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2442 usleep_range(1000, 3000);
2445 static int _dwc2_hcd_suspend(struct usb_hcd
*hcd
)
2447 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
2448 unsigned long flags
;
2452 spin_lock_irqsave(&hsotg
->lock
, flags
);
2454 if (hsotg
->lx_state
!= DWC2_L0
)
2457 if (!HCD_HW_ACCESSIBLE(hcd
))
2460 if (!hsotg
->core_params
->hibernation
)
2461 goto skip_power_saving
;
2464 * Drive USB suspend and disable port Power
2465 * if usb bus is not suspended.
2467 if (!hsotg
->bus_suspended
) {
2468 hprt0
= dwc2_read_hprt0(hsotg
);
2469 hprt0
|= HPRT0_SUSP
;
2470 hprt0
&= ~HPRT0_PWR
;
2471 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
2474 /* Enter hibernation */
2475 ret
= dwc2_enter_hibernation(hsotg
);
2477 if (ret
!= -ENOTSUPP
)
2479 "enter hibernation failed\n");
2480 goto skip_power_saving
;
2483 /* Ask phy to be suspended */
2484 if (!IS_ERR_OR_NULL(hsotg
->uphy
)) {
2485 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2486 usb_phy_set_suspend(hsotg
->uphy
, true);
2487 spin_lock_irqsave(&hsotg
->lock
, flags
);
2490 /* After entering hibernation, hardware is no more accessible */
2491 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
2494 hsotg
->lx_state
= DWC2_L2
;
2496 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2501 static int _dwc2_hcd_resume(struct usb_hcd
*hcd
)
2503 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
2504 unsigned long flags
;
2507 spin_lock_irqsave(&hsotg
->lock
, flags
);
2509 if (hsotg
->lx_state
!= DWC2_L2
)
2512 if (!hsotg
->core_params
->hibernation
) {
2513 hsotg
->lx_state
= DWC2_L0
;
2518 * Set HW accessible bit before powering on the controller
2519 * since an interrupt may rise.
2521 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
2524 * Enable power if not already done.
2525 * This must not be spinlocked since duration
2526 * of this call is unknown.
2528 if (!IS_ERR_OR_NULL(hsotg
->uphy
)) {
2529 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2530 usb_phy_set_suspend(hsotg
->uphy
, false);
2531 spin_lock_irqsave(&hsotg
->lock
, flags
);
2534 /* Exit hibernation */
2535 ret
= dwc2_exit_hibernation(hsotg
, true);
2536 if (ret
&& (ret
!= -ENOTSUPP
))
2537 dev_err(hsotg
->dev
, "exit hibernation failed\n");
2539 hsotg
->lx_state
= DWC2_L0
;
2541 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2543 if (hsotg
->bus_suspended
) {
2544 spin_lock_irqsave(&hsotg
->lock
, flags
);
2545 hsotg
->flags
.b
.port_suspend_change
= 1;
2546 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2547 dwc2_port_resume(hsotg
);
2549 /* Wait for controller to correctly update D+/D- level */
2550 usleep_range(3000, 5000);
2553 * Clear Port Enable and Port Status changes.
2554 * Enable Port Power.
2556 dwc2_writel(HPRT0_PWR
| HPRT0_CONNDET
|
2557 HPRT0_ENACHG
, hsotg
->regs
+ HPRT0
);
2558 /* Wait for controller to detect Port Connect */
2559 usleep_range(5000, 7000);
2564 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2569 /* Returns the current frame number */
2570 static int _dwc2_hcd_get_frame_number(struct usb_hcd
*hcd
)
2572 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
2574 return dwc2_hcd_get_frame_number(hsotg
);
2577 static void dwc2_dump_urb_info(struct usb_hcd
*hcd
, struct urb
*urb
,
2580 #ifdef VERBOSE_DEBUG
2581 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
2585 dev_vdbg(hsotg
->dev
, "%s, urb %p\n", fn_name
, urb
);
2586 dev_vdbg(hsotg
->dev
, " Device address: %d\n",
2587 usb_pipedevice(urb
->pipe
));
2588 dev_vdbg(hsotg
->dev
, " Endpoint: %d, %s\n",
2589 usb_pipeendpoint(urb
->pipe
),
2590 usb_pipein(urb
->pipe
) ? "IN" : "OUT");
2592 switch (usb_pipetype(urb
->pipe
)) {
2594 pipetype
= "CONTROL";
2599 case PIPE_INTERRUPT
:
2600 pipetype
= "INTERRUPT";
2602 case PIPE_ISOCHRONOUS
:
2603 pipetype
= "ISOCHRONOUS";
2606 pipetype
= "UNKNOWN";
2610 dev_vdbg(hsotg
->dev
, " Endpoint type: %s %s (%s)\n", pipetype
,
2611 usb_urb_dir_in(urb
) ? "IN" : "OUT", usb_pipein(urb
->pipe
) ?
2614 switch (urb
->dev
->speed
) {
2615 case USB_SPEED_HIGH
:
2618 case USB_SPEED_FULL
:
2629 dev_vdbg(hsotg
->dev
, " Speed: %s\n", speed
);
2630 dev_vdbg(hsotg
->dev
, " Max packet size: %d\n",
2631 usb_maxpacket(urb
->dev
, urb
->pipe
, usb_pipeout(urb
->pipe
)));
2632 dev_vdbg(hsotg
->dev
, " Data buffer length: %d\n",
2633 urb
->transfer_buffer_length
);
2634 dev_vdbg(hsotg
->dev
, " Transfer buffer: %p, Transfer DMA: %08lx\n",
2635 urb
->transfer_buffer
, (unsigned long)urb
->transfer_dma
);
2636 dev_vdbg(hsotg
->dev
, " Setup buffer: %p, Setup DMA: %08lx\n",
2637 urb
->setup_packet
, (unsigned long)urb
->setup_dma
);
2638 dev_vdbg(hsotg
->dev
, " Interval: %d\n", urb
->interval
);
2640 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
2643 for (i
= 0; i
< urb
->number_of_packets
; i
++) {
2644 dev_vdbg(hsotg
->dev
, " ISO Desc %d:\n", i
);
2645 dev_vdbg(hsotg
->dev
, " offset: %d, length %d\n",
2646 urb
->iso_frame_desc
[i
].offset
,
2647 urb
->iso_frame_desc
[i
].length
);
2654 * Starts processing a USB transfer request specified by a USB Request Block
2655 * (URB). mem_flags indicates the type of memory allocation to use while
2656 * processing this URB.
2658 static int _dwc2_hcd_urb_enqueue(struct usb_hcd
*hcd
, struct urb
*urb
,
2661 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
2662 struct usb_host_endpoint
*ep
= urb
->ep
;
2663 struct dwc2_hcd_urb
*dwc2_urb
;
2666 int alloc_bandwidth
= 0;
2670 unsigned long flags
;
2672 bool qh_allocated
= false;
2673 struct dwc2_qtd
*qtd
;
2676 dev_vdbg(hsotg
->dev
, "DWC OTG HCD URB Enqueue\n");
2677 dwc2_dump_urb_info(hcd
, urb
, "urb_enqueue");
2683 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
||
2684 usb_pipetype(urb
->pipe
) == PIPE_INTERRUPT
) {
2685 spin_lock_irqsave(&hsotg
->lock
, flags
);
2686 if (!dwc2_hcd_is_bandwidth_allocated(hsotg
, ep
))
2687 alloc_bandwidth
= 1;
2688 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2691 switch (usb_pipetype(urb
->pipe
)) {
2693 ep_type
= USB_ENDPOINT_XFER_CONTROL
;
2695 case PIPE_ISOCHRONOUS
:
2696 ep_type
= USB_ENDPOINT_XFER_ISOC
;
2699 ep_type
= USB_ENDPOINT_XFER_BULK
;
2701 case PIPE_INTERRUPT
:
2702 ep_type
= USB_ENDPOINT_XFER_INT
;
2705 dev_warn(hsotg
->dev
, "Wrong ep type\n");
2708 dwc2_urb
= dwc2_hcd_urb_alloc(hsotg
, urb
->number_of_packets
,
2713 dwc2_hcd_urb_set_pipeinfo(hsotg
, dwc2_urb
, usb_pipedevice(urb
->pipe
),
2714 usb_pipeendpoint(urb
->pipe
), ep_type
,
2715 usb_pipein(urb
->pipe
),
2716 usb_maxpacket(urb
->dev
, urb
->pipe
,
2717 !(usb_pipein(urb
->pipe
))));
2719 buf
= urb
->transfer_buffer
;
2721 if (hcd
->self
.uses_dma
) {
2722 if (!buf
&& (urb
->transfer_dma
& 3)) {
2724 "%s: unaligned transfer with no transfer_buffer",
2731 if (!(urb
->transfer_flags
& URB_NO_INTERRUPT
))
2732 tflags
|= URB_GIVEBACK_ASAP
;
2733 if (urb
->transfer_flags
& URB_ZERO_PACKET
)
2734 tflags
|= URB_SEND_ZERO_PACKET
;
2736 dwc2_urb
->priv
= urb
;
2737 dwc2_urb
->buf
= buf
;
2738 dwc2_urb
->dma
= urb
->transfer_dma
;
2739 dwc2_urb
->length
= urb
->transfer_buffer_length
;
2740 dwc2_urb
->setup_packet
= urb
->setup_packet
;
2741 dwc2_urb
->setup_dma
= urb
->setup_dma
;
2742 dwc2_urb
->flags
= tflags
;
2743 dwc2_urb
->interval
= urb
->interval
;
2744 dwc2_urb
->status
= -EINPROGRESS
;
2746 for (i
= 0; i
< urb
->number_of_packets
; ++i
)
2747 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb
, i
,
2748 urb
->iso_frame_desc
[i
].offset
,
2749 urb
->iso_frame_desc
[i
].length
);
2751 urb
->hcpriv
= dwc2_urb
;
2752 qh
= (struct dwc2_qh
*) ep
->hcpriv
;
2753 /* Create QH for the endpoint if it doesn't exist */
2755 qh
= dwc2_hcd_qh_create(hsotg
, dwc2_urb
, mem_flags
);
2761 qh_allocated
= true;
2764 qtd
= kzalloc(sizeof(*qtd
), mem_flags
);
2770 spin_lock_irqsave(&hsotg
->lock
, flags
);
2771 retval
= usb_hcd_link_urb_to_ep(hcd
, urb
);
2775 retval
= dwc2_hcd_urb_enqueue(hsotg
, dwc2_urb
, qh
, qtd
);
2779 if (alloc_bandwidth
) {
2780 dwc2_allocate_bus_bandwidth(hcd
,
2781 dwc2_hcd_get_ep_bandwidth(hsotg
, ep
),
2785 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2790 dwc2_urb
->priv
= NULL
;
2791 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
2793 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2798 struct dwc2_qtd
*qtd2
, *qtd2_tmp
;
2801 dwc2_hcd_qh_unlink(hsotg
, qh
);
2802 /* Free each QTD in the QH's QTD list */
2803 list_for_each_entry_safe(qtd2
, qtd2_tmp
, &qh
->qtd_list
,
2805 dwc2_hcd_qtd_unlink_and_free(hsotg
, qtd2
, qh
);
2806 dwc2_hcd_qh_free(hsotg
, qh
);
2815 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
2817 static int _dwc2_hcd_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
,
2820 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
2822 unsigned long flags
;
2824 dev_dbg(hsotg
->dev
, "DWC OTG HCD URB Dequeue\n");
2825 dwc2_dump_urb_info(hcd
, urb
, "urb_dequeue");
2827 spin_lock_irqsave(&hsotg
->lock
, flags
);
2829 rc
= usb_hcd_check_unlink_urb(hcd
, urb
, status
);
2834 dev_dbg(hsotg
->dev
, "## urb->hcpriv is NULL ##\n");
2838 rc
= dwc2_hcd_urb_dequeue(hsotg
, urb
->hcpriv
);
2840 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
2845 /* Higher layer software sets URB status */
2846 spin_unlock(&hsotg
->lock
);
2847 usb_hcd_giveback_urb(hcd
, urb
, status
);
2848 spin_lock(&hsotg
->lock
);
2850 dev_dbg(hsotg
->dev
, "Called usb_hcd_giveback_urb()\n");
2851 dev_dbg(hsotg
->dev
, " urb->status = %d\n", urb
->status
);
2853 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2859 * Frees resources in the DWC_otg controller related to a given endpoint. Also
2860 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
2861 * must already be dequeued.
2863 static void _dwc2_hcd_endpoint_disable(struct usb_hcd
*hcd
,
2864 struct usb_host_endpoint
*ep
)
2866 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
2869 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
2870 ep
->desc
.bEndpointAddress
, ep
->hcpriv
);
2871 dwc2_hcd_endpoint_disable(hsotg
, ep
, 250);
2875 * Resets endpoint specific parameter values, in current version used to reset
2876 * the data toggle (as a WA). This function can be called from usb_clear_halt
2879 static void _dwc2_hcd_endpoint_reset(struct usb_hcd
*hcd
,
2880 struct usb_host_endpoint
*ep
)
2882 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
2883 unsigned long flags
;
2886 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
2887 ep
->desc
.bEndpointAddress
);
2889 spin_lock_irqsave(&hsotg
->lock
, flags
);
2890 dwc2_hcd_endpoint_reset(hsotg
, ep
);
2891 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2895 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
2896 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
2899 * This function is called by the USB core when an interrupt occurs
2901 static irqreturn_t
_dwc2_hcd_irq(struct usb_hcd
*hcd
)
2903 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
2905 return dwc2_handle_hcd_intr(hsotg
);
2909 * Creates Status Change bitmap for the root hub and root port. The bitmap is
2910 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
2911 * is the status change indicator for the single root port. Returns 1 if either
2912 * change indicator is 1, otherwise returns 0.
2914 static int _dwc2_hcd_hub_status_data(struct usb_hcd
*hcd
, char *buf
)
2916 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
2918 buf
[0] = dwc2_hcd_is_status_changed(hsotg
, 1) << 1;
2922 /* Handles hub class-specific requests */
2923 static int _dwc2_hcd_hub_control(struct usb_hcd
*hcd
, u16 typereq
, u16 wvalue
,
2924 u16 windex
, char *buf
, u16 wlength
)
2926 int retval
= dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd
), typereq
,
2927 wvalue
, windex
, buf
, wlength
);
2931 /* Handles hub TT buffer clear completions */
2932 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd
*hcd
,
2933 struct usb_host_endpoint
*ep
)
2935 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
2937 unsigned long flags
;
2943 spin_lock_irqsave(&hsotg
->lock
, flags
);
2944 qh
->tt_buffer_dirty
= 0;
2946 if (hsotg
->flags
.b
.port_connect_status
)
2947 dwc2_hcd_queue_transactions(hsotg
, DWC2_TRANSACTION_ALL
);
2949 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2952 static struct hc_driver dwc2_hc_driver
= {
2953 .description
= "dwc2_hsotg",
2954 .product_desc
= "DWC OTG Controller",
2955 .hcd_priv_size
= sizeof(struct wrapper_priv_data
),
2957 .irq
= _dwc2_hcd_irq
,
2958 .flags
= HCD_MEMORY
| HCD_USB2
,
2960 .start
= _dwc2_hcd_start
,
2961 .stop
= _dwc2_hcd_stop
,
2962 .urb_enqueue
= _dwc2_hcd_urb_enqueue
,
2963 .urb_dequeue
= _dwc2_hcd_urb_dequeue
,
2964 .endpoint_disable
= _dwc2_hcd_endpoint_disable
,
2965 .endpoint_reset
= _dwc2_hcd_endpoint_reset
,
2966 .get_frame_number
= _dwc2_hcd_get_frame_number
,
2968 .hub_status_data
= _dwc2_hcd_hub_status_data
,
2969 .hub_control
= _dwc2_hcd_hub_control
,
2970 .clear_tt_buffer_complete
= _dwc2_hcd_clear_tt_buffer_complete
,
2972 .bus_suspend
= _dwc2_hcd_suspend
,
2973 .bus_resume
= _dwc2_hcd_resume
,
2977 * Frees secondary storage associated with the dwc2_hsotg structure contained
2978 * in the struct usb_hcd field
2980 static void dwc2_hcd_free(struct dwc2_hsotg
*hsotg
)
2986 dev_dbg(hsotg
->dev
, "DWC OTG HCD FREE\n");
2988 /* Free memory for QH/QTD lists */
2989 dwc2_qh_list_free(hsotg
, &hsotg
->non_periodic_sched_inactive
);
2990 dwc2_qh_list_free(hsotg
, &hsotg
->non_periodic_sched_active
);
2991 dwc2_qh_list_free(hsotg
, &hsotg
->periodic_sched_inactive
);
2992 dwc2_qh_list_free(hsotg
, &hsotg
->periodic_sched_ready
);
2993 dwc2_qh_list_free(hsotg
, &hsotg
->periodic_sched_assigned
);
2994 dwc2_qh_list_free(hsotg
, &hsotg
->periodic_sched_queued
);
2996 /* Free memory for the host channels */
2997 for (i
= 0; i
< MAX_EPS_CHANNELS
; i
++) {
2998 struct dwc2_host_chan
*chan
= hsotg
->hc_ptr_array
[i
];
3001 dev_dbg(hsotg
->dev
, "HCD Free channel #%i, chan=%p\n",
3003 hsotg
->hc_ptr_array
[i
] = NULL
;
3008 if (hsotg
->core_params
->dma_enable
> 0) {
3009 if (hsotg
->status_buf
) {
3010 dma_free_coherent(hsotg
->dev
, DWC2_HCD_STATUS_BUF_SIZE
,
3012 hsotg
->status_buf_dma
);
3013 hsotg
->status_buf
= NULL
;
3016 kfree(hsotg
->status_buf
);
3017 hsotg
->status_buf
= NULL
;
3020 ahbcfg
= dwc2_readl(hsotg
->regs
+ GAHBCFG
);
3022 /* Disable all interrupts */
3023 ahbcfg
&= ~GAHBCFG_GLBL_INTR_EN
;
3024 dwc2_writel(ahbcfg
, hsotg
->regs
+ GAHBCFG
);
3025 dwc2_writel(0, hsotg
->regs
+ GINTMSK
);
3027 if (hsotg
->hw_params
.snpsid
>= DWC2_CORE_REV_3_00a
) {
3028 dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
3029 dctl
|= DCTL_SFTDISCON
;
3030 dwc2_writel(dctl
, hsotg
->regs
+ DCTL
);
3033 if (hsotg
->wq_otg
) {
3034 if (!cancel_work_sync(&hsotg
->wf_otg
))
3035 flush_workqueue(hsotg
->wq_otg
);
3036 destroy_workqueue(hsotg
->wq_otg
);
3039 del_timer(&hsotg
->wkp_timer
);
3042 static void dwc2_hcd_release(struct dwc2_hsotg
*hsotg
)
3044 /* Turn off all host-specific interrupts */
3045 dwc2_disable_host_interrupts(hsotg
);
3047 dwc2_hcd_free(hsotg
);
3051 * Initializes the HCD. This function allocates memory for and initializes the
3052 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
3053 * USB bus with the core and calls the hc_driver->start() function. It returns
3054 * a negative error on failure.
3056 int dwc2_hcd_init(struct dwc2_hsotg
*hsotg
, int irq
)
3058 struct usb_hcd
*hcd
;
3059 struct dwc2_host_chan
*channel
;
3061 int i
, num_channels
;
3067 dev_dbg(hsotg
->dev
, "DWC OTG HCD INIT\n");
3071 hcfg
= dwc2_readl(hsotg
->regs
+ HCFG
);
3072 dev_dbg(hsotg
->dev
, "hcfg=%08x\n", hcfg
);
3074 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3075 hsotg
->frame_num_array
= kzalloc(sizeof(*hsotg
->frame_num_array
) *
3076 FRAME_NUM_ARRAY_SIZE
, GFP_KERNEL
);
3077 if (!hsotg
->frame_num_array
)
3079 hsotg
->last_frame_num_array
= kzalloc(
3080 sizeof(*hsotg
->last_frame_num_array
) *
3081 FRAME_NUM_ARRAY_SIZE
, GFP_KERNEL
);
3082 if (!hsotg
->last_frame_num_array
)
3084 hsotg
->last_frame_num
= HFNUM_MAX_FRNUM
;
3087 /* Check if the bus driver or platform code has setup a dma_mask */
3088 if (hsotg
->core_params
->dma_enable
> 0 &&
3089 hsotg
->dev
->dma_mask
== NULL
) {
3090 dev_warn(hsotg
->dev
,
3091 "dma_mask not set, disabling DMA\n");
3092 hsotg
->core_params
->dma_enable
= 0;
3093 hsotg
->core_params
->dma_desc_enable
= 0;
3096 /* Set device flags indicating whether the HCD supports DMA */
3097 if (hsotg
->core_params
->dma_enable
> 0) {
3098 if (dma_set_mask(hsotg
->dev
, DMA_BIT_MASK(32)) < 0)
3099 dev_warn(hsotg
->dev
, "can't set DMA mask\n");
3100 if (dma_set_coherent_mask(hsotg
->dev
, DMA_BIT_MASK(32)) < 0)
3101 dev_warn(hsotg
->dev
, "can't set coherent DMA mask\n");
3104 hcd
= usb_create_hcd(&dwc2_hc_driver
, hsotg
->dev
, dev_name(hsotg
->dev
));
3108 if (hsotg
->core_params
->dma_enable
<= 0)
3109 hcd
->self
.uses_dma
= 0;
3113 ((struct wrapper_priv_data
*) &hcd
->hcd_priv
)->hsotg
= hsotg
;
3117 * Disable the global interrupt until all the interrupt handlers are
3120 dwc2_disable_global_interrupts(hsotg
);
3122 /* Initialize the DWC_otg core, and select the Phy type */
3123 retval
= dwc2_core_init(hsotg
, true);
3127 /* Create new workqueue and init work */
3129 hsotg
->wq_otg
= create_singlethread_workqueue("dwc2");
3130 if (!hsotg
->wq_otg
) {
3131 dev_err(hsotg
->dev
, "Failed to create workqueue\n");
3134 INIT_WORK(&hsotg
->wf_otg
, dwc2_conn_id_status_change
);
3136 setup_timer(&hsotg
->wkp_timer
, dwc2_wakeup_detected
,
3137 (unsigned long)hsotg
);
3139 /* Initialize the non-periodic schedule */
3140 INIT_LIST_HEAD(&hsotg
->non_periodic_sched_inactive
);
3141 INIT_LIST_HEAD(&hsotg
->non_periodic_sched_active
);
3143 /* Initialize the periodic schedule */
3144 INIT_LIST_HEAD(&hsotg
->periodic_sched_inactive
);
3145 INIT_LIST_HEAD(&hsotg
->periodic_sched_ready
);
3146 INIT_LIST_HEAD(&hsotg
->periodic_sched_assigned
);
3147 INIT_LIST_HEAD(&hsotg
->periodic_sched_queued
);
3150 * Create a host channel descriptor for each host channel implemented
3151 * in the controller. Initialize the channel descriptor array.
3153 INIT_LIST_HEAD(&hsotg
->free_hc_list
);
3154 num_channels
= hsotg
->core_params
->host_channels
;
3155 memset(&hsotg
->hc_ptr_array
[0], 0, sizeof(hsotg
->hc_ptr_array
));
3157 for (i
= 0; i
< num_channels
; i
++) {
3158 channel
= kzalloc(sizeof(*channel
), GFP_KERNEL
);
3159 if (channel
== NULL
)
3161 channel
->hc_num
= i
;
3162 hsotg
->hc_ptr_array
[i
] = channel
;
3165 if (hsotg
->core_params
->uframe_sched
> 0)
3166 dwc2_hcd_init_usecs(hsotg
);
3168 /* Initialize hsotg start work */
3169 INIT_DELAYED_WORK(&hsotg
->start_work
, dwc2_hcd_start_func
);
3171 /* Initialize port reset work */
3172 INIT_DELAYED_WORK(&hsotg
->reset_work
, dwc2_hcd_reset_func
);
3175 * Allocate space for storing data on status transactions. Normally no
3176 * data is sent, but this space acts as a bit bucket. This must be
3177 * done after usb_add_hcd since that function allocates the DMA buffer
3180 if (hsotg
->core_params
->dma_enable
> 0)
3181 hsotg
->status_buf
= dma_alloc_coherent(hsotg
->dev
,
3182 DWC2_HCD_STATUS_BUF_SIZE
,
3183 &hsotg
->status_buf_dma
, GFP_KERNEL
);
3185 hsotg
->status_buf
= kzalloc(DWC2_HCD_STATUS_BUF_SIZE
,
3188 if (!hsotg
->status_buf
)
3192 * Create kmem caches to handle descriptor buffers in descriptor
3194 * Alignment must be set to 512 bytes.
3196 if (hsotg
->core_params
->dma_desc_enable
||
3197 hsotg
->core_params
->dma_desc_fs_enable
) {
3198 hsotg
->desc_gen_cache
= kmem_cache_create("dwc2-gen-desc",
3199 sizeof(struct dwc2_hcd_dma_desc
) *
3200 MAX_DMA_DESC_NUM_GENERIC
, 512, SLAB_CACHE_DMA
,
3202 if (!hsotg
->desc_gen_cache
) {
3204 "unable to create dwc2 generic desc cache\n");
3207 * Disable descriptor dma mode since it will not be
3210 hsotg
->core_params
->dma_desc_enable
= 0;
3211 hsotg
->core_params
->dma_desc_fs_enable
= 0;
3214 hsotg
->desc_hsisoc_cache
= kmem_cache_create("dwc2-hsisoc-desc",
3215 sizeof(struct dwc2_hcd_dma_desc
) *
3216 MAX_DMA_DESC_NUM_HS_ISOC
, 512, 0, NULL
);
3217 if (!hsotg
->desc_hsisoc_cache
) {
3219 "unable to create dwc2 hs isoc desc cache\n");
3221 kmem_cache_destroy(hsotg
->desc_gen_cache
);
3224 * Disable descriptor dma mode since it will not be
3227 hsotg
->core_params
->dma_desc_enable
= 0;
3228 hsotg
->core_params
->dma_desc_fs_enable
= 0;
3232 hsotg
->otg_port
= 1;
3233 hsotg
->frame_list
= NULL
;
3234 hsotg
->frame_list_dma
= 0;
3235 hsotg
->periodic_qh_count
= 0;
3237 /* Initiate lx_state to L3 disconnected state */
3238 hsotg
->lx_state
= DWC2_L3
;
3240 hcd
->self
.otg_port
= hsotg
->otg_port
;
3242 /* Don't support SG list at this point */
3243 hcd
->self
.sg_tablesize
= 0;
3245 if (!IS_ERR_OR_NULL(hsotg
->uphy
))
3246 otg_set_host(hsotg
->uphy
->otg
, &hcd
->self
);
3249 * Finish generic HCD initialization and start the HCD. This function
3250 * allocates the DMA buffer pool, registers the USB bus, requests the
3251 * IRQ line, and calls hcd_start method.
3253 retval
= usb_add_hcd(hcd
, irq
, IRQF_SHARED
);
3257 device_wakeup_enable(hcd
->self
.controller
);
3259 dwc2_hcd_dump_state(hsotg
);
3261 dwc2_enable_global_interrupts(hsotg
);
3266 kmem_cache_destroy(hsotg
->desc_gen_cache
);
3267 kmem_cache_destroy(hsotg
->desc_hsisoc_cache
);
3269 dwc2_hcd_release(hsotg
);
3273 kfree(hsotg
->core_params
);
3275 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3276 kfree(hsotg
->last_frame_num_array
);
3277 kfree(hsotg
->frame_num_array
);
3280 dev_err(hsotg
->dev
, "%s() FAILED, returning %d\n", __func__
, retval
);
3286 * Frees memory and resources associated with the HCD and deregisters the bus.
3288 void dwc2_hcd_remove(struct dwc2_hsotg
*hsotg
)
3290 struct usb_hcd
*hcd
;
3292 dev_dbg(hsotg
->dev
, "DWC OTG HCD REMOVE\n");
3294 hcd
= dwc2_hsotg_to_hcd(hsotg
);
3295 dev_dbg(hsotg
->dev
, "hsotg->hcd = %p\n", hcd
);
3298 dev_dbg(hsotg
->dev
, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
3303 if (!IS_ERR_OR_NULL(hsotg
->uphy
))
3304 otg_set_host(hsotg
->uphy
->otg
, NULL
);
3306 usb_remove_hcd(hcd
);
3309 kmem_cache_destroy(hsotg
->desc_gen_cache
);
3310 kmem_cache_destroy(hsotg
->desc_hsisoc_cache
);
3312 dwc2_hcd_release(hsotg
);
3315 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3316 kfree(hsotg
->last_frame_num_array
);
3317 kfree(hsotg
->frame_num_array
);