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mmc: mediatek: add SD write protect support
[linux-2.6/btrfs-unstable.git] / drivers / mmc / host / mtk-sd.c
blobf01972eb57e967030817ba8768cf92b3fecafee0
1 /*
2 * Copyright (c) 2014-2015 MediaTek Inc.
3 * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/module.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/ioport.h>
20 #include <linux/irq.h>
21 #include <linux/of_address.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_gpio.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31
32 #include <linux/mmc/card.h>
33 #include <linux/mmc/core.h>
34 #include <linux/mmc/host.h>
35 #include <linux/mmc/mmc.h>
36 #include <linux/mmc/sd.h>
37 #include <linux/mmc/sdio.h>
38 #include <linux/mmc/slot-gpio.h>
39
40 #define MAX_BD_NUM 1024
41
42 /*--------------------------------------------------------------------------*/
43 /* Common Definition */
44 /*--------------------------------------------------------------------------*/
45 #define MSDC_BUS_1BITS 0x0
46 #define MSDC_BUS_4BITS 0x1
47 #define MSDC_BUS_8BITS 0x2
48
49 #define MSDC_BURST_64B 0x6
50
51 /*--------------------------------------------------------------------------*/
52 /* Register Offset */
53 /*--------------------------------------------------------------------------*/
54 #define MSDC_CFG 0x0
55 #define MSDC_IOCON 0x04
56 #define MSDC_PS 0x08
57 #define MSDC_INT 0x0c
58 #define MSDC_INTEN 0x10
59 #define MSDC_FIFOCS 0x14
60 #define SDC_CFG 0x30
61 #define SDC_CMD 0x34
62 #define SDC_ARG 0x38
63 #define SDC_STS 0x3c
64 #define SDC_RESP0 0x40
65 #define SDC_RESP1 0x44
66 #define SDC_RESP2 0x48
67 #define SDC_RESP3 0x4c
68 #define SDC_BLK_NUM 0x50
69 #define EMMC_IOCON 0x7c
70 #define SDC_ACMD_RESP 0x80
71 #define MSDC_DMA_SA 0x90
72 #define MSDC_DMA_CTRL 0x98
73 #define MSDC_DMA_CFG 0x9c
74 #define MSDC_PATCH_BIT 0xb0
75 #define MSDC_PATCH_BIT1 0xb4
76 #define MSDC_PAD_TUNE 0xec
77 #define PAD_DS_TUNE 0x188
78 #define EMMC50_CFG0 0x208
79
80 /*--------------------------------------------------------------------------*/
81 /* Register Mask */
82 /*--------------------------------------------------------------------------*/
83
84 /* MSDC_CFG mask */
85 #define MSDC_CFG_MODE (0x1 << 0) /* RW */
86 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
87 #define MSDC_CFG_RST (0x1 << 2) /* RW */
88 #define MSDC_CFG_PIO (0x1 << 3) /* RW */
89 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
90 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
91 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
92 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */
93 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */
94 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
95 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */
96
97 /* MSDC_IOCON mask */
98 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
99 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
100 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
101 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
102 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
103 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
104 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */
105 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
106 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
107 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
108 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
109 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
110 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
111 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
112 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
113 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
114
115 /* MSDC_PS mask */
116 #define MSDC_PS_CDEN (0x1 << 0) /* RW */
117 #define MSDC_PS_CDSTS (0x1 << 1) /* R */
118 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
119 #define MSDC_PS_DAT (0xff << 16) /* R */
120 #define MSDC_PS_CMD (0x1 << 24) /* R */
121 #define MSDC_PS_WP (0x1 << 31) /* R */
122
123 /* MSDC_INT mask */
124 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
125 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */
126 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
127 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
128 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
129 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
130 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
131 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
132 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
133 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
134 #define MSDC_INT_CSTA (0x1 << 11) /* R */
135 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
136 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
137 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
138 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
139 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
140 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */
141 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */
142 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */
143
144 /* MSDC_INTEN mask */
145 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
146 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
147 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
148 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
149 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
150 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
151 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
152 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
153 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
154 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
155 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
156 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
157 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
158 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
159 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
160 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
161 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */
162 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */
163 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */
164
165 /* MSDC_FIFOCS mask */
166 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
167 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
168 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */
169
170 /* SDC_CFG mask */
171 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
172 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
173 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
174 #define SDC_CFG_SDIO (0x1 << 19) /* RW */
175 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
176 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
177 #define SDC_CFG_DTOC (0xff << 24) /* RW */
178
179 /* SDC_STS mask */
180 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
181 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
182 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
183
184 /* MSDC_DMA_CTRL mask */
185 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
186 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
187 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
188 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
189 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
190 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
191
192 /* MSDC_DMA_CFG mask */
193 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
194 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
195 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */
196 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */
197 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */
198
199 /* MSDC_PATCH_BIT mask */
200 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
201 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7)
202 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10)
203 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
204 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
205 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
206 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
207 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
208 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
209 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
210 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
211 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
212
213 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */
214 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */
215
216 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */
217 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */
218 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */
219
220 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */
221 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */
222 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */
223
224 #define REQ_CMD_EIO (0x1 << 0)
225 #define REQ_CMD_TMO (0x1 << 1)
226 #define REQ_DAT_ERR (0x1 << 2)
227 #define REQ_STOP_EIO (0x1 << 3)
228 #define REQ_STOP_TMO (0x1 << 4)
229 #define REQ_CMD_BUSY (0x1 << 5)
230
231 #define MSDC_PREPARE_FLAG (0x1 << 0)
232 #define MSDC_ASYNC_FLAG (0x1 << 1)
233 #define MSDC_MMAP_FLAG (0x1 << 2)
234
235 #define MTK_MMC_AUTOSUSPEND_DELAY 50
236 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
237 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
238
239 #define PAD_DELAY_MAX 32 /* PAD delay cells */
240 /*--------------------------------------------------------------------------*/
241 /* Descriptor Structure */
242 /*--------------------------------------------------------------------------*/
243 struct mt_gpdma_desc {
244 u32 gpd_info;
245 #define GPDMA_DESC_HWO (0x1 << 0)
246 #define GPDMA_DESC_BDP (0x1 << 1)
247 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
248 #define GPDMA_DESC_INT (0x1 << 16)
249 u32 next;
250 u32 ptr;
251 u32 gpd_data_len;
252 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
253 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */
254 u32 arg;
255 u32 blknum;
256 u32 cmd;
257 };
258
259 struct mt_bdma_desc {
260 u32 bd_info;
261 #define BDMA_DESC_EOL (0x1 << 0)
262 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
263 #define BDMA_DESC_BLKPAD (0x1 << 17)
264 #define BDMA_DESC_DWPAD (0x1 << 18)
265 u32 next;
266 u32 ptr;
267 u32 bd_data_len;
268 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
269 };
270
271 struct msdc_dma {
272 struct scatterlist *sg; /* I/O scatter list */
273 struct mt_gpdma_desc *gpd; /* pointer to gpd array */
274 struct mt_bdma_desc *bd; /* pointer to bd array */
275 dma_addr_t gpd_addr; /* the physical address of gpd array */
276 dma_addr_t bd_addr; /* the physical address of bd array */
277 };
278
279 struct msdc_save_para {
280 u32 msdc_cfg;
281 u32 iocon;
282 u32 sdc_cfg;
283 u32 pad_tune;
284 u32 patch_bit0;
285 u32 patch_bit1;
286 u32 pad_ds_tune;
287 u32 emmc50_cfg0;
288 };
289
290 struct msdc_delay_phase {
291 u8 maxlen;
292 u8 start;
293 u8 final_phase;
294 };
295
296 struct msdc_host {
297 struct device *dev;
298 struct mmc_host *mmc; /* mmc structure */
299 int cmd_rsp;
300
301 spinlock_t lock;
302 struct mmc_request *mrq;
303 struct mmc_command *cmd;
304 struct mmc_data *data;
305 int error;
306
307 void __iomem *base; /* host base address */
308
309 struct msdc_dma dma; /* dma channel */
310 u64 dma_mask;
311
312 u32 timeout_ns; /* data timeout ns */
313 u32 timeout_clks; /* data timeout clks */
314
315 struct pinctrl *pinctrl;
316 struct pinctrl_state *pins_default;
317 struct pinctrl_state *pins_uhs;
318 struct delayed_work req_timeout;
319 int irq; /* host interrupt */
320
321 struct clk *src_clk; /* msdc source clock */
322 struct clk *h_clk; /* msdc h_clk */
323 u32 mclk; /* mmc subsystem clock frequency */
324 u32 src_clk_freq; /* source clock frequency */
325 u32 sclk; /* SD/MS bus clock frequency */
326 unsigned char timing;
327 bool vqmmc_enabled;
328 u32 hs400_ds_delay;
329 struct msdc_save_para save_para; /* used when gate HCLK */
330 };
331
332 static void sdr_set_bits(void __iomem *reg, u32 bs)
333 {
334 u32 val = readl(reg);
335
336 val |= bs;
337 writel(val, reg);
338 }
339
340 static void sdr_clr_bits(void __iomem *reg, u32 bs)
341 {
342 u32 val = readl(reg);
343
344 val &= ~bs;
345 writel(val, reg);
346 }
347
348 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
349 {
350 unsigned int tv = readl(reg);
351
352 tv &= ~field;
353 tv |= ((val) << (ffs((unsigned int)field) - 1));
354 writel(tv, reg);
355 }
356
357 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
358 {
359 unsigned int tv = readl(reg);
360
361 *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
362 }
363
364 static void msdc_reset_hw(struct msdc_host *host)
365 {
366 u32 val;
367
368 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
369 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST)
370 cpu_relax();
371
372 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
373 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR)
374 cpu_relax();
375
376 val = readl(host->base + MSDC_INT);
377 writel(val, host->base + MSDC_INT);
378 }
379
380 static void msdc_cmd_next(struct msdc_host *host,
381 struct mmc_request *mrq, struct mmc_command *cmd);
382
383 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
384 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
385 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
386 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
387 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
388 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
389
390 static u8 msdc_dma_calcs(u8 *buf, u32 len)
391 {
392 u32 i, sum = 0;
393
394 for (i = 0; i < len; i++)
395 sum += buf[i];
396 return 0xff - (u8) sum;
397 }
398
399 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
400 struct mmc_data *data)
401 {
402 unsigned int j, dma_len;
403 dma_addr_t dma_address;
404 u32 dma_ctrl;
405 struct scatterlist *sg;
406 struct mt_gpdma_desc *gpd;
407 struct mt_bdma_desc *bd;
408
409 sg = data->sg;
410
411 gpd = dma->gpd;
412 bd = dma->bd;
413
414 /* modify gpd */
415 gpd->gpd_info |= GPDMA_DESC_HWO;
416 gpd->gpd_info |= GPDMA_DESC_BDP;
417 /* need to clear first. use these bits to calc checksum */
418 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
419 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
420
421 /* modify bd */
422 for_each_sg(data->sg, sg, data->sg_count, j) {
423 dma_address = sg_dma_address(sg);
424 dma_len = sg_dma_len(sg);
425
426 /* init bd */
427 bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
428 bd[j].bd_info &= ~BDMA_DESC_DWPAD;
429 bd[j].ptr = (u32)dma_address;
430 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
431 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
432
433 if (j == data->sg_count - 1) /* the last bd */
434 bd[j].bd_info |= BDMA_DESC_EOL;
435 else
436 bd[j].bd_info &= ~BDMA_DESC_EOL;
437
438 /* checksume need to clear first */
439 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
440 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
441 }
442
443 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
444 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
445 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
446 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8);
447 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
448 writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA);
449 }
450
451 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq)
452 {
453 struct mmc_data *data = mrq->data;
454
455 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
456 bool read = (data->flags & MMC_DATA_READ) != 0;
457
458 data->host_cookie |= MSDC_PREPARE_FLAG;
459 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
460 read ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
461 }
462 }
463
464 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq)
465 {
466 struct mmc_data *data = mrq->data;
467
468 if (data->host_cookie & MSDC_ASYNC_FLAG)
469 return;
470
471 if (data->host_cookie & MSDC_PREPARE_FLAG) {
472 bool read = (data->flags & MMC_DATA_READ) != 0;
473
474 dma_unmap_sg(host->dev, data->sg, data->sg_len,
475 read ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
476 data->host_cookie &= ~MSDC_PREPARE_FLAG;
477 }
478 }
479
480 /* clock control primitives */
481 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
482 {
483 u32 timeout, clk_ns;
484 u32 mode = 0;
485
486 host->timeout_ns = ns;
487 host->timeout_clks = clks;
488 if (host->sclk == 0) {
489 timeout = 0;
490 } else {
491 clk_ns = 1000000000UL / host->sclk;
492 timeout = (ns + clk_ns - 1) / clk_ns + clks;
493 /* in 1048576 sclk cycle unit */
494 timeout = (timeout + (0x1 << 20) - 1) >> 20;
495 sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode);
496 /*DDR mode will double the clk cycles for data timeout */
497 timeout = mode >= 2 ? timeout * 2 : timeout;
498 timeout = timeout > 1 ? timeout - 1 : 0;
499 timeout = timeout > 255 ? 255 : timeout;
500 }
501 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout);
502 }
503
504 static void msdc_gate_clock(struct msdc_host *host)
505 {
506 clk_disable_unprepare(host->src_clk);
507 clk_disable_unprepare(host->h_clk);
508 }
509
510 static void msdc_ungate_clock(struct msdc_host *host)
511 {
512 clk_prepare_enable(host->h_clk);
513 clk_prepare_enable(host->src_clk);
514 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
515 cpu_relax();
516 }
517
518 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
519 {
520 u32 mode;
521 u32 flags;
522 u32 div;
523 u32 sclk;
524
525 if (!hz) {
526 dev_dbg(host->dev, "set mclk to 0\n");
527 host->mclk = 0;
528 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
529 return;
530 }
531
532 flags = readl(host->base + MSDC_INTEN);
533 sdr_clr_bits(host->base + MSDC_INTEN, flags);
534 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
535 if (timing == MMC_TIMING_UHS_DDR50 ||
536 timing == MMC_TIMING_MMC_DDR52 ||
537 timing == MMC_TIMING_MMC_HS400) {
538 if (timing == MMC_TIMING_MMC_HS400)
539 mode = 0x3;
540 else
541 mode = 0x2; /* ddr mode and use divisor */
542
543 if (hz >= (host->src_clk_freq >> 2)) {
544 div = 0; /* mean div = 1/4 */
545 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
546 } else {
547 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
548 sclk = (host->src_clk_freq >> 2) / div;
549 div = (div >> 1);
550 }
551
552 if (timing == MMC_TIMING_MMC_HS400 &&
553 hz >= (host->src_clk_freq >> 1)) {
554 sdr_set_bits(host->base + MSDC_CFG,
555 MSDC_CFG_HS400_CK_MODE);
556 sclk = host->src_clk_freq >> 1;
557 div = 0; /* div is ignore when bit18 is set */
558 }
559 } else if (hz >= host->src_clk_freq) {
560 mode = 0x1; /* no divisor */
561 div = 0;
562 sclk = host->src_clk_freq;
563 } else {
564 mode = 0x0; /* use divisor */
565 if (hz >= (host->src_clk_freq >> 1)) {
566 div = 0; /* mean div = 1/2 */
567 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
568 } else {
569 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
570 sclk = (host->src_clk_freq >> 2) / div;
571 }
572 }
573 sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
574 (mode << 8) | (div % 0xff));
575 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
576 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
577 cpu_relax();
578 host->sclk = sclk;
579 host->mclk = hz;
580 host->timing = timing;
581 /* need because clk changed. */
582 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
583 sdr_set_bits(host->base + MSDC_INTEN, flags);
584
585 dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->sclk, timing);
586 }
587
588 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
589 struct mmc_request *mrq, struct mmc_command *cmd)
590 {
591 u32 resp;
592
593 switch (mmc_resp_type(cmd)) {
594 /* Actually, R1, R5, R6, R7 are the same */
595 case MMC_RSP_R1:
596 resp = 0x1;
597 break;
598 case MMC_RSP_R1B:
599 resp = 0x7;
600 break;
601 case MMC_RSP_R2:
602 resp = 0x2;
603 break;
604 case MMC_RSP_R3:
605 resp = 0x3;
606 break;
607 case MMC_RSP_NONE:
608 default:
609 resp = 0x0;
610 break;
611 }
612
613 return resp;
614 }
615
616 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
617 struct mmc_request *mrq, struct mmc_command *cmd)
618 {
619 /* rawcmd :
620 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
621 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
622 */
623 u32 opcode = cmd->opcode;
624 u32 resp = msdc_cmd_find_resp(host, mrq, cmd);
625 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
626
627 host->cmd_rsp = resp;
628
629 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
630 opcode == MMC_STOP_TRANSMISSION)
631 rawcmd |= (0x1 << 14);
632 else if (opcode == SD_SWITCH_VOLTAGE)
633 rawcmd |= (0x1 << 30);
634 else if (opcode == SD_APP_SEND_SCR ||
635 opcode == SD_APP_SEND_NUM_WR_BLKS ||
636 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
637 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
638 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
639 rawcmd |= (0x1 << 11);
640
641 if (cmd->data) {
642 struct mmc_data *data = cmd->data;
643
644 if (mmc_op_multi(opcode)) {
645 if (mmc_card_mmc(host->mmc->card) && mrq->sbc &&
646 !(mrq->sbc->arg & 0xFFFF0000))
647 rawcmd |= 0x2 << 28; /* AutoCMD23 */
648 }
649
650 rawcmd |= ((data->blksz & 0xFFF) << 16);
651 if (data->flags & MMC_DATA_WRITE)
652 rawcmd |= (0x1 << 13);
653 if (data->blocks > 1)
654 rawcmd |= (0x2 << 11);
655 else
656 rawcmd |= (0x1 << 11);
657 /* Always use dma mode */
658 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
659
660 if (host->timeout_ns != data->timeout_ns ||
661 host->timeout_clks != data->timeout_clks)
662 msdc_set_timeout(host, data->timeout_ns,
663 data->timeout_clks);
664
665 writel(data->blocks, host->base + SDC_BLK_NUM);
666 }
667 return rawcmd;
668 }
669
670 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq,
671 struct mmc_command *cmd, struct mmc_data *data)
672 {
673 bool read;
674
675 WARN_ON(host->data);
676 host->data = data;
677 read = data->flags & MMC_DATA_READ;
678
679 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
680 msdc_dma_setup(host, &host->dma, data);
681 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
682 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
683 dev_dbg(host->dev, "DMA start\n");
684 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
685 __func__, cmd->opcode, data->blocks, read);
686 }
687
688 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
689 struct mmc_command *cmd)
690 {
691 u32 *rsp = cmd->resp;
692
693 rsp[0] = readl(host->base + SDC_ACMD_RESP);
694
695 if (events & MSDC_INT_ACMDRDY) {
696 cmd->error = 0;
697 } else {
698 msdc_reset_hw(host);
699 if (events & MSDC_INT_ACMDCRCERR) {
700 cmd->error = -EILSEQ;
701 host->error |= REQ_STOP_EIO;
702 } else if (events & MSDC_INT_ACMDTMO) {
703 cmd->error = -ETIMEDOUT;
704 host->error |= REQ_STOP_TMO;
705 }
706 dev_err(host->dev,
707 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
708 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
709 }
710 return cmd->error;
711 }
712
713 static void msdc_track_cmd_data(struct msdc_host *host,
714 struct mmc_command *cmd, struct mmc_data *data)
715 {
716 if (host->error)
717 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
718 __func__, cmd->opcode, cmd->arg, host->error);
719 }
720
721 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
722 {
723 unsigned long flags;
724 bool ret;
725
726 ret = cancel_delayed_work(&host->req_timeout);
727 if (!ret) {
728 /* delay work already running */
729 return;
730 }
731 spin_lock_irqsave(&host->lock, flags);
732 host->mrq = NULL;
733 spin_unlock_irqrestore(&host->lock, flags);
734
735 msdc_track_cmd_data(host, mrq->cmd, mrq->data);
736 if (mrq->data)
737 msdc_unprepare_data(host, mrq);
738 mmc_request_done(host->mmc, mrq);
739
740 pm_runtime_mark_last_busy(host->dev);
741 pm_runtime_put_autosuspend(host->dev);
742 }
743
744 /* returns true if command is fully handled; returns false otherwise */
745 static bool msdc_cmd_done(struct msdc_host *host, int events,
746 struct mmc_request *mrq, struct mmc_command *cmd)
747 {
748 bool done = false;
749 bool sbc_error;
750 unsigned long flags;
751 u32 *rsp = cmd->resp;
752
753 if (mrq->sbc && cmd == mrq->cmd &&
754 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
755 | MSDC_INT_ACMDTMO)))
756 msdc_auto_cmd_done(host, events, mrq->sbc);
757
758 sbc_error = mrq->sbc && mrq->sbc->error;
759
760 if (!sbc_error && !(events & (MSDC_INT_CMDRDY
761 | MSDC_INT_RSPCRCERR
762 | MSDC_INT_CMDTMO)))
763 return done;
764
765 spin_lock_irqsave(&host->lock, flags);
766 done = !host->cmd;
767 host->cmd = NULL;
768 spin_unlock_irqrestore(&host->lock, flags);
769
770 if (done)
771 return true;
772
773 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
774
775 if (cmd->flags & MMC_RSP_PRESENT) {
776 if (cmd->flags & MMC_RSP_136) {
777 rsp[0] = readl(host->base + SDC_RESP3);
778 rsp[1] = readl(host->base + SDC_RESP2);
779 rsp[2] = readl(host->base + SDC_RESP1);
780 rsp[3] = readl(host->base + SDC_RESP0);
781 } else {
782 rsp[0] = readl(host->base + SDC_RESP0);
783 }
784 }
785
786 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
787 msdc_reset_hw(host);
788 if (events & MSDC_INT_RSPCRCERR) {
789 cmd->error = -EILSEQ;
790 host->error |= REQ_CMD_EIO;
791 } else if (events & MSDC_INT_CMDTMO) {
792 cmd->error = -ETIMEDOUT;
793 host->error |= REQ_CMD_TMO;
794 }
795 }
796 if (cmd->error)
797 dev_dbg(host->dev,
798 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
799 __func__, cmd->opcode, cmd->arg, rsp[0],
800 cmd->error);
801
802 msdc_cmd_next(host, mrq, cmd);
803 return true;
804 }
805
806 /* It is the core layer's responsibility to ensure card status
807 * is correct before issue a request. but host design do below
808 * checks recommended.
809 */
810 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
811 struct mmc_request *mrq, struct mmc_command *cmd)
812 {
813 /* The max busy time we can endure is 20ms */
814 unsigned long tmo = jiffies + msecs_to_jiffies(20);
815
816 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) &&
817 time_before(jiffies, tmo))
818 cpu_relax();
819 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) {
820 dev_err(host->dev, "CMD bus busy detected\n");
821 host->error |= REQ_CMD_BUSY;
822 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
823 return false;
824 }
825
826 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
827 tmo = jiffies + msecs_to_jiffies(20);
828 /* R1B or with data, should check SDCBUSY */
829 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) &&
830 time_before(jiffies, tmo))
831 cpu_relax();
832 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) {
833 dev_err(host->dev, "Controller busy detected\n");
834 host->error |= REQ_CMD_BUSY;
835 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
836 return false;
837 }
838 }
839 return true;
840 }
841
842 static void msdc_start_command(struct msdc_host *host,
843 struct mmc_request *mrq, struct mmc_command *cmd)
844 {
845 u32 rawcmd;
846
847 WARN_ON(host->cmd);
848 host->cmd = cmd;
849
850 if (!msdc_cmd_is_ready(host, mrq, cmd))
851 return;
852
853 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
854 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
855 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
856 msdc_reset_hw(host);
857 }
858
859 cmd->error = 0;
860 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
861 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
862
863 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
864 writel(cmd->arg, host->base + SDC_ARG);
865 writel(rawcmd, host->base + SDC_CMD);
866 }
867
868 static void msdc_cmd_next(struct msdc_host *host,
869 struct mmc_request *mrq, struct mmc_command *cmd)
870 {
871 if (cmd->error || (mrq->sbc && mrq->sbc->error))
872 msdc_request_done(host, mrq);
873 else if (cmd == mrq->sbc)
874 msdc_start_command(host, mrq, mrq->cmd);
875 else if (!cmd->data)
876 msdc_request_done(host, mrq);
877 else
878 msdc_start_data(host, mrq, cmd, cmd->data);
879 }
880
881 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
882 {
883 struct msdc_host *host = mmc_priv(mmc);
884
885 host->error = 0;
886 WARN_ON(host->mrq);
887 host->mrq = mrq;
888
889 pm_runtime_get_sync(host->dev);
890
891 if (mrq->data)
892 msdc_prepare_data(host, mrq);
893
894 /* if SBC is required, we have HW option and SW option.
895 * if HW option is enabled, and SBC does not have "special" flags,
896 * use HW option, otherwise use SW option
897 */
898 if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
899 (mrq->sbc->arg & 0xFFFF0000)))
900 msdc_start_command(host, mrq, mrq->sbc);
901 else
902 msdc_start_command(host, mrq, mrq->cmd);
903 }
904
905 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
906 bool is_first_req)
907 {
908 struct msdc_host *host = mmc_priv(mmc);
909 struct mmc_data *data = mrq->data;
910
911 if (!data)
912 return;
913
914 msdc_prepare_data(host, mrq);
915 data->host_cookie |= MSDC_ASYNC_FLAG;
916 }
917
918 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
919 int err)
920 {
921 struct msdc_host *host = mmc_priv(mmc);
922 struct mmc_data *data;
923
924 data = mrq->data;
925 if (!data)
926 return;
927 if (data->host_cookie) {
928 data->host_cookie &= ~MSDC_ASYNC_FLAG;
929 msdc_unprepare_data(host, mrq);
930 }
931 }
932
933 static void msdc_data_xfer_next(struct msdc_host *host,
934 struct mmc_request *mrq, struct mmc_data *data)
935 {
936 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
937 !mrq->sbc)
938 msdc_start_command(host, mrq, mrq->stop);
939 else
940 msdc_request_done(host, mrq);
941 }
942
943 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
944 struct mmc_request *mrq, struct mmc_data *data)
945 {
946 struct mmc_command *stop = data->stop;
947 unsigned long flags;
948 bool done;
949 unsigned int check_data = events &
950 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
951 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
952 | MSDC_INT_DMA_PROTECT);
953
954 spin_lock_irqsave(&host->lock, flags);
955 done = !host->data;
956 if (check_data)
957 host->data = NULL;
958 spin_unlock_irqrestore(&host->lock, flags);
959
960 if (done)
961 return true;
962
963 if (check_data || (stop && stop->error)) {
964 dev_dbg(host->dev, "DMA status: 0x%8X\n",
965 readl(host->base + MSDC_DMA_CFG));
966 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
967 1);
968 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
969 cpu_relax();
970 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
971 dev_dbg(host->dev, "DMA stop\n");
972
973 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
974 data->bytes_xfered = data->blocks * data->blksz;
975 } else {
976 dev_dbg(host->dev, "interrupt events: %x\n", events);
977 msdc_reset_hw(host);
978 host->error |= REQ_DAT_ERR;
979 data->bytes_xfered = 0;
980
981 if (events & MSDC_INT_DATTMO)
982 data->error = -ETIMEDOUT;
983 else if (events & MSDC_INT_DATCRCERR)
984 data->error = -EILSEQ;
985
986 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
987 __func__, mrq->cmd->opcode, data->blocks);
988 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
989 (int)data->error, data->bytes_xfered);
990 }
991
992 msdc_data_xfer_next(host, mrq, data);
993 done = true;
994 }
995 return done;
996 }
997
998 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
999 {
1000 u32 val = readl(host->base + SDC_CFG);
1001
1002 val &= ~SDC_CFG_BUSWIDTH;
1003
1004 switch (width) {
1005 default:
1006 case MMC_BUS_WIDTH_1:
1007 val |= (MSDC_BUS_1BITS << 16);
1008 break;
1009 case MMC_BUS_WIDTH_4:
1010 val |= (MSDC_BUS_4BITS << 16);
1011 break;
1012 case MMC_BUS_WIDTH_8:
1013 val |= (MSDC_BUS_8BITS << 16);
1014 break;
1015 }
1016
1017 writel(val, host->base + SDC_CFG);
1018 dev_dbg(host->dev, "Bus Width = %d", width);
1019 }
1020
1021 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1022 {
1023 struct msdc_host *host = mmc_priv(mmc);
1024 int min_uv, max_uv;
1025 int ret = 0;
1026
1027 if (!IS_ERR(mmc->supply.vqmmc)) {
1028 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1029 min_uv = 3300000;
1030 max_uv = 3300000;
1031 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
1032 min_uv = 1800000;
1033 max_uv = 1800000;
1034 } else {
1035 dev_err(host->dev, "Unsupported signal voltage!\n");
1036 return -EINVAL;
1037 }
1038
1039 ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
1040 if (ret) {
1041 dev_err(host->dev,
1042 "Regulator set error %d: %d - %d\n",
1043 ret, min_uv, max_uv);
1044 } else {
1045 /* Apply different pinctrl settings for different signal voltage */
1046 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1047 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1048 else
1049 pinctrl_select_state(host->pinctrl, host->pins_default);
1050 }
1051 }
1052 return ret;
1053 }
1054
1055 static int msdc_card_busy(struct mmc_host *mmc)
1056 {
1057 struct msdc_host *host = mmc_priv(mmc);
1058 u32 status = readl(host->base + MSDC_PS);
1059
1060 /* check if any pin between dat[0:3] is low */
1061 if (((status >> 16) & 0xf) != 0xf)
1062 return 1;
1063
1064 return 0;
1065 }
1066
1067 static void msdc_request_timeout(struct work_struct *work)
1068 {
1069 struct msdc_host *host = container_of(work, struct msdc_host,
1070 req_timeout.work);
1071
1072 /* simulate HW timeout status */
1073 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1074 if (host->mrq) {
1075 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1076 host->mrq, host->mrq->cmd->opcode);
1077 if (host->cmd) {
1078 dev_err(host->dev, "%s: aborting cmd=%d\n",
1079 __func__, host->cmd->opcode);
1080 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1081 host->cmd);
1082 } else if (host->data) {
1083 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1084 __func__, host->mrq->cmd->opcode,
1085 host->data->blocks);
1086 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1087 host->data);
1088 }
1089 }
1090 }
1091
1092 static irqreturn_t msdc_irq(int irq, void *dev_id)
1093 {
1094 struct msdc_host *host = (struct msdc_host *) dev_id;
1095
1096 while (true) {
1097 unsigned long flags;
1098 struct mmc_request *mrq;
1099 struct mmc_command *cmd;
1100 struct mmc_data *data;
1101 u32 events, event_mask;
1102
1103 spin_lock_irqsave(&host->lock, flags);
1104 events = readl(host->base + MSDC_INT);
1105 event_mask = readl(host->base + MSDC_INTEN);
1106 /* clear interrupts */
1107 writel(events & event_mask, host->base + MSDC_INT);
1108
1109 mrq = host->mrq;
1110 cmd = host->cmd;
1111 data = host->data;
1112 spin_unlock_irqrestore(&host->lock, flags);
1113
1114 if (!(events & event_mask))
1115 break;
1116
1117 if (!mrq) {
1118 dev_err(host->dev,
1119 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1120 __func__, events, event_mask);
1121 WARN_ON(1);
1122 break;
1123 }
1124
1125 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1126
1127 if (cmd)
1128 msdc_cmd_done(host, events, mrq, cmd);
1129 else if (data)
1130 msdc_data_xfer_done(host, events, mrq, data);
1131 }
1132
1133 return IRQ_HANDLED;
1134 }
1135
1136 static void msdc_init_hw(struct msdc_host *host)
1137 {
1138 u32 val;
1139
1140 /* Configure to MMC/SD mode, clock free running */
1141 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1142
1143 /* Reset */
1144 msdc_reset_hw(host);
1145
1146 /* Disable card detection */
1147 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1148
1149 /* Disable and clear all interrupts */
1150 writel(0, host->base + MSDC_INTEN);
1151 val = readl(host->base + MSDC_INT);
1152 writel(val, host->base + MSDC_INT);
1153
1154 writel(0, host->base + MSDC_PAD_TUNE);
1155 writel(0, host->base + MSDC_IOCON);
1156 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1157 writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1158 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1159 writel(0xffff0089, host->base + MSDC_PATCH_BIT1);
1160 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1161
1162 /* Configure to enable SDIO mode.
1163 * it's must otherwise sdio cmd5 failed
1164 */
1165 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1166
1167 /* disable detect SDIO device interrupt function */
1168 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1169
1170 /* Configure to default data timeout */
1171 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1172
1173 dev_dbg(host->dev, "init hardware done!");
1174 }
1175
1176 static void msdc_deinit_hw(struct msdc_host *host)
1177 {
1178 u32 val;
1179 /* Disable and clear all interrupts */
1180 writel(0, host->base + MSDC_INTEN);
1181
1182 val = readl(host->base + MSDC_INT);
1183 writel(val, host->base + MSDC_INT);
1184 }
1185
1186 /* init gpd and bd list in msdc_drv_probe */
1187 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1188 {
1189 struct mt_gpdma_desc *gpd = dma->gpd;
1190 struct mt_bdma_desc *bd = dma->bd;
1191 int i;
1192
1193 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
1194
1195 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1196 gpd->ptr = (u32)dma->bd_addr; /* physical address */
1197 /* gpd->next is must set for desc DMA
1198 * That's why must alloc 2 gpd structure.
1199 */
1200 gpd->next = (u32)dma->gpd_addr + sizeof(struct mt_gpdma_desc);
1201 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1202 for (i = 0; i < (MAX_BD_NUM - 1); i++)
1203 bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1);
1204 }
1205
1206 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1207 {
1208 struct msdc_host *host = mmc_priv(mmc);
1209 int ret;
1210
1211 pm_runtime_get_sync(host->dev);
1212
1213 msdc_set_buswidth(host, ios->bus_width);
1214
1215 /* Suspend/Resume will do power off/on */
1216 switch (ios->power_mode) {
1217 case MMC_POWER_UP:
1218 if (!IS_ERR(mmc->supply.vmmc)) {
1219 msdc_init_hw(host);
1220 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1221 ios->vdd);
1222 if (ret) {
1223 dev_err(host->dev, "Failed to set vmmc power!\n");
1224 goto end;
1225 }
1226 }
1227 break;
1228 case MMC_POWER_ON:
1229 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1230 ret = regulator_enable(mmc->supply.vqmmc);
1231 if (ret)
1232 dev_err(host->dev, "Failed to set vqmmc power!\n");
1233 else
1234 host->vqmmc_enabled = true;
1235 }
1236 break;
1237 case MMC_POWER_OFF:
1238 if (!IS_ERR(mmc->supply.vmmc))
1239 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1240
1241 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1242 regulator_disable(mmc->supply.vqmmc);
1243 host->vqmmc_enabled = false;
1244 }
1245 break;
1246 default:
1247 break;
1248 }
1249
1250 if (host->mclk != ios->clock || host->timing != ios->timing)
1251 msdc_set_mclk(host, ios->timing, ios->clock);
1252
1253 end:
1254 pm_runtime_mark_last_busy(host->dev);
1255 pm_runtime_put_autosuspend(host->dev);
1256 }
1257
1258 static u32 test_delay_bit(u32 delay, u32 bit)
1259 {
1260 bit %= PAD_DELAY_MAX;
1261 return delay & (1 << bit);
1262 }
1263
1264 static int get_delay_len(u32 delay, u32 start_bit)
1265 {
1266 int i;
1267
1268 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
1269 if (test_delay_bit(delay, start_bit + i) == 0)
1270 return i;
1271 }
1272 return PAD_DELAY_MAX - start_bit;
1273 }
1274
1275 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
1276 {
1277 int start = 0, len = 0;
1278 int start_final = 0, len_final = 0;
1279 u8 final_phase = 0xff;
1280 struct msdc_delay_phase delay_phase = { 0, };
1281
1282 if (delay == 0) {
1283 dev_err(host->dev, "phase error: [map:%x]\n", delay);
1284 delay_phase.final_phase = final_phase;
1285 return delay_phase;
1286 }
1287
1288 while (start < PAD_DELAY_MAX) {
1289 len = get_delay_len(delay, start);
1290 if (len_final < len) {
1291 start_final = start;
1292 len_final = len;
1293 }
1294 start += len ? len : 1;
1295 if (len >= 8 && start_final < 4)
1296 break;
1297 }
1298
1299 /* The rule is that to find the smallest delay cell */
1300 if (start_final == 0)
1301 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
1302 else
1303 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
1304 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
1305 delay, len_final, final_phase);
1306
1307 delay_phase.maxlen = len_final;
1308 delay_phase.start = start_final;
1309 delay_phase.final_phase = final_phase;
1310 return delay_phase;
1311 }
1312
1313 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
1314 {
1315 struct msdc_host *host = mmc_priv(mmc);
1316 u32 rise_delay = 0, fall_delay = 0;
1317 struct msdc_delay_phase final_rise_delay, final_fall_delay;
1318 u8 final_delay, final_maxlen;
1319 int cmd_err;
1320 int i;
1321
1322 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1323 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1324 sdr_set_field(host->base + MSDC_PAD_TUNE,
1325 MSDC_PAD_TUNE_CMDRDLY, i);
1326 mmc_send_tuning(mmc, opcode, &cmd_err);
1327 if (!cmd_err)
1328 rise_delay |= (1 << i);
1329 }
1330
1331 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1332 for (i = 0; i < PAD_DELAY_MAX; i++) {
1333 sdr_set_field(host->base + MSDC_PAD_TUNE,
1334 MSDC_PAD_TUNE_CMDRDLY, i);
1335 mmc_send_tuning(mmc, opcode, &cmd_err);
1336 if (!cmd_err)
1337 fall_delay |= (1 << i);
1338 }
1339
1340 final_rise_delay = get_best_delay(host, rise_delay);
1341 final_fall_delay = get_best_delay(host, fall_delay);
1342
1343 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1344 if (final_maxlen == final_rise_delay.maxlen) {
1345 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1346 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
1347 final_rise_delay.final_phase);
1348 final_delay = final_rise_delay.final_phase;
1349 } else {
1350 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1351 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
1352 final_fall_delay.final_phase);
1353 final_delay = final_fall_delay.final_phase;
1354 }
1355
1356 return final_delay == 0xff ? -EIO : 0;
1357 }
1358
1359 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
1360 {
1361 struct msdc_host *host = mmc_priv(mmc);
1362 u32 rise_delay = 0, fall_delay = 0;
1363 struct msdc_delay_phase final_rise_delay, final_fall_delay;
1364 u8 final_delay, final_maxlen;
1365 int i, ret;
1366
1367 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1368 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1369 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1370 sdr_set_field(host->base + MSDC_PAD_TUNE,
1371 MSDC_PAD_TUNE_DATRRDLY, i);
1372 ret = mmc_send_tuning(mmc, opcode, NULL);
1373 if (!ret)
1374 rise_delay |= (1 << i);
1375 }
1376
1377 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1378 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1379 for (i = 0; i < PAD_DELAY_MAX; i++) {
1380 sdr_set_field(host->base + MSDC_PAD_TUNE,
1381 MSDC_PAD_TUNE_DATRRDLY, i);
1382 ret = mmc_send_tuning(mmc, opcode, NULL);
1383 if (!ret)
1384 fall_delay |= (1 << i);
1385 }
1386
1387 final_rise_delay = get_best_delay(host, rise_delay);
1388 final_fall_delay = get_best_delay(host, fall_delay);
1389
1390 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1391 /* Rising edge is more stable, prefer to use it */
1392 if (final_rise_delay.maxlen >= 10)
1393 final_maxlen = final_rise_delay.maxlen;
1394 if (final_maxlen == final_rise_delay.maxlen) {
1395 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1396 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1397 sdr_set_field(host->base + MSDC_PAD_TUNE,
1398 MSDC_PAD_TUNE_DATRRDLY,
1399 final_rise_delay.final_phase);
1400 final_delay = final_rise_delay.final_phase;
1401 } else {
1402 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1403 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1404 sdr_set_field(host->base + MSDC_PAD_TUNE,
1405 MSDC_PAD_TUNE_DATRRDLY,
1406 final_fall_delay.final_phase);
1407 final_delay = final_fall_delay.final_phase;
1408 }
1409
1410 return final_delay == 0xff ? -EIO : 0;
1411 }
1412
1413 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1414 {
1415 struct msdc_host *host = mmc_priv(mmc);
1416 int ret;
1417
1418 pm_runtime_get_sync(host->dev);
1419 ret = msdc_tune_response(mmc, opcode);
1420 if (ret == -EIO) {
1421 dev_err(host->dev, "Tune response fail!\n");
1422 goto out;
1423 }
1424 ret = msdc_tune_data(mmc, opcode);
1425 if (ret == -EIO)
1426 dev_err(host->dev, "Tune data fail!\n");
1427
1428 out:
1429 pm_runtime_mark_last_busy(host->dev);
1430 pm_runtime_put_autosuspend(host->dev);
1431 return ret;
1432 }
1433
1434 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1435 {
1436 struct msdc_host *host = mmc_priv(mmc);
1437
1438 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
1439 return 0;
1440 }
1441
1442 static void msdc_hw_reset(struct mmc_host *mmc)
1443 {
1444 struct msdc_host *host = mmc_priv(mmc);
1445
1446 sdr_set_bits(host->base + EMMC_IOCON, 1);
1447 udelay(10); /* 10us is enough */
1448 sdr_clr_bits(host->base + EMMC_IOCON, 1);
1449 }
1450
1451 static struct mmc_host_ops mt_msdc_ops = {
1452 .post_req = msdc_post_req,
1453 .pre_req = msdc_pre_req,
1454 .request = msdc_ops_request,
1455 .set_ios = msdc_ops_set_ios,
1456 .get_ro = mmc_gpio_get_ro,
1457 .start_signal_voltage_switch = msdc_ops_switch_volt,
1458 .card_busy = msdc_card_busy,
1459 .execute_tuning = msdc_execute_tuning,
1460 .prepare_hs400_tuning = msdc_prepare_hs400_tuning,
1461 .hw_reset = msdc_hw_reset,
1462 };
1463
1464 static int msdc_drv_probe(struct platform_device *pdev)
1465 {
1466 struct mmc_host *mmc;
1467 struct msdc_host *host;
1468 struct resource *res;
1469 int ret;
1470
1471 if (!pdev->dev.of_node) {
1472 dev_err(&pdev->dev, "No DT found\n");
1473 return -EINVAL;
1474 }
1475 /* Allocate MMC host for this device */
1476 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
1477 if (!mmc)
1478 return -ENOMEM;
1479
1480 host = mmc_priv(mmc);
1481 ret = mmc_of_parse(mmc);
1482 if (ret)
1483 goto host_free;
1484
1485 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1486 host->base = devm_ioremap_resource(&pdev->dev, res);
1487 if (IS_ERR(host->base)) {
1488 ret = PTR_ERR(host->base);
1489 goto host_free;
1490 }
1491
1492 ret = mmc_regulator_get_supply(mmc);
1493 if (ret == -EPROBE_DEFER)
1494 goto host_free;
1495
1496 host->src_clk = devm_clk_get(&pdev->dev, "source");
1497 if (IS_ERR(host->src_clk)) {
1498 ret = PTR_ERR(host->src_clk);
1499 goto host_free;
1500 }
1501
1502 host->h_clk = devm_clk_get(&pdev->dev, "hclk");
1503 if (IS_ERR(host->h_clk)) {
1504 ret = PTR_ERR(host->h_clk);
1505 goto host_free;
1506 }
1507
1508 host->irq = platform_get_irq(pdev, 0);
1509 if (host->irq < 0) {
1510 ret = -EINVAL;
1511 goto host_free;
1512 }
1513
1514 host->pinctrl = devm_pinctrl_get(&pdev->dev);
1515 if (IS_ERR(host->pinctrl)) {
1516 ret = PTR_ERR(host->pinctrl);
1517 dev_err(&pdev->dev, "Cannot find pinctrl!\n");
1518 goto host_free;
1519 }
1520
1521 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
1522 if (IS_ERR(host->pins_default)) {
1523 ret = PTR_ERR(host->pins_default);
1524 dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
1525 goto host_free;
1526 }
1527
1528 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
1529 if (IS_ERR(host->pins_uhs)) {
1530 ret = PTR_ERR(host->pins_uhs);
1531 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
1532 goto host_free;
1533 }
1534
1535 if (!of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
1536 &host->hs400_ds_delay))
1537 dev_dbg(&pdev->dev, "hs400-ds-delay: %x\n",
1538 host->hs400_ds_delay);
1539
1540 host->dev = &pdev->dev;
1541 host->mmc = mmc;
1542 host->src_clk_freq = clk_get_rate(host->src_clk);
1543 /* Set host parameters to mmc */
1544 mmc->ops = &mt_msdc_ops;
1545 mmc->f_min = host->src_clk_freq / (4 * 255);
1546
1547 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
1548 /* MMC core transfer sizes tunable parameters */
1549 mmc->max_segs = MAX_BD_NUM;
1550 mmc->max_seg_size = BDMA_DESC_BUFLEN;
1551 mmc->max_blk_size = 2048;
1552 mmc->max_req_size = 512 * 1024;
1553 mmc->max_blk_count = mmc->max_req_size / 512;
1554 host->dma_mask = DMA_BIT_MASK(32);
1555 mmc_dev(mmc)->dma_mask = &host->dma_mask;
1556
1557 host->timeout_clks = 3 * 1048576;
1558 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
1559 2 * sizeof(struct mt_gpdma_desc),
1560 &host->dma.gpd_addr, GFP_KERNEL);
1561 host->dma.bd = dma_alloc_coherent(&pdev->dev,
1562 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1563 &host->dma.bd_addr, GFP_KERNEL);
1564 if (!host->dma.gpd || !host->dma.bd) {
1565 ret = -ENOMEM;
1566 goto release_mem;
1567 }
1568 msdc_init_gpd_bd(host, &host->dma);
1569 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
1570 spin_lock_init(&host->lock);
1571
1572 platform_set_drvdata(pdev, mmc);
1573 msdc_ungate_clock(host);
1574 msdc_init_hw(host);
1575
1576 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
1577 IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host);
1578 if (ret)
1579 goto release;
1580
1581 pm_runtime_set_active(host->dev);
1582 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
1583 pm_runtime_use_autosuspend(host->dev);
1584 pm_runtime_enable(host->dev);
1585 ret = mmc_add_host(mmc);
1586
1587 if (ret)
1588 goto end;
1589
1590 return 0;
1591 end:
1592 pm_runtime_disable(host->dev);
1593 release:
1594 platform_set_drvdata(pdev, NULL);
1595 msdc_deinit_hw(host);
1596 msdc_gate_clock(host);
1597 release_mem:
1598 if (host->dma.gpd)
1599 dma_free_coherent(&pdev->dev,
1600 2 * sizeof(struct mt_gpdma_desc),
1601 host->dma.gpd, host->dma.gpd_addr);
1602 if (host->dma.bd)
1603 dma_free_coherent(&pdev->dev,
1604 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1605 host->dma.bd, host->dma.bd_addr);
1606 host_free:
1607 mmc_free_host(mmc);
1608
1609 return ret;
1610 }
1611
1612 static int msdc_drv_remove(struct platform_device *pdev)
1613 {
1614 struct mmc_host *mmc;
1615 struct msdc_host *host;
1616
1617 mmc = platform_get_drvdata(pdev);
1618 host = mmc_priv(mmc);
1619
1620 pm_runtime_get_sync(host->dev);
1621
1622 platform_set_drvdata(pdev, NULL);
1623 mmc_remove_host(host->mmc);
1624 msdc_deinit_hw(host);
1625 msdc_gate_clock(host);
1626
1627 pm_runtime_disable(host->dev);
1628 pm_runtime_put_noidle(host->dev);
1629 dma_free_coherent(&pdev->dev,
1630 sizeof(struct mt_gpdma_desc),
1631 host->dma.gpd, host->dma.gpd_addr);
1632 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1633 host->dma.bd, host->dma.bd_addr);
1634
1635 mmc_free_host(host->mmc);
1636
1637 return 0;
1638 }
1639
1640 #ifdef CONFIG_PM
1641 static void msdc_save_reg(struct msdc_host *host)
1642 {
1643 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
1644 host->save_para.iocon = readl(host->base + MSDC_IOCON);
1645 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
1646 host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
1647 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
1648 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
1649 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
1650 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
1651 }
1652
1653 static void msdc_restore_reg(struct msdc_host *host)
1654 {
1655 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
1656 writel(host->save_para.iocon, host->base + MSDC_IOCON);
1657 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
1658 writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE);
1659 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
1660 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
1661 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
1662 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
1663 }
1664
1665 static int msdc_runtime_suspend(struct device *dev)
1666 {
1667 struct mmc_host *mmc = dev_get_drvdata(dev);
1668 struct msdc_host *host = mmc_priv(mmc);
1669
1670 msdc_save_reg(host);
1671 msdc_gate_clock(host);
1672 return 0;
1673 }
1674
1675 static int msdc_runtime_resume(struct device *dev)
1676 {
1677 struct mmc_host *mmc = dev_get_drvdata(dev);
1678 struct msdc_host *host = mmc_priv(mmc);
1679
1680 msdc_ungate_clock(host);
1681 msdc_restore_reg(host);
1682 return 0;
1683 }
1684 #endif
1685
1686 static const struct dev_pm_ops msdc_dev_pm_ops = {
1687 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1688 pm_runtime_force_resume)
1689 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
1690 };
1691
1692 static const struct of_device_id msdc_of_ids[] = {
1693 { .compatible = "mediatek,mt8135-mmc", },
1694 {}
1695 };
1696
1697 static struct platform_driver mt_msdc_driver = {
1698 .probe = msdc_drv_probe,
1699 .remove = msdc_drv_remove,
1700 .driver = {
1701 .name = "mtk-msdc",
1702 .of_match_table = msdc_of_ids,
1703 .pm = &msdc_dev_pm_ops,
1704 },
1705 };
1706
1707 module_platform_driver(mt_msdc_driver);
1708 MODULE_LICENSE("GPL v2");
1709 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");
(deprecated) Btrfs devel tree