2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
8 #include <linux/vmalloc.h>
9 #include <linux/delay.h>
14 #include <linux/delay.h>
16 #define TIMEOUT_100_MS 100
18 static const uint32_t qla8044_reg_tbl
[] = {
19 QLA8044_PEG_HALT_STATUS1
,
20 QLA8044_PEG_HALT_STATUS2
,
21 QLA8044_PEG_ALIVE_COUNTER
,
22 QLA8044_CRB_DRV_ACTIVE
,
23 QLA8044_CRB_DEV_STATE
,
24 QLA8044_CRB_DRV_STATE
,
25 QLA8044_CRB_DRV_SCRATCH
,
26 QLA8044_CRB_DEV_PART_INFO1
,
27 QLA8044_CRB_IDC_VER_MAJOR
,
35 /* 8044 Flash Read/Write functions */
37 qla8044_rd_reg(struct qla_hw_data
*ha
, ulong addr
)
39 return readl((void __iomem
*) (ha
->nx_pcibase
+ addr
));
43 qla8044_wr_reg(struct qla_hw_data
*ha
, ulong addr
, uint32_t val
)
45 writel(val
, (void __iomem
*)((ha
)->nx_pcibase
+ addr
));
49 qla8044_rd_direct(struct scsi_qla_host
*vha
,
50 const uint32_t crb_reg
)
52 struct qla_hw_data
*ha
= vha
->hw
;
54 if (crb_reg
< CRB_REG_INDEX_MAX
)
55 return qla8044_rd_reg(ha
, qla8044_reg_tbl
[crb_reg
]);
57 return QLA_FUNCTION_FAILED
;
61 qla8044_wr_direct(struct scsi_qla_host
*vha
,
62 const uint32_t crb_reg
,
65 struct qla_hw_data
*ha
= vha
->hw
;
67 if (crb_reg
< CRB_REG_INDEX_MAX
)
68 qla8044_wr_reg(ha
, qla8044_reg_tbl
[crb_reg
], value
);
72 qla8044_set_win_base(scsi_qla_host_t
*vha
, uint32_t addr
)
75 int ret_val
= QLA_SUCCESS
;
76 struct qla_hw_data
*ha
= vha
->hw
;
78 qla8044_wr_reg(ha
, QLA8044_CRB_WIN_FUNC(ha
->portnum
), addr
);
79 val
= qla8044_rd_reg(ha
, QLA8044_CRB_WIN_FUNC(ha
->portnum
));
82 ql_log(ql_log_warn
, vha
, 0xb087,
83 "%s: Failed to set register window : "
84 "addr written 0x%x, read 0x%x!\n",
86 ret_val
= QLA_FUNCTION_FAILED
;
92 qla8044_rd_reg_indirect(scsi_qla_host_t
*vha
, uint32_t addr
, uint32_t *data
)
94 int ret_val
= QLA_SUCCESS
;
95 struct qla_hw_data
*ha
= vha
->hw
;
97 ret_val
= qla8044_set_win_base(vha
, addr
);
99 *data
= qla8044_rd_reg(ha
, QLA8044_WILDCARD
);
101 ql_log(ql_log_warn
, vha
, 0xb088,
102 "%s: failed read of addr 0x%x!\n", __func__
, addr
);
107 qla8044_wr_reg_indirect(scsi_qla_host_t
*vha
, uint32_t addr
, uint32_t data
)
109 int ret_val
= QLA_SUCCESS
;
110 struct qla_hw_data
*ha
= vha
->hw
;
112 ret_val
= qla8044_set_win_base(vha
, addr
);
114 qla8044_wr_reg(ha
, QLA8044_WILDCARD
, data
);
116 ql_log(ql_log_warn
, vha
, 0xb089,
117 "%s: failed wrt to addr 0x%x, data 0x%x\n",
118 __func__
, addr
, data
);
123 * qla8044_read_write_crb_reg - Read from raddr and write value to waddr.
125 * @ha : Pointer to adapter structure
126 * @raddr : CRB address to read from
127 * @waddr : CRB address to write to
131 qla8044_read_write_crb_reg(struct scsi_qla_host
*vha
,
132 uint32_t raddr
, uint32_t waddr
)
136 qla8044_rd_reg_indirect(vha
, raddr
, &value
);
137 qla8044_wr_reg_indirect(vha
, waddr
, value
);
141 qla8044_poll_wait_for_ready(struct scsi_qla_host
*vha
, uint32_t addr1
,
144 unsigned long timeout
;
147 /* jiffies after 100ms */
148 timeout
= jiffies
+ msecs_to_jiffies(TIMEOUT_100_MS
);
150 qla8044_rd_reg_indirect(vha
, addr1
, &temp
);
151 if ((temp
& mask
) != 0)
153 if (time_after_eq(jiffies
, timeout
)) {
154 ql_log(ql_log_warn
, vha
, 0xb151,
155 "Error in processing rdmdio entry\n");
164 qla8044_ipmdio_rd_reg(struct scsi_qla_host
*vha
,
165 uint32_t addr1
, uint32_t addr3
, uint32_t mask
, uint32_t addr
)
170 ret
= qla8044_poll_wait_for_ready(vha
, addr1
, mask
);
174 temp
= (0x40000000 | addr
);
175 qla8044_wr_reg_indirect(vha
, addr1
, temp
);
177 ret
= qla8044_poll_wait_for_ready(vha
, addr1
, mask
);
181 qla8044_rd_reg_indirect(vha
, addr3
, &ret
);
188 qla8044_poll_wait_ipmdio_bus_idle(struct scsi_qla_host
*vha
,
189 uint32_t addr1
, uint32_t addr2
, uint32_t addr3
, uint32_t mask
)
191 unsigned long timeout
;
194 /* jiffies after 100 msecs */
195 timeout
= jiffies
+ msecs_to_jiffies(TIMEOUT_100_MS
);
197 temp
= qla8044_ipmdio_rd_reg(vha
, addr1
, addr3
, mask
, addr2
);
198 if ((temp
& 0x1) != 1)
200 if (time_after_eq(jiffies
, timeout
)) {
201 ql_log(ql_log_warn
, vha
, 0xb152,
202 "Error in processing mdiobus idle\n");
211 qla8044_ipmdio_wr_reg(struct scsi_qla_host
*vha
, uint32_t addr1
,
212 uint32_t addr3
, uint32_t mask
, uint32_t addr
, uint32_t value
)
216 ret
= qla8044_poll_wait_for_ready(vha
, addr1
, mask
);
220 qla8044_wr_reg_indirect(vha
, addr3
, value
);
221 qla8044_wr_reg_indirect(vha
, addr1
, addr
);
223 ret
= qla8044_poll_wait_for_ready(vha
, addr1
, mask
);
230 * qla8044_rmw_crb_reg - Read value from raddr, AND with test_mask,
231 * Shift Left,Right/OR/XOR with values RMW header and write value to waddr.
233 * @vha : Pointer to adapter structure
234 * @raddr : CRB address to read from
235 * @waddr : CRB address to write to
236 * @p_rmw_hdr : header with shift/or/xor values.
240 qla8044_rmw_crb_reg(struct scsi_qla_host
*vha
,
241 uint32_t raddr
, uint32_t waddr
, struct qla8044_rmw
*p_rmw_hdr
)
245 if (p_rmw_hdr
->index_a
)
246 value
= vha
->reset_tmplt
.array
[p_rmw_hdr
->index_a
];
248 qla8044_rd_reg_indirect(vha
, raddr
, &value
);
249 value
&= p_rmw_hdr
->test_mask
;
250 value
<<= p_rmw_hdr
->shl
;
251 value
>>= p_rmw_hdr
->shr
;
252 value
|= p_rmw_hdr
->or_value
;
253 value
^= p_rmw_hdr
->xor_value
;
254 qla8044_wr_reg_indirect(vha
, waddr
, value
);
259 qla8044_set_qsnt_ready(struct scsi_qla_host
*vha
)
262 struct qla_hw_data
*ha
= vha
->hw
;
264 qsnt_state
= qla8044_rd_direct(vha
, QLA8044_CRB_DRV_STATE_INDEX
);
265 qsnt_state
|= (1 << ha
->portnum
);
266 qla8044_wr_direct(vha
, QLA8044_CRB_DRV_STATE_INDEX
, qsnt_state
);
267 ql_log(ql_log_info
, vha
, 0xb08e, "%s(%ld): qsnt_state: 0x%08x\n",
268 __func__
, vha
->host_no
, qsnt_state
);
272 qla8044_clear_qsnt_ready(struct scsi_qla_host
*vha
)
275 struct qla_hw_data
*ha
= vha
->hw
;
277 qsnt_state
= qla8044_rd_direct(vha
, QLA8044_CRB_DRV_STATE_INDEX
);
278 qsnt_state
&= ~(1 << ha
->portnum
);
279 qla8044_wr_direct(vha
, QLA8044_CRB_DRV_STATE_INDEX
, qsnt_state
);
280 ql_log(ql_log_info
, vha
, 0xb08f, "%s(%ld): qsnt_state: 0x%08x\n",
281 __func__
, vha
->host_no
, qsnt_state
);
286 * qla8044_lock_recovery - Recovers the idc_lock.
287 * @ha : Pointer to adapter structure
289 * Lock Recovery Register
290 * 5-2 Lock recovery owner: Function ID of driver doing lock recovery,
291 * valid if bits 1..0 are set by driver doing lock recovery.
292 * 1-0 1 - Driver intends to force unlock the IDC lock.
293 * 2 - Driver is moving forward to unlock the IDC lock. Driver clears
294 * this field after force unlocking the IDC lock.
296 * Lock Recovery process
297 * a. Read the IDC_LOCK_RECOVERY register. If the value in bits 1..0 is
298 * greater than 0, then wait for the other driver to unlock otherwise
299 * move to the next step.
300 * b. Indicate intent to force-unlock by writing 1h to the IDC_LOCK_RECOVERY
301 * register bits 1..0 and also set the function# in bits 5..2.
302 * c. Read the IDC_LOCK_RECOVERY register again after a delay of 200ms.
303 * Wait for the other driver to perform lock recovery if the function
304 * number in bits 5..2 has changed, otherwise move to the next step.
305 * d. Write a value of 2h to the IDC_LOCK_RECOVERY register bits 1..0
306 * leaving your function# in bits 5..2.
307 * e. Force unlock using the DRIVER_UNLOCK register and immediately clear
308 * the IDC_LOCK_RECOVERY bits 5..0 by writing 0.
311 qla8044_lock_recovery(struct scsi_qla_host
*vha
)
313 uint32_t lock
= 0, lockid
;
314 struct qla_hw_data
*ha
= vha
->hw
;
316 lockid
= qla8044_rd_reg(ha
, QLA8044_DRV_LOCKRECOVERY
);
318 /* Check for other Recovery in progress, go wait */
319 if ((lockid
& IDC_LOCK_RECOVERY_STATE_MASK
) != 0)
320 return QLA_FUNCTION_FAILED
;
322 /* Intent to Recover */
323 qla8044_wr_reg(ha
, QLA8044_DRV_LOCKRECOVERY
,
325 IDC_LOCK_RECOVERY_STATE_SHIFT_BITS
) | INTENT_TO_RECOVER
);
328 /* Check Intent to Recover is advertised */
329 lockid
= qla8044_rd_reg(ha
, QLA8044_DRV_LOCKRECOVERY
);
330 if ((lockid
& IDC_LOCK_RECOVERY_OWNER_MASK
) != (ha
->portnum
<<
331 IDC_LOCK_RECOVERY_STATE_SHIFT_BITS
))
332 return QLA_FUNCTION_FAILED
;
334 ql_dbg(ql_dbg_p3p
, vha
, 0xb08B, "%s:%d: IDC Lock recovery initiated\n"
335 , __func__
, ha
->portnum
);
337 /* Proceed to Recover */
338 qla8044_wr_reg(ha
, QLA8044_DRV_LOCKRECOVERY
,
339 (ha
->portnum
<< IDC_LOCK_RECOVERY_STATE_SHIFT_BITS
) |
343 qla8044_wr_reg(ha
, QLA8044_DRV_LOCK_ID
, 0xFF);
344 qla8044_rd_reg(ha
, QLA8044_DRV_UNLOCK
);
346 /* Clear bits 0-5 in IDC_RECOVERY register*/
347 qla8044_wr_reg(ha
, QLA8044_DRV_LOCKRECOVERY
, 0);
350 lock
= qla8044_rd_reg(ha
, QLA8044_DRV_LOCK
);
352 lockid
= qla8044_rd_reg(ha
, QLA8044_DRV_LOCK_ID
);
353 lockid
= ((lockid
+ (1 << 8)) & ~0xFF) | ha
->portnum
;
354 qla8044_wr_reg(ha
, QLA8044_DRV_LOCK_ID
, lockid
);
357 return QLA_FUNCTION_FAILED
;
361 qla8044_idc_lock(struct qla_hw_data
*ha
)
363 uint32_t ret_val
= QLA_SUCCESS
, timeout
= 0, status
= 0;
364 uint32_t lock_id
, lock_cnt
, func_num
, tmo_owner
= 0, first_owner
= 0;
365 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
367 while (status
== 0) {
368 /* acquire semaphore5 from PCI HW block */
369 status
= qla8044_rd_reg(ha
, QLA8044_DRV_LOCK
);
372 /* Increment Counter (8-31) and update func_num (0-7) on
373 * getting a successful lock */
374 lock_id
= qla8044_rd_reg(ha
, QLA8044_DRV_LOCK_ID
);
375 lock_id
= ((lock_id
+ (1 << 8)) & ~0xFF) | ha
->portnum
;
376 qla8044_wr_reg(ha
, QLA8044_DRV_LOCK_ID
, lock_id
);
381 first_owner
= qla8044_rd_reg(ha
, QLA8044_DRV_LOCK_ID
);
384 (QLA8044_DRV_LOCK_TIMEOUT
/ QLA8044_DRV_LOCK_MSLEEP
)) {
385 tmo_owner
= qla8044_rd_reg(ha
, QLA8044_DRV_LOCK_ID
);
386 func_num
= tmo_owner
& 0xFF;
387 lock_cnt
= tmo_owner
>> 8;
388 ql_log(ql_log_warn
, vha
, 0xb114,
389 "%s: Lock by func %d failed after 2s, lock held "
390 "by func %d, lock count %d, first_owner %d\n",
391 __func__
, ha
->portnum
, func_num
, lock_cnt
,
392 (first_owner
& 0xFF));
393 if (first_owner
!= tmo_owner
) {
394 /* Some other driver got lock,
395 * OR same driver got lock again (counter
396 * value changed), when we were waiting for
397 * lock. Retry for another 2 sec */
398 ql_dbg(ql_dbg_p3p
, vha
, 0xb115,
399 "%s: %d: IDC lock failed\n",
400 __func__
, ha
->portnum
);
403 /* Same driver holding lock > 2sec.
405 if (qla8044_lock_recovery(vha
) == QLA_SUCCESS
) {
406 /* Recovered and got lock */
407 ret_val
= QLA_SUCCESS
;
408 ql_dbg(ql_dbg_p3p
, vha
, 0xb116,
409 "%s:IDC lock Recovery by %d"
410 "successful...\n", __func__
,
413 /* Recovery Failed, some other function
414 * has the lock, wait for 2secs
417 ql_dbg(ql_dbg_p3p
, vha
, 0xb08a,
418 "%s: IDC lock Recovery by %d "
419 "failed, Retrying timeout\n", __func__
,
424 msleep(QLA8044_DRV_LOCK_MSLEEP
);
430 qla8044_idc_unlock(struct qla_hw_data
*ha
)
433 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
435 id
= qla8044_rd_reg(ha
, QLA8044_DRV_LOCK_ID
);
437 if ((id
& 0xFF) != ha
->portnum
) {
438 ql_log(ql_log_warn
, vha
, 0xb118,
439 "%s: IDC Unlock by %d failed, lock owner is %d!\n",
440 __func__
, ha
->portnum
, (id
& 0xFF));
444 /* Keep lock counter value, update the ha->func_num to 0xFF */
445 qla8044_wr_reg(ha
, QLA8044_DRV_LOCK_ID
, (id
| 0xFF));
446 qla8044_rd_reg(ha
, QLA8044_DRV_UNLOCK
);
449 /* 8044 Flash Lock/Unlock functions */
451 qla8044_flash_lock(scsi_qla_host_t
*vha
)
455 uint32_t lock_status
= 0;
456 int ret_val
= QLA_SUCCESS
;
457 struct qla_hw_data
*ha
= vha
->hw
;
459 while (lock_status
== 0) {
460 lock_status
= qla8044_rd_reg(ha
, QLA8044_FLASH_LOCK
);
464 if (++timeout
>= QLA8044_FLASH_LOCK_TIMEOUT
/ 20) {
465 lock_owner
= qla8044_rd_reg(ha
,
466 QLA8044_FLASH_LOCK_ID
);
467 ql_log(ql_log_warn
, vha
, 0xb113,
468 "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d",
469 __func__
, ha
->portnum
, lock_owner
);
470 ret_val
= QLA_FUNCTION_FAILED
;
475 qla8044_wr_reg(ha
, QLA8044_FLASH_LOCK_ID
, ha
->portnum
);
480 qla8044_flash_unlock(scsi_qla_host_t
*vha
)
482 struct qla_hw_data
*ha
= vha
->hw
;
484 /* Reading FLASH_UNLOCK register unlocks the Flash */
485 qla8044_wr_reg(ha
, QLA8044_FLASH_LOCK_ID
, 0xFF);
486 qla8044_rd_reg(ha
, QLA8044_FLASH_UNLOCK
);
491 void qla8044_flash_lock_recovery(struct scsi_qla_host
*vha
)
494 if (qla8044_flash_lock(vha
)) {
495 /* Someone else is holding the lock. */
496 ql_log(ql_log_warn
, vha
, 0xb120, "Resetting flash_lock\n");
500 * Either we got the lock, or someone
501 * else died while holding it.
502 * In either case, unlock.
504 qla8044_flash_unlock(vha
);
508 * Address and length are byte address
511 qla8044_read_flash_data(scsi_qla_host_t
*vha
, uint8_t *p_data
,
512 uint32_t flash_addr
, int u32_word_count
)
514 int i
, ret_val
= QLA_SUCCESS
;
517 if (qla8044_flash_lock(vha
) != QLA_SUCCESS
) {
518 ret_val
= QLA_FUNCTION_FAILED
;
519 goto exit_lock_error
;
522 if (flash_addr
& 0x03) {
523 ql_log(ql_log_warn
, vha
, 0xb117,
524 "%s: Illegal addr = 0x%x\n", __func__
, flash_addr
);
525 ret_val
= QLA_FUNCTION_FAILED
;
526 goto exit_flash_read
;
529 for (i
= 0; i
< u32_word_count
; i
++) {
530 if (qla8044_wr_reg_indirect(vha
, QLA8044_FLASH_DIRECT_WINDOW
,
531 (flash_addr
& 0xFFFF0000))) {
532 ql_log(ql_log_warn
, vha
, 0xb119,
533 "%s: failed to write addr 0x%x to "
534 "FLASH_DIRECT_WINDOW\n! ",
535 __func__
, flash_addr
);
536 ret_val
= QLA_FUNCTION_FAILED
;
537 goto exit_flash_read
;
540 ret_val
= qla8044_rd_reg_indirect(vha
,
541 QLA8044_FLASH_DIRECT_DATA(flash_addr
),
543 if (ret_val
!= QLA_SUCCESS
) {
544 ql_log(ql_log_warn
, vha
, 0xb08c,
545 "%s: failed to read addr 0x%x!\n",
546 __func__
, flash_addr
);
547 goto exit_flash_read
;
550 *(uint32_t *)p_data
= u32_word
;
552 flash_addr
= flash_addr
+ 4;
556 qla8044_flash_unlock(vha
);
563 * Address and length are byte address
566 qla8044_read_optrom_data(struct scsi_qla_host
*vha
, uint8_t *buf
,
567 uint32_t offset
, uint32_t length
)
569 scsi_block_requests(vha
->host
);
570 if (qla8044_read_flash_data(vha
, (uint8_t *)buf
, offset
, length
/ 4)
572 ql_log(ql_log_warn
, vha
, 0xb08d,
573 "%s: Failed to read from flash\n",
576 scsi_unblock_requests(vha
->host
);
581 qla8044_need_reset(struct scsi_qla_host
*vha
)
583 uint32_t drv_state
, drv_active
;
585 struct qla_hw_data
*ha
= vha
->hw
;
587 drv_active
= qla8044_rd_direct(vha
, QLA8044_CRB_DRV_ACTIVE_INDEX
);
588 drv_state
= qla8044_rd_direct(vha
, QLA8044_CRB_DRV_STATE_INDEX
);
590 rval
= drv_state
& (1 << ha
->portnum
);
592 if (ha
->flags
.eeh_busy
&& drv_active
)
598 * qla8044_write_list - Write the value (p_entry->arg2) to address specified
599 * by p_entry->arg1 for all entries in header with delay of p_hdr->delay between
602 * @vha : Pointer to adapter structure
603 * @p_hdr : reset_entry header for WRITE_LIST opcode.
607 qla8044_write_list(struct scsi_qla_host
*vha
,
608 struct qla8044_reset_entry_hdr
*p_hdr
)
610 struct qla8044_entry
*p_entry
;
613 p_entry
= (struct qla8044_entry
*)((char *)p_hdr
+
614 sizeof(struct qla8044_reset_entry_hdr
));
616 for (i
= 0; i
< p_hdr
->count
; i
++, p_entry
++) {
617 qla8044_wr_reg_indirect(vha
, p_entry
->arg1
, p_entry
->arg2
);
619 udelay((uint32_t)(p_hdr
->delay
));
624 * qla8044_read_write_list - Read from address specified by p_entry->arg1,
625 * write value read to address specified by p_entry->arg2, for all entries in
626 * header with delay of p_hdr->delay between entries.
628 * @vha : Pointer to adapter structure
629 * @p_hdr : reset_entry header for READ_WRITE_LIST opcode.
633 qla8044_read_write_list(struct scsi_qla_host
*vha
,
634 struct qla8044_reset_entry_hdr
*p_hdr
)
636 struct qla8044_entry
*p_entry
;
639 p_entry
= (struct qla8044_entry
*)((char *)p_hdr
+
640 sizeof(struct qla8044_reset_entry_hdr
));
642 for (i
= 0; i
< p_hdr
->count
; i
++, p_entry
++) {
643 qla8044_read_write_crb_reg(vha
, p_entry
->arg1
,
646 udelay((uint32_t)(p_hdr
->delay
));
651 * qla8044_poll_reg - Poll the given CRB addr for duration msecs till
652 * value read ANDed with test_mask is equal to test_result.
654 * @ha : Pointer to adapter structure
655 * @addr : CRB register address
656 * @duration : Poll for total of "duration" msecs
657 * @test_mask : Mask value read with "test_mask"
658 * @test_result : Compare (value&test_mask) with test_result.
660 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
663 qla8044_poll_reg(struct scsi_qla_host
*vha
, uint32_t addr
,
664 int duration
, uint32_t test_mask
, uint32_t test_result
)
669 int ret_val
= QLA_SUCCESS
;
671 ret_val
= qla8044_rd_reg_indirect(vha
, addr
, &value
);
672 if (ret_val
== QLA_FUNCTION_FAILED
) {
677 /* poll every 1/10 of the total duration */
678 retries
= duration
/10;
681 if ((value
& test_mask
) != test_result
) {
684 ret_val
= qla8044_rd_reg_indirect(vha
, addr
, &value
);
685 if (ret_val
== QLA_FUNCTION_FAILED
) {
697 vha
->reset_tmplt
.seq_error
++;
698 ql_log(ql_log_fatal
, vha
, 0xb090,
699 "%s: Poll Failed: 0x%08x 0x%08x 0x%08x\n",
700 __func__
, value
, test_mask
, test_result
);
703 return timeout_error
;
707 * qla8044_poll_list - For all entries in the POLL_LIST header, poll read CRB
708 * register specified by p_entry->arg1 and compare (value AND test_mask) with
709 * test_result to validate it. Wait for p_hdr->delay between processing entries.
711 * @ha : Pointer to adapter structure
712 * @p_hdr : reset_entry header for POLL_LIST opcode.
716 qla8044_poll_list(struct scsi_qla_host
*vha
,
717 struct qla8044_reset_entry_hdr
*p_hdr
)
720 struct qla8044_entry
*p_entry
;
721 struct qla8044_poll
*p_poll
;
725 p_poll
= (struct qla8044_poll
*)
726 ((char *)p_hdr
+ sizeof(struct qla8044_reset_entry_hdr
));
728 /* Entries start after 8 byte qla8044_poll, poll header contains
729 * the test_mask, test_value.
731 p_entry
= (struct qla8044_entry
*)((char *)p_poll
+
732 sizeof(struct qla8044_poll
));
734 delay
= (long)p_hdr
->delay
;
737 for (i
= 0; i
< p_hdr
->count
; i
++, p_entry
++)
738 qla8044_poll_reg(vha
, p_entry
->arg1
,
739 delay
, p_poll
->test_mask
, p_poll
->test_value
);
741 for (i
= 0; i
< p_hdr
->count
; i
++, p_entry
++) {
743 if (qla8044_poll_reg(vha
,
744 p_entry
->arg1
, delay
,
746 p_poll
->test_value
)) {
748 * (data_read&test_mask != test_value)
749 * read TIMEOUT_ADDR (arg1) and
750 * ADDR (arg2) registers
752 qla8044_rd_reg_indirect(vha
,
753 p_entry
->arg1
, &value
);
754 qla8044_rd_reg_indirect(vha
,
755 p_entry
->arg2
, &value
);
763 * qla8044_poll_write_list - Write dr_value, ar_value to dr_addr/ar_addr,
764 * read ar_addr, if (value& test_mask != test_mask) re-read till timeout
767 * @vha : Pointer to adapter structure
768 * @p_hdr : reset entry header for POLL_WRITE_LIST opcode.
772 qla8044_poll_write_list(struct scsi_qla_host
*vha
,
773 struct qla8044_reset_entry_hdr
*p_hdr
)
776 struct qla8044_quad_entry
*p_entry
;
777 struct qla8044_poll
*p_poll
;
780 p_poll
= (struct qla8044_poll
*)((char *)p_hdr
+
781 sizeof(struct qla8044_reset_entry_hdr
));
783 p_entry
= (struct qla8044_quad_entry
*)((char *)p_poll
+
784 sizeof(struct qla8044_poll
));
786 delay
= (long)p_hdr
->delay
;
788 for (i
= 0; i
< p_hdr
->count
; i
++, p_entry
++) {
789 qla8044_wr_reg_indirect(vha
,
790 p_entry
->dr_addr
, p_entry
->dr_value
);
791 qla8044_wr_reg_indirect(vha
,
792 p_entry
->ar_addr
, p_entry
->ar_value
);
794 if (qla8044_poll_reg(vha
,
795 p_entry
->ar_addr
, delay
,
797 p_poll
->test_value
)) {
798 ql_dbg(ql_dbg_p3p
, vha
, 0xb091,
799 "%s: Timeout Error: poll list, ",
801 ql_dbg(ql_dbg_p3p
, vha
, 0xb092,
802 "item_num %d, entry_num %d\n", i
,
803 vha
->reset_tmplt
.seq_index
);
810 * qla8044_read_modify_write - Read value from p_entry->arg1, modify the
811 * value, write value to p_entry->arg2. Process entries with p_hdr->delay
814 * @vha : Pointer to adapter structure
815 * @p_hdr : header with shift/or/xor values.
819 qla8044_read_modify_write(struct scsi_qla_host
*vha
,
820 struct qla8044_reset_entry_hdr
*p_hdr
)
822 struct qla8044_entry
*p_entry
;
823 struct qla8044_rmw
*p_rmw_hdr
;
826 p_rmw_hdr
= (struct qla8044_rmw
*)((char *)p_hdr
+
827 sizeof(struct qla8044_reset_entry_hdr
));
829 p_entry
= (struct qla8044_entry
*)((char *)p_rmw_hdr
+
830 sizeof(struct qla8044_rmw
));
832 for (i
= 0; i
< p_hdr
->count
; i
++, p_entry
++) {
833 qla8044_rmw_crb_reg(vha
, p_entry
->arg1
,
834 p_entry
->arg2
, p_rmw_hdr
);
836 udelay((uint32_t)(p_hdr
->delay
));
841 * qla8044_pause - Wait for p_hdr->delay msecs, called between processing
842 * two entries of a sequence.
844 * @vha : Pointer to adapter structure
845 * @p_hdr : Common reset entry header.
849 void qla8044_pause(struct scsi_qla_host
*vha
,
850 struct qla8044_reset_entry_hdr
*p_hdr
)
853 mdelay((uint32_t)((long)p_hdr
->delay
));
857 * qla8044_template_end - Indicates end of reset sequence processing.
859 * @vha : Pointer to adapter structure
860 * @p_hdr : Common reset entry header.
864 qla8044_template_end(struct scsi_qla_host
*vha
,
865 struct qla8044_reset_entry_hdr
*p_hdr
)
867 vha
->reset_tmplt
.template_end
= 1;
869 if (vha
->reset_tmplt
.seq_error
== 0) {
870 ql_dbg(ql_dbg_p3p
, vha
, 0xb093,
871 "%s: Reset sequence completed SUCCESSFULLY.\n", __func__
);
873 ql_log(ql_log_fatal
, vha
, 0xb094,
874 "%s: Reset sequence completed with some timeout "
875 "errors.\n", __func__
);
880 * qla8044_poll_read_list - Write ar_value to ar_addr register, read ar_addr,
881 * if (value & test_mask != test_value) re-read till timeout value expires,
882 * read dr_addr register and assign to reset_tmplt.array.
884 * @vha : Pointer to adapter structure
885 * @p_hdr : Common reset entry header.
889 qla8044_poll_read_list(struct scsi_qla_host
*vha
,
890 struct qla8044_reset_entry_hdr
*p_hdr
)
894 struct qla8044_quad_entry
*p_entry
;
895 struct qla8044_poll
*p_poll
;
899 p_poll
= (struct qla8044_poll
*)
900 ((char *)p_hdr
+ sizeof(struct qla8044_reset_entry_hdr
));
902 p_entry
= (struct qla8044_quad_entry
*)
903 ((char *)p_poll
+ sizeof(struct qla8044_poll
));
905 delay
= (long)p_hdr
->delay
;
907 for (i
= 0; i
< p_hdr
->count
; i
++, p_entry
++) {
908 qla8044_wr_reg_indirect(vha
, p_entry
->ar_addr
,
911 if (qla8044_poll_reg(vha
, p_entry
->ar_addr
, delay
,
912 p_poll
->test_mask
, p_poll
->test_value
)) {
913 ql_dbg(ql_dbg_p3p
, vha
, 0xb095,
914 "%s: Timeout Error: poll "
916 ql_dbg(ql_dbg_p3p
, vha
, 0xb096,
919 vha
->reset_tmplt
.seq_index
);
921 index
= vha
->reset_tmplt
.array_index
;
922 qla8044_rd_reg_indirect(vha
,
923 p_entry
->dr_addr
, &value
);
924 vha
->reset_tmplt
.array
[index
++] = value
;
925 if (index
== QLA8044_MAX_RESET_SEQ_ENTRIES
)
926 vha
->reset_tmplt
.array_index
= 1;
933 * qla8031_process_reset_template - Process all entries in reset template
934 * till entry with SEQ_END opcode, which indicates end of the reset template
935 * processing. Each entry has a Reset Entry header, entry opcode/command, with
936 * size of the entry, number of entries in sub-sequence and delay in microsecs
937 * or timeout in millisecs.
939 * @ha : Pointer to adapter structure
940 * @p_buff : Common reset entry header.
944 qla8044_process_reset_template(struct scsi_qla_host
*vha
,
948 struct qla8044_reset_entry_hdr
*p_hdr
;
949 char *p_entry
= p_buff
;
951 vha
->reset_tmplt
.seq_end
= 0;
952 vha
->reset_tmplt
.template_end
= 0;
953 entries
= vha
->reset_tmplt
.hdr
->entries
;
954 index
= vha
->reset_tmplt
.seq_index
;
956 for (; (!vha
->reset_tmplt
.seq_end
) && (index
< entries
); index
++) {
957 p_hdr
= (struct qla8044_reset_entry_hdr
*)p_entry
;
958 switch (p_hdr
->cmd
) {
961 case OPCODE_WRITE_LIST
:
962 qla8044_write_list(vha
, p_hdr
);
964 case OPCODE_READ_WRITE_LIST
:
965 qla8044_read_write_list(vha
, p_hdr
);
967 case OPCODE_POLL_LIST
:
968 qla8044_poll_list(vha
, p_hdr
);
970 case OPCODE_POLL_WRITE_LIST
:
971 qla8044_poll_write_list(vha
, p_hdr
);
973 case OPCODE_READ_MODIFY_WRITE
:
974 qla8044_read_modify_write(vha
, p_hdr
);
976 case OPCODE_SEQ_PAUSE
:
977 qla8044_pause(vha
, p_hdr
);
980 vha
->reset_tmplt
.seq_end
= 1;
982 case OPCODE_TMPL_END
:
983 qla8044_template_end(vha
, p_hdr
);
985 case OPCODE_POLL_READ_LIST
:
986 qla8044_poll_read_list(vha
, p_hdr
);
989 ql_log(ql_log_fatal
, vha
, 0xb097,
990 "%s: Unknown command ==> 0x%04x on "
991 "entry = %d\n", __func__
, p_hdr
->cmd
, index
);
995 *Set pointer to next entry in the sequence.
997 p_entry
+= p_hdr
->size
;
999 vha
->reset_tmplt
.seq_index
= index
;
1003 qla8044_process_init_seq(struct scsi_qla_host
*vha
)
1005 qla8044_process_reset_template(vha
,
1006 vha
->reset_tmplt
.init_offset
);
1007 if (vha
->reset_tmplt
.seq_end
!= 1)
1008 ql_log(ql_log_fatal
, vha
, 0xb098,
1009 "%s: Abrupt INIT Sub-Sequence end.\n",
1014 qla8044_process_stop_seq(struct scsi_qla_host
*vha
)
1016 vha
->reset_tmplt
.seq_index
= 0;
1017 qla8044_process_reset_template(vha
, vha
->reset_tmplt
.stop_offset
);
1018 if (vha
->reset_tmplt
.seq_end
!= 1)
1019 ql_log(ql_log_fatal
, vha
, 0xb099,
1020 "%s: Abrupt STOP Sub-Sequence end.\n", __func__
);
1024 qla8044_process_start_seq(struct scsi_qla_host
*vha
)
1026 qla8044_process_reset_template(vha
, vha
->reset_tmplt
.start_offset
);
1027 if (vha
->reset_tmplt
.template_end
!= 1)
1028 ql_log(ql_log_fatal
, vha
, 0xb09a,
1029 "%s: Abrupt START Sub-Sequence end.\n",
1034 qla8044_lockless_flash_read_u32(struct scsi_qla_host
*vha
,
1035 uint32_t flash_addr
, uint8_t *p_data
, int u32_word_count
)
1039 uint32_t flash_offset
;
1040 uint32_t addr
= flash_addr
;
1041 int ret_val
= QLA_SUCCESS
;
1043 flash_offset
= addr
& (QLA8044_FLASH_SECTOR_SIZE
- 1);
1046 ql_log(ql_log_fatal
, vha
, 0xb09b, "%s: Illegal addr = 0x%x\n",
1048 ret_val
= QLA_FUNCTION_FAILED
;
1049 goto exit_lockless_read
;
1052 ret_val
= qla8044_wr_reg_indirect(vha
,
1053 QLA8044_FLASH_DIRECT_WINDOW
, (addr
));
1055 if (ret_val
!= QLA_SUCCESS
) {
1056 ql_log(ql_log_fatal
, vha
, 0xb09c,
1057 "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW!\n",
1059 goto exit_lockless_read
;
1062 /* Check if data is spread across multiple sectors */
1063 if ((flash_offset
+ (u32_word_count
* sizeof(uint32_t))) >
1064 (QLA8044_FLASH_SECTOR_SIZE
- 1)) {
1065 /* Multi sector read */
1066 for (i
= 0; i
< u32_word_count
; i
++) {
1067 ret_val
= qla8044_rd_reg_indirect(vha
,
1068 QLA8044_FLASH_DIRECT_DATA(addr
), &u32_word
);
1069 if (ret_val
!= QLA_SUCCESS
) {
1070 ql_log(ql_log_fatal
, vha
, 0xb09d,
1071 "%s: failed to read addr 0x%x!\n",
1073 goto exit_lockless_read
;
1075 *(uint32_t *)p_data
= u32_word
;
1076 p_data
= p_data
+ 4;
1078 flash_offset
= flash_offset
+ 4;
1079 if (flash_offset
> (QLA8044_FLASH_SECTOR_SIZE
- 1)) {
1080 /* This write is needed once for each sector */
1081 ret_val
= qla8044_wr_reg_indirect(vha
,
1082 QLA8044_FLASH_DIRECT_WINDOW
, (addr
));
1083 if (ret_val
!= QLA_SUCCESS
) {
1084 ql_log(ql_log_fatal
, vha
, 0xb09f,
1085 "%s: failed to write addr "
1086 "0x%x to FLASH_DIRECT_WINDOW!\n",
1088 goto exit_lockless_read
;
1094 /* Single sector read */
1095 for (i
= 0; i
< u32_word_count
; i
++) {
1096 ret_val
= qla8044_rd_reg_indirect(vha
,
1097 QLA8044_FLASH_DIRECT_DATA(addr
), &u32_word
);
1098 if (ret_val
!= QLA_SUCCESS
) {
1099 ql_log(ql_log_fatal
, vha
, 0xb0a0,
1100 "%s: failed to read addr 0x%x!\n",
1102 goto exit_lockless_read
;
1104 *(uint32_t *)p_data
= u32_word
;
1105 p_data
= p_data
+ 4;
1115 * qla8044_ms_mem_write_128b - Writes data to MS/off-chip memory
1117 * @vha : Pointer to adapter structure
1118 * addr : Flash address to write to
1119 * data : Data to be written
1120 * count : word_count to be written
1122 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1125 qla8044_ms_mem_write_128b(struct scsi_qla_host
*vha
,
1126 uint64_t addr
, uint32_t *data
, uint32_t count
)
1128 int i
, j
, ret_val
= QLA_SUCCESS
;
1130 unsigned long flags
;
1131 struct qla_hw_data
*ha
= vha
->hw
;
1133 /* Only 128-bit aligned access */
1135 ret_val
= QLA_FUNCTION_FAILED
;
1136 goto exit_ms_mem_write
;
1138 write_lock_irqsave(&ha
->hw_lock
, flags
);
1141 ret_val
= qla8044_wr_reg_indirect(vha
, MD_MIU_TEST_AGT_ADDR_HI
, 0);
1142 if (ret_val
== QLA_FUNCTION_FAILED
) {
1143 ql_log(ql_log_fatal
, vha
, 0xb0a1,
1144 "%s: write to AGT_ADDR_HI failed!\n", __func__
);
1145 goto exit_ms_mem_write_unlock
;
1148 for (i
= 0; i
< count
; i
++, addr
+= 16) {
1149 if (!((addr_in_range(addr
, QLA8044_ADDR_QDR_NET
,
1150 QLA8044_ADDR_QDR_NET_MAX
)) ||
1151 (addr_in_range(addr
, QLA8044_ADDR_DDR_NET
,
1152 QLA8044_ADDR_DDR_NET_MAX
)))) {
1153 ret_val
= QLA_FUNCTION_FAILED
;
1154 goto exit_ms_mem_write_unlock
;
1157 ret_val
= qla8044_wr_reg_indirect(vha
,
1158 MD_MIU_TEST_AGT_ADDR_LO
, addr
);
1161 ret_val
+= qla8044_wr_reg_indirect(vha
,
1162 MD_MIU_TEST_AGT_WRDATA_LO
, *data
++);
1163 ret_val
+= qla8044_wr_reg_indirect(vha
,
1164 MD_MIU_TEST_AGT_WRDATA_HI
, *data
++);
1165 ret_val
+= qla8044_wr_reg_indirect(vha
,
1166 MD_MIU_TEST_AGT_WRDATA_ULO
, *data
++);
1167 ret_val
+= qla8044_wr_reg_indirect(vha
,
1168 MD_MIU_TEST_AGT_WRDATA_UHI
, *data
++);
1169 if (ret_val
== QLA_FUNCTION_FAILED
) {
1170 ql_log(ql_log_fatal
, vha
, 0xb0a2,
1171 "%s: write to AGT_WRDATA failed!\n",
1173 goto exit_ms_mem_write_unlock
;
1176 /* Check write status */
1177 ret_val
= qla8044_wr_reg_indirect(vha
, MD_MIU_TEST_AGT_CTRL
,
1178 MIU_TA_CTL_WRITE_ENABLE
);
1179 ret_val
+= qla8044_wr_reg_indirect(vha
, MD_MIU_TEST_AGT_CTRL
,
1180 MIU_TA_CTL_WRITE_START
);
1181 if (ret_val
== QLA_FUNCTION_FAILED
) {
1182 ql_log(ql_log_fatal
, vha
, 0xb0a3,
1183 "%s: write to AGT_CTRL failed!\n", __func__
);
1184 goto exit_ms_mem_write_unlock
;
1187 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
1188 ret_val
= qla8044_rd_reg_indirect(vha
,
1189 MD_MIU_TEST_AGT_CTRL
, &agt_ctrl
);
1190 if (ret_val
== QLA_FUNCTION_FAILED
) {
1191 ql_log(ql_log_fatal
, vha
, 0xb0a4,
1192 "%s: failed to read "
1193 "MD_MIU_TEST_AGT_CTRL!\n", __func__
);
1194 goto exit_ms_mem_write_unlock
;
1196 if ((agt_ctrl
& MIU_TA_CTL_BUSY
) == 0)
1200 /* Status check failed */
1201 if (j
>= MAX_CTL_CHECK
) {
1202 ql_log(ql_log_fatal
, vha
, 0xb0a5,
1203 "%s: MS memory write failed!\n",
1205 ret_val
= QLA_FUNCTION_FAILED
;
1206 goto exit_ms_mem_write_unlock
;
1210 exit_ms_mem_write_unlock
:
1211 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
1218 qla8044_copy_bootloader(struct scsi_qla_host
*vha
)
1221 uint32_t src
, count
, size
;
1223 int ret_val
= QLA_SUCCESS
;
1224 struct qla_hw_data
*ha
= vha
->hw
;
1226 src
= QLA8044_BOOTLOADER_FLASH_ADDR
;
1227 dest
= qla8044_rd_reg(ha
, QLA8044_BOOTLOADER_ADDR
);
1228 size
= qla8044_rd_reg(ha
, QLA8044_BOOTLOADER_SIZE
);
1230 /* 128 bit alignment check */
1232 size
= (size
+ 16) & ~0xF;
1237 p_cache
= vmalloc(size
);
1238 if (p_cache
== NULL
) {
1239 ql_log(ql_log_fatal
, vha
, 0xb0a6,
1240 "%s: Failed to allocate memory for "
1241 "boot loader cache\n", __func__
);
1242 ret_val
= QLA_FUNCTION_FAILED
;
1243 goto exit_copy_bootloader
;
1246 ret_val
= qla8044_lockless_flash_read_u32(vha
, src
,
1247 p_cache
, size
/sizeof(uint32_t));
1248 if (ret_val
== QLA_FUNCTION_FAILED
) {
1249 ql_log(ql_log_fatal
, vha
, 0xb0a7,
1250 "%s: Error reading F/W from flash!!!\n", __func__
);
1251 goto exit_copy_error
;
1253 ql_dbg(ql_dbg_p3p
, vha
, 0xb0a8, "%s: Read F/W from flash!\n",
1256 /* 128 bit/16 byte write to MS memory */
1257 ret_val
= qla8044_ms_mem_write_128b(vha
, dest
,
1258 (uint32_t *)p_cache
, count
);
1259 if (ret_val
== QLA_FUNCTION_FAILED
) {
1260 ql_log(ql_log_fatal
, vha
, 0xb0a9,
1261 "%s: Error writing F/W to MS !!!\n", __func__
);
1262 goto exit_copy_error
;
1264 ql_dbg(ql_dbg_p3p
, vha
, 0xb0aa,
1265 "%s: Wrote F/W (size %d) to MS !!!\n",
1271 exit_copy_bootloader
:
1276 qla8044_restart(struct scsi_qla_host
*vha
)
1278 int ret_val
= QLA_SUCCESS
;
1279 struct qla_hw_data
*ha
= vha
->hw
;
1281 qla8044_process_stop_seq(vha
);
1283 /* Collect minidump */
1285 qla8044_get_minidump(vha
);
1287 ql_log(ql_log_fatal
, vha
, 0xb14c,
1288 "Minidump disabled.\n");
1290 qla8044_process_init_seq(vha
);
1292 if (qla8044_copy_bootloader(vha
)) {
1293 ql_log(ql_log_fatal
, vha
, 0xb0ab,
1294 "%s: Copy bootloader, firmware restart failed!\n",
1296 ret_val
= QLA_FUNCTION_FAILED
;
1301 * Loads F/W from flash
1303 qla8044_wr_reg(ha
, QLA8044_FW_IMAGE_VALID
, QLA8044_BOOT_FROM_FLASH
);
1305 qla8044_process_start_seq(vha
);
1312 * qla8044_check_cmd_peg_status - Check peg status to see if Peg is
1315 * @ha : Pointer to adapter structure
1317 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1320 qla8044_check_cmd_peg_status(struct scsi_qla_host
*vha
)
1322 uint32_t val
, ret_val
= QLA_FUNCTION_FAILED
;
1323 int retries
= CRB_CMDPEG_CHECK_RETRY_COUNT
;
1324 struct qla_hw_data
*ha
= vha
->hw
;
1327 val
= qla8044_rd_reg(ha
, QLA8044_CMDPEG_STATE
);
1328 if (val
== PHAN_INITIALIZE_COMPLETE
) {
1329 ql_dbg(ql_dbg_p3p
, vha
, 0xb0ac,
1330 "%s: Command Peg initialization "
1331 "complete! state=0x%x\n", __func__
, val
);
1332 ret_val
= QLA_SUCCESS
;
1335 msleep(CRB_CMDPEG_CHECK_DELAY
);
1336 } while (--retries
);
1342 qla8044_start_firmware(struct scsi_qla_host
*vha
)
1344 int ret_val
= QLA_SUCCESS
;
1346 if (qla8044_restart(vha
)) {
1347 ql_log(ql_log_fatal
, vha
, 0xb0ad,
1348 "%s: Restart Error!!!, Need Reset!!!\n",
1350 ret_val
= QLA_FUNCTION_FAILED
;
1353 ql_dbg(ql_dbg_p3p
, vha
, 0xb0af,
1354 "%s: Restart done!\n", __func__
);
1356 ret_val
= qla8044_check_cmd_peg_status(vha
);
1358 ql_log(ql_log_fatal
, vha
, 0xb0b0,
1359 "%s: Peg not initialized!\n", __func__
);
1360 ret_val
= QLA_FUNCTION_FAILED
;
1368 qla8044_clear_drv_active(struct qla_hw_data
*ha
)
1370 uint32_t drv_active
;
1371 struct scsi_qla_host
*vha
= pci_get_drvdata(ha
->pdev
);
1373 drv_active
= qla8044_rd_direct(vha
, QLA8044_CRB_DRV_ACTIVE_INDEX
);
1374 drv_active
&= ~(1 << (ha
->portnum
));
1376 ql_log(ql_log_info
, vha
, 0xb0b1,
1377 "%s(%ld): drv_active: 0x%08x\n",
1378 __func__
, vha
->host_no
, drv_active
);
1380 qla8044_wr_direct(vha
, QLA8044_CRB_DRV_ACTIVE_INDEX
, drv_active
);
1384 * qla8044_device_bootstrap - Initialize device, set DEV_READY, start fw
1385 * @ha: pointer to adapter structure
1387 * Note: IDC lock must be held upon entry
1390 qla8044_device_bootstrap(struct scsi_qla_host
*vha
)
1392 int rval
= QLA_FUNCTION_FAILED
;
1394 uint32_t old_count
= 0, count
= 0;
1397 struct qla_hw_data
*ha
= vha
->hw
;
1399 need_reset
= qla8044_need_reset(vha
);
1402 old_count
= qla8044_rd_direct(vha
,
1403 QLA8044_PEG_ALIVE_COUNTER_INDEX
);
1405 for (i
= 0; i
< 10; i
++) {
1408 count
= qla8044_rd_direct(vha
,
1409 QLA8044_PEG_ALIVE_COUNTER_INDEX
);
1410 if (count
!= old_count
) {
1415 qla8044_flash_lock_recovery(vha
);
1417 /* We are trying to perform a recovery here. */
1418 if (ha
->flags
.isp82xx_fw_hung
)
1419 qla8044_flash_lock_recovery(vha
);
1422 /* set to DEV_INITIALIZING */
1423 ql_log(ql_log_info
, vha
, 0xb0b2,
1424 "%s: HW State: INITIALIZING\n", __func__
);
1425 qla8044_wr_direct(vha
, QLA8044_CRB_DEV_STATE_INDEX
,
1426 QLA8XXX_DEV_INITIALIZING
);
1428 qla8044_idc_unlock(ha
);
1429 rval
= qla8044_start_firmware(vha
);
1430 qla8044_idc_lock(ha
);
1432 if (rval
!= QLA_SUCCESS
) {
1433 ql_log(ql_log_info
, vha
, 0xb0b3,
1434 "%s: HW State: FAILED\n", __func__
);
1435 qla8044_clear_drv_active(ha
);
1436 qla8044_wr_direct(vha
, QLA8044_CRB_DEV_STATE_INDEX
,
1437 QLA8XXX_DEV_FAILED
);
1441 /* For ISP8044, If IDC_CTRL GRACEFUL_RESET_BIT1 is set , reset it after
1442 * device goes to INIT state. */
1443 idc_ctrl
= qla8044_rd_reg(ha
, QLA8044_IDC_DRV_CTRL
);
1444 if (idc_ctrl
& GRACEFUL_RESET_BIT1
) {
1445 qla8044_wr_reg(ha
, QLA8044_IDC_DRV_CTRL
,
1446 (idc_ctrl
& ~GRACEFUL_RESET_BIT1
));
1451 ql_log(ql_log_info
, vha
, 0xb0b4,
1452 "%s: HW State: READY\n", __func__
);
1453 qla8044_wr_direct(vha
, QLA8044_CRB_DEV_STATE_INDEX
, QLA8XXX_DEV_READY
);
1458 /*-------------------------Reset Sequence Functions-----------------------*/
1460 qla8044_dump_reset_seq_hdr(struct scsi_qla_host
*vha
)
1464 if (!vha
->reset_tmplt
.buff
) {
1465 ql_log(ql_log_fatal
, vha
, 0xb0b5,
1466 "%s: Error Invalid reset_seq_template\n", __func__
);
1470 phdr
= vha
->reset_tmplt
.buff
;
1471 ql_dbg(ql_dbg_p3p
, vha
, 0xb0b6,
1472 "Reset Template :\n\t0x%X 0x%X 0x%X 0x%X"
1473 "0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n"
1474 "\t0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n\n",
1475 *phdr
, *(phdr
+1), *(phdr
+2), *(phdr
+3), *(phdr
+4),
1476 *(phdr
+5), *(phdr
+6), *(phdr
+7), *(phdr
+ 8),
1477 *(phdr
+9), *(phdr
+10), *(phdr
+11), *(phdr
+12),
1478 *(phdr
+13), *(phdr
+14), *(phdr
+15));
1482 * qla8044_reset_seq_checksum_test - Validate Reset Sequence template.
1484 * @ha : Pointer to adapter structure
1486 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1489 qla8044_reset_seq_checksum_test(struct scsi_qla_host
*vha
)
1492 uint16_t *buff
= (uint16_t *)vha
->reset_tmplt
.buff
;
1493 int u16_count
= vha
->reset_tmplt
.hdr
->size
/ sizeof(uint16_t);
1495 while (u16_count
-- > 0)
1499 sum
= (sum
& 0xFFFF) + (sum
>> 16);
1501 /* checksum of 0 indicates a valid template */
1505 ql_log(ql_log_fatal
, vha
, 0xb0b7,
1506 "%s: Reset seq checksum failed\n", __func__
);
1507 return QLA_FUNCTION_FAILED
;
1512 * qla8044_read_reset_template - Read Reset Template from Flash, validate
1513 * the template and store offsets of stop/start/init offsets in ha->reset_tmplt.
1515 * @ha : Pointer to adapter structure
1518 qla8044_read_reset_template(struct scsi_qla_host
*vha
)
1521 uint32_t addr
, tmplt_hdr_def_size
, tmplt_hdr_size
;
1523 vha
->reset_tmplt
.seq_error
= 0;
1524 vha
->reset_tmplt
.buff
= vmalloc(QLA8044_RESTART_TEMPLATE_SIZE
);
1525 if (vha
->reset_tmplt
.buff
== NULL
) {
1526 ql_log(ql_log_fatal
, vha
, 0xb0b8,
1527 "%s: Failed to allocate reset template resources\n",
1529 goto exit_read_reset_template
;
1532 p_buff
= vha
->reset_tmplt
.buff
;
1533 addr
= QLA8044_RESET_TEMPLATE_ADDR
;
1535 tmplt_hdr_def_size
=
1536 sizeof(struct qla8044_reset_template_hdr
) / sizeof(uint32_t);
1538 ql_dbg(ql_dbg_p3p
, vha
, 0xb0b9,
1539 "%s: Read template hdr size %d from Flash\n",
1540 __func__
, tmplt_hdr_def_size
);
1542 /* Copy template header from flash */
1543 if (qla8044_read_flash_data(vha
, p_buff
, addr
, tmplt_hdr_def_size
)) {
1544 ql_log(ql_log_fatal
, vha
, 0xb0ba,
1545 "%s: Failed to read reset template\n", __func__
);
1546 goto exit_read_template_error
;
1549 vha
->reset_tmplt
.hdr
=
1550 (struct qla8044_reset_template_hdr
*) vha
->reset_tmplt
.buff
;
1552 /* Validate the template header size and signature */
1553 tmplt_hdr_size
= vha
->reset_tmplt
.hdr
->hdr_size
/sizeof(uint32_t);
1554 if ((tmplt_hdr_size
!= tmplt_hdr_def_size
) ||
1555 (vha
->reset_tmplt
.hdr
->signature
!= RESET_TMPLT_HDR_SIGNATURE
)) {
1556 ql_log(ql_log_fatal
, vha
, 0xb0bb,
1557 "%s: Template Header size invalid %d "
1558 "tmplt_hdr_def_size %d!!!\n", __func__
,
1559 tmplt_hdr_size
, tmplt_hdr_def_size
);
1560 goto exit_read_template_error
;
1563 addr
= QLA8044_RESET_TEMPLATE_ADDR
+ vha
->reset_tmplt
.hdr
->hdr_size
;
1564 p_buff
= vha
->reset_tmplt
.buff
+ vha
->reset_tmplt
.hdr
->hdr_size
;
1565 tmplt_hdr_def_size
= (vha
->reset_tmplt
.hdr
->size
-
1566 vha
->reset_tmplt
.hdr
->hdr_size
)/sizeof(uint32_t);
1568 ql_dbg(ql_dbg_p3p
, vha
, 0xb0bc,
1569 "%s: Read rest of the template size %d\n",
1570 __func__
, vha
->reset_tmplt
.hdr
->size
);
1572 /* Copy rest of the template */
1573 if (qla8044_read_flash_data(vha
, p_buff
, addr
, tmplt_hdr_def_size
)) {
1574 ql_log(ql_log_fatal
, vha
, 0xb0bd,
1575 "%s: Failed to read reset tempelate\n", __func__
);
1576 goto exit_read_template_error
;
1579 /* Integrity check */
1580 if (qla8044_reset_seq_checksum_test(vha
)) {
1581 ql_log(ql_log_fatal
, vha
, 0xb0be,
1582 "%s: Reset Seq checksum failed!\n", __func__
);
1583 goto exit_read_template_error
;
1586 ql_dbg(ql_dbg_p3p
, vha
, 0xb0bf,
1587 "%s: Reset Seq checksum passed! Get stop, "
1588 "start and init seq offsets\n", __func__
);
1590 /* Get STOP, START, INIT sequence offsets */
1591 vha
->reset_tmplt
.init_offset
= vha
->reset_tmplt
.buff
+
1592 vha
->reset_tmplt
.hdr
->init_seq_offset
;
1594 vha
->reset_tmplt
.start_offset
= vha
->reset_tmplt
.buff
+
1595 vha
->reset_tmplt
.hdr
->start_seq_offset
;
1597 vha
->reset_tmplt
.stop_offset
= vha
->reset_tmplt
.buff
+
1598 vha
->reset_tmplt
.hdr
->hdr_size
;
1600 qla8044_dump_reset_seq_hdr(vha
);
1602 goto exit_read_reset_template
;
1604 exit_read_template_error
:
1605 vfree(vha
->reset_tmplt
.buff
);
1607 exit_read_reset_template
:
1612 qla8044_set_idc_dontreset(struct scsi_qla_host
*vha
)
1615 struct qla_hw_data
*ha
= vha
->hw
;
1617 idc_ctrl
= qla8044_rd_reg(ha
, QLA8044_IDC_DRV_CTRL
);
1618 idc_ctrl
|= DONTRESET_BIT0
;
1619 ql_dbg(ql_dbg_p3p
, vha
, 0xb0c0,
1620 "%s: idc_ctrl = %d\n", __func__
, idc_ctrl
);
1621 qla8044_wr_reg(ha
, QLA8044_IDC_DRV_CTRL
, idc_ctrl
);
1625 qla8044_set_rst_ready(struct scsi_qla_host
*vha
)
1628 struct qla_hw_data
*ha
= vha
->hw
;
1630 drv_state
= qla8044_rd_direct(vha
, QLA8044_CRB_DRV_STATE_INDEX
);
1632 /* For ISP8044, drv_active register has 1 bit per function,
1633 * shift 1 by func_num to set a bit for the function.*/
1634 drv_state
|= (1 << ha
->portnum
);
1636 ql_log(ql_log_info
, vha
, 0xb0c1,
1637 "%s(%ld): drv_state: 0x%08x\n",
1638 __func__
, vha
->host_no
, drv_state
);
1639 qla8044_wr_direct(vha
, QLA8044_CRB_DRV_STATE_INDEX
, drv_state
);
1643 * qla8044_need_reset_handler - Code to start reset sequence
1644 * @ha: pointer to adapter structure
1646 * Note: IDC lock must be held upon entry
1649 qla8044_need_reset_handler(struct scsi_qla_host
*vha
)
1651 uint32_t dev_state
= 0, drv_state
, drv_active
;
1652 unsigned long reset_timeout
;
1653 struct qla_hw_data
*ha
= vha
->hw
;
1655 ql_log(ql_log_fatal
, vha
, 0xb0c2,
1656 "%s: Performing ISP error recovery\n", __func__
);
1658 if (vha
->flags
.online
) {
1659 qla8044_idc_unlock(ha
);
1660 qla2x00_abort_isp_cleanup(vha
);
1661 ha
->isp_ops
->get_flash_version(vha
, vha
->req
->ring
);
1662 ha
->isp_ops
->nvram_config(vha
);
1663 qla8044_idc_lock(ha
);
1666 dev_state
= qla8044_rd_direct(vha
,
1667 QLA8044_CRB_DEV_STATE_INDEX
);
1668 drv_state
= qla8044_rd_direct(vha
,
1669 QLA8044_CRB_DRV_STATE_INDEX
);
1670 drv_active
= qla8044_rd_direct(vha
,
1671 QLA8044_CRB_DRV_ACTIVE_INDEX
);
1673 ql_log(ql_log_info
, vha
, 0xb0c5,
1674 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x dev_state = 0x%x\n",
1675 __func__
, vha
->host_no
, drv_state
, drv_active
, dev_state
);
1677 qla8044_set_rst_ready(vha
);
1679 /* wait for 10 seconds for reset ack from all functions */
1680 reset_timeout
= jiffies
+ (ha
->fcoe_reset_timeout
* HZ
);
1683 if (time_after_eq(jiffies
, reset_timeout
)) {
1684 ql_log(ql_log_info
, vha
, 0xb0c4,
1685 "%s: Function %d: Reset Ack Timeout!, drv_state: 0x%08x, drv_active: 0x%08x\n",
1686 __func__
, ha
->portnum
, drv_state
, drv_active
);
1690 qla8044_idc_unlock(ha
);
1692 qla8044_idc_lock(ha
);
1694 dev_state
= qla8044_rd_direct(vha
,
1695 QLA8044_CRB_DEV_STATE_INDEX
);
1696 drv_state
= qla8044_rd_direct(vha
,
1697 QLA8044_CRB_DRV_STATE_INDEX
);
1698 drv_active
= qla8044_rd_direct(vha
,
1699 QLA8044_CRB_DRV_ACTIVE_INDEX
);
1700 } while (((drv_state
& drv_active
) != drv_active
) &&
1701 (dev_state
== QLA8XXX_DEV_NEED_RESET
));
1703 /* Remove IDC participation of functions not acknowledging */
1704 if (drv_state
!= drv_active
) {
1705 ql_log(ql_log_info
, vha
, 0xb0c7,
1706 "%s(%ld): Function %d turning off drv_active of non-acking function 0x%x\n",
1707 __func__
, vha
->host_no
, ha
->portnum
,
1708 (drv_active
^ drv_state
));
1709 drv_active
= drv_active
& drv_state
;
1710 qla8044_wr_direct(vha
, QLA8044_CRB_DRV_ACTIVE_INDEX
,
1714 * Reset owner should execute reset recovery,
1715 * if all functions acknowledged
1717 if ((ha
->flags
.nic_core_reset_owner
) &&
1718 (dev_state
== QLA8XXX_DEV_NEED_RESET
)) {
1719 ha
->flags
.nic_core_reset_owner
= 0;
1720 qla8044_device_bootstrap(vha
);
1725 /* Exit if non active function */
1726 if (!(drv_active
& (1 << ha
->portnum
))) {
1727 ha
->flags
.nic_core_reset_owner
= 0;
1732 * Execute Reset Recovery if Reset Owner or Function 7
1733 * is the only active function
1735 if (ha
->flags
.nic_core_reset_owner
||
1736 ((drv_state
& drv_active
) == QLA8044_FUN7_ACTIVE_INDEX
)) {
1737 ha
->flags
.nic_core_reset_owner
= 0;
1738 qla8044_device_bootstrap(vha
);
1743 qla8044_set_drv_active(struct scsi_qla_host
*vha
)
1745 uint32_t drv_active
;
1746 struct qla_hw_data
*ha
= vha
->hw
;
1748 drv_active
= qla8044_rd_direct(vha
, QLA8044_CRB_DRV_ACTIVE_INDEX
);
1750 /* For ISP8044, drv_active register has 1 bit per function,
1751 * shift 1 by func_num to set a bit for the function.*/
1752 drv_active
|= (1 << ha
->portnum
);
1754 ql_log(ql_log_info
, vha
, 0xb0c8,
1755 "%s(%ld): drv_active: 0x%08x\n",
1756 __func__
, vha
->host_no
, drv_active
);
1757 qla8044_wr_direct(vha
, QLA8044_CRB_DRV_ACTIVE_INDEX
, drv_active
);
1761 qla8044_check_drv_active(struct scsi_qla_host
*vha
)
1763 uint32_t drv_active
;
1764 struct qla_hw_data
*ha
= vha
->hw
;
1766 drv_active
= qla8044_rd_direct(vha
, QLA8044_CRB_DRV_ACTIVE_INDEX
);
1767 if (drv_active
& (1 << ha
->portnum
))
1770 return QLA_TEST_FAILED
;
1774 qla8044_clear_idc_dontreset(struct scsi_qla_host
*vha
)
1777 struct qla_hw_data
*ha
= vha
->hw
;
1779 idc_ctrl
= qla8044_rd_reg(ha
, QLA8044_IDC_DRV_CTRL
);
1780 idc_ctrl
&= ~DONTRESET_BIT0
;
1781 ql_log(ql_log_info
, vha
, 0xb0c9,
1782 "%s: idc_ctrl = %d\n", __func__
,
1784 qla8044_wr_reg(ha
, QLA8044_IDC_DRV_CTRL
, idc_ctrl
);
1788 qla8044_set_idc_ver(struct scsi_qla_host
*vha
)
1791 uint32_t drv_active
;
1792 int rval
= QLA_SUCCESS
;
1793 struct qla_hw_data
*ha
= vha
->hw
;
1795 drv_active
= qla8044_rd_direct(vha
, QLA8044_CRB_DRV_ACTIVE_INDEX
);
1796 if (drv_active
== (1 << ha
->portnum
)) {
1797 idc_ver
= qla8044_rd_direct(vha
,
1798 QLA8044_CRB_DRV_IDC_VERSION_INDEX
);
1800 idc_ver
|= QLA8044_IDC_VER_MAJ_VALUE
;
1801 qla8044_wr_direct(vha
, QLA8044_CRB_DRV_IDC_VERSION_INDEX
,
1803 ql_log(ql_log_info
, vha
, 0xb0ca,
1804 "%s: IDC version updated to %d\n",
1807 idc_ver
= qla8044_rd_direct(vha
,
1808 QLA8044_CRB_DRV_IDC_VERSION_INDEX
);
1810 if (QLA8044_IDC_VER_MAJ_VALUE
!= idc_ver
) {
1811 ql_log(ql_log_info
, vha
, 0xb0cb,
1812 "%s: qla4xxx driver IDC version %d "
1813 "is not compatible with IDC version %d "
1814 "of other drivers!\n",
1815 __func__
, QLA8044_IDC_VER_MAJ_VALUE
,
1817 rval
= QLA_FUNCTION_FAILED
;
1818 goto exit_set_idc_ver
;
1822 /* Update IDC_MINOR_VERSION */
1823 idc_ver
= qla8044_rd_reg(ha
, QLA8044_CRB_IDC_VER_MINOR
);
1824 idc_ver
&= ~(0x03 << (ha
->portnum
* 2));
1825 idc_ver
|= (QLA8044_IDC_VER_MIN_VALUE
<< (ha
->portnum
* 2));
1826 qla8044_wr_reg(ha
, QLA8044_CRB_IDC_VER_MINOR
, idc_ver
);
1833 qla8044_update_idc_reg(struct scsi_qla_host
*vha
)
1835 uint32_t drv_active
;
1836 int rval
= QLA_SUCCESS
;
1837 struct qla_hw_data
*ha
= vha
->hw
;
1839 if (vha
->flags
.init_done
)
1840 goto exit_update_idc_reg
;
1842 qla8044_idc_lock(ha
);
1843 qla8044_set_drv_active(vha
);
1845 drv_active
= qla8044_rd_direct(vha
,
1846 QLA8044_CRB_DRV_ACTIVE_INDEX
);
1848 /* If we are the first driver to load and
1849 * ql2xdontresethba is not set, clear IDC_CTRL BIT0. */
1850 if ((drv_active
== (1 << ha
->portnum
)) && !ql2xdontresethba
)
1851 qla8044_clear_idc_dontreset(vha
);
1853 rval
= qla8044_set_idc_ver(vha
);
1854 if (rval
== QLA_FUNCTION_FAILED
)
1855 qla8044_clear_drv_active(ha
);
1856 qla8044_idc_unlock(ha
);
1858 exit_update_idc_reg
:
1863 * qla8044_need_qsnt_handler - Code to start qsnt
1864 * @ha: pointer to adapter structure
1867 qla8044_need_qsnt_handler(struct scsi_qla_host
*vha
)
1869 unsigned long qsnt_timeout
;
1870 uint32_t drv_state
, drv_active
, dev_state
;
1871 struct qla_hw_data
*ha
= vha
->hw
;
1873 if (vha
->flags
.online
)
1874 qla2x00_quiesce_io(vha
);
1878 qla8044_set_qsnt_ready(vha
);
1880 /* Wait for 30 secs for all functions to ack qsnt mode */
1881 qsnt_timeout
= jiffies
+ (QSNT_ACK_TOV
* HZ
);
1882 drv_state
= qla8044_rd_direct(vha
, QLA8044_CRB_DRV_STATE_INDEX
);
1883 drv_active
= qla8044_rd_direct(vha
, QLA8044_CRB_DRV_ACTIVE_INDEX
);
1885 /* Shift drv_active by 1 to match drv_state. As quiescent ready bit
1886 position is at bit 1 and drv active is at bit 0 */
1887 drv_active
= drv_active
<< 1;
1889 while (drv_state
!= drv_active
) {
1890 if (time_after_eq(jiffies
, qsnt_timeout
)) {
1891 /* Other functions did not ack, changing state to
1894 clear_bit(ISP_QUIESCE_NEEDED
, &vha
->dpc_flags
);
1895 qla8044_wr_direct(vha
, QLA8044_CRB_DEV_STATE_INDEX
,
1897 qla8044_clear_qsnt_ready(vha
);
1898 ql_log(ql_log_info
, vha
, 0xb0cc,
1899 "Timeout waiting for quiescent ack!!!\n");
1902 qla8044_idc_unlock(ha
);
1904 qla8044_idc_lock(ha
);
1906 drv_state
= qla8044_rd_direct(vha
,
1907 QLA8044_CRB_DRV_STATE_INDEX
);
1908 drv_active
= qla8044_rd_direct(vha
,
1909 QLA8044_CRB_DRV_ACTIVE_INDEX
);
1910 drv_active
= drv_active
<< 1;
1913 /* All functions have Acked. Set quiescent state */
1914 dev_state
= qla8044_rd_direct(vha
, QLA8044_CRB_DEV_STATE_INDEX
);
1916 if (dev_state
== QLA8XXX_DEV_NEED_QUIESCENT
) {
1917 qla8044_wr_direct(vha
, QLA8044_CRB_DEV_STATE_INDEX
,
1918 QLA8XXX_DEV_QUIESCENT
);
1919 ql_log(ql_log_info
, vha
, 0xb0cd,
1920 "%s: HW State: QUIESCENT\n", __func__
);
1925 * qla8044_device_state_handler - Adapter state machine
1926 * @ha: pointer to host adapter structure.
1928 * Note: IDC lock must be UNLOCKED upon entry
1931 qla8044_device_state_handler(struct scsi_qla_host
*vha
)
1934 int rval
= QLA_SUCCESS
;
1935 unsigned long dev_init_timeout
;
1936 struct qla_hw_data
*ha
= vha
->hw
;
1938 rval
= qla8044_update_idc_reg(vha
);
1939 if (rval
== QLA_FUNCTION_FAILED
)
1942 dev_state
= qla8044_rd_direct(vha
, QLA8044_CRB_DEV_STATE_INDEX
);
1943 ql_dbg(ql_dbg_p3p
, vha
, 0xb0ce,
1944 "Device state is 0x%x = %s\n",
1945 dev_state
, dev_state
< MAX_STATES
?
1946 qdev_state(dev_state
) : "Unknown");
1948 /* wait for 30 seconds for device to go ready */
1949 dev_init_timeout
= jiffies
+ (ha
->fcoe_dev_init_timeout
* HZ
);
1951 qla8044_idc_lock(ha
);
1954 if (time_after_eq(jiffies
, dev_init_timeout
)) {
1955 if (qla8044_check_drv_active(vha
) == QLA_SUCCESS
) {
1956 ql_log(ql_log_warn
, vha
, 0xb0cf,
1957 "%s: Device Init Failed 0x%x = %s\n",
1958 QLA2XXX_DRIVER_NAME
, dev_state
,
1959 dev_state
< MAX_STATES
?
1960 qdev_state(dev_state
) : "Unknown");
1961 qla8044_wr_direct(vha
,
1962 QLA8044_CRB_DEV_STATE_INDEX
,
1963 QLA8XXX_DEV_FAILED
);
1967 dev_state
= qla8044_rd_direct(vha
, QLA8044_CRB_DEV_STATE_INDEX
);
1968 ql_log(ql_log_info
, vha
, 0xb0d0,
1969 "Device state is 0x%x = %s\n",
1970 dev_state
, dev_state
< MAX_STATES
?
1971 qdev_state(dev_state
) : "Unknown");
1973 /* NOTE: Make sure idc unlocked upon exit of switch statement */
1974 switch (dev_state
) {
1975 case QLA8XXX_DEV_READY
:
1976 ha
->flags
.nic_core_reset_owner
= 0;
1978 case QLA8XXX_DEV_COLD
:
1979 rval
= qla8044_device_bootstrap(vha
);
1981 case QLA8XXX_DEV_INITIALIZING
:
1982 qla8044_idc_unlock(ha
);
1984 qla8044_idc_lock(ha
);
1986 case QLA8XXX_DEV_NEED_RESET
:
1987 /* For ISP8044, if NEED_RESET is set by any driver,
1988 * it should be honored, irrespective of IDC_CTRL
1990 qla8044_need_reset_handler(vha
);
1992 case QLA8XXX_DEV_NEED_QUIESCENT
:
1993 /* idc locked/unlocked in handler */
1994 qla8044_need_qsnt_handler(vha
);
1996 /* Reset the init timeout after qsnt handler */
1997 dev_init_timeout
= jiffies
+
1998 (ha
->fcoe_reset_timeout
* HZ
);
2000 case QLA8XXX_DEV_QUIESCENT
:
2001 ql_log(ql_log_info
, vha
, 0xb0d1,
2002 "HW State: QUIESCENT\n");
2004 qla8044_idc_unlock(ha
);
2006 qla8044_idc_lock(ha
);
2008 /* Reset the init timeout after qsnt handler */
2009 dev_init_timeout
= jiffies
+
2010 (ha
->fcoe_reset_timeout
* HZ
);
2012 case QLA8XXX_DEV_FAILED
:
2013 ha
->flags
.nic_core_reset_owner
= 0;
2014 qla8044_idc_unlock(ha
);
2015 qla8xxx_dev_failed_handler(vha
);
2016 rval
= QLA_FUNCTION_FAILED
;
2017 qla8044_idc_lock(ha
);
2020 qla8044_idc_unlock(ha
);
2021 qla8xxx_dev_failed_handler(vha
);
2022 rval
= QLA_FUNCTION_FAILED
;
2023 qla8044_idc_lock(ha
);
2028 qla8044_idc_unlock(ha
);
2035 * qla4_8xxx_check_temp - Check the ISP82XX temperature.
2036 * @ha: adapter block pointer.
2038 * Note: The caller should not hold the idc lock.
2041 qla8044_check_temp(struct scsi_qla_host
*vha
)
2043 uint32_t temp
, temp_state
, temp_val
;
2044 int status
= QLA_SUCCESS
;
2046 temp
= qla8044_rd_direct(vha
, QLA8044_CRB_TEMP_STATE_INDEX
);
2047 temp_state
= qla82xx_get_temp_state(temp
);
2048 temp_val
= qla82xx_get_temp_val(temp
);
2050 if (temp_state
== QLA82XX_TEMP_PANIC
) {
2051 ql_log(ql_log_warn
, vha
, 0xb0d2,
2052 "Device temperature %d degrees C"
2053 " exceeds maximum allowed. Hardware has been shut"
2054 " down\n", temp_val
);
2055 status
= QLA_FUNCTION_FAILED
;
2057 } else if (temp_state
== QLA82XX_TEMP_WARN
) {
2058 ql_log(ql_log_warn
, vha
, 0xb0d3,
2059 "Device temperature %d"
2060 " degrees C exceeds operating range."
2061 " Immediate action needed.\n", temp_val
);
2066 int qla8044_read_temperature(scsi_qla_host_t
*vha
)
2070 temp
= qla8044_rd_direct(vha
, QLA8044_CRB_TEMP_STATE_INDEX
);
2071 return qla82xx_get_temp_val(temp
);
2075 * qla8044_check_fw_alive - Check firmware health
2076 * @ha: Pointer to host adapter structure.
2078 * Context: Interrupt
2081 qla8044_check_fw_alive(struct scsi_qla_host
*vha
)
2083 uint32_t fw_heartbeat_counter
;
2084 uint32_t halt_status1
, halt_status2
;
2085 int status
= QLA_SUCCESS
;
2087 fw_heartbeat_counter
= qla8044_rd_direct(vha
,
2088 QLA8044_PEG_ALIVE_COUNTER_INDEX
);
2090 /* If PEG_ALIVE_COUNTER is 0xffffffff, AER/EEH is in progress, ignore */
2091 if (fw_heartbeat_counter
== 0xffffffff) {
2092 ql_dbg(ql_dbg_p3p
, vha
, 0xb0d4,
2093 "scsi%ld: %s: Device in frozen "
2094 "state, QLA82XX_PEG_ALIVE_COUNTER is 0xffffffff\n",
2095 vha
->host_no
, __func__
);
2099 if (vha
->fw_heartbeat_counter
== fw_heartbeat_counter
) {
2100 vha
->seconds_since_last_heartbeat
++;
2101 /* FW not alive after 2 seconds */
2102 if (vha
->seconds_since_last_heartbeat
== 2) {
2103 vha
->seconds_since_last_heartbeat
= 0;
2104 halt_status1
= qla8044_rd_direct(vha
,
2105 QLA8044_PEG_HALT_STATUS1_INDEX
);
2106 halt_status2
= qla8044_rd_direct(vha
,
2107 QLA8044_PEG_HALT_STATUS2_INDEX
);
2109 ql_log(ql_log_info
, vha
, 0xb0d5,
2110 "scsi(%ld): %s, ISP8044 "
2111 "Dumping hw/fw registers:\n"
2112 " PEG_HALT_STATUS1: 0x%x, "
2113 "PEG_HALT_STATUS2: 0x%x,\n",
2114 vha
->host_no
, __func__
, halt_status1
,
2116 status
= QLA_FUNCTION_FAILED
;
2119 vha
->seconds_since_last_heartbeat
= 0;
2121 vha
->fw_heartbeat_counter
= fw_heartbeat_counter
;
2126 qla8044_watchdog(struct scsi_qla_host
*vha
)
2128 uint32_t dev_state
, halt_status
;
2129 int halt_status_unrecoverable
= 0;
2130 struct qla_hw_data
*ha
= vha
->hw
;
2132 /* don't poll if reset is going on or FW hang in quiescent state */
2133 if (!(test_bit(ABORT_ISP_ACTIVE
, &vha
->dpc_flags
) ||
2134 test_bit(FCOE_CTX_RESET_NEEDED
, &vha
->dpc_flags
))) {
2135 dev_state
= qla8044_rd_direct(vha
, QLA8044_CRB_DEV_STATE_INDEX
);
2137 if (qla8044_check_fw_alive(vha
)) {
2138 ha
->flags
.isp82xx_fw_hung
= 1;
2139 ql_log(ql_log_warn
, vha
, 0xb10a,
2140 "Firmware hung.\n");
2141 qla82xx_clear_pending_mbx(vha
);
2144 if (qla8044_check_temp(vha
)) {
2145 set_bit(ISP_UNRECOVERABLE
, &vha
->dpc_flags
);
2146 ha
->flags
.isp82xx_fw_hung
= 1;
2147 qla2xxx_wake_dpc(vha
);
2148 } else if (dev_state
== QLA8XXX_DEV_NEED_RESET
&&
2149 !test_bit(ISP_ABORT_NEEDED
, &vha
->dpc_flags
)) {
2150 ql_log(ql_log_info
, vha
, 0xb0d6,
2151 "%s: HW State: NEED RESET!\n",
2153 set_bit(ISP_ABORT_NEEDED
, &vha
->dpc_flags
);
2154 qla2xxx_wake_dpc(vha
);
2155 } else if (dev_state
== QLA8XXX_DEV_NEED_QUIESCENT
&&
2156 !test_bit(ISP_QUIESCE_NEEDED
, &vha
->dpc_flags
)) {
2157 ql_log(ql_log_info
, vha
, 0xb0d7,
2158 "%s: HW State: NEED QUIES detected!\n",
2160 set_bit(ISP_QUIESCE_NEEDED
, &vha
->dpc_flags
);
2161 qla2xxx_wake_dpc(vha
);
2163 /* Check firmware health */
2164 if (ha
->flags
.isp82xx_fw_hung
) {
2165 halt_status
= qla8044_rd_direct(vha
,
2166 QLA8044_PEG_HALT_STATUS1_INDEX
);
2168 QLA8044_HALT_STATUS_FW_RESET
) {
2169 ql_log(ql_log_fatal
, vha
,
2170 0xb0d8, "%s: Firmware "
2171 "error detected device "
2174 } else if (halt_status
&
2175 QLA8044_HALT_STATUS_UNRECOVERABLE
) {
2176 halt_status_unrecoverable
= 1;
2179 /* Since we cannot change dev_state in interrupt
2180 * context, set appropriate DPC flag then wakeup
2182 if (halt_status_unrecoverable
) {
2183 set_bit(ISP_UNRECOVERABLE
,
2187 QLA8XXX_DEV_QUIESCENT
) {
2188 set_bit(FCOE_CTX_RESET_NEEDED
,
2190 ql_log(ql_log_info
, vha
, 0xb0d9,
2191 "%s: FW CONTEXT Reset "
2192 "needed!\n", __func__
);
2194 ql_log(ql_log_info
, vha
,
2196 "detect abort needed\n",
2198 set_bit(ISP_ABORT_NEEDED
,
2202 qla2xxx_wake_dpc(vha
);
2210 qla8044_minidump_process_control(struct scsi_qla_host
*vha
,
2211 struct qla8044_minidump_entry_hdr
*entry_hdr
)
2213 struct qla8044_minidump_entry_crb
*crb_entry
;
2214 uint32_t read_value
, opcode
, poll_time
, addr
, index
;
2215 uint32_t crb_addr
, rval
= QLA_SUCCESS
;
2216 unsigned long wtime
;
2217 struct qla8044_minidump_template_hdr
*tmplt_hdr
;
2219 struct qla_hw_data
*ha
= vha
->hw
;
2221 ql_dbg(ql_dbg_p3p
, vha
, 0xb0dd, "Entering fn: %s\n", __func__
);
2222 tmplt_hdr
= (struct qla8044_minidump_template_hdr
*)
2224 crb_entry
= (struct qla8044_minidump_entry_crb
*)entry_hdr
;
2226 crb_addr
= crb_entry
->addr
;
2227 for (i
= 0; i
< crb_entry
->op_count
; i
++) {
2228 opcode
= crb_entry
->crb_ctrl
.opcode
;
2230 if (opcode
& QLA82XX_DBG_OPCODE_WR
) {
2231 qla8044_wr_reg_indirect(vha
, crb_addr
,
2232 crb_entry
->value_1
);
2233 opcode
&= ~QLA82XX_DBG_OPCODE_WR
;
2236 if (opcode
& QLA82XX_DBG_OPCODE_RW
) {
2237 qla8044_rd_reg_indirect(vha
, crb_addr
, &read_value
);
2238 qla8044_wr_reg_indirect(vha
, crb_addr
, read_value
);
2239 opcode
&= ~QLA82XX_DBG_OPCODE_RW
;
2242 if (opcode
& QLA82XX_DBG_OPCODE_AND
) {
2243 qla8044_rd_reg_indirect(vha
, crb_addr
, &read_value
);
2244 read_value
&= crb_entry
->value_2
;
2245 opcode
&= ~QLA82XX_DBG_OPCODE_AND
;
2246 if (opcode
& QLA82XX_DBG_OPCODE_OR
) {
2247 read_value
|= crb_entry
->value_3
;
2248 opcode
&= ~QLA82XX_DBG_OPCODE_OR
;
2250 qla8044_wr_reg_indirect(vha
, crb_addr
, read_value
);
2252 if (opcode
& QLA82XX_DBG_OPCODE_OR
) {
2253 qla8044_rd_reg_indirect(vha
, crb_addr
, &read_value
);
2254 read_value
|= crb_entry
->value_3
;
2255 qla8044_wr_reg_indirect(vha
, crb_addr
, read_value
);
2256 opcode
&= ~QLA82XX_DBG_OPCODE_OR
;
2258 if (opcode
& QLA82XX_DBG_OPCODE_POLL
) {
2259 poll_time
= crb_entry
->crb_strd
.poll_timeout
;
2260 wtime
= jiffies
+ poll_time
;
2261 qla8044_rd_reg_indirect(vha
, crb_addr
, &read_value
);
2264 if ((read_value
& crb_entry
->value_2
) ==
2265 crb_entry
->value_1
) {
2267 } else if (time_after_eq(jiffies
, wtime
)) {
2268 /* capturing dump failed */
2269 rval
= QLA_FUNCTION_FAILED
;
2272 qla8044_rd_reg_indirect(vha
,
2273 crb_addr
, &read_value
);
2276 opcode
&= ~QLA82XX_DBG_OPCODE_POLL
;
2279 if (opcode
& QLA82XX_DBG_OPCODE_RDSTATE
) {
2280 if (crb_entry
->crb_strd
.state_index_a
) {
2281 index
= crb_entry
->crb_strd
.state_index_a
;
2282 addr
= tmplt_hdr
->saved_state_array
[index
];
2287 qla8044_rd_reg_indirect(vha
, addr
, &read_value
);
2288 index
= crb_entry
->crb_ctrl
.state_index_v
;
2289 tmplt_hdr
->saved_state_array
[index
] = read_value
;
2290 opcode
&= ~QLA82XX_DBG_OPCODE_RDSTATE
;
2293 if (opcode
& QLA82XX_DBG_OPCODE_WRSTATE
) {
2294 if (crb_entry
->crb_strd
.state_index_a
) {
2295 index
= crb_entry
->crb_strd
.state_index_a
;
2296 addr
= tmplt_hdr
->saved_state_array
[index
];
2301 if (crb_entry
->crb_ctrl
.state_index_v
) {
2302 index
= crb_entry
->crb_ctrl
.state_index_v
;
2304 tmplt_hdr
->saved_state_array
[index
];
2306 read_value
= crb_entry
->value_1
;
2309 qla8044_wr_reg_indirect(vha
, addr
, read_value
);
2310 opcode
&= ~QLA82XX_DBG_OPCODE_WRSTATE
;
2313 if (opcode
& QLA82XX_DBG_OPCODE_MDSTATE
) {
2314 index
= crb_entry
->crb_ctrl
.state_index_v
;
2315 read_value
= tmplt_hdr
->saved_state_array
[index
];
2316 read_value
<<= crb_entry
->crb_ctrl
.shl
;
2317 read_value
>>= crb_entry
->crb_ctrl
.shr
;
2318 if (crb_entry
->value_2
)
2319 read_value
&= crb_entry
->value_2
;
2320 read_value
|= crb_entry
->value_3
;
2321 read_value
+= crb_entry
->value_1
;
2322 tmplt_hdr
->saved_state_array
[index
] = read_value
;
2323 opcode
&= ~QLA82XX_DBG_OPCODE_MDSTATE
;
2325 crb_addr
+= crb_entry
->crb_strd
.addr_stride
;
2331 qla8044_minidump_process_rdcrb(struct scsi_qla_host
*vha
,
2332 struct qla8044_minidump_entry_hdr
*entry_hdr
, uint32_t **d_ptr
)
2334 uint32_t r_addr
, r_stride
, loop_cnt
, i
, r_value
;
2335 struct qla8044_minidump_entry_crb
*crb_hdr
;
2336 uint32_t *data_ptr
= *d_ptr
;
2338 ql_dbg(ql_dbg_p3p
, vha
, 0xb0de, "Entering fn: %s\n", __func__
);
2339 crb_hdr
= (struct qla8044_minidump_entry_crb
*)entry_hdr
;
2340 r_addr
= crb_hdr
->addr
;
2341 r_stride
= crb_hdr
->crb_strd
.addr_stride
;
2342 loop_cnt
= crb_hdr
->op_count
;
2344 for (i
= 0; i
< loop_cnt
; i
++) {
2345 qla8044_rd_reg_indirect(vha
, r_addr
, &r_value
);
2346 *data_ptr
++ = r_addr
;
2347 *data_ptr
++ = r_value
;
2354 qla8044_minidump_process_rdmem(struct scsi_qla_host
*vha
,
2355 struct qla8044_minidump_entry_hdr
*entry_hdr
, uint32_t **d_ptr
)
2357 uint32_t r_addr
, r_value
, r_data
;
2358 uint32_t i
, j
, loop_cnt
;
2359 struct qla8044_minidump_entry_rdmem
*m_hdr
;
2360 unsigned long flags
;
2361 uint32_t *data_ptr
= *d_ptr
;
2362 struct qla_hw_data
*ha
= vha
->hw
;
2364 ql_dbg(ql_dbg_p3p
, vha
, 0xb0df, "Entering fn: %s\n", __func__
);
2365 m_hdr
= (struct qla8044_minidump_entry_rdmem
*)entry_hdr
;
2366 r_addr
= m_hdr
->read_addr
;
2367 loop_cnt
= m_hdr
->read_data_size
/16;
2369 ql_dbg(ql_dbg_p3p
, vha
, 0xb0f0,
2370 "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
2371 __func__
, r_addr
, m_hdr
->read_data_size
);
2374 ql_dbg(ql_dbg_p3p
, vha
, 0xb0f1,
2375 "[%s]: Read addr 0x%x not 16 bytes aligned\n",
2377 return QLA_FUNCTION_FAILED
;
2380 if (m_hdr
->read_data_size
% 16) {
2381 ql_dbg(ql_dbg_p3p
, vha
, 0xb0f2,
2382 "[%s]: Read data[0x%x] not multiple of 16 bytes\n",
2383 __func__
, m_hdr
->read_data_size
);
2384 return QLA_FUNCTION_FAILED
;
2387 ql_dbg(ql_dbg_p3p
, vha
, 0xb0f3,
2388 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
2389 __func__
, r_addr
, m_hdr
->read_data_size
, loop_cnt
);
2391 write_lock_irqsave(&ha
->hw_lock
, flags
);
2392 for (i
= 0; i
< loop_cnt
; i
++) {
2393 qla8044_wr_reg_indirect(vha
, MD_MIU_TEST_AGT_ADDR_LO
, r_addr
);
2395 qla8044_wr_reg_indirect(vha
, MD_MIU_TEST_AGT_ADDR_HI
, r_value
);
2396 r_value
= MIU_TA_CTL_ENABLE
;
2397 qla8044_wr_reg_indirect(vha
, MD_MIU_TEST_AGT_CTRL
, r_value
);
2398 r_value
= MIU_TA_CTL_START_ENABLE
;
2399 qla8044_wr_reg_indirect(vha
, MD_MIU_TEST_AGT_CTRL
, r_value
);
2401 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
2402 qla8044_rd_reg_indirect(vha
, MD_MIU_TEST_AGT_CTRL
,
2404 if ((r_value
& MIU_TA_CTL_BUSY
) == 0)
2408 if (j
>= MAX_CTL_CHECK
) {
2409 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
2413 for (j
= 0; j
< 4; j
++) {
2414 qla8044_rd_reg_indirect(vha
, MD_MIU_TEST_AGT_RDDATA
[j
],
2416 *data_ptr
++ = r_data
;
2421 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
2423 ql_dbg(ql_dbg_p3p
, vha
, 0xb0f4,
2424 "Leaving fn: %s datacount: 0x%x\n",
2425 __func__
, (loop_cnt
* 16));
2431 /* ISP83xx flash read for _RDROM _BOARD */
2433 qla8044_minidump_process_rdrom(struct scsi_qla_host
*vha
,
2434 struct qla8044_minidump_entry_hdr
*entry_hdr
, uint32_t **d_ptr
)
2436 uint32_t fl_addr
, u32_count
, rval
;
2437 struct qla8044_minidump_entry_rdrom
*rom_hdr
;
2438 uint32_t *data_ptr
= *d_ptr
;
2440 rom_hdr
= (struct qla8044_minidump_entry_rdrom
*)entry_hdr
;
2441 fl_addr
= rom_hdr
->read_addr
;
2442 u32_count
= (rom_hdr
->read_data_size
)/sizeof(uint32_t);
2444 ql_dbg(ql_dbg_p3p
, vha
, 0xb0f5, "[%s]: fl_addr: 0x%x, count: 0x%x\n",
2445 __func__
, fl_addr
, u32_count
);
2447 rval
= qla8044_lockless_flash_read_u32(vha
, fl_addr
,
2448 (u8
*)(data_ptr
), u32_count
);
2450 if (rval
!= QLA_SUCCESS
) {
2451 ql_log(ql_log_fatal
, vha
, 0xb0f6,
2452 "%s: Flash Read Error,Count=%d\n", __func__
, u32_count
);
2453 return QLA_FUNCTION_FAILED
;
2455 data_ptr
+= u32_count
;
2462 qla8044_mark_entry_skipped(struct scsi_qla_host
*vha
,
2463 struct qla8044_minidump_entry_hdr
*entry_hdr
, int index
)
2465 entry_hdr
->d_ctrl
.driver_flags
|= QLA82XX_DBG_SKIPPED_FLAG
;
2467 ql_log(ql_log_info
, vha
, 0xb0f7,
2468 "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
2469 vha
->host_no
, index
, entry_hdr
->entry_type
,
2470 entry_hdr
->d_ctrl
.entry_capture_mask
);
2474 qla8044_minidump_process_l2tag(struct scsi_qla_host
*vha
,
2475 struct qla8044_minidump_entry_hdr
*entry_hdr
,
2478 uint32_t addr
, r_addr
, c_addr
, t_r_addr
;
2479 uint32_t i
, k
, loop_count
, t_value
, r_cnt
, r_value
;
2480 unsigned long p_wait
, w_time
, p_mask
;
2481 uint32_t c_value_w
, c_value_r
;
2482 struct qla8044_minidump_entry_cache
*cache_hdr
;
2483 int rval
= QLA_FUNCTION_FAILED
;
2484 uint32_t *data_ptr
= *d_ptr
;
2486 ql_dbg(ql_dbg_p3p
, vha
, 0xb0f8, "Entering fn: %s\n", __func__
);
2487 cache_hdr
= (struct qla8044_minidump_entry_cache
*)entry_hdr
;
2489 loop_count
= cache_hdr
->op_count
;
2490 r_addr
= cache_hdr
->read_addr
;
2491 c_addr
= cache_hdr
->control_addr
;
2492 c_value_w
= cache_hdr
->cache_ctrl
.write_value
;
2494 t_r_addr
= cache_hdr
->tag_reg_addr
;
2495 t_value
= cache_hdr
->addr_ctrl
.init_tag_value
;
2496 r_cnt
= cache_hdr
->read_ctrl
.read_addr_cnt
;
2497 p_wait
= cache_hdr
->cache_ctrl
.poll_wait
;
2498 p_mask
= cache_hdr
->cache_ctrl
.poll_mask
;
2500 for (i
= 0; i
< loop_count
; i
++) {
2501 qla8044_wr_reg_indirect(vha
, t_r_addr
, t_value
);
2503 qla8044_wr_reg_indirect(vha
, c_addr
, c_value_w
);
2506 w_time
= jiffies
+ p_wait
;
2508 qla8044_rd_reg_indirect(vha
, c_addr
,
2510 if ((c_value_r
& p_mask
) == 0) {
2512 } else if (time_after_eq(jiffies
, w_time
)) {
2513 /* capturing dump failed */
2520 for (k
= 0; k
< r_cnt
; k
++) {
2521 qla8044_rd_reg_indirect(vha
, addr
, &r_value
);
2522 *data_ptr
++ = r_value
;
2523 addr
+= cache_hdr
->read_ctrl
.read_addr_stride
;
2525 t_value
+= cache_hdr
->addr_ctrl
.tag_value_stride
;
2532 qla8044_minidump_process_l1cache(struct scsi_qla_host
*vha
,
2533 struct qla8044_minidump_entry_hdr
*entry_hdr
, uint32_t **d_ptr
)
2535 uint32_t addr
, r_addr
, c_addr
, t_r_addr
;
2536 uint32_t i
, k
, loop_count
, t_value
, r_cnt
, r_value
;
2538 struct qla8044_minidump_entry_cache
*cache_hdr
;
2539 uint32_t *data_ptr
= *d_ptr
;
2541 cache_hdr
= (struct qla8044_minidump_entry_cache
*)entry_hdr
;
2542 loop_count
= cache_hdr
->op_count
;
2543 r_addr
= cache_hdr
->read_addr
;
2544 c_addr
= cache_hdr
->control_addr
;
2545 c_value_w
= cache_hdr
->cache_ctrl
.write_value
;
2547 t_r_addr
= cache_hdr
->tag_reg_addr
;
2548 t_value
= cache_hdr
->addr_ctrl
.init_tag_value
;
2549 r_cnt
= cache_hdr
->read_ctrl
.read_addr_cnt
;
2551 for (i
= 0; i
< loop_count
; i
++) {
2552 qla8044_wr_reg_indirect(vha
, t_r_addr
, t_value
);
2553 qla8044_wr_reg_indirect(vha
, c_addr
, c_value_w
);
2555 for (k
= 0; k
< r_cnt
; k
++) {
2556 qla8044_rd_reg_indirect(vha
, addr
, &r_value
);
2557 *data_ptr
++ = r_value
;
2558 addr
+= cache_hdr
->read_ctrl
.read_addr_stride
;
2560 t_value
+= cache_hdr
->addr_ctrl
.tag_value_stride
;
2566 qla8044_minidump_process_rdocm(struct scsi_qla_host
*vha
,
2567 struct qla8044_minidump_entry_hdr
*entry_hdr
, uint32_t **d_ptr
)
2569 uint32_t r_addr
, r_stride
, loop_cnt
, i
, r_value
;
2570 struct qla8044_minidump_entry_rdocm
*ocm_hdr
;
2571 uint32_t *data_ptr
= *d_ptr
;
2572 struct qla_hw_data
*ha
= vha
->hw
;
2574 ql_dbg(ql_dbg_p3p
, vha
, 0xb0f9, "Entering fn: %s\n", __func__
);
2576 ocm_hdr
= (struct qla8044_minidump_entry_rdocm
*)entry_hdr
;
2577 r_addr
= ocm_hdr
->read_addr
;
2578 r_stride
= ocm_hdr
->read_addr_stride
;
2579 loop_cnt
= ocm_hdr
->op_count
;
2581 ql_dbg(ql_dbg_p3p
, vha
, 0xb0fa,
2582 "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n",
2583 __func__
, r_addr
, r_stride
, loop_cnt
);
2585 for (i
= 0; i
< loop_cnt
; i
++) {
2586 r_value
= readl((void __iomem
*)(r_addr
+ ha
->nx_pcibase
));
2587 *data_ptr
++ = r_value
;
2590 ql_dbg(ql_dbg_p3p
, vha
, 0xb0fb, "Leaving fn: %s datacount: 0x%lx\n",
2591 __func__
, (long unsigned int) (loop_cnt
* sizeof(uint32_t)));
2597 qla8044_minidump_process_rdmux(struct scsi_qla_host
*vha
,
2598 struct qla8044_minidump_entry_hdr
*entry_hdr
,
2601 uint32_t r_addr
, s_stride
, s_addr
, s_value
, loop_cnt
, i
, r_value
;
2602 struct qla8044_minidump_entry_mux
*mux_hdr
;
2603 uint32_t *data_ptr
= *d_ptr
;
2605 ql_dbg(ql_dbg_p3p
, vha
, 0xb0fc, "Entering fn: %s\n", __func__
);
2607 mux_hdr
= (struct qla8044_minidump_entry_mux
*)entry_hdr
;
2608 r_addr
= mux_hdr
->read_addr
;
2609 s_addr
= mux_hdr
->select_addr
;
2610 s_stride
= mux_hdr
->select_value_stride
;
2611 s_value
= mux_hdr
->select_value
;
2612 loop_cnt
= mux_hdr
->op_count
;
2614 for (i
= 0; i
< loop_cnt
; i
++) {
2615 qla8044_wr_reg_indirect(vha
, s_addr
, s_value
);
2616 qla8044_rd_reg_indirect(vha
, r_addr
, &r_value
);
2617 *data_ptr
++ = s_value
;
2618 *data_ptr
++ = r_value
;
2619 s_value
+= s_stride
;
2625 qla8044_minidump_process_queue(struct scsi_qla_host
*vha
,
2626 struct qla8044_minidump_entry_hdr
*entry_hdr
,
2629 uint32_t s_addr
, r_addr
;
2630 uint32_t r_stride
, r_value
, r_cnt
, qid
= 0;
2631 uint32_t i
, k
, loop_cnt
;
2632 struct qla8044_minidump_entry_queue
*q_hdr
;
2633 uint32_t *data_ptr
= *d_ptr
;
2635 ql_dbg(ql_dbg_p3p
, vha
, 0xb0fd, "Entering fn: %s\n", __func__
);
2636 q_hdr
= (struct qla8044_minidump_entry_queue
*)entry_hdr
;
2637 s_addr
= q_hdr
->select_addr
;
2638 r_cnt
= q_hdr
->rd_strd
.read_addr_cnt
;
2639 r_stride
= q_hdr
->rd_strd
.read_addr_stride
;
2640 loop_cnt
= q_hdr
->op_count
;
2642 for (i
= 0; i
< loop_cnt
; i
++) {
2643 qla8044_wr_reg_indirect(vha
, s_addr
, qid
);
2644 r_addr
= q_hdr
->read_addr
;
2645 for (k
= 0; k
< r_cnt
; k
++) {
2646 qla8044_rd_reg_indirect(vha
, r_addr
, &r_value
);
2647 *data_ptr
++ = r_value
;
2650 qid
+= q_hdr
->q_strd
.queue_id_stride
;
2655 /* ISP83xx functions to process new minidump entries... */
2657 qla8044_minidump_process_pollrd(struct scsi_qla_host
*vha
,
2658 struct qla8044_minidump_entry_hdr
*entry_hdr
,
2661 uint32_t r_addr
, s_addr
, s_value
, r_value
, poll_wait
, poll_mask
;
2662 uint16_t s_stride
, i
;
2663 struct qla8044_minidump_entry_pollrd
*pollrd_hdr
;
2664 uint32_t *data_ptr
= *d_ptr
;
2666 pollrd_hdr
= (struct qla8044_minidump_entry_pollrd
*) entry_hdr
;
2667 s_addr
= pollrd_hdr
->select_addr
;
2668 r_addr
= pollrd_hdr
->read_addr
;
2669 s_value
= pollrd_hdr
->select_value
;
2670 s_stride
= pollrd_hdr
->select_value_stride
;
2672 poll_wait
= pollrd_hdr
->poll_wait
;
2673 poll_mask
= pollrd_hdr
->poll_mask
;
2675 for (i
= 0; i
< pollrd_hdr
->op_count
; i
++) {
2676 qla8044_wr_reg_indirect(vha
, s_addr
, s_value
);
2677 poll_wait
= pollrd_hdr
->poll_wait
;
2679 qla8044_rd_reg_indirect(vha
, s_addr
, &r_value
);
2680 if ((r_value
& poll_mask
) != 0) {
2683 usleep_range(1000, 1100);
2684 if (--poll_wait
== 0) {
2685 ql_log(ql_log_fatal
, vha
, 0xb0fe,
2686 "%s: TIMEOUT\n", __func__
);
2691 qla8044_rd_reg_indirect(vha
, r_addr
, &r_value
);
2692 *data_ptr
++ = s_value
;
2693 *data_ptr
++ = r_value
;
2695 s_value
+= s_stride
;
2701 return QLA_FUNCTION_FAILED
;
2705 qla8044_minidump_process_rdmux2(struct scsi_qla_host
*vha
,
2706 struct qla8044_minidump_entry_hdr
*entry_hdr
, uint32_t **d_ptr
)
2708 uint32_t sel_val1
, sel_val2
, t_sel_val
, data
, i
;
2709 uint32_t sel_addr1
, sel_addr2
, sel_val_mask
, read_addr
;
2710 struct qla8044_minidump_entry_rdmux2
*rdmux2_hdr
;
2711 uint32_t *data_ptr
= *d_ptr
;
2713 rdmux2_hdr
= (struct qla8044_minidump_entry_rdmux2
*) entry_hdr
;
2714 sel_val1
= rdmux2_hdr
->select_value_1
;
2715 sel_val2
= rdmux2_hdr
->select_value_2
;
2716 sel_addr1
= rdmux2_hdr
->select_addr_1
;
2717 sel_addr2
= rdmux2_hdr
->select_addr_2
;
2718 sel_val_mask
= rdmux2_hdr
->select_value_mask
;
2719 read_addr
= rdmux2_hdr
->read_addr
;
2721 for (i
= 0; i
< rdmux2_hdr
->op_count
; i
++) {
2722 qla8044_wr_reg_indirect(vha
, sel_addr1
, sel_val1
);
2723 t_sel_val
= sel_val1
& sel_val_mask
;
2724 *data_ptr
++ = t_sel_val
;
2726 qla8044_wr_reg_indirect(vha
, sel_addr2
, t_sel_val
);
2727 qla8044_rd_reg_indirect(vha
, read_addr
, &data
);
2731 qla8044_wr_reg_indirect(vha
, sel_addr1
, sel_val2
);
2732 t_sel_val
= sel_val2
& sel_val_mask
;
2733 *data_ptr
++ = t_sel_val
;
2735 qla8044_wr_reg_indirect(vha
, sel_addr2
, t_sel_val
);
2736 qla8044_rd_reg_indirect(vha
, read_addr
, &data
);
2740 sel_val1
+= rdmux2_hdr
->select_value_stride
;
2741 sel_val2
+= rdmux2_hdr
->select_value_stride
;
2748 qla8044_minidump_process_pollrdmwr(struct scsi_qla_host
*vha
,
2749 struct qla8044_minidump_entry_hdr
*entry_hdr
,
2752 uint32_t poll_wait
, poll_mask
, r_value
, data
;
2753 uint32_t addr_1
, addr_2
, value_1
, value_2
;
2754 struct qla8044_minidump_entry_pollrdmwr
*poll_hdr
;
2755 uint32_t *data_ptr
= *d_ptr
;
2757 poll_hdr
= (struct qla8044_minidump_entry_pollrdmwr
*) entry_hdr
;
2758 addr_1
= poll_hdr
->addr_1
;
2759 addr_2
= poll_hdr
->addr_2
;
2760 value_1
= poll_hdr
->value_1
;
2761 value_2
= poll_hdr
->value_2
;
2762 poll_mask
= poll_hdr
->poll_mask
;
2764 qla8044_wr_reg_indirect(vha
, addr_1
, value_1
);
2766 poll_wait
= poll_hdr
->poll_wait
;
2768 qla8044_rd_reg_indirect(vha
, addr_1
, &r_value
);
2770 if ((r_value
& poll_mask
) != 0) {
2773 usleep_range(1000, 1100);
2774 if (--poll_wait
== 0) {
2775 ql_log(ql_log_fatal
, vha
, 0xb0ff,
2776 "%s: TIMEOUT\n", __func__
);
2782 qla8044_rd_reg_indirect(vha
, addr_2
, &data
);
2783 data
&= poll_hdr
->modify_mask
;
2784 qla8044_wr_reg_indirect(vha
, addr_2
, data
);
2785 qla8044_wr_reg_indirect(vha
, addr_1
, value_2
);
2787 poll_wait
= poll_hdr
->poll_wait
;
2789 qla8044_rd_reg_indirect(vha
, addr_1
, &r_value
);
2791 if ((r_value
& poll_mask
) != 0) {
2794 usleep_range(1000, 1100);
2795 if (--poll_wait
== 0) {
2796 ql_log(ql_log_fatal
, vha
, 0xb100,
2797 "%s: TIMEOUT2\n", __func__
);
2803 *data_ptr
++ = addr_2
;
2811 return QLA_FUNCTION_FAILED
;
2814 #define ISP8044_PEX_DMA_ENGINE_INDEX 8
2815 #define ISP8044_PEX_DMA_BASE_ADDRESS 0x77320000
2816 #define ISP8044_PEX_DMA_NUM_OFFSET 0x10000
2817 #define ISP8044_PEX_DMA_CMD_ADDR_LOW 0x0
2818 #define ISP8044_PEX_DMA_CMD_ADDR_HIGH 0x04
2819 #define ISP8044_PEX_DMA_CMD_STS_AND_CNTRL 0x08
2821 #define ISP8044_PEX_DMA_READ_SIZE (16 * 1024)
2822 #define ISP8044_PEX_DMA_MAX_WAIT (100 * 100) /* Max wait of 100 msecs */
2825 qla8044_check_dma_engine_state(struct scsi_qla_host
*vha
)
2827 struct qla_hw_data
*ha
= vha
->hw
;
2828 int rval
= QLA_SUCCESS
;
2829 uint32_t dma_eng_num
= 0, cmd_sts_and_cntrl
= 0;
2830 uint64_t dma_base_addr
= 0;
2831 struct qla8044_minidump_template_hdr
*tmplt_hdr
= NULL
;
2833 tmplt_hdr
= ha
->md_tmplt_hdr
;
2835 tmplt_hdr
->saved_state_array
[ISP8044_PEX_DMA_ENGINE_INDEX
];
2836 dma_base_addr
= ISP8044_PEX_DMA_BASE_ADDRESS
+
2837 (dma_eng_num
* ISP8044_PEX_DMA_NUM_OFFSET
);
2839 /* Read the pex-dma's command-status-and-control register. */
2840 rval
= qla8044_rd_reg_indirect(vha
,
2841 (dma_base_addr
+ ISP8044_PEX_DMA_CMD_STS_AND_CNTRL
),
2842 &cmd_sts_and_cntrl
);
2844 return QLA_FUNCTION_FAILED
;
2846 /* Check if requested pex-dma engine is available. */
2847 if (cmd_sts_and_cntrl
& BIT_31
)
2850 return QLA_FUNCTION_FAILED
;
2854 qla8044_start_pex_dma(struct scsi_qla_host
*vha
,
2855 struct qla8044_minidump_entry_rdmem_pex_dma
*m_hdr
)
2857 struct qla_hw_data
*ha
= vha
->hw
;
2858 int rval
= QLA_SUCCESS
, wait
= 0;
2859 uint32_t dma_eng_num
= 0, cmd_sts_and_cntrl
= 0;
2860 uint64_t dma_base_addr
= 0;
2861 struct qla8044_minidump_template_hdr
*tmplt_hdr
= NULL
;
2863 tmplt_hdr
= ha
->md_tmplt_hdr
;
2865 tmplt_hdr
->saved_state_array
[ISP8044_PEX_DMA_ENGINE_INDEX
];
2866 dma_base_addr
= ISP8044_PEX_DMA_BASE_ADDRESS
+
2867 (dma_eng_num
* ISP8044_PEX_DMA_NUM_OFFSET
);
2869 rval
= qla8044_wr_reg_indirect(vha
,
2870 dma_base_addr
+ ISP8044_PEX_DMA_CMD_ADDR_LOW
,
2871 m_hdr
->desc_card_addr
);
2875 rval
= qla8044_wr_reg_indirect(vha
,
2876 dma_base_addr
+ ISP8044_PEX_DMA_CMD_ADDR_HIGH
, 0);
2880 rval
= qla8044_wr_reg_indirect(vha
,
2881 dma_base_addr
+ ISP8044_PEX_DMA_CMD_STS_AND_CNTRL
,
2882 m_hdr
->start_dma_cmd
);
2886 /* Wait for dma operation to complete. */
2887 for (wait
= 0; wait
< ISP8044_PEX_DMA_MAX_WAIT
; wait
++) {
2888 rval
= qla8044_rd_reg_indirect(vha
,
2889 (dma_base_addr
+ ISP8044_PEX_DMA_CMD_STS_AND_CNTRL
),
2890 &cmd_sts_and_cntrl
);
2894 if ((cmd_sts_and_cntrl
& BIT_1
) == 0)
2900 /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */
2901 if (wait
>= ISP8044_PEX_DMA_MAX_WAIT
) {
2902 rval
= QLA_FUNCTION_FAILED
;
2911 qla8044_minidump_pex_dma_read(struct scsi_qla_host
*vha
,
2912 struct qla8044_minidump_entry_hdr
*entry_hdr
, uint32_t **d_ptr
)
2914 struct qla_hw_data
*ha
= vha
->hw
;
2915 int rval
= QLA_SUCCESS
;
2916 struct qla8044_minidump_entry_rdmem_pex_dma
*m_hdr
= NULL
;
2917 uint32_t chunk_size
, read_size
;
2918 uint8_t *data_ptr
= (uint8_t *)*d_ptr
;
2919 void *rdmem_buffer
= NULL
;
2920 dma_addr_t rdmem_dma
;
2921 struct qla8044_pex_dma_descriptor dma_desc
;
2923 rval
= qla8044_check_dma_engine_state(vha
);
2924 if (rval
!= QLA_SUCCESS
) {
2925 ql_dbg(ql_dbg_p3p
, vha
, 0xb147,
2926 "DMA engine not available. Fallback to rdmem-read.\n");
2927 return QLA_FUNCTION_FAILED
;
2930 m_hdr
= (void *)entry_hdr
;
2932 rdmem_buffer
= dma_alloc_coherent(&ha
->pdev
->dev
,
2933 ISP8044_PEX_DMA_READ_SIZE
, &rdmem_dma
, GFP_KERNEL
);
2934 if (!rdmem_buffer
) {
2935 ql_dbg(ql_dbg_p3p
, vha
, 0xb148,
2936 "Unable to allocate rdmem dma buffer\n");
2937 return QLA_FUNCTION_FAILED
;
2940 /* Prepare pex-dma descriptor to be written to MS memory. */
2941 /* dma-desc-cmd layout:
2942 * 0-3: dma-desc-cmd 0-3
2943 * 4-7: pcid function number
2944 * 8-15: dma-desc-cmd 8-15
2945 * dma_bus_addr: dma buffer address
2946 * cmd.read_data_size: amount of data-chunk to be read.
2948 dma_desc
.cmd
.dma_desc_cmd
= (m_hdr
->dma_desc_cmd
& 0xff0f);
2949 dma_desc
.cmd
.dma_desc_cmd
|=
2950 ((PCI_FUNC(ha
->pdev
->devfn
) & 0xf) << 0x4);
2952 dma_desc
.dma_bus_addr
= rdmem_dma
;
2953 dma_desc
.cmd
.read_data_size
= chunk_size
= ISP8044_PEX_DMA_READ_SIZE
;
2957 * Perform rdmem operation using pex-dma.
2958 * Prepare dma in chunks of ISP8044_PEX_DMA_READ_SIZE.
2960 while (read_size
< m_hdr
->read_data_size
) {
2961 if (m_hdr
->read_data_size
- read_size
<
2962 ISP8044_PEX_DMA_READ_SIZE
) {
2963 chunk_size
= (m_hdr
->read_data_size
- read_size
);
2964 dma_desc
.cmd
.read_data_size
= chunk_size
;
2967 dma_desc
.src_addr
= m_hdr
->read_addr
+ read_size
;
2969 /* Prepare: Write pex-dma descriptor to MS memory. */
2970 rval
= qla8044_ms_mem_write_128b(vha
,
2971 m_hdr
->desc_card_addr
, (void *)&dma_desc
,
2972 (sizeof(struct qla8044_pex_dma_descriptor
)/16));
2974 ql_log(ql_log_warn
, vha
, 0xb14a,
2975 "%s: Error writing rdmem-dma-init to MS !!!\n",
2979 ql_dbg(ql_dbg_p3p
, vha
, 0xb14b,
2980 "%s: Dma-descriptor: Instruct for rdmem dma "
2981 "(chunk_size 0x%x).\n", __func__
, chunk_size
);
2983 /* Execute: Start pex-dma operation. */
2984 rval
= qla8044_start_pex_dma(vha
, m_hdr
);
2988 memcpy(data_ptr
, rdmem_buffer
, chunk_size
);
2989 data_ptr
+= chunk_size
;
2990 read_size
+= chunk_size
;
2993 *d_ptr
= (void *)data_ptr
;
2997 dma_free_coherent(&ha
->pdev
->dev
, ISP8044_PEX_DMA_READ_SIZE
,
2998 rdmem_buffer
, rdmem_dma
);
3004 qla8044_minidump_process_rddfe(struct scsi_qla_host
*vha
,
3005 struct qla8044_minidump_entry_hdr
*entry_hdr
, uint32_t **d_ptr
)
3008 uint32_t addr1
, addr2
, value
, data
, temp
, wrVal
;
3009 uint8_t stride
, stride2
;
3011 uint32_t poll
, mask
, modify_mask
;
3012 uint32_t wait_count
= 0;
3014 uint32_t *data_ptr
= *d_ptr
;
3016 struct qla8044_minidump_entry_rddfe
*rddfe
;
3017 rddfe
= (struct qla8044_minidump_entry_rddfe
*) entry_hdr
;
3019 addr1
= rddfe
->addr_1
;
3020 value
= rddfe
->value
;
3021 stride
= rddfe
->stride
;
3022 stride2
= rddfe
->stride2
;
3023 count
= rddfe
->count
;
3027 modify_mask
= rddfe
->modify_mask
;
3029 addr2
= addr1
+ stride
;
3031 for (loop_cnt
= 0x0; loop_cnt
< count
; loop_cnt
++) {
3032 qla8044_wr_reg_indirect(vha
, addr1
, (0x40000000 | value
));
3035 while (wait_count
< poll
) {
3036 qla8044_rd_reg_indirect(vha
, addr1
, &temp
);
3037 if ((temp
& mask
) != 0)
3042 if (wait_count
== poll
) {
3043 ql_log(ql_log_warn
, vha
, 0xb153,
3044 "%s: TIMEOUT\n", __func__
);
3047 qla8044_rd_reg_indirect(vha
, addr2
, &temp
);
3048 temp
= temp
& modify_mask
;
3049 temp
= (temp
| ((loop_cnt
<< 16) | loop_cnt
));
3050 wrVal
= ((temp
<< 16) | temp
);
3052 qla8044_wr_reg_indirect(vha
, addr2
, wrVal
);
3053 qla8044_wr_reg_indirect(vha
, addr1
, value
);
3056 while (wait_count
< poll
) {
3057 qla8044_rd_reg_indirect(vha
, addr1
, &temp
);
3058 if ((temp
& mask
) != 0)
3062 if (wait_count
== poll
) {
3063 ql_log(ql_log_warn
, vha
, 0xb154,
3064 "%s: TIMEOUT\n", __func__
);
3068 qla8044_wr_reg_indirect(vha
, addr1
,
3069 ((0x40000000 | value
) + stride2
));
3071 while (wait_count
< poll
) {
3072 qla8044_rd_reg_indirect(vha
, addr1
, &temp
);
3073 if ((temp
& mask
) != 0)
3078 if (wait_count
== poll
) {
3079 ql_log(ql_log_warn
, vha
, 0xb155,
3080 "%s: TIMEOUT\n", __func__
);
3084 qla8044_rd_reg_indirect(vha
, addr2
, &data
);
3086 *data_ptr
++ = wrVal
;
3101 qla8044_minidump_process_rdmdio(struct scsi_qla_host
*vha
,
3102 struct qla8044_minidump_entry_hdr
*entry_hdr
, uint32_t **d_ptr
)
3105 uint32_t addr1
, addr2
, value1
, value2
, data
, selVal
;
3106 uint8_t stride1
, stride2
;
3107 uint32_t addr3
, addr4
, addr5
, addr6
, addr7
;
3108 uint16_t count
, loop_cnt
;
3110 uint32_t *data_ptr
= *d_ptr
;
3112 struct qla8044_minidump_entry_rdmdio
*rdmdio
;
3114 rdmdio
= (struct qla8044_minidump_entry_rdmdio
*) entry_hdr
;
3116 addr1
= rdmdio
->addr_1
;
3117 addr2
= rdmdio
->addr_2
;
3118 value1
= rdmdio
->value_1
;
3119 stride1
= rdmdio
->stride_1
;
3120 stride2
= rdmdio
->stride_2
;
3121 count
= rdmdio
->count
;
3123 mask
= rdmdio
->mask
;
3124 value2
= rdmdio
->value_2
;
3126 addr3
= addr1
+ stride1
;
3128 for (loop_cnt
= 0; loop_cnt
< count
; loop_cnt
++) {
3129 ret
= qla8044_poll_wait_ipmdio_bus_idle(vha
, addr1
, addr2
,
3134 addr4
= addr2
- stride1
;
3135 ret
= qla8044_ipmdio_wr_reg(vha
, addr1
, addr3
, mask
, addr4
,
3140 addr5
= addr2
- (2 * stride1
);
3141 ret
= qla8044_ipmdio_wr_reg(vha
, addr1
, addr3
, mask
, addr5
,
3146 addr6
= addr2
- (3 * stride1
);
3147 ret
= qla8044_ipmdio_wr_reg(vha
, addr1
, addr3
, mask
,
3152 ret
= qla8044_poll_wait_ipmdio_bus_idle(vha
, addr1
, addr2
,
3157 addr7
= addr2
- (4 * stride1
);
3158 data
= qla8044_ipmdio_rd_reg(vha
, addr1
, addr3
, mask
, addr7
);
3162 selVal
= (value2
<< 18) | (value1
<< 2) | 2;
3164 stride2
= rdmdio
->stride_2
;
3165 *data_ptr
++ = selVal
;
3168 value1
= value1
+ stride2
;
3178 static uint32_t qla8044_minidump_process_pollwr(struct scsi_qla_host
*vha
,
3179 struct qla8044_minidump_entry_hdr
*entry_hdr
, uint32_t **d_ptr
)
3181 uint32_t addr1
, addr2
, value1
, value2
, poll
, r_value
;
3182 uint32_t wait_count
= 0;
3183 struct qla8044_minidump_entry_pollwr
*pollwr_hdr
;
3185 pollwr_hdr
= (struct qla8044_minidump_entry_pollwr
*)entry_hdr
;
3186 addr1
= pollwr_hdr
->addr_1
;
3187 addr2
= pollwr_hdr
->addr_2
;
3188 value1
= pollwr_hdr
->value_1
;
3189 value2
= pollwr_hdr
->value_2
;
3191 poll
= pollwr_hdr
->poll
;
3193 while (wait_count
< poll
) {
3194 qla8044_rd_reg_indirect(vha
, addr1
, &r_value
);
3196 if ((r_value
& poll
) != 0)
3201 if (wait_count
== poll
) {
3202 ql_log(ql_log_warn
, vha
, 0xb156, "%s: TIMEOUT\n", __func__
);
3206 qla8044_wr_reg_indirect(vha
, addr2
, value2
);
3207 qla8044_wr_reg_indirect(vha
, addr1
, value1
);
3210 while (wait_count
< poll
) {
3211 qla8044_rd_reg_indirect(vha
, addr1
, &r_value
);
3213 if ((r_value
& poll
) != 0)
3226 * qla8044_collect_md_data - Retrieve firmware minidump data.
3227 * @ha: pointer to adapter structure
3230 qla8044_collect_md_data(struct scsi_qla_host
*vha
)
3232 int num_entry_hdr
= 0;
3233 struct qla8044_minidump_entry_hdr
*entry_hdr
;
3234 struct qla8044_minidump_template_hdr
*tmplt_hdr
;
3236 uint32_t data_collected
= 0, f_capture_mask
;
3237 int i
, rval
= QLA_FUNCTION_FAILED
;
3239 uint32_t timestamp
, idc_control
;
3240 struct qla_hw_data
*ha
= vha
->hw
;
3243 ql_log(ql_log_info
, vha
, 0xb101,
3244 "%s(%ld) No buffer to dump\n",
3245 __func__
, vha
->host_no
);
3249 if (ha
->fw_dumped
) {
3250 ql_log(ql_log_warn
, vha
, 0xb10d,
3251 "Firmware has been previously dumped (%p) "
3252 "-- ignoring request.\n", ha
->fw_dump
);
3258 if (!ha
->md_tmplt_hdr
|| !ha
->md_dump
) {
3259 ql_log(ql_log_warn
, vha
, 0xb10e,
3260 "Memory not allocated for minidump capture\n");
3264 qla8044_idc_lock(ha
);
3265 idc_control
= qla8044_rd_reg(ha
, QLA8044_IDC_DRV_CTRL
);
3266 if (idc_control
& GRACEFUL_RESET_BIT1
) {
3267 ql_log(ql_log_warn
, vha
, 0xb112,
3268 "Forced reset from application, "
3269 "ignore minidump capture\n");
3270 qla8044_wr_reg(ha
, QLA8044_IDC_DRV_CTRL
,
3271 (idc_control
& ~GRACEFUL_RESET_BIT1
));
3272 qla8044_idc_unlock(ha
);
3276 qla8044_idc_unlock(ha
);
3278 if (qla82xx_validate_template_chksum(vha
)) {
3279 ql_log(ql_log_info
, vha
, 0xb109,
3280 "Template checksum validation error\n");
3284 tmplt_hdr
= (struct qla8044_minidump_template_hdr
*)
3286 data_ptr
= (uint32_t *)((uint8_t *)ha
->md_dump
);
3287 num_entry_hdr
= tmplt_hdr
->num_of_entries
;
3289 ql_dbg(ql_dbg_p3p
, vha
, 0xb11a,
3290 "Capture Mask obtained: 0x%x\n", tmplt_hdr
->capture_debug_level
);
3292 f_capture_mask
= tmplt_hdr
->capture_debug_level
& 0xFF;
3294 /* Validate whether required debug level is set */
3295 if ((f_capture_mask
& 0x3) != 0x3) {
3296 ql_log(ql_log_warn
, vha
, 0xb10f,
3297 "Minimum required capture mask[0x%x] level not set\n",
3301 tmplt_hdr
->driver_capture_mask
= ql2xmdcapmask
;
3302 ql_log(ql_log_info
, vha
, 0xb102,
3303 "[%s]: starting data ptr: %p\n",
3304 __func__
, data_ptr
);
3305 ql_log(ql_log_info
, vha
, 0xb10b,
3306 "[%s]: no of entry headers in Template: 0x%x\n",
3307 __func__
, num_entry_hdr
);
3308 ql_log(ql_log_info
, vha
, 0xb10c,
3309 "[%s]: Total_data_size 0x%x, %d obtained\n",
3310 __func__
, ha
->md_dump_size
, ha
->md_dump_size
);
3312 /* Update current timestamp before taking dump */
3313 now
= get_jiffies_64();
3314 timestamp
= (u32
)(jiffies_to_msecs(now
) / 1000);
3315 tmplt_hdr
->driver_timestamp
= timestamp
;
3317 entry_hdr
= (struct qla8044_minidump_entry_hdr
*)
3318 (((uint8_t *)ha
->md_tmplt_hdr
) + tmplt_hdr
->first_entry_offset
);
3319 tmplt_hdr
->saved_state_array
[QLA8044_SS_OCM_WNDREG_INDEX
] =
3320 tmplt_hdr
->ocm_window_reg
[ha
->portnum
];
3322 /* Walk through the entry headers - validate/perform required action */
3323 for (i
= 0; i
< num_entry_hdr
; i
++) {
3324 if (data_collected
> ha
->md_dump_size
) {
3325 ql_log(ql_log_info
, vha
, 0xb103,
3326 "Data collected: [0x%x], "
3327 "Total Dump size: [0x%x]\n",
3328 data_collected
, ha
->md_dump_size
);
3332 if (!(entry_hdr
->d_ctrl
.entry_capture_mask
&
3334 entry_hdr
->d_ctrl
.driver_flags
|=
3335 QLA82XX_DBG_SKIPPED_FLAG
;
3336 goto skip_nxt_entry
;
3339 ql_dbg(ql_dbg_p3p
, vha
, 0xb104,
3340 "Data collected: [0x%x], Dump size left:[0x%x]\n",
3342 (ha
->md_dump_size
- data_collected
));
3344 /* Decode the entry type and take required action to capture
3347 switch (entry_hdr
->entry_type
) {
3349 qla8044_mark_entry_skipped(vha
, entry_hdr
, i
);
3352 rval
= qla8044_minidump_process_control(vha
,
3354 if (rval
!= QLA_SUCCESS
) {
3355 qla8044_mark_entry_skipped(vha
, entry_hdr
, i
);
3360 qla8044_minidump_process_rdcrb(vha
,
3361 entry_hdr
, &data_ptr
);
3364 rval
= qla8044_minidump_pex_dma_read(vha
,
3365 entry_hdr
, &data_ptr
);
3366 if (rval
!= QLA_SUCCESS
) {
3367 rval
= qla8044_minidump_process_rdmem(vha
,
3368 entry_hdr
, &data_ptr
);
3369 if (rval
!= QLA_SUCCESS
) {
3370 qla8044_mark_entry_skipped(vha
,
3378 rval
= qla8044_minidump_process_rdrom(vha
,
3379 entry_hdr
, &data_ptr
);
3380 if (rval
!= QLA_SUCCESS
) {
3381 qla8044_mark_entry_skipped(vha
,
3389 rval
= qla8044_minidump_process_l2tag(vha
,
3390 entry_hdr
, &data_ptr
);
3391 if (rval
!= QLA_SUCCESS
) {
3392 qla8044_mark_entry_skipped(vha
, entry_hdr
, i
);
3400 qla8044_minidump_process_l1cache(vha
,
3401 entry_hdr
, &data_ptr
);
3404 qla8044_minidump_process_rdocm(vha
,
3405 entry_hdr
, &data_ptr
);
3408 qla8044_minidump_process_rdmux(vha
,
3409 entry_hdr
, &data_ptr
);
3412 qla8044_minidump_process_queue(vha
,
3413 entry_hdr
, &data_ptr
);
3415 case QLA8044_POLLRD
:
3416 rval
= qla8044_minidump_process_pollrd(vha
,
3417 entry_hdr
, &data_ptr
);
3418 if (rval
!= QLA_SUCCESS
)
3419 qla8044_mark_entry_skipped(vha
, entry_hdr
, i
);
3421 case QLA8044_RDMUX2
:
3422 qla8044_minidump_process_rdmux2(vha
,
3423 entry_hdr
, &data_ptr
);
3425 case QLA8044_POLLRDMWR
:
3426 rval
= qla8044_minidump_process_pollrdmwr(vha
,
3427 entry_hdr
, &data_ptr
);
3428 if (rval
!= QLA_SUCCESS
)
3429 qla8044_mark_entry_skipped(vha
, entry_hdr
, i
);
3432 rval
= qla8044_minidump_process_rddfe(vha
, entry_hdr
,
3434 if (rval
!= QLA_SUCCESS
)
3435 qla8044_mark_entry_skipped(vha
, entry_hdr
, i
);
3437 case QLA8044_RDMDIO
:
3438 rval
= qla8044_minidump_process_rdmdio(vha
, entry_hdr
,
3440 if (rval
!= QLA_SUCCESS
)
3441 qla8044_mark_entry_skipped(vha
, entry_hdr
, i
);
3443 case QLA8044_POLLWR
:
3444 rval
= qla8044_minidump_process_pollwr(vha
, entry_hdr
,
3446 if (rval
!= QLA_SUCCESS
)
3447 qla8044_mark_entry_skipped(vha
, entry_hdr
, i
);
3451 qla8044_mark_entry_skipped(vha
, entry_hdr
, i
);
3455 data_collected
= (uint8_t *)data_ptr
-
3456 (uint8_t *)((uint8_t *)ha
->md_dump
);
3459 * next entry in the template
3461 entry_hdr
= (struct qla8044_minidump_entry_hdr
*)
3462 (((uint8_t *)entry_hdr
) + entry_hdr
->entry_size
);
3465 if (data_collected
!= ha
->md_dump_size
) {
3466 ql_log(ql_log_info
, vha
, 0xb105,
3467 "Dump data mismatch: Data collected: "
3468 "[0x%x], total_data_size:[0x%x]\n",
3469 data_collected
, ha
->md_dump_size
);
3470 rval
= QLA_FUNCTION_FAILED
;
3474 ql_log(ql_log_info
, vha
, 0xb110,
3475 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
3476 vha
->host_no
, ha
->md_tmplt_hdr
, vha
->host_no
, ha
->md_dump
);
3478 qla2x00_post_uevent_work(vha
, QLA_UEVENT_CODE_FW_DUMP
);
3481 ql_log(ql_log_info
, vha
, 0xb106,
3482 "Leaving fn: %s Last entry: 0x%x\n",
3489 qla8044_get_minidump(struct scsi_qla_host
*vha
)
3491 struct qla_hw_data
*ha
= vha
->hw
;
3493 if (!qla8044_collect_md_data(vha
)) {
3495 ha
->prev_minidump_failed
= 0;
3497 ql_log(ql_log_fatal
, vha
, 0xb0db,
3498 "%s: Unable to collect minidump\n",
3500 ha
->prev_minidump_failed
= 1;
3505 qla8044_poll_flash_status_reg(struct scsi_qla_host
*vha
)
3507 uint32_t flash_status
;
3508 int retries
= QLA8044_FLASH_READ_RETRY_COUNT
;
3509 int ret_val
= QLA_SUCCESS
;
3512 ret_val
= qla8044_rd_reg_indirect(vha
, QLA8044_FLASH_STATUS
,
3515 ql_log(ql_log_warn
, vha
, 0xb13c,
3516 "%s: Failed to read FLASH_STATUS reg.\n",
3520 if ((flash_status
& QLA8044_FLASH_STATUS_READY
) ==
3521 QLA8044_FLASH_STATUS_READY
)
3523 msleep(QLA8044_FLASH_STATUS_REG_POLL_DELAY
);
3527 ret_val
= QLA_FUNCTION_FAILED
;
3533 qla8044_write_flash_status_reg(struct scsi_qla_host
*vha
,
3536 int ret_val
= QLA_SUCCESS
;
3539 cmd
= vha
->hw
->fdt_wrt_sts_reg_cmd
;
3541 ret_val
= qla8044_wr_reg_indirect(vha
, QLA8044_FLASH_ADDR
,
3542 QLA8044_FLASH_STATUS_WRITE_DEF_SIG
| cmd
);
3544 ql_log(ql_log_warn
, vha
, 0xb125,
3545 "%s: Failed to write to FLASH_ADDR.\n", __func__
);
3549 ret_val
= qla8044_wr_reg_indirect(vha
, QLA8044_FLASH_WRDATA
, data
);
3551 ql_log(ql_log_warn
, vha
, 0xb126,
3552 "%s: Failed to write to FLASH_WRDATA.\n", __func__
);
3556 ret_val
= qla8044_wr_reg_indirect(vha
, QLA8044_FLASH_CONTROL
,
3557 QLA8044_FLASH_SECOND_ERASE_MS_VAL
);
3559 ql_log(ql_log_warn
, vha
, 0xb127,
3560 "%s: Failed to write to FLASH_CONTROL.\n", __func__
);
3564 ret_val
= qla8044_poll_flash_status_reg(vha
);
3566 ql_log(ql_log_warn
, vha
, 0xb128,
3567 "%s: Error polling flash status reg.\n", __func__
);
3574 * This function assumes that the flash lock is held.
3577 qla8044_unprotect_flash(scsi_qla_host_t
*vha
)
3580 struct qla_hw_data
*ha
= vha
->hw
;
3582 ret_val
= qla8044_write_flash_status_reg(vha
, ha
->fdt_wrt_enable
);
3584 ql_log(ql_log_warn
, vha
, 0xb139,
3585 "%s: Write flash status failed.\n", __func__
);
3591 * This function assumes that the flash lock is held.
3594 qla8044_protect_flash(scsi_qla_host_t
*vha
)
3597 struct qla_hw_data
*ha
= vha
->hw
;
3599 ret_val
= qla8044_write_flash_status_reg(vha
, ha
->fdt_wrt_disable
);
3601 ql_log(ql_log_warn
, vha
, 0xb13b,
3602 "%s: Write flash status failed.\n", __func__
);
3609 qla8044_erase_flash_sector(struct scsi_qla_host
*vha
,
3610 uint32_t sector_start_addr
)
3612 uint32_t reversed_addr
;
3613 int ret_val
= QLA_SUCCESS
;
3615 ret_val
= qla8044_poll_flash_status_reg(vha
);
3617 ql_log(ql_log_warn
, vha
, 0xb12e,
3618 "%s: Poll flash status after erase failed..\n", __func__
);
3621 reversed_addr
= (((sector_start_addr
& 0xFF) << 16) |
3622 (sector_start_addr
& 0xFF00) |
3623 ((sector_start_addr
& 0xFF0000) >> 16));
3625 ret_val
= qla8044_wr_reg_indirect(vha
,
3626 QLA8044_FLASH_WRDATA
, reversed_addr
);
3628 ql_log(ql_log_warn
, vha
, 0xb12f,
3629 "%s: Failed to write to FLASH_WRDATA.\n", __func__
);
3631 ret_val
= qla8044_wr_reg_indirect(vha
, QLA8044_FLASH_ADDR
,
3632 QLA8044_FLASH_ERASE_SIG
| vha
->hw
->fdt_erase_cmd
);
3634 ql_log(ql_log_warn
, vha
, 0xb130,
3635 "%s: Failed to write to FLASH_ADDR.\n", __func__
);
3637 ret_val
= qla8044_wr_reg_indirect(vha
, QLA8044_FLASH_CONTROL
,
3638 QLA8044_FLASH_LAST_ERASE_MS_VAL
);
3640 ql_log(ql_log_warn
, vha
, 0xb131,
3641 "%s: Failed write to FLASH_CONTROL.\n", __func__
);
3643 ret_val
= qla8044_poll_flash_status_reg(vha
);
3645 ql_log(ql_log_warn
, vha
, 0xb132,
3646 "%s: Poll flash status failed.\n", __func__
);
3654 * qla8044_flash_write_u32 - Write data to flash
3656 * @ha : Pointer to adapter structure
3657 * addr : Flash address to write to
3658 * p_data : Data to be written
3660 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
3662 * NOTE: Lock should be held on entry
3665 qla8044_flash_write_u32(struct scsi_qla_host
*vha
, uint32_t addr
,
3668 int ret_val
= QLA_SUCCESS
;
3670 ret_val
= qla8044_wr_reg_indirect(vha
, QLA8044_FLASH_ADDR
,
3671 0x00800000 | (addr
>> 2));
3673 ql_log(ql_log_warn
, vha
, 0xb134,
3674 "%s: Failed write to FLASH_ADDR.\n", __func__
);
3677 ret_val
= qla8044_wr_reg_indirect(vha
, QLA8044_FLASH_WRDATA
, *p_data
);
3679 ql_log(ql_log_warn
, vha
, 0xb135,
3680 "%s: Failed write to FLASH_WRDATA.\n", __func__
);
3683 ret_val
= qla8044_wr_reg_indirect(vha
, QLA8044_FLASH_CONTROL
, 0x3D);
3685 ql_log(ql_log_warn
, vha
, 0xb136,
3686 "%s: Failed write to FLASH_CONTROL.\n", __func__
);
3689 ret_val
= qla8044_poll_flash_status_reg(vha
);
3691 ql_log(ql_log_warn
, vha
, 0xb137,
3692 "%s: Poll flash status failed.\n", __func__
);
3700 qla8044_write_flash_buffer_mode(scsi_qla_host_t
*vha
, uint32_t *dwptr
,
3701 uint32_t faddr
, uint32_t dwords
)
3703 int ret
= QLA_FUNCTION_FAILED
;
3706 if (dwords
< QLA8044_MIN_OPTROM_BURST_DWORDS
||
3707 dwords
> QLA8044_MAX_OPTROM_BURST_DWORDS
) {
3708 ql_dbg(ql_dbg_user
, vha
, 0xb123,
3709 "Got unsupported dwords = 0x%x.\n",
3711 return QLA_FUNCTION_FAILED
;
3714 qla8044_rd_reg_indirect(vha
, QLA8044_FLASH_SPI_CONTROL
, &spi_val
);
3715 qla8044_wr_reg_indirect(vha
, QLA8044_FLASH_SPI_CONTROL
,
3716 spi_val
| QLA8044_FLASH_SPI_CTL
);
3717 qla8044_wr_reg_indirect(vha
, QLA8044_FLASH_ADDR
,
3718 QLA8044_FLASH_FIRST_TEMP_VAL
);
3720 /* First DWORD write to FLASH_WRDATA */
3721 ret
= qla8044_wr_reg_indirect(vha
, QLA8044_FLASH_WRDATA
,
3723 qla8044_wr_reg_indirect(vha
, QLA8044_FLASH_CONTROL
,
3724 QLA8044_FLASH_FIRST_MS_PATTERN
);
3726 ret
= qla8044_poll_flash_status_reg(vha
);
3728 ql_log(ql_log_warn
, vha
, 0xb124,
3729 "%s: Failed.\n", __func__
);
3735 qla8044_wr_reg_indirect(vha
, QLA8044_FLASH_ADDR
,
3736 QLA8044_FLASH_SECOND_TEMP_VAL
);
3739 /* Second to N-1 DWORDS writes */
3740 while (dwords
!= 1) {
3741 qla8044_wr_reg_indirect(vha
, QLA8044_FLASH_WRDATA
, *dwptr
++);
3742 qla8044_wr_reg_indirect(vha
, QLA8044_FLASH_CONTROL
,
3743 QLA8044_FLASH_SECOND_MS_PATTERN
);
3744 ret
= qla8044_poll_flash_status_reg(vha
);
3746 ql_log(ql_log_warn
, vha
, 0xb129,
3747 "%s: Failed.\n", __func__
);
3753 qla8044_wr_reg_indirect(vha
, QLA8044_FLASH_ADDR
,
3754 QLA8044_FLASH_FIRST_TEMP_VAL
| (faddr
>> 2));
3756 /* Last DWORD write */
3757 qla8044_wr_reg_indirect(vha
, QLA8044_FLASH_WRDATA
, *dwptr
++);
3758 qla8044_wr_reg_indirect(vha
, QLA8044_FLASH_CONTROL
,
3759 QLA8044_FLASH_LAST_MS_PATTERN
);
3760 ret
= qla8044_poll_flash_status_reg(vha
);
3762 ql_log(ql_log_warn
, vha
, 0xb12a,
3763 "%s: Failed.\n", __func__
);
3766 qla8044_rd_reg_indirect(vha
, QLA8044_FLASH_SPI_STATUS
, &spi_val
);
3768 if ((spi_val
& QLA8044_FLASH_SPI_CTL
) == QLA8044_FLASH_SPI_CTL
) {
3769 ql_log(ql_log_warn
, vha
, 0xb12b,
3770 "%s: Failed.\n", __func__
);
3772 /* Operation failed, clear error bit. */
3773 qla8044_rd_reg_indirect(vha
, QLA8044_FLASH_SPI_CONTROL
,
3775 qla8044_wr_reg_indirect(vha
, QLA8044_FLASH_SPI_CONTROL
,
3776 spi_val
| QLA8044_FLASH_SPI_CTL
);
3783 qla8044_write_flash_dword_mode(scsi_qla_host_t
*vha
, uint32_t *dwptr
,
3784 uint32_t faddr
, uint32_t dwords
)
3786 int ret
= QLA_FUNCTION_FAILED
;
3789 for (liter
= 0; liter
< dwords
; liter
++, faddr
+= 4, dwptr
++) {
3790 ret
= qla8044_flash_write_u32(vha
, faddr
, dwptr
);
3792 ql_dbg(ql_dbg_p3p
, vha
, 0xb141,
3793 "%s: flash address=%x data=%x.\n", __func__
,
3803 qla8044_write_optrom_data(struct scsi_qla_host
*vha
, uint8_t *buf
,
3804 uint32_t offset
, uint32_t length
)
3806 int rval
= QLA_FUNCTION_FAILED
, i
, burst_iter_count
;
3807 int dword_count
, erase_sec_count
;
3808 uint32_t erase_offset
;
3809 uint8_t *p_cache
, *p_src
;
3811 erase_offset
= offset
;
3813 p_cache
= kcalloc(length
, sizeof(uint8_t), GFP_KERNEL
);
3815 return QLA_FUNCTION_FAILED
;
3817 memcpy(p_cache
, buf
, length
);
3819 dword_count
= length
/ sizeof(uint32_t);
3820 /* Since the offset and legth are sector aligned, it will be always
3821 * multiple of burst_iter_count (64)
3823 burst_iter_count
= dword_count
/ QLA8044_MAX_OPTROM_BURST_DWORDS
;
3824 erase_sec_count
= length
/ QLA8044_SECTOR_SIZE
;
3827 scsi_block_requests(vha
->host
);
3828 /* Lock and enable write for whole operation. */
3829 qla8044_flash_lock(vha
);
3830 qla8044_unprotect_flash(vha
);
3832 /* Erasing the sectors */
3833 for (i
= 0; i
< erase_sec_count
; i
++) {
3834 rval
= qla8044_erase_flash_sector(vha
, erase_offset
);
3835 ql_dbg(ql_dbg_user
, vha
, 0xb138,
3836 "Done erase of sector=0x%x.\n",
3839 ql_log(ql_log_warn
, vha
, 0xb121,
3840 "Failed to erase the sector having address: "
3841 "0x%x.\n", erase_offset
);
3844 erase_offset
+= QLA8044_SECTOR_SIZE
;
3846 ql_dbg(ql_dbg_user
, vha
, 0xb13f,
3847 "Got write for addr = 0x%x length=0x%x.\n",
3850 for (i
= 0; i
< burst_iter_count
; i
++) {
3852 /* Go with write. */
3853 rval
= qla8044_write_flash_buffer_mode(vha
, (uint32_t *)p_src
,
3854 offset
, QLA8044_MAX_OPTROM_BURST_DWORDS
);
3856 /* Buffer Mode failed skip to dword mode */
3857 ql_log(ql_log_warn
, vha
, 0xb122,
3858 "Failed to write flash in buffer mode, "
3859 "Reverting to slow-write.\n");
3860 rval
= qla8044_write_flash_dword_mode(vha
,
3861 (uint32_t *)p_src
, offset
,
3862 QLA8044_MAX_OPTROM_BURST_DWORDS
);
3864 p_src
+= sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS
;
3865 offset
+= sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS
;
3867 ql_dbg(ql_dbg_user
, vha
, 0xb133,
3871 qla8044_protect_flash(vha
);
3872 qla8044_flash_unlock(vha
);
3873 scsi_unblock_requests(vha
->host
);
3879 #define LEG_INT_PTR_B31 (1 << 31)
3880 #define LEG_INT_PTR_B30 (1 << 30)
3881 #define PF_BITS_MASK (0xF << 16)
3883 * qla8044_intr_handler() - Process interrupts for the ISP8044
3885 * @dev_id: SCSI driver HA context
3887 * Called by system whenever the host adapter generates an interrupt.
3889 * Returns handled flag.
3892 qla8044_intr_handler(int irq
, void *dev_id
)
3894 scsi_qla_host_t
*vha
;
3895 struct qla_hw_data
*ha
;
3896 struct rsp_que
*rsp
;
3897 struct device_reg_82xx __iomem
*reg
;
3899 unsigned long flags
;
3903 uint32_t leg_int_ptr
= 0, pf_bit
;
3905 rsp
= (struct rsp_que
*) dev_id
;
3907 ql_log(ql_log_info
, NULL
, 0xb143,
3908 "%s(): NULL response queue pointer\n", __func__
);
3912 vha
= pci_get_drvdata(ha
->pdev
);
3914 if (unlikely(pci_channel_offline(ha
->pdev
)))
3917 leg_int_ptr
= qla8044_rd_reg(ha
, LEG_INTR_PTR_OFFSET
);
3919 /* Legacy interrupt is valid if bit31 of leg_int_ptr is set */
3920 if (!(leg_int_ptr
& (LEG_INT_PTR_B31
))) {
3921 ql_dbg(ql_dbg_p3p
, vha
, 0xb144,
3922 "%s: Legacy Interrupt Bit 31 not set, "
3923 "spurious interrupt!\n", __func__
);
3927 pf_bit
= ha
->portnum
<< 16;
3928 /* Validate the PCIE function ID set in leg_int_ptr bits [19..16] */
3929 if ((leg_int_ptr
& (PF_BITS_MASK
)) != pf_bit
) {
3930 ql_dbg(ql_dbg_p3p
, vha
, 0xb145,
3931 "%s: Incorrect function ID 0x%x in "
3932 "legacy interrupt register, "
3933 "ha->pf_bit = 0x%x\n", __func__
,
3934 (leg_int_ptr
& (PF_BITS_MASK
)), pf_bit
);
3938 /* To de-assert legacy interrupt, write 0 to Legacy Interrupt Trigger
3939 * Control register and poll till Legacy Interrupt Pointer register
3942 qla8044_wr_reg(ha
, LEG_INTR_TRIG_OFFSET
, 0);
3944 leg_int_ptr
= qla8044_rd_reg(ha
, LEG_INTR_PTR_OFFSET
);
3945 if ((leg_int_ptr
& (PF_BITS_MASK
)) != pf_bit
)
3947 } while (leg_int_ptr
& (LEG_INT_PTR_B30
));
3949 reg
= &ha
->iobase
->isp82
;
3950 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
3951 for (iter
= 1; iter
--; ) {
3953 if (RD_REG_DWORD(®
->host_int
)) {
3954 stat
= RD_REG_DWORD(®
->host_status
);
3955 if ((stat
& HSRX_RISC_INT
) == 0)
3958 switch (stat
& 0xff) {
3963 qla82xx_mbx_completion(vha
, MSW(stat
));
3964 status
|= MBX_INTERRUPT
;
3968 mb
[1] = RD_REG_WORD(®
->mailbox_out
[1]);
3969 mb
[2] = RD_REG_WORD(®
->mailbox_out
[2]);
3970 mb
[3] = RD_REG_WORD(®
->mailbox_out
[3]);
3971 qla2x00_async_event(vha
, rsp
, mb
);
3974 qla24xx_process_response_queue(vha
, rsp
);
3977 ql_dbg(ql_dbg_p3p
, vha
, 0xb146,
3978 "Unrecognized interrupt type "
3979 "(%d).\n", stat
& 0xff);
3983 WRT_REG_DWORD(®
->host_int
, 0);
3986 qla2x00_handle_mbx_completion(ha
, status
);
3987 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
3993 qla8044_idc_dontreset(struct qla_hw_data
*ha
)
3997 idc_ctrl
= qla8044_rd_reg(ha
, QLA8044_IDC_DRV_CTRL
);
3998 return idc_ctrl
& DONTRESET_BIT0
;
4002 qla8044_clear_rst_ready(scsi_qla_host_t
*vha
)
4006 drv_state
= qla8044_rd_direct(vha
, QLA8044_CRB_DRV_STATE_INDEX
);
4009 * For ISP8044, drv_active register has 1 bit per function,
4010 * shift 1 by func_num to set a bit for the function.
4011 * For ISP82xx, drv_active has 4 bits per function
4013 drv_state
&= ~(1 << vha
->hw
->portnum
);
4015 ql_dbg(ql_dbg_p3p
, vha
, 0xb13d,
4016 "drv_state: 0x%08x\n", drv_state
);
4017 qla8044_wr_direct(vha
, QLA8044_CRB_DRV_STATE_INDEX
, drv_state
);
4021 qla8044_abort_isp(scsi_qla_host_t
*vha
)
4025 struct qla_hw_data
*ha
= vha
->hw
;
4027 qla8044_idc_lock(ha
);
4028 dev_state
= qla8044_rd_direct(vha
, QLA8044_CRB_DEV_STATE_INDEX
);
4030 if (ql2xdontresethba
)
4031 qla8044_set_idc_dontreset(vha
);
4033 /* If device_state is NEED_RESET, go ahead with
4034 * Reset,irrespective of ql2xdontresethba. This is to allow a
4035 * non-reset-owner to force a reset. Non-reset-owner sets
4036 * the IDC_CTRL BIT0 to prevent Reset-owner from doing a Reset
4037 * and then forces a Reset by setting device_state to
4039 if (dev_state
== QLA8XXX_DEV_READY
) {
4040 /* If IDC_CTRL DONTRESETHBA_BIT0 is set don't do reset
4042 if (qla8044_idc_dontreset(ha
) == DONTRESET_BIT0
) {
4043 ql_dbg(ql_dbg_p3p
, vha
, 0xb13e,
4044 "Reset recovery disabled\n");
4045 rval
= QLA_FUNCTION_FAILED
;
4046 goto exit_isp_reset
;
4049 ql_dbg(ql_dbg_p3p
, vha
, 0xb140,
4050 "HW State: NEED RESET\n");
4051 qla8044_wr_direct(vha
, QLA8044_CRB_DEV_STATE_INDEX
,
4052 QLA8XXX_DEV_NEED_RESET
);
4055 /* For ISP8044, Reset owner is NIC, iSCSI or FCOE based on priority
4056 * and which drivers are present. Unlike ISP82XX, the function setting
4057 * NEED_RESET, may not be the Reset owner. */
4058 qla83xx_reset_ownership(vha
);
4060 qla8044_idc_unlock(ha
);
4061 rval
= qla8044_device_state_handler(vha
);
4062 qla8044_idc_lock(ha
);
4063 qla8044_clear_rst_ready(vha
);
4066 qla8044_idc_unlock(ha
);
4067 if (rval
== QLA_SUCCESS
) {
4068 ha
->flags
.isp82xx_fw_hung
= 0;
4069 ha
->flags
.nic_core_reset_hdlr_active
= 0;
4070 rval
= qla82xx_restart_isp(vha
);
4077 qla8044_fw_dump(scsi_qla_host_t
*vha
, int hardware_locked
)
4079 struct qla_hw_data
*ha
= vha
->hw
;
4081 if (!ha
->allow_cna_fw_dump
)
4084 scsi_block_requests(vha
->host
);
4085 ha
->flags
.isp82xx_no_md_cap
= 1;
4086 qla8044_idc_lock(ha
);
4087 qla82xx_set_reset_owner(vha
);
4088 qla8044_idc_unlock(ha
);
4089 qla2x00_wait_for_chip_reset(vha
);
4090 scsi_unblock_requests(vha
->host
);