1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/ipv6.h>
38 #include <net/checksum.h>
39 #include <net/ip6_checksum.h>
40 #include <linux/ethtool.h>
41 #include <linux/if_vlan.h>
42 #include <scsi/fc/fc_fcoe.h>
45 #include "ixgbe_common.h"
47 char ixgbe_driver_name
[] = "ixgbe";
48 static const char ixgbe_driver_string
[] =
49 "Intel(R) 10 Gigabit PCI Express Network Driver";
51 #define DRV_VERSION "2.0.24-k2"
52 const char ixgbe_driver_version
[] = DRV_VERSION
;
53 static char ixgbe_copyright
[] = "Copyright (c) 1999-2009 Intel Corporation.";
55 static const struct ixgbe_info
*ixgbe_info_tbl
[] = {
56 [board_82598
] = &ixgbe_82598_info
,
57 [board_82599
] = &ixgbe_82599_info
,
60 /* ixgbe_pci_tbl - PCI Device ID Table
62 * Wildcard entries (PCI_ANY_ID) should come last
63 * Last entry must be all 0s
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
68 static struct pci_device_id ixgbe_pci_tbl
[] = {
69 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598
),
71 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_DUAL_PORT
),
73 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_SINGLE_PORT
),
75 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT
),
77 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_CX4
),
79 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_CX4_DUAL_PORT
),
81 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_DA_DUAL_PORT
),
83 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
),
85 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_XF_LR
),
87 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_SFP_LOM
),
89 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_BX
),
91 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4
),
93 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_XAUI_LOM
),
95 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP
),
98 /* required last entry */
101 MODULE_DEVICE_TABLE(pci
, ixgbe_pci_tbl
);
103 #ifdef CONFIG_IXGBE_DCA
104 static int ixgbe_notify_dca(struct notifier_block
*, unsigned long event
,
106 static struct notifier_block dca_notifier
= {
107 .notifier_call
= ixgbe_notify_dca
,
113 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
114 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
115 MODULE_LICENSE("GPL");
116 MODULE_VERSION(DRV_VERSION
);
118 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
120 static void ixgbe_release_hw_control(struct ixgbe_adapter
*adapter
)
124 /* Let firmware take over control of h/w */
125 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
126 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
127 ctrl_ext
& ~IXGBE_CTRL_EXT_DRV_LOAD
);
130 static void ixgbe_get_hw_control(struct ixgbe_adapter
*adapter
)
134 /* Let firmware know the driver has taken over */
135 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
136 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
137 ctrl_ext
| IXGBE_CTRL_EXT_DRV_LOAD
);
141 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
142 * @adapter: pointer to adapter struct
143 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
144 * @queue: queue to map the corresponding interrupt to
145 * @msix_vector: the vector to map to the corresponding queue
148 static void ixgbe_set_ivar(struct ixgbe_adapter
*adapter
, s8 direction
,
149 u8 queue
, u8 msix_vector
)
152 struct ixgbe_hw
*hw
= &adapter
->hw
;
153 switch (hw
->mac
.type
) {
154 case ixgbe_mac_82598EB
:
155 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
158 index
= (((direction
* 64) + queue
) >> 2) & 0x1F;
159 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(index
));
160 ivar
&= ~(0xFF << (8 * (queue
& 0x3)));
161 ivar
|= (msix_vector
<< (8 * (queue
& 0x3)));
162 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(index
), ivar
);
164 case ixgbe_mac_82599EB
:
165 if (direction
== -1) {
167 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
168 index
= ((queue
& 1) * 8);
169 ivar
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_IVAR_MISC
);
170 ivar
&= ~(0xFF << index
);
171 ivar
|= (msix_vector
<< index
);
172 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_IVAR_MISC
, ivar
);
175 /* tx or rx causes */
176 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
177 index
= ((16 * (queue
& 1)) + (8 * direction
));
178 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(queue
>> 1));
179 ivar
&= ~(0xFF << index
);
180 ivar
|= (msix_vector
<< index
);
181 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(queue
>> 1), ivar
);
189 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter
*adapter
,
190 struct ixgbe_tx_buffer
193 tx_buffer_info
->dma
= 0;
194 if (tx_buffer_info
->skb
) {
195 skb_dma_unmap(&adapter
->pdev
->dev
, tx_buffer_info
->skb
,
197 dev_kfree_skb_any(tx_buffer_info
->skb
);
198 tx_buffer_info
->skb
= NULL
;
200 tx_buffer_info
->time_stamp
= 0;
201 /* tx_buffer_info must be completely set up in the transmit path */
204 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter
*adapter
,
205 struct ixgbe_ring
*tx_ring
,
208 struct ixgbe_hw
*hw
= &adapter
->hw
;
210 /* Detect a transmit hang in hardware, this serializes the
211 * check with the clearing of time_stamp and movement of eop */
212 adapter
->detect_tx_hung
= false;
213 if (tx_ring
->tx_buffer_info
[eop
].time_stamp
&&
214 time_after(jiffies
, tx_ring
->tx_buffer_info
[eop
].time_stamp
+ HZ
) &&
215 !(IXGBE_READ_REG(&adapter
->hw
, IXGBE_TFCS
) & IXGBE_TFCS_TXOFF
)) {
216 /* detected Tx unit hang */
217 union ixgbe_adv_tx_desc
*tx_desc
;
218 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
219 DPRINTK(DRV
, ERR
, "Detected Tx Unit Hang\n"
221 " TDH, TDT <%x>, <%x>\n"
222 " next_to_use <%x>\n"
223 " next_to_clean <%x>\n"
224 "tx_buffer_info[next_to_clean]\n"
225 " time_stamp <%lx>\n"
227 tx_ring
->queue_index
,
228 IXGBE_READ_REG(hw
, tx_ring
->head
),
229 IXGBE_READ_REG(hw
, tx_ring
->tail
),
230 tx_ring
->next_to_use
, eop
,
231 tx_ring
->tx_buffer_info
[eop
].time_stamp
, jiffies
);
238 #define IXGBE_MAX_TXD_PWR 14
239 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
241 /* Tx Descriptors needed, worst case */
242 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
243 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
244 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
245 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
247 static void ixgbe_tx_timeout(struct net_device
*netdev
);
250 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
251 * @adapter: board private structure
252 * @tx_ring: tx ring to clean
254 * returns true if transmit work is done
256 static bool ixgbe_clean_tx_irq(struct ixgbe_adapter
*adapter
,
257 struct ixgbe_ring
*tx_ring
)
259 struct net_device
*netdev
= adapter
->netdev
;
260 union ixgbe_adv_tx_desc
*tx_desc
, *eop_desc
;
261 struct ixgbe_tx_buffer
*tx_buffer_info
;
262 unsigned int i
, eop
, count
= 0;
263 unsigned int total_bytes
= 0, total_packets
= 0;
265 i
= tx_ring
->next_to_clean
;
266 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
267 eop_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
269 while ((eop_desc
->wb
.status
& cpu_to_le32(IXGBE_TXD_STAT_DD
)) &&
270 (count
< tx_ring
->work_limit
)) {
271 bool cleaned
= false;
272 for ( ; !cleaned
; count
++) {
274 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, i
);
275 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
276 cleaned
= (i
== eop
);
277 skb
= tx_buffer_info
->skb
;
279 if (cleaned
&& skb
) {
280 unsigned int segs
, bytecount
;
282 /* gso_segs is currently only valid for tcp */
283 segs
= skb_shinfo(skb
)->gso_segs
?: 1;
284 /* multiply data chunks by size of headers */
285 bytecount
= ((segs
- 1) * skb_headlen(skb
)) +
287 total_packets
+= segs
;
288 total_bytes
+= bytecount
;
291 ixgbe_unmap_and_free_tx_resource(adapter
,
294 tx_desc
->wb
.status
= 0;
297 if (i
== tx_ring
->count
)
301 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
302 eop_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
305 tx_ring
->next_to_clean
= i
;
307 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
308 if (unlikely(count
&& netif_carrier_ok(netdev
) &&
309 (IXGBE_DESC_UNUSED(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
310 /* Make sure that anybody stopping the queue after this
311 * sees the new next_to_clean.
314 if (__netif_subqueue_stopped(netdev
, tx_ring
->queue_index
) &&
315 !test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
316 netif_wake_subqueue(netdev
, tx_ring
->queue_index
);
317 ++adapter
->restart_queue
;
321 if (adapter
->detect_tx_hung
) {
322 if (ixgbe_check_tx_hang(adapter
, tx_ring
, i
)) {
323 /* schedule immediate reset if we believe we hung */
325 "tx hang %d detected, resetting adapter\n",
326 adapter
->tx_timeout_count
+ 1);
327 ixgbe_tx_timeout(adapter
->netdev
);
331 /* re-arm the interrupt */
332 if (count
>= tx_ring
->work_limit
) {
333 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
334 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS
,
336 else if (tx_ring
->v_idx
& 0xFFFFFFFF)
337 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(0),
340 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(1),
341 (tx_ring
->v_idx
>> 32));
345 tx_ring
->total_bytes
+= total_bytes
;
346 tx_ring
->total_packets
+= total_packets
;
347 tx_ring
->stats
.packets
+= total_packets
;
348 tx_ring
->stats
.bytes
+= total_bytes
;
349 adapter
->net_stats
.tx_bytes
+= total_bytes
;
350 adapter
->net_stats
.tx_packets
+= total_packets
;
351 return (count
< tx_ring
->work_limit
);
354 #ifdef CONFIG_IXGBE_DCA
355 static void ixgbe_update_rx_dca(struct ixgbe_adapter
*adapter
,
356 struct ixgbe_ring
*rx_ring
)
360 int q
= rx_ring
- adapter
->rx_ring
;
362 if (rx_ring
->cpu
!= cpu
) {
363 rxctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
));
364 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
365 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK
;
366 rxctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
367 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
368 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599
;
369 rxctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
370 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599
);
372 rxctrl
|= IXGBE_DCA_RXCTRL_DESC_DCA_EN
;
373 rxctrl
|= IXGBE_DCA_RXCTRL_HEAD_DCA_EN
;
374 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN
);
375 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN
|
376 IXGBE_DCA_RXCTRL_DESC_HSRO_EN
);
377 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
), rxctrl
);
383 static void ixgbe_update_tx_dca(struct ixgbe_adapter
*adapter
,
384 struct ixgbe_ring
*tx_ring
)
388 int q
= tx_ring
- adapter
->tx_ring
;
390 if (tx_ring
->cpu
!= cpu
) {
391 txctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_DCA_TXCTRL(q
));
392 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
393 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK
;
394 txctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
395 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
396 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599
;
397 txctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
398 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599
);
400 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
401 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_TXCTRL(q
), txctrl
);
407 static void ixgbe_setup_dca(struct ixgbe_adapter
*adapter
)
411 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
414 /* always use CB2 mode, difference is masked in the CB driver */
415 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 2);
417 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
418 adapter
->tx_ring
[i
].cpu
= -1;
419 ixgbe_update_tx_dca(adapter
, &adapter
->tx_ring
[i
]);
421 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
422 adapter
->rx_ring
[i
].cpu
= -1;
423 ixgbe_update_rx_dca(adapter
, &adapter
->rx_ring
[i
]);
427 static int __ixgbe_notify_dca(struct device
*dev
, void *data
)
429 struct net_device
*netdev
= dev_get_drvdata(dev
);
430 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
431 unsigned long event
= *(unsigned long *)data
;
434 case DCA_PROVIDER_ADD
:
435 /* if we're already enabled, don't do it again */
436 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
438 if (dca_add_requester(dev
) == 0) {
439 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
440 ixgbe_setup_dca(adapter
);
443 /* Fall Through since DCA is disabled. */
444 case DCA_PROVIDER_REMOVE
:
445 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
446 dca_remove_requester(dev
);
447 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
448 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
456 #endif /* CONFIG_IXGBE_DCA */
458 * ixgbe_receive_skb - Send a completed packet up the stack
459 * @adapter: board private structure
460 * @skb: packet to send up
461 * @status: hardware indication of status of receive
462 * @rx_ring: rx descriptor ring (for a specific queue) to setup
463 * @rx_desc: rx descriptor
465 static void ixgbe_receive_skb(struct ixgbe_q_vector
*q_vector
,
466 struct sk_buff
*skb
, u8 status
,
467 struct ixgbe_ring
*ring
,
468 union ixgbe_adv_rx_desc
*rx_desc
)
470 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
471 struct napi_struct
*napi
= &q_vector
->napi
;
472 bool is_vlan
= (status
& IXGBE_RXD_STAT_VP
);
473 u16 tag
= le16_to_cpu(rx_desc
->wb
.upper
.vlan
);
475 skb_record_rx_queue(skb
, ring
->queue_index
);
476 if (!(adapter
->flags
& IXGBE_FLAG_IN_NETPOLL
)) {
477 if (adapter
->vlgrp
&& is_vlan
&& (tag
!= 0))
478 vlan_gro_receive(napi
, adapter
->vlgrp
, tag
, skb
);
480 napi_gro_receive(napi
, skb
);
482 if (adapter
->vlgrp
&& is_vlan
&& (tag
!= 0))
483 vlan_hwaccel_rx(skb
, adapter
->vlgrp
, tag
);
490 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
491 * @adapter: address of board private structure
492 * @status_err: hardware indication of status of receive
493 * @skb: skb currently being received and modified
495 static inline void ixgbe_rx_checksum(struct ixgbe_adapter
*adapter
,
496 u32 status_err
, struct sk_buff
*skb
)
498 skb
->ip_summed
= CHECKSUM_NONE
;
500 /* Rx csum disabled */
501 if (!(adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
))
504 /* if IP and error */
505 if ((status_err
& IXGBE_RXD_STAT_IPCS
) &&
506 (status_err
& IXGBE_RXDADV_ERR_IPE
)) {
507 adapter
->hw_csum_rx_error
++;
511 if (!(status_err
& IXGBE_RXD_STAT_L4CS
))
514 if (status_err
& IXGBE_RXDADV_ERR_TCPE
) {
515 adapter
->hw_csum_rx_error
++;
519 /* It must be a TCP or UDP packet with a valid checksum */
520 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
521 adapter
->hw_csum_rx_good
++;
524 static inline void ixgbe_release_rx_desc(struct ixgbe_hw
*hw
,
525 struct ixgbe_ring
*rx_ring
, u32 val
)
528 * Force memory writes to complete before letting h/w
529 * know there are new descriptors to fetch. (Only
530 * applicable for weak-ordered memory model archs,
534 IXGBE_WRITE_REG(hw
, IXGBE_RDT(rx_ring
->reg_idx
), val
);
538 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
539 * @adapter: address of board private structure
541 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter
*adapter
,
542 struct ixgbe_ring
*rx_ring
,
545 struct pci_dev
*pdev
= adapter
->pdev
;
546 union ixgbe_adv_rx_desc
*rx_desc
;
547 struct ixgbe_rx_buffer
*bi
;
549 unsigned int bufsz
= rx_ring
->rx_buf_len
+ NET_IP_ALIGN
;
551 i
= rx_ring
->next_to_use
;
552 bi
= &rx_ring
->rx_buffer_info
[i
];
554 while (cleaned_count
--) {
555 rx_desc
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
558 (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
)) {
560 bi
->page
= alloc_page(GFP_ATOMIC
);
562 adapter
->alloc_rx_page_failed
++;
567 /* use a half page if we're re-using */
568 bi
->page_offset
^= (PAGE_SIZE
/ 2);
571 bi
->page_dma
= pci_map_page(pdev
, bi
->page
,
579 skb
= netdev_alloc_skb(adapter
->netdev
, bufsz
);
582 adapter
->alloc_rx_buff_failed
++;
587 * Make buffer alignment 2 beyond a 16 byte boundary
588 * this will result in a 16 byte aligned IP header after
589 * the 14 byte MAC header is removed
591 skb_reserve(skb
, NET_IP_ALIGN
);
594 bi
->dma
= pci_map_single(pdev
, skb
->data
, bufsz
,
597 /* Refresh the desc even if buffer_addrs didn't change because
598 * each write-back erases this info. */
599 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
600 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
601 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
603 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
607 if (i
== rx_ring
->count
)
609 bi
= &rx_ring
->rx_buffer_info
[i
];
613 if (rx_ring
->next_to_use
!= i
) {
614 rx_ring
->next_to_use
= i
;
616 i
= (rx_ring
->count
- 1);
618 ixgbe_release_rx_desc(&adapter
->hw
, rx_ring
, i
);
622 static inline u16
ixgbe_get_hdr_info(union ixgbe_adv_rx_desc
*rx_desc
)
624 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.hdr_info
;
627 static inline u16
ixgbe_get_pkt_info(union ixgbe_adv_rx_desc
*rx_desc
)
629 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
632 static inline u32
ixgbe_get_rsc_count(union ixgbe_adv_rx_desc
*rx_desc
)
634 return (le32_to_cpu(rx_desc
->wb
.lower
.lo_dword
.data
) &
635 IXGBE_RXDADV_RSCCNT_MASK
) >>
636 IXGBE_RXDADV_RSCCNT_SHIFT
;
640 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
641 * @skb: pointer to the last skb in the rsc queue
643 * This function changes a queue full of hw rsc buffers into a completed
644 * packet. It uses the ->prev pointers to find the first packet and then
645 * turns it into the frag list owner.
647 static inline struct sk_buff
*ixgbe_transform_rsc_queue(struct sk_buff
*skb
)
649 unsigned int frag_list_size
= 0;
652 struct sk_buff
*prev
= skb
->prev
;
653 frag_list_size
+= skb
->len
;
658 skb_shinfo(skb
)->frag_list
= skb
->next
;
660 skb
->len
+= frag_list_size
;
661 skb
->data_len
+= frag_list_size
;
662 skb
->truesize
+= frag_list_size
;
666 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector
*q_vector
,
667 struct ixgbe_ring
*rx_ring
,
668 int *work_done
, int work_to_do
)
670 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
671 struct pci_dev
*pdev
= adapter
->pdev
;
672 union ixgbe_adv_rx_desc
*rx_desc
, *next_rxd
;
673 struct ixgbe_rx_buffer
*rx_buffer_info
, *next_buffer
;
675 unsigned int i
, rsc_count
= 0;
678 bool cleaned
= false;
679 int cleaned_count
= 0;
680 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
682 i
= rx_ring
->next_to_clean
;
683 rx_desc
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
684 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
685 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
687 while (staterr
& IXGBE_RXD_STAT_DD
) {
689 if (*work_done
>= work_to_do
)
693 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
694 hdr_info
= le16_to_cpu(ixgbe_get_hdr_info(rx_desc
));
695 len
= (hdr_info
& IXGBE_RXDADV_HDRBUFLEN_MASK
) >>
696 IXGBE_RXDADV_HDRBUFLEN_SHIFT
;
697 if (hdr_info
& IXGBE_RXDADV_SPH
)
698 adapter
->rx_hdr_split
++;
699 if (len
> IXGBE_RX_HDR_SIZE
)
700 len
= IXGBE_RX_HDR_SIZE
;
701 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
703 len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
707 skb
= rx_buffer_info
->skb
;
708 prefetch(skb
->data
- NET_IP_ALIGN
);
709 rx_buffer_info
->skb
= NULL
;
711 if (len
&& !skb_shinfo(skb
)->nr_frags
) {
712 pci_unmap_single(pdev
, rx_buffer_info
->dma
,
719 pci_unmap_page(pdev
, rx_buffer_info
->page_dma
,
720 PAGE_SIZE
/ 2, PCI_DMA_FROMDEVICE
);
721 rx_buffer_info
->page_dma
= 0;
722 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
723 rx_buffer_info
->page
,
724 rx_buffer_info
->page_offset
,
727 if ((rx_ring
->rx_buf_len
> (PAGE_SIZE
/ 2)) ||
728 (page_count(rx_buffer_info
->page
) != 1))
729 rx_buffer_info
->page
= NULL
;
731 get_page(rx_buffer_info
->page
);
733 skb
->len
+= upper_len
;
734 skb
->data_len
+= upper_len
;
735 skb
->truesize
+= upper_len
;
739 if (i
== rx_ring
->count
)
742 next_rxd
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
746 if (adapter
->flags
& IXGBE_FLAG_RSC_CAPABLE
)
747 rsc_count
= ixgbe_get_rsc_count(rx_desc
);
750 u32 nextp
= (staterr
& IXGBE_RXDADV_NEXTP_MASK
) >>
751 IXGBE_RXDADV_NEXTP_SHIFT
;
752 next_buffer
= &rx_ring
->rx_buffer_info
[nextp
];
753 rx_ring
->rsc_count
+= (rsc_count
- 1);
755 next_buffer
= &rx_ring
->rx_buffer_info
[i
];
758 if (staterr
& IXGBE_RXD_STAT_EOP
) {
760 skb
= ixgbe_transform_rsc_queue(skb
);
761 rx_ring
->stats
.packets
++;
762 rx_ring
->stats
.bytes
+= skb
->len
;
764 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
765 rx_buffer_info
->skb
= next_buffer
->skb
;
766 rx_buffer_info
->dma
= next_buffer
->dma
;
767 next_buffer
->skb
= skb
;
768 next_buffer
->dma
= 0;
770 skb
->next
= next_buffer
->skb
;
771 skb
->next
->prev
= skb
;
773 adapter
->non_eop_descs
++;
777 if (staterr
& IXGBE_RXDADV_ERR_FRAME_ERR_MASK
) {
778 dev_kfree_skb_irq(skb
);
782 ixgbe_rx_checksum(adapter
, staterr
, skb
);
784 /* probably a little skewed due to removing CRC */
785 total_rx_bytes
+= skb
->len
;
788 skb
->protocol
= eth_type_trans(skb
, adapter
->netdev
);
790 /* if ddp, not passing to ULD unless for FCP_RSP or error */
791 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
792 if (!ixgbe_fcoe_ddp(adapter
, rx_desc
, skb
))
794 #endif /* IXGBE_FCOE */
795 ixgbe_receive_skb(q_vector
, skb
, staterr
, rx_ring
, rx_desc
);
798 rx_desc
->wb
.upper
.status_error
= 0;
800 /* return some buffers to hardware, one at a time is too slow */
801 if (cleaned_count
>= IXGBE_RX_BUFFER_WRITE
) {
802 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
806 /* use prefetched values */
808 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
810 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
813 rx_ring
->next_to_clean
= i
;
814 cleaned_count
= IXGBE_DESC_UNUSED(rx_ring
);
817 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
819 rx_ring
->total_packets
+= total_rx_packets
;
820 rx_ring
->total_bytes
+= total_rx_bytes
;
821 adapter
->net_stats
.rx_bytes
+= total_rx_bytes
;
822 adapter
->net_stats
.rx_packets
+= total_rx_packets
;
827 static int ixgbe_clean_rxonly(struct napi_struct
*, int);
829 * ixgbe_configure_msix - Configure MSI-X hardware
830 * @adapter: board private structure
832 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
835 static void ixgbe_configure_msix(struct ixgbe_adapter
*adapter
)
837 struct ixgbe_q_vector
*q_vector
;
838 int i
, j
, q_vectors
, v_idx
, r_idx
;
841 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
844 * Populate the IVAR table and set the ITR values to the
845 * corresponding register.
847 for (v_idx
= 0; v_idx
< q_vectors
; v_idx
++) {
848 q_vector
= adapter
->q_vector
[v_idx
];
849 /* XXX for_each_bit(...) */
850 r_idx
= find_first_bit(q_vector
->rxr_idx
,
851 adapter
->num_rx_queues
);
853 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
854 j
= adapter
->rx_ring
[r_idx
].reg_idx
;
855 ixgbe_set_ivar(adapter
, 0, j
, v_idx
);
856 r_idx
= find_next_bit(q_vector
->rxr_idx
,
857 adapter
->num_rx_queues
,
860 r_idx
= find_first_bit(q_vector
->txr_idx
,
861 adapter
->num_tx_queues
);
863 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
864 j
= adapter
->tx_ring
[r_idx
].reg_idx
;
865 ixgbe_set_ivar(adapter
, 1, j
, v_idx
);
866 r_idx
= find_next_bit(q_vector
->txr_idx
,
867 adapter
->num_tx_queues
,
871 /* if this is a tx only vector halve the interrupt rate */
872 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
873 q_vector
->eitr
= (adapter
->eitr_param
>> 1);
874 else if (q_vector
->rxr_count
)
876 q_vector
->eitr
= adapter
->eitr_param
;
879 * since this is initial set up don't need to call
880 * ixgbe_write_eitr helper
882 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITR(v_idx
),
883 EITR_INTS_PER_SEC_TO_REG(q_vector
->eitr
));
886 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
887 ixgbe_set_ivar(adapter
, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX
,
889 else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
890 ixgbe_set_ivar(adapter
, -1, 1, v_idx
);
891 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITR(v_idx
), 1950);
893 /* set up to autoclear timer, and the vectors */
894 mask
= IXGBE_EIMS_ENABLE_MASK
;
895 mask
&= ~(IXGBE_EIMS_OTHER
| IXGBE_EIMS_LSC
);
896 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIAC
, mask
);
903 latency_invalid
= 255
907 * ixgbe_update_itr - update the dynamic ITR value based on statistics
908 * @adapter: pointer to adapter
909 * @eitr: eitr setting (ints per sec) to give last timeslice
910 * @itr_setting: current throttle rate in ints/second
911 * @packets: the number of packets during this measurement interval
912 * @bytes: the number of bytes during this measurement interval
914 * Stores a new ITR value based on packets and byte
915 * counts during the last interrupt. The advantage of per interrupt
916 * computation is faster updates and more accurate ITR for the current
917 * traffic pattern. Constants in this function were computed
918 * based on theoretical maximum wire speed and thresholds were set based
919 * on testing data as well as attempting to minimize response time
920 * while increasing bulk throughput.
921 * this functionality is controlled by the InterruptThrottleRate module
922 * parameter (see ixgbe_param.c)
924 static u8
ixgbe_update_itr(struct ixgbe_adapter
*adapter
,
925 u32 eitr
, u8 itr_setting
,
926 int packets
, int bytes
)
928 unsigned int retval
= itr_setting
;
933 goto update_itr_done
;
936 /* simple throttlerate management
937 * 0-20MB/s lowest (100000 ints/s)
938 * 20-100MB/s low (20000 ints/s)
939 * 100-1249MB/s bulk (8000 ints/s)
941 /* what was last interrupt timeslice? */
942 timepassed_us
= 1000000/eitr
;
943 bytes_perint
= bytes
/ timepassed_us
; /* bytes/usec */
945 switch (itr_setting
) {
947 if (bytes_perint
> adapter
->eitr_low
)
948 retval
= low_latency
;
951 if (bytes_perint
> adapter
->eitr_high
)
952 retval
= bulk_latency
;
953 else if (bytes_perint
<= adapter
->eitr_low
)
954 retval
= lowest_latency
;
957 if (bytes_perint
<= adapter
->eitr_high
)
958 retval
= low_latency
;
967 * ixgbe_write_eitr - write EITR register in hardware specific way
968 * @adapter: pointer to adapter struct
969 * @v_idx: vector index into q_vector array
970 * @itr_reg: new value to be written in *register* format, not ints/s
972 * This function is made to be called by ethtool and by the driver
973 * when it needs to update EITR registers at runtime. Hardware
974 * specific quirks/differences are taken care of here.
976 void ixgbe_write_eitr(struct ixgbe_adapter
*adapter
, int v_idx
, u32 itr_reg
)
978 struct ixgbe_hw
*hw
= &adapter
->hw
;
979 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
980 /* must write high and low 16 bits to reset counter */
981 itr_reg
|= (itr_reg
<< 16);
982 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
984 * set the WDIS bit to not clear the timer bits and cause an
985 * immediate assertion of the interrupt
987 itr_reg
|= IXGBE_EITR_CNT_WDIS
;
989 IXGBE_WRITE_REG(hw
, IXGBE_EITR(v_idx
), itr_reg
);
992 static void ixgbe_set_itr_msix(struct ixgbe_q_vector
*q_vector
)
994 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
996 u8 current_itr
, ret_itr
;
997 int i
, r_idx
, v_idx
= q_vector
->v_idx
;
998 struct ixgbe_ring
*rx_ring
, *tx_ring
;
1000 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1001 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1002 tx_ring
= &(adapter
->tx_ring
[r_idx
]);
1003 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1005 tx_ring
->total_packets
,
1006 tx_ring
->total_bytes
);
1007 /* if the result for this queue would decrease interrupt
1008 * rate for this vector then use that result */
1009 q_vector
->tx_itr
= ((q_vector
->tx_itr
> ret_itr
) ?
1010 q_vector
->tx_itr
- 1 : ret_itr
);
1011 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1015 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1016 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1017 rx_ring
= &(adapter
->rx_ring
[r_idx
]);
1018 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1020 rx_ring
->total_packets
,
1021 rx_ring
->total_bytes
);
1022 /* if the result for this queue would decrease interrupt
1023 * rate for this vector then use that result */
1024 q_vector
->rx_itr
= ((q_vector
->rx_itr
> ret_itr
) ?
1025 q_vector
->rx_itr
- 1 : ret_itr
);
1026 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1030 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1032 switch (current_itr
) {
1033 /* counts and packets in update_itr are dependent on these numbers */
1034 case lowest_latency
:
1038 new_itr
= 20000; /* aka hwitr = ~200 */
1046 if (new_itr
!= q_vector
->eitr
) {
1049 /* save the algorithm value here, not the smoothed one */
1050 q_vector
->eitr
= new_itr
;
1051 /* do an exponential smoothing */
1052 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
1053 itr_reg
= EITR_INTS_PER_SEC_TO_REG(new_itr
);
1054 ixgbe_write_eitr(adapter
, v_idx
, itr_reg
);
1060 static void ixgbe_check_fan_failure(struct ixgbe_adapter
*adapter
, u32 eicr
)
1062 struct ixgbe_hw
*hw
= &adapter
->hw
;
1064 if ((adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) &&
1065 (eicr
& IXGBE_EICR_GPI_SDP1
)) {
1066 DPRINTK(PROBE
, CRIT
, "Fan has stopped, replace the adapter\n");
1067 /* write to clear the interrupt */
1068 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1072 static void ixgbe_check_sfp_event(struct ixgbe_adapter
*adapter
, u32 eicr
)
1074 struct ixgbe_hw
*hw
= &adapter
->hw
;
1076 if (eicr
& IXGBE_EICR_GPI_SDP1
) {
1077 /* Clear the interrupt */
1078 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1079 schedule_work(&adapter
->multispeed_fiber_task
);
1080 } else if (eicr
& IXGBE_EICR_GPI_SDP2
) {
1081 /* Clear the interrupt */
1082 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP2
);
1083 schedule_work(&adapter
->sfp_config_module_task
);
1085 /* Interrupt isn't for us... */
1090 static void ixgbe_check_lsc(struct ixgbe_adapter
*adapter
)
1092 struct ixgbe_hw
*hw
= &adapter
->hw
;
1095 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
1096 adapter
->link_check_timeout
= jiffies
;
1097 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1098 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_LSC
);
1099 schedule_work(&adapter
->watchdog_task
);
1103 static irqreturn_t
ixgbe_msix_lsc(int irq
, void *data
)
1105 struct net_device
*netdev
= data
;
1106 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1107 struct ixgbe_hw
*hw
= &adapter
->hw
;
1111 * Workaround for Silicon errata. Use clear-by-write instead
1112 * of clear-by-read. Reading with EICS will return the
1113 * interrupt causes without clearing, which later be done
1114 * with the write to EICR.
1116 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICS
);
1117 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, eicr
);
1119 if (eicr
& IXGBE_EICR_LSC
)
1120 ixgbe_check_lsc(adapter
);
1122 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
1123 ixgbe_check_fan_failure(adapter
, eicr
);
1125 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
1126 ixgbe_check_sfp_event(adapter
, eicr
);
1127 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1128 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMS_OTHER
);
1133 static irqreturn_t
ixgbe_msix_clean_tx(int irq
, void *data
)
1135 struct ixgbe_q_vector
*q_vector
= data
;
1136 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1137 struct ixgbe_ring
*tx_ring
;
1140 if (!q_vector
->txr_count
)
1143 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1144 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1145 tx_ring
= &(adapter
->tx_ring
[r_idx
]);
1146 #ifdef CONFIG_IXGBE_DCA
1147 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1148 ixgbe_update_tx_dca(adapter
, tx_ring
);
1150 tx_ring
->total_bytes
= 0;
1151 tx_ring
->total_packets
= 0;
1152 ixgbe_clean_tx_irq(adapter
, tx_ring
);
1153 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1161 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1163 * @data: pointer to our q_vector struct for this interrupt vector
1165 static irqreturn_t
ixgbe_msix_clean_rx(int irq
, void *data
)
1167 struct ixgbe_q_vector
*q_vector
= data
;
1168 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1169 struct ixgbe_ring
*rx_ring
;
1173 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1174 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1175 rx_ring
= &(adapter
->rx_ring
[r_idx
]);
1176 rx_ring
->total_bytes
= 0;
1177 rx_ring
->total_packets
= 0;
1178 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1182 if (!q_vector
->rxr_count
)
1185 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1186 rx_ring
= &(adapter
->rx_ring
[r_idx
]);
1187 /* disable interrupts on this vector only */
1188 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
1189 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, rx_ring
->v_idx
);
1190 else if (rx_ring
->v_idx
& 0xFFFFFFFF)
1191 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), rx_ring
->v_idx
);
1193 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1),
1194 (rx_ring
->v_idx
>> 32));
1195 napi_schedule(&q_vector
->napi
);
1200 static irqreturn_t
ixgbe_msix_clean_many(int irq
, void *data
)
1202 ixgbe_msix_clean_rx(irq
, data
);
1203 ixgbe_msix_clean_tx(irq
, data
);
1208 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter
*adapter
,
1213 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1214 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1215 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
1217 mask
= (qmask
& 0xFFFFFFFF);
1218 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(0), mask
);
1219 mask
= (qmask
>> 32);
1220 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(1), mask
);
1222 /* skip the flush */
1226 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1227 * @napi: napi struct with our devices info in it
1228 * @budget: amount of work driver is allowed to do this pass, in packets
1230 * This function is optimized for cleaning one queue only on a single
1233 static int ixgbe_clean_rxonly(struct napi_struct
*napi
, int budget
)
1235 struct ixgbe_q_vector
*q_vector
=
1236 container_of(napi
, struct ixgbe_q_vector
, napi
);
1237 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1238 struct ixgbe_ring
*rx_ring
= NULL
;
1242 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1243 rx_ring
= &(adapter
->rx_ring
[r_idx
]);
1244 #ifdef CONFIG_IXGBE_DCA
1245 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1246 ixgbe_update_rx_dca(adapter
, rx_ring
);
1249 ixgbe_clean_rx_irq(q_vector
, rx_ring
, &work_done
, budget
);
1251 /* If all Rx work done, exit the polling mode */
1252 if (work_done
< budget
) {
1253 napi_complete(napi
);
1254 if (adapter
->itr_setting
& 1)
1255 ixgbe_set_itr_msix(q_vector
);
1256 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1257 ixgbe_irq_enable_queues(adapter
, rx_ring
->v_idx
);
1264 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1265 * @napi: napi struct with our devices info in it
1266 * @budget: amount of work driver is allowed to do this pass, in packets
1268 * This function will clean more than one rx queue associated with a
1271 static int ixgbe_clean_rxonly_many(struct napi_struct
*napi
, int budget
)
1273 struct ixgbe_q_vector
*q_vector
=
1274 container_of(napi
, struct ixgbe_q_vector
, napi
);
1275 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1276 struct ixgbe_ring
*rx_ring
= NULL
;
1277 int work_done
= 0, i
;
1279 u64 enable_mask
= 0;
1281 /* attempt to distribute budget to each queue fairly, but don't allow
1282 * the budget to go below 1 because we'll exit polling */
1283 budget
/= (q_vector
->rxr_count
?: 1);
1284 budget
= max(budget
, 1);
1285 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1286 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1287 rx_ring
= &(adapter
->rx_ring
[r_idx
]);
1288 #ifdef CONFIG_IXGBE_DCA
1289 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1290 ixgbe_update_rx_dca(adapter
, rx_ring
);
1292 ixgbe_clean_rx_irq(q_vector
, rx_ring
, &work_done
, budget
);
1293 enable_mask
|= rx_ring
->v_idx
;
1294 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1298 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1299 rx_ring
= &(adapter
->rx_ring
[r_idx
]);
1300 /* If all Rx work done, exit the polling mode */
1301 if (work_done
< budget
) {
1302 napi_complete(napi
);
1303 if (adapter
->itr_setting
& 1)
1304 ixgbe_set_itr_msix(q_vector
);
1305 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1306 ixgbe_irq_enable_queues(adapter
, enable_mask
);
1312 static inline void map_vector_to_rxq(struct ixgbe_adapter
*a
, int v_idx
,
1315 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
1317 set_bit(r_idx
, q_vector
->rxr_idx
);
1318 q_vector
->rxr_count
++;
1319 a
->rx_ring
[r_idx
].v_idx
= (u64
)1 << v_idx
;
1322 static inline void map_vector_to_txq(struct ixgbe_adapter
*a
, int v_idx
,
1325 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
1327 set_bit(t_idx
, q_vector
->txr_idx
);
1328 q_vector
->txr_count
++;
1329 a
->tx_ring
[t_idx
].v_idx
= (u64
)1 << v_idx
;
1333 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1334 * @adapter: board private structure to initialize
1335 * @vectors: allotted vector count for descriptor rings
1337 * This function maps descriptor rings to the queue-specific vectors
1338 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1339 * one vector per ring/queue, but on a constrained vector budget, we
1340 * group the rings as "efficiently" as possible. You would add new
1341 * mapping configurations in here.
1343 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter
*adapter
,
1347 int rxr_idx
= 0, txr_idx
= 0;
1348 int rxr_remaining
= adapter
->num_rx_queues
;
1349 int txr_remaining
= adapter
->num_tx_queues
;
1354 /* No mapping required if MSI-X is disabled. */
1355 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
1359 * The ideal configuration...
1360 * We have enough vectors to map one per queue.
1362 if (vectors
== adapter
->num_rx_queues
+ adapter
->num_tx_queues
) {
1363 for (; rxr_idx
< rxr_remaining
; v_start
++, rxr_idx
++)
1364 map_vector_to_rxq(adapter
, v_start
, rxr_idx
);
1366 for (; txr_idx
< txr_remaining
; v_start
++, txr_idx
++)
1367 map_vector_to_txq(adapter
, v_start
, txr_idx
);
1373 * If we don't have enough vectors for a 1-to-1
1374 * mapping, we'll have to group them so there are
1375 * multiple queues per vector.
1377 /* Re-adjusting *qpv takes care of the remainder. */
1378 for (i
= v_start
; i
< vectors
; i
++) {
1379 rqpv
= DIV_ROUND_UP(rxr_remaining
, vectors
- i
);
1380 for (j
= 0; j
< rqpv
; j
++) {
1381 map_vector_to_rxq(adapter
, i
, rxr_idx
);
1386 for (i
= v_start
; i
< vectors
; i
++) {
1387 tqpv
= DIV_ROUND_UP(txr_remaining
, vectors
- i
);
1388 for (j
= 0; j
< tqpv
; j
++) {
1389 map_vector_to_txq(adapter
, i
, txr_idx
);
1400 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1401 * @adapter: board private structure
1403 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1404 * interrupts from the kernel.
1406 static int ixgbe_request_msix_irqs(struct ixgbe_adapter
*adapter
)
1408 struct net_device
*netdev
= adapter
->netdev
;
1409 irqreturn_t (*handler
)(int, void *);
1410 int i
, vector
, q_vectors
, err
;
1413 /* Decrement for Other and TCP Timer vectors */
1414 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1416 /* Map the Tx/Rx rings to the vectors we were allotted. */
1417 err
= ixgbe_map_rings_to_vectors(adapter
, q_vectors
);
1421 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1422 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1423 &ixgbe_msix_clean_many)
1424 for (vector
= 0; vector
< q_vectors
; vector
++) {
1425 handler
= SET_HANDLER(adapter
->q_vector
[vector
]);
1427 if(handler
== &ixgbe_msix_clean_rx
) {
1428 sprintf(adapter
->name
[vector
], "%s-%s-%d",
1429 netdev
->name
, "rx", ri
++);
1431 else if(handler
== &ixgbe_msix_clean_tx
) {
1432 sprintf(adapter
->name
[vector
], "%s-%s-%d",
1433 netdev
->name
, "tx", ti
++);
1436 sprintf(adapter
->name
[vector
], "%s-%s-%d",
1437 netdev
->name
, "TxRx", vector
);
1439 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
1440 handler
, 0, adapter
->name
[vector
],
1441 adapter
->q_vector
[vector
]);
1444 "request_irq failed for MSIX interrupt "
1445 "Error: %d\n", err
);
1446 goto free_queue_irqs
;
1450 sprintf(adapter
->name
[vector
], "%s:lsc", netdev
->name
);
1451 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
1452 &ixgbe_msix_lsc
, 0, adapter
->name
[vector
], netdev
);
1455 "request_irq for msix_lsc failed: %d\n", err
);
1456 goto free_queue_irqs
;
1462 for (i
= vector
- 1; i
>= 0; i
--)
1463 free_irq(adapter
->msix_entries
[--vector
].vector
,
1464 adapter
->q_vector
[i
]);
1465 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
1466 pci_disable_msix(adapter
->pdev
);
1467 kfree(adapter
->msix_entries
);
1468 adapter
->msix_entries
= NULL
;
1473 static void ixgbe_set_itr(struct ixgbe_adapter
*adapter
)
1475 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
1477 u32 new_itr
= q_vector
->eitr
;
1478 struct ixgbe_ring
*rx_ring
= &adapter
->rx_ring
[0];
1479 struct ixgbe_ring
*tx_ring
= &adapter
->tx_ring
[0];
1481 q_vector
->tx_itr
= ixgbe_update_itr(adapter
, new_itr
,
1483 tx_ring
->total_packets
,
1484 tx_ring
->total_bytes
);
1485 q_vector
->rx_itr
= ixgbe_update_itr(adapter
, new_itr
,
1487 rx_ring
->total_packets
,
1488 rx_ring
->total_bytes
);
1490 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1492 switch (current_itr
) {
1493 /* counts and packets in update_itr are dependent on these numbers */
1494 case lowest_latency
:
1498 new_itr
= 20000; /* aka hwitr = ~200 */
1507 if (new_itr
!= q_vector
->eitr
) {
1510 /* save the algorithm value here, not the smoothed one */
1511 q_vector
->eitr
= new_itr
;
1512 /* do an exponential smoothing */
1513 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
1514 itr_reg
= EITR_INTS_PER_SEC_TO_REG(new_itr
);
1515 ixgbe_write_eitr(adapter
, 0, itr_reg
);
1522 * ixgbe_irq_enable - Enable default interrupt generation settings
1523 * @adapter: board private structure
1525 static inline void ixgbe_irq_enable(struct ixgbe_adapter
*adapter
)
1529 mask
= (IXGBE_EIMS_ENABLE_MASK
& ~IXGBE_EIMS_RTX_QUEUE
);
1530 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
1531 mask
|= IXGBE_EIMS_GPI_SDP1
;
1532 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
1533 mask
|= IXGBE_EIMS_ECC
;
1534 mask
|= IXGBE_EIMS_GPI_SDP1
;
1535 mask
|= IXGBE_EIMS_GPI_SDP2
;
1538 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
1539 ixgbe_irq_enable_queues(adapter
, ~0);
1540 IXGBE_WRITE_FLUSH(&adapter
->hw
);
1544 * ixgbe_intr - legacy mode Interrupt Handler
1545 * @irq: interrupt number
1546 * @data: pointer to a network interface device structure
1548 static irqreturn_t
ixgbe_intr(int irq
, void *data
)
1550 struct net_device
*netdev
= data
;
1551 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1552 struct ixgbe_hw
*hw
= &adapter
->hw
;
1553 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
1557 * Workaround for silicon errata. Mask the interrupts
1558 * before the read of EICR.
1560 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
1562 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1563 * therefore no explict interrupt disable is necessary */
1564 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICR
);
1566 /* shared interrupt alert!
1567 * make sure interrupts are enabled because the read will
1568 * have disabled interrupts due to EIAM */
1569 ixgbe_irq_enable(adapter
);
1570 return IRQ_NONE
; /* Not our interrupt */
1573 if (eicr
& IXGBE_EICR_LSC
)
1574 ixgbe_check_lsc(adapter
);
1576 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
1577 ixgbe_check_sfp_event(adapter
, eicr
);
1579 ixgbe_check_fan_failure(adapter
, eicr
);
1581 if (napi_schedule_prep(&(q_vector
->napi
))) {
1582 adapter
->tx_ring
[0].total_packets
= 0;
1583 adapter
->tx_ring
[0].total_bytes
= 0;
1584 adapter
->rx_ring
[0].total_packets
= 0;
1585 adapter
->rx_ring
[0].total_bytes
= 0;
1586 /* would disable interrupts here but EIAM disabled it */
1587 __napi_schedule(&(q_vector
->napi
));
1593 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter
*adapter
)
1595 int i
, q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1597 for (i
= 0; i
< q_vectors
; i
++) {
1598 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
1599 bitmap_zero(q_vector
->rxr_idx
, MAX_RX_QUEUES
);
1600 bitmap_zero(q_vector
->txr_idx
, MAX_TX_QUEUES
);
1601 q_vector
->rxr_count
= 0;
1602 q_vector
->txr_count
= 0;
1607 * ixgbe_request_irq - initialize interrupts
1608 * @adapter: board private structure
1610 * Attempts to configure interrupts using the best available
1611 * capabilities of the hardware and kernel.
1613 static int ixgbe_request_irq(struct ixgbe_adapter
*adapter
)
1615 struct net_device
*netdev
= adapter
->netdev
;
1618 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
1619 err
= ixgbe_request_msix_irqs(adapter
);
1620 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
1621 err
= request_irq(adapter
->pdev
->irq
, &ixgbe_intr
, 0,
1622 netdev
->name
, netdev
);
1624 err
= request_irq(adapter
->pdev
->irq
, &ixgbe_intr
, IRQF_SHARED
,
1625 netdev
->name
, netdev
);
1629 DPRINTK(PROBE
, ERR
, "request_irq failed, Error %d\n", err
);
1634 static void ixgbe_free_irq(struct ixgbe_adapter
*adapter
)
1636 struct net_device
*netdev
= adapter
->netdev
;
1638 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
1641 q_vectors
= adapter
->num_msix_vectors
;
1644 free_irq(adapter
->msix_entries
[i
].vector
, netdev
);
1647 for (; i
>= 0; i
--) {
1648 free_irq(adapter
->msix_entries
[i
].vector
,
1649 adapter
->q_vector
[i
]);
1652 ixgbe_reset_q_vectors(adapter
);
1654 free_irq(adapter
->pdev
->irq
, netdev
);
1659 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1660 * @adapter: board private structure
1662 static inline void ixgbe_irq_disable(struct ixgbe_adapter
*adapter
)
1664 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1665 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, ~0);
1667 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, 0xFFFF0000);
1668 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), ~0);
1669 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), ~0);
1671 IXGBE_WRITE_FLUSH(&adapter
->hw
);
1672 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
1674 for (i
= 0; i
< adapter
->num_msix_vectors
; i
++)
1675 synchronize_irq(adapter
->msix_entries
[i
].vector
);
1677 synchronize_irq(adapter
->pdev
->irq
);
1682 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1685 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter
*adapter
)
1687 struct ixgbe_hw
*hw
= &adapter
->hw
;
1689 IXGBE_WRITE_REG(hw
, IXGBE_EITR(0),
1690 EITR_INTS_PER_SEC_TO_REG(adapter
->eitr_param
));
1692 ixgbe_set_ivar(adapter
, 0, 0, 0);
1693 ixgbe_set_ivar(adapter
, 1, 0, 0);
1695 map_vector_to_rxq(adapter
, 0, 0);
1696 map_vector_to_txq(adapter
, 0, 0);
1698 DPRINTK(HW
, INFO
, "Legacy interrupt IVAR setup done\n");
1702 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1703 * @adapter: board private structure
1705 * Configure the Tx unit of the MAC after a reset.
1707 static void ixgbe_configure_tx(struct ixgbe_adapter
*adapter
)
1710 struct ixgbe_hw
*hw
= &adapter
->hw
;
1711 u32 i
, j
, tdlen
, txctrl
;
1713 /* Setup the HW Tx Head and Tail descriptor pointers */
1714 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
1715 struct ixgbe_ring
*ring
= &adapter
->tx_ring
[i
];
1718 tdlen
= ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
1719 IXGBE_WRITE_REG(hw
, IXGBE_TDBAL(j
),
1720 (tdba
& DMA_BIT_MASK(32)));
1721 IXGBE_WRITE_REG(hw
, IXGBE_TDBAH(j
), (tdba
>> 32));
1722 IXGBE_WRITE_REG(hw
, IXGBE_TDLEN(j
), tdlen
);
1723 IXGBE_WRITE_REG(hw
, IXGBE_TDH(j
), 0);
1724 IXGBE_WRITE_REG(hw
, IXGBE_TDT(j
), 0);
1725 adapter
->tx_ring
[i
].head
= IXGBE_TDH(j
);
1726 adapter
->tx_ring
[i
].tail
= IXGBE_TDT(j
);
1727 /* Disable Tx Head Writeback RO bit, since this hoses
1728 * bookkeeping if things aren't delivered in order.
1730 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(j
));
1731 txctrl
&= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN
;
1732 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(j
), txctrl
);
1734 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
1735 /* We enable 8 traffic classes, DCB only */
1736 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
1737 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
, (IXGBE_MTQC_RT_ENA
|
1738 IXGBE_MTQC_8TC_8TQ
));
1742 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1744 static void ixgbe_configure_srrctl(struct ixgbe_adapter
*adapter
, int index
)
1746 struct ixgbe_ring
*rx_ring
;
1750 struct ixgbe_ring_feature
*feature
= adapter
->ring_feature
;
1752 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
1753 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
1754 int dcb_i
= feature
[RING_F_DCB
].indices
;
1756 queue0
= index
>> 4;
1757 else if (dcb_i
== 4)
1758 queue0
= index
>> 5;
1760 dev_err(&adapter
->pdev
->dev
, "Invalid DCB "
1763 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
1764 struct ixgbe_ring_feature
*f
;
1766 rx_ring
= &adapter
->rx_ring
[queue0
];
1767 f
= &adapter
->ring_feature
[RING_F_FCOE
];
1768 if ((queue0
== 0) && (index
> rx_ring
->reg_idx
))
1769 queue0
= f
->mask
+ index
-
1770 rx_ring
->reg_idx
- 1;
1772 #endif /* IXGBE_FCOE */
1777 mask
= (unsigned long) feature
[RING_F_RSS
].mask
;
1778 queue0
= index
& mask
;
1779 index
= index
& mask
;
1782 rx_ring
= &adapter
->rx_ring
[queue0
];
1784 srrctl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SRRCTL(index
));
1786 srrctl
&= ~IXGBE_SRRCTL_BSIZEHDR_MASK
;
1787 srrctl
&= ~IXGBE_SRRCTL_BSIZEPKT_MASK
;
1789 srrctl
|= (IXGBE_RX_HDR_SIZE
<< IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT
) &
1790 IXGBE_SRRCTL_BSIZEHDR_MASK
;
1792 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
1793 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1794 srrctl
|= IXGBE_MAX_RXBUFFER
>> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
1796 srrctl
|= (PAGE_SIZE
/ 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
1798 srrctl
|= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS
;
1800 srrctl
|= ALIGN(rx_ring
->rx_buf_len
, 1024) >>
1801 IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
1802 srrctl
|= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF
;
1805 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_SRRCTL(index
), srrctl
);
1808 static u32
ixgbe_setup_mrqc(struct ixgbe_adapter
*adapter
)
1813 if (!(adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
1816 mask
= adapter
->flags
& (IXGBE_FLAG_RSS_ENABLED
1817 #ifdef CONFIG_IXGBE_DCB
1818 | IXGBE_FLAG_DCB_ENABLED
1823 case (IXGBE_FLAG_RSS_ENABLED
):
1824 mrqc
= IXGBE_MRQC_RSSEN
;
1826 #ifdef CONFIG_IXGBE_DCB
1827 case (IXGBE_FLAG_DCB_ENABLED
):
1828 mrqc
= IXGBE_MRQC_RT8TCEN
;
1830 #endif /* CONFIG_IXGBE_DCB */
1839 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1840 * @adapter: board private structure
1842 * Configure the Rx unit of the MAC after a reset.
1844 static void ixgbe_configure_rx(struct ixgbe_adapter
*adapter
)
1847 struct ixgbe_hw
*hw
= &adapter
->hw
;
1848 struct net_device
*netdev
= adapter
->netdev
;
1849 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
1851 u32 rdlen
, rxctrl
, rxcsum
;
1852 static const u32 seed
[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1853 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1854 0x6A3E67EA, 0x14364D17, 0x3BED200D};
1856 u32 reta
= 0, mrqc
= 0;
1861 /* Decide whether to use packet split mode or not */
1862 adapter
->flags
|= IXGBE_FLAG_RX_PS_ENABLED
;
1865 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
1866 adapter
->flags
&= ~IXGBE_FLAG_RX_PS_ENABLED
;
1867 #endif /* IXGBE_FCOE */
1869 /* Set the RX buffer length according to the mode */
1870 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
1871 rx_buf_len
= IXGBE_RX_HDR_SIZE
;
1872 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
1873 /* PSRTYPE must be initialized in 82599 */
1874 u32 psrtype
= IXGBE_PSRTYPE_TCPHDR
|
1875 IXGBE_PSRTYPE_UDPHDR
|
1876 IXGBE_PSRTYPE_IPV4HDR
|
1877 IXGBE_PSRTYPE_IPV6HDR
|
1878 IXGBE_PSRTYPE_L2HDR
;
1879 IXGBE_WRITE_REG(hw
, IXGBE_PSRTYPE(0), psrtype
);
1882 if (!(adapter
->flags
& IXGBE_FLAG_RSC_ENABLED
) &&
1883 (netdev
->mtu
<= ETH_DATA_LEN
))
1884 rx_buf_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
1886 rx_buf_len
= ALIGN(max_frame
, 1024);
1889 fctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_FCTRL
);
1890 fctrl
|= IXGBE_FCTRL_BAM
;
1891 fctrl
|= IXGBE_FCTRL_DPF
; /* discard pause frames when FC enabled */
1892 fctrl
|= IXGBE_FCTRL_PMCF
;
1893 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_FCTRL
, fctrl
);
1895 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
1896 if (adapter
->netdev
->mtu
<= ETH_DATA_LEN
)
1897 hlreg0
&= ~IXGBE_HLREG0_JUMBOEN
;
1899 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
1901 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
1902 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
1904 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
1906 rdlen
= adapter
->rx_ring
[0].count
* sizeof(union ixgbe_adv_rx_desc
);
1907 /* disable receives while setting up the descriptors */
1908 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
1909 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
1912 * Setup the HW Rx Head and Tail Descriptor Pointers and
1913 * the Base and Length of the Rx Descriptor Ring
1915 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
1916 rdba
= adapter
->rx_ring
[i
].dma
;
1917 j
= adapter
->rx_ring
[i
].reg_idx
;
1918 IXGBE_WRITE_REG(hw
, IXGBE_RDBAL(j
), (rdba
& DMA_BIT_MASK(32)));
1919 IXGBE_WRITE_REG(hw
, IXGBE_RDBAH(j
), (rdba
>> 32));
1920 IXGBE_WRITE_REG(hw
, IXGBE_RDLEN(j
), rdlen
);
1921 IXGBE_WRITE_REG(hw
, IXGBE_RDH(j
), 0);
1922 IXGBE_WRITE_REG(hw
, IXGBE_RDT(j
), 0);
1923 adapter
->rx_ring
[i
].head
= IXGBE_RDH(j
);
1924 adapter
->rx_ring
[i
].tail
= IXGBE_RDT(j
);
1925 adapter
->rx_ring
[i
].rx_buf_len
= rx_buf_len
;
1928 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
1929 struct ixgbe_ring_feature
*f
;
1930 f
= &adapter
->ring_feature
[RING_F_FCOE
];
1931 if ((rx_buf_len
< IXGBE_FCOE_JUMBO_FRAME_SIZE
) &&
1932 (i
>= f
->mask
) && (i
< f
->mask
+ f
->indices
))
1933 adapter
->rx_ring
[i
].rx_buf_len
=
1934 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
1937 #endif /* IXGBE_FCOE */
1938 ixgbe_configure_srrctl(adapter
, j
);
1941 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
1943 * For VMDq support of different descriptor types or
1944 * buffer sizes through the use of multiple SRRCTL
1945 * registers, RDRXCTL.MVMEN must be set to 1
1947 * also, the manual doesn't mention it clearly but DCA hints
1948 * will only use queue 0's tags unless this bit is set. Side
1949 * effects of setting this bit are only that SRRCTL must be
1950 * fully programmed [0..15]
1952 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
1953 rdrxctl
|= IXGBE_RDRXCTL_MVMEN
;
1954 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
1957 /* Program MRQC for the distribution of queues */
1958 mrqc
= ixgbe_setup_mrqc(adapter
);
1960 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
1961 /* Fill out redirection table */
1962 for (i
= 0, j
= 0; i
< 128; i
++, j
++) {
1963 if (j
== adapter
->ring_feature
[RING_F_RSS
].indices
)
1965 /* reta = 4-byte sliding window of
1966 * 0x00..(indices-1)(indices-1)00..etc. */
1967 reta
= (reta
<< 8) | (j
* 0x11);
1969 IXGBE_WRITE_REG(hw
, IXGBE_RETA(i
>> 2), reta
);
1972 /* Fill out hash function seeds */
1973 for (i
= 0; i
< 10; i
++)
1974 IXGBE_WRITE_REG(hw
, IXGBE_RSSRK(i
), seed
[i
]);
1976 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
1977 mrqc
|= IXGBE_MRQC_RSSEN
;
1978 /* Perform hash on these packet types */
1979 mrqc
|= IXGBE_MRQC_RSS_FIELD_IPV4
1980 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1981 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1982 | IXGBE_MRQC_RSS_FIELD_IPV6
1983 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1984 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
;
1986 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, mrqc
);
1988 rxcsum
= IXGBE_READ_REG(hw
, IXGBE_RXCSUM
);
1990 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
||
1991 adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
) {
1992 /* Disable indicating checksum in descriptor, enables
1994 rxcsum
|= IXGBE_RXCSUM_PCSD
;
1996 if (!(rxcsum
& IXGBE_RXCSUM_PCSD
)) {
1997 /* Enable IPv4 payload checksum for UDP fragments
1998 * if PCSD is not set */
1999 rxcsum
|= IXGBE_RXCSUM_IPPCSE
;
2002 IXGBE_WRITE_REG(hw
, IXGBE_RXCSUM
, rxcsum
);
2004 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2005 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
2006 rdrxctl
|= IXGBE_RDRXCTL_CRCSTRIP
;
2007 rdrxctl
&= ~IXGBE_RDRXCTL_RSCFRSTSIZE
;
2008 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
2011 if (adapter
->flags
& IXGBE_FLAG_RSC_ENABLED
) {
2012 /* Enable 82599 HW-RSC */
2013 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2014 j
= adapter
->rx_ring
[i
].reg_idx
;
2015 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(j
));
2016 rscctrl
|= IXGBE_RSCCTL_RSCEN
;
2018 * we must limit the number of descriptors so that the
2019 * total size of max desc * buf_len is not greater
2022 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
2023 #if (MAX_SKB_FRAGS > 16)
2024 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2025 #elif (MAX_SKB_FRAGS > 8)
2026 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2027 #elif (MAX_SKB_FRAGS > 4)
2028 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2030 rscctrl
|= IXGBE_RSCCTL_MAXDESC_1
;
2033 if (rx_buf_len
< IXGBE_RXBUFFER_4096
)
2034 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2035 else if (rx_buf_len
< IXGBE_RXBUFFER_8192
)
2036 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2038 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2040 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(j
), rscctrl
);
2042 /* Disable RSC for ACK packets */
2043 IXGBE_WRITE_REG(hw
, IXGBE_RSCDBU
,
2044 (IXGBE_RSCDBU_RSCACKDIS
| IXGBE_READ_REG(hw
, IXGBE_RSCDBU
)));
2048 static void ixgbe_vlan_rx_add_vid(struct net_device
*netdev
, u16 vid
)
2050 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2051 struct ixgbe_hw
*hw
= &adapter
->hw
;
2053 /* add VID to filter table */
2054 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, 0, true);
2057 static void ixgbe_vlan_rx_kill_vid(struct net_device
*netdev
, u16 vid
)
2059 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2060 struct ixgbe_hw
*hw
= &adapter
->hw
;
2062 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2063 ixgbe_irq_disable(adapter
);
2065 vlan_group_set_device(adapter
->vlgrp
, vid
, NULL
);
2067 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2068 ixgbe_irq_enable(adapter
);
2070 /* remove VID from filter table */
2071 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, 0, false);
2074 static void ixgbe_vlan_rx_register(struct net_device
*netdev
,
2075 struct vlan_group
*grp
)
2077 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2081 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2082 ixgbe_irq_disable(adapter
);
2083 adapter
->vlgrp
= grp
;
2086 * For a DCB driver, always enable VLAN tag stripping so we can
2087 * still receive traffic from a DCB-enabled host even if we're
2090 ctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_VLNCTRL
);
2091 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
2092 ctrl
|= IXGBE_VLNCTRL_VME
| IXGBE_VLNCTRL_VFE
;
2093 ctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2094 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_VLNCTRL
, ctrl
);
2095 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
2096 ctrl
|= IXGBE_VLNCTRL_VFE
;
2097 /* enable VLAN tag insert/strip */
2098 ctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_VLNCTRL
);
2099 ctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2100 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_VLNCTRL
, ctrl
);
2101 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2102 j
= adapter
->rx_ring
[i
].reg_idx
;
2103 ctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_RXDCTL(j
));
2104 ctrl
|= IXGBE_RXDCTL_VME
;
2105 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_RXDCTL(j
), ctrl
);
2108 ixgbe_vlan_rx_add_vid(netdev
, 0);
2110 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2111 ixgbe_irq_enable(adapter
);
2114 static void ixgbe_restore_vlan(struct ixgbe_adapter
*adapter
)
2116 ixgbe_vlan_rx_register(adapter
->netdev
, adapter
->vlgrp
);
2118 if (adapter
->vlgrp
) {
2120 for (vid
= 0; vid
< VLAN_GROUP_ARRAY_LEN
; vid
++) {
2121 if (!vlan_group_get_device(adapter
->vlgrp
, vid
))
2123 ixgbe_vlan_rx_add_vid(adapter
->netdev
, vid
);
2128 static u8
*ixgbe_addr_list_itr(struct ixgbe_hw
*hw
, u8
**mc_addr_ptr
, u32
*vmdq
)
2130 struct dev_mc_list
*mc_ptr
;
2131 u8
*addr
= *mc_addr_ptr
;
2134 mc_ptr
= container_of(addr
, struct dev_mc_list
, dmi_addr
[0]);
2136 *mc_addr_ptr
= mc_ptr
->next
->dmi_addr
;
2138 *mc_addr_ptr
= NULL
;
2144 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2145 * @netdev: network interface device structure
2147 * The set_rx_method entry point is called whenever the unicast/multicast
2148 * address list or the network interface flags are updated. This routine is
2149 * responsible for configuring the hardware for proper unicast, multicast and
2152 static void ixgbe_set_rx_mode(struct net_device
*netdev
)
2154 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2155 struct ixgbe_hw
*hw
= &adapter
->hw
;
2157 u8
*addr_list
= NULL
;
2160 /* Check for Promiscuous and All Multicast modes */
2162 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
2163 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
2165 if (netdev
->flags
& IFF_PROMISC
) {
2166 hw
->addr_ctrl
.user_set_promisc
= 1;
2167 fctrl
|= (IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
2168 vlnctrl
&= ~IXGBE_VLNCTRL_VFE
;
2170 if (netdev
->flags
& IFF_ALLMULTI
) {
2171 fctrl
|= IXGBE_FCTRL_MPE
;
2172 fctrl
&= ~IXGBE_FCTRL_UPE
;
2174 fctrl
&= ~(IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
2176 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
2177 hw
->addr_ctrl
.user_set_promisc
= 0;
2180 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
2181 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2183 /* reprogram secondary unicast list */
2184 addr_count
= netdev
->uc_count
;
2186 addr_list
= netdev
->uc_list
->dmi_addr
;
2187 hw
->mac
.ops
.update_uc_addr_list(hw
, addr_list
, addr_count
,
2188 ixgbe_addr_list_itr
);
2190 /* reprogram multicast list */
2191 addr_count
= netdev
->mc_count
;
2193 addr_list
= netdev
->mc_list
->dmi_addr
;
2194 hw
->mac
.ops
.update_mc_addr_list(hw
, addr_list
, addr_count
,
2195 ixgbe_addr_list_itr
);
2198 static void ixgbe_napi_enable_all(struct ixgbe_adapter
*adapter
)
2201 struct ixgbe_q_vector
*q_vector
;
2202 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2204 /* legacy and MSI only use one vector */
2205 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2208 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
2209 struct napi_struct
*napi
;
2210 q_vector
= adapter
->q_vector
[q_idx
];
2211 if (!q_vector
->rxr_count
)
2213 napi
= &q_vector
->napi
;
2214 if ((adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) &&
2215 (q_vector
->rxr_count
> 1))
2216 napi
->poll
= &ixgbe_clean_rxonly_many
;
2222 static void ixgbe_napi_disable_all(struct ixgbe_adapter
*adapter
)
2225 struct ixgbe_q_vector
*q_vector
;
2226 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2228 /* legacy and MSI only use one vector */
2229 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2232 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
2233 q_vector
= adapter
->q_vector
[q_idx
];
2234 if (!q_vector
->rxr_count
)
2236 napi_disable(&q_vector
->napi
);
2240 #ifdef CONFIG_IXGBE_DCB
2242 * ixgbe_configure_dcb - Configure DCB hardware
2243 * @adapter: ixgbe adapter struct
2245 * This is called by the driver on open to configure the DCB hardware.
2246 * This is also called by the gennetlink interface when reconfiguring
2249 static void ixgbe_configure_dcb(struct ixgbe_adapter
*adapter
)
2251 struct ixgbe_hw
*hw
= &adapter
->hw
;
2252 u32 txdctl
, vlnctrl
;
2255 ixgbe_dcb_check_config(&adapter
->dcb_cfg
);
2256 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, DCB_TX_CONFIG
);
2257 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, DCB_RX_CONFIG
);
2259 /* reconfigure the hardware */
2260 ixgbe_dcb_hw_config(&adapter
->hw
, &adapter
->dcb_cfg
);
2262 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2263 j
= adapter
->tx_ring
[i
].reg_idx
;
2264 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2265 /* PThresh workaround for Tx hang with DFP enabled. */
2267 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
2269 /* Enable VLAN tag insert/strip */
2270 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
2271 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
2272 vlnctrl
|= IXGBE_VLNCTRL_VME
| IXGBE_VLNCTRL_VFE
;
2273 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2274 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2275 } else if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2276 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
2277 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2278 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2279 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2280 j
= adapter
->rx_ring
[i
].reg_idx
;
2281 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
2282 vlnctrl
|= IXGBE_RXDCTL_VME
;
2283 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
2286 hw
->mac
.ops
.set_vfta(&adapter
->hw
, 0, 0, true);
2290 static void ixgbe_configure(struct ixgbe_adapter
*adapter
)
2292 struct net_device
*netdev
= adapter
->netdev
;
2295 ixgbe_set_rx_mode(netdev
);
2297 ixgbe_restore_vlan(adapter
);
2298 #ifdef CONFIG_IXGBE_DCB
2299 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
2300 netif_set_gso_max_size(netdev
, 32768);
2301 ixgbe_configure_dcb(adapter
);
2303 netif_set_gso_max_size(netdev
, 65536);
2306 netif_set_gso_max_size(netdev
, 65536);
2310 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
2311 ixgbe_configure_fcoe(adapter
);
2313 #endif /* IXGBE_FCOE */
2314 ixgbe_configure_tx(adapter
);
2315 ixgbe_configure_rx(adapter
);
2316 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
2317 ixgbe_alloc_rx_buffers(adapter
, &adapter
->rx_ring
[i
],
2318 (adapter
->rx_ring
[i
].count
- 1));
2321 static inline bool ixgbe_is_sfp(struct ixgbe_hw
*hw
)
2323 switch (hw
->phy
.type
) {
2324 case ixgbe_phy_sfp_avago
:
2325 case ixgbe_phy_sfp_ftl
:
2326 case ixgbe_phy_sfp_intel
:
2327 case ixgbe_phy_sfp_unknown
:
2328 case ixgbe_phy_tw_tyco
:
2329 case ixgbe_phy_tw_unknown
:
2337 * ixgbe_sfp_link_config - set up SFP+ link
2338 * @adapter: pointer to private adapter struct
2340 static void ixgbe_sfp_link_config(struct ixgbe_adapter
*adapter
)
2342 struct ixgbe_hw
*hw
= &adapter
->hw
;
2344 if (hw
->phy
.multispeed_fiber
) {
2346 * In multispeed fiber setups, the device may not have
2347 * had a physical connection when the driver loaded.
2348 * If that's the case, the initial link configuration
2349 * couldn't get the MAC into 10G or 1G mode, so we'll
2350 * never have a link status change interrupt fire.
2351 * We need to try and force an autonegotiation
2352 * session, then bring up link.
2354 hw
->mac
.ops
.setup_sfp(hw
);
2355 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
2356 schedule_work(&adapter
->multispeed_fiber_task
);
2359 * Direct Attach Cu and non-multispeed fiber modules
2360 * still need to be configured properly prior to
2363 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_MOD_TASK
))
2364 schedule_work(&adapter
->sfp_config_module_task
);
2369 * ixgbe_non_sfp_link_config - set up non-SFP+ link
2370 * @hw: pointer to private hardware struct
2372 * Returns 0 on success, negative on failure
2374 static int ixgbe_non_sfp_link_config(struct ixgbe_hw
*hw
)
2377 bool link_up
= false;
2378 u32 ret
= IXGBE_ERR_LINK_SETUP
;
2380 if (hw
->mac
.ops
.check_link
)
2381 ret
= hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
2386 if (hw
->mac
.ops
.get_link_capabilities
)
2387 ret
= hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
,
2392 if (hw
->mac
.ops
.setup_link_speed
)
2393 ret
= hw
->mac
.ops
.setup_link_speed(hw
, autoneg
, true, link_up
);
2398 #define IXGBE_MAX_RX_DESC_POLL 10
2399 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter
*adapter
,
2402 int j
= adapter
->rx_ring
[rxr
].reg_idx
;
2405 for (k
= 0; k
< IXGBE_MAX_RX_DESC_POLL
; k
++) {
2406 if (IXGBE_READ_REG(&adapter
->hw
,
2407 IXGBE_RXDCTL(j
)) & IXGBE_RXDCTL_ENABLE
)
2412 if (k
>= IXGBE_MAX_RX_DESC_POLL
) {
2413 DPRINTK(DRV
, ERR
, "RXDCTL.ENABLE on Rx queue %d "
2414 "not set within the polling period\n", rxr
);
2416 ixgbe_release_rx_desc(&adapter
->hw
, &adapter
->rx_ring
[rxr
],
2417 (adapter
->rx_ring
[rxr
].count
- 1));
2420 static int ixgbe_up_complete(struct ixgbe_adapter
*adapter
)
2422 struct net_device
*netdev
= adapter
->netdev
;
2423 struct ixgbe_hw
*hw
= &adapter
->hw
;
2425 int num_rx_rings
= adapter
->num_rx_queues
;
2427 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
2428 u32 txdctl
, rxdctl
, mhadd
;
2432 ixgbe_get_hw_control(adapter
);
2434 if ((adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) ||
2435 (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
)) {
2436 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2437 gpie
= (IXGBE_GPIE_MSIX_MODE
| IXGBE_GPIE_EIAME
|
2438 IXGBE_GPIE_PBA_SUPPORT
| IXGBE_GPIE_OCD
);
2443 /* XXX: to interrupt immediately for EICS writes, enable this */
2444 /* gpie |= IXGBE_GPIE_EIMEN; */
2445 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
2448 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)) {
2449 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2450 * specifically only auto mask tx and rx interrupts */
2451 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
2454 /* Enable fan failure interrupt if media type is copper */
2455 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
2456 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
2457 gpie
|= IXGBE_SDP1_GPIEN
;
2458 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
2461 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2462 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
2463 gpie
|= IXGBE_SDP1_GPIEN
;
2464 gpie
|= IXGBE_SDP2_GPIEN
;
2465 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
2469 /* adjust max frame to be able to do baby jumbo for FCoE */
2470 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
2471 (max_frame
< IXGBE_FCOE_JUMBO_FRAME_SIZE
))
2472 max_frame
= IXGBE_FCOE_JUMBO_FRAME_SIZE
;
2474 #endif /* IXGBE_FCOE */
2475 mhadd
= IXGBE_READ_REG(hw
, IXGBE_MHADD
);
2476 if (max_frame
!= (mhadd
>> IXGBE_MHADD_MFS_SHIFT
)) {
2477 mhadd
&= ~IXGBE_MHADD_MFS_MASK
;
2478 mhadd
|= max_frame
<< IXGBE_MHADD_MFS_SHIFT
;
2480 IXGBE_WRITE_REG(hw
, IXGBE_MHADD
, mhadd
);
2483 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2484 j
= adapter
->tx_ring
[i
].reg_idx
;
2485 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2486 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2487 txdctl
|= (8 << 16);
2488 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
2491 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2492 /* DMATXCTL.EN must be set after all Tx queue config is done */
2493 dmatxctl
= IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
);
2494 dmatxctl
|= IXGBE_DMATXCTL_TE
;
2495 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
, dmatxctl
);
2497 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2498 j
= adapter
->tx_ring
[i
].reg_idx
;
2499 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2500 txdctl
|= IXGBE_TXDCTL_ENABLE
;
2501 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
2504 for (i
= 0; i
< num_rx_rings
; i
++) {
2505 j
= adapter
->rx_ring
[i
].reg_idx
;
2506 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
2507 /* enable PTHRESH=32 descriptors (half the internal cache)
2508 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2509 * this also removes a pesky rx_no_buffer_count increment */
2511 rxdctl
|= IXGBE_RXDCTL_ENABLE
;
2512 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), rxdctl
);
2513 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
2514 ixgbe_rx_desc_queue_enable(adapter
, i
);
2516 /* enable all receives */
2517 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
2518 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2519 rxdctl
|= (IXGBE_RXCTRL_DMBYPS
| IXGBE_RXCTRL_RXEN
);
2521 rxdctl
|= IXGBE_RXCTRL_RXEN
;
2522 hw
->mac
.ops
.enable_rx_dma(hw
, rxdctl
);
2524 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
2525 ixgbe_configure_msix(adapter
);
2527 ixgbe_configure_msi_and_legacy(adapter
);
2529 clear_bit(__IXGBE_DOWN
, &adapter
->state
);
2530 ixgbe_napi_enable_all(adapter
);
2532 /* clear any pending interrupts, may auto mask */
2533 IXGBE_READ_REG(hw
, IXGBE_EICR
);
2535 ixgbe_irq_enable(adapter
);
2538 * If this adapter has a fan, check to see if we had a failure
2539 * before we enabled the interrupt.
2541 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
2542 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
2543 if (esdp
& IXGBE_ESDP_SDP1
)
2545 "Fan has stopped, replace the adapter\n");
2549 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2550 * arrived before interrupts were enabled. We need to kick off
2551 * the SFP+ module setup first, then try to bring up link.
2552 * If we're not hot-pluggable SFP+, we just need to configure link
2555 err
= hw
->phy
.ops
.identify(hw
);
2556 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
2557 DPRINTK(PROBE
, ERR
, "PHY not supported on this NIC %d\n", err
);
2558 ixgbe_down(adapter
);
2562 if (ixgbe_is_sfp(hw
)) {
2563 ixgbe_sfp_link_config(adapter
);
2565 err
= ixgbe_non_sfp_link_config(hw
);
2567 DPRINTK(PROBE
, ERR
, "link_config FAILED %d\n", err
);
2570 /* enable transmits */
2571 netif_tx_start_all_queues(netdev
);
2573 /* bring the link up in the watchdog, this could race with our first
2574 * link up interrupt but shouldn't be a problem */
2575 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
2576 adapter
->link_check_timeout
= jiffies
;
2577 mod_timer(&adapter
->watchdog_timer
, jiffies
);
2581 void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
)
2583 WARN_ON(in_interrupt());
2584 while (test_and_set_bit(__IXGBE_RESETTING
, &adapter
->state
))
2586 ixgbe_down(adapter
);
2588 clear_bit(__IXGBE_RESETTING
, &adapter
->state
);
2591 int ixgbe_up(struct ixgbe_adapter
*adapter
)
2593 /* hardware has been reset, we need to reload some things */
2594 ixgbe_configure(adapter
);
2596 return ixgbe_up_complete(adapter
);
2599 void ixgbe_reset(struct ixgbe_adapter
*adapter
)
2601 struct ixgbe_hw
*hw
= &adapter
->hw
;
2604 err
= hw
->mac
.ops
.init_hw(hw
);
2605 if (err
&& (err
!= IXGBE_ERR_SFP_NOT_PRESENT
))
2606 dev_err(&adapter
->pdev
->dev
, "Hardware Error\n");
2608 /* reprogram the RAR[0] in case user changed it. */
2609 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, 0, IXGBE_RAH_AV
);
2614 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2615 * @adapter: board private structure
2616 * @rx_ring: ring to free buffers from
2618 static void ixgbe_clean_rx_ring(struct ixgbe_adapter
*adapter
,
2619 struct ixgbe_ring
*rx_ring
)
2621 struct pci_dev
*pdev
= adapter
->pdev
;
2625 /* Free all the Rx ring sk_buffs */
2627 for (i
= 0; i
< rx_ring
->count
; i
++) {
2628 struct ixgbe_rx_buffer
*rx_buffer_info
;
2630 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
2631 if (rx_buffer_info
->dma
) {
2632 pci_unmap_single(pdev
, rx_buffer_info
->dma
,
2633 rx_ring
->rx_buf_len
,
2634 PCI_DMA_FROMDEVICE
);
2635 rx_buffer_info
->dma
= 0;
2637 if (rx_buffer_info
->skb
) {
2638 struct sk_buff
*skb
= rx_buffer_info
->skb
;
2639 rx_buffer_info
->skb
= NULL
;
2641 struct sk_buff
*this = skb
;
2643 dev_kfree_skb(this);
2646 if (!rx_buffer_info
->page
)
2648 pci_unmap_page(pdev
, rx_buffer_info
->page_dma
, PAGE_SIZE
/ 2,
2649 PCI_DMA_FROMDEVICE
);
2650 rx_buffer_info
->page_dma
= 0;
2651 put_page(rx_buffer_info
->page
);
2652 rx_buffer_info
->page
= NULL
;
2653 rx_buffer_info
->page_offset
= 0;
2656 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
2657 memset(rx_ring
->rx_buffer_info
, 0, size
);
2659 /* Zero out the descriptor ring */
2660 memset(rx_ring
->desc
, 0, rx_ring
->size
);
2662 rx_ring
->next_to_clean
= 0;
2663 rx_ring
->next_to_use
= 0;
2666 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->head
);
2668 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->tail
);
2672 * ixgbe_clean_tx_ring - Free Tx Buffers
2673 * @adapter: board private structure
2674 * @tx_ring: ring to be cleaned
2676 static void ixgbe_clean_tx_ring(struct ixgbe_adapter
*adapter
,
2677 struct ixgbe_ring
*tx_ring
)
2679 struct ixgbe_tx_buffer
*tx_buffer_info
;
2683 /* Free all the Tx ring sk_buffs */
2685 for (i
= 0; i
< tx_ring
->count
; i
++) {
2686 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
2687 ixgbe_unmap_and_free_tx_resource(adapter
, tx_buffer_info
);
2690 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
2691 memset(tx_ring
->tx_buffer_info
, 0, size
);
2693 /* Zero out the descriptor ring */
2694 memset(tx_ring
->desc
, 0, tx_ring
->size
);
2696 tx_ring
->next_to_use
= 0;
2697 tx_ring
->next_to_clean
= 0;
2700 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->head
);
2702 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
2706 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2707 * @adapter: board private structure
2709 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter
*adapter
)
2713 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
2714 ixgbe_clean_rx_ring(adapter
, &adapter
->rx_ring
[i
]);
2718 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2719 * @adapter: board private structure
2721 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter
*adapter
)
2725 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2726 ixgbe_clean_tx_ring(adapter
, &adapter
->tx_ring
[i
]);
2729 void ixgbe_down(struct ixgbe_adapter
*adapter
)
2731 struct net_device
*netdev
= adapter
->netdev
;
2732 struct ixgbe_hw
*hw
= &adapter
->hw
;
2737 /* signal that we are down to the interrupt handler */
2738 set_bit(__IXGBE_DOWN
, &adapter
->state
);
2740 /* disable receives */
2741 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
2742 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
2744 netif_tx_disable(netdev
);
2746 IXGBE_WRITE_FLUSH(hw
);
2749 netif_tx_stop_all_queues(netdev
);
2751 ixgbe_irq_disable(adapter
);
2753 ixgbe_napi_disable_all(adapter
);
2755 del_timer_sync(&adapter
->watchdog_timer
);
2756 cancel_work_sync(&adapter
->watchdog_task
);
2758 /* disable transmits in the hardware now that interrupts are off */
2759 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2760 j
= adapter
->tx_ring
[i
].reg_idx
;
2761 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2762 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
),
2763 (txdctl
& ~IXGBE_TXDCTL_ENABLE
));
2765 /* Disable the Tx DMA engine on 82599 */
2766 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
2767 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
,
2768 (IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
) &
2769 ~IXGBE_DMATXCTL_TE
));
2771 netif_carrier_off(netdev
);
2773 if (!pci_channel_offline(adapter
->pdev
))
2774 ixgbe_reset(adapter
);
2775 ixgbe_clean_all_tx_rings(adapter
);
2776 ixgbe_clean_all_rx_rings(adapter
);
2778 #ifdef CONFIG_IXGBE_DCA
2779 /* since we reset the hardware DCA settings were cleared */
2780 ixgbe_setup_dca(adapter
);
2785 * ixgbe_poll - NAPI Rx polling callback
2786 * @napi: structure for representing this polling device
2787 * @budget: how many packets driver is allowed to clean
2789 * This function is used for legacy and MSI, NAPI mode
2791 static int ixgbe_poll(struct napi_struct
*napi
, int budget
)
2793 struct ixgbe_q_vector
*q_vector
=
2794 container_of(napi
, struct ixgbe_q_vector
, napi
);
2795 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2796 int tx_clean_complete
, work_done
= 0;
2798 #ifdef CONFIG_IXGBE_DCA
2799 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
2800 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
);
2801 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
);
2805 tx_clean_complete
= ixgbe_clean_tx_irq(adapter
, adapter
->tx_ring
);
2806 ixgbe_clean_rx_irq(q_vector
, adapter
->rx_ring
, &work_done
, budget
);
2808 if (!tx_clean_complete
)
2811 /* If budget not fully consumed, exit the polling mode */
2812 if (work_done
< budget
) {
2813 napi_complete(napi
);
2814 if (adapter
->itr_setting
& 1)
2815 ixgbe_set_itr(adapter
);
2816 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2817 ixgbe_irq_enable_queues(adapter
, IXGBE_EIMS_RTX_QUEUE
);
2823 * ixgbe_tx_timeout - Respond to a Tx Hang
2824 * @netdev: network interface device structure
2826 static void ixgbe_tx_timeout(struct net_device
*netdev
)
2828 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2830 /* Do the reset outside of interrupt context */
2831 schedule_work(&adapter
->reset_task
);
2834 static void ixgbe_reset_task(struct work_struct
*work
)
2836 struct ixgbe_adapter
*adapter
;
2837 adapter
= container_of(work
, struct ixgbe_adapter
, reset_task
);
2839 /* If we're already down or resetting, just bail */
2840 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
2841 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
2844 adapter
->tx_timeout_count
++;
2846 ixgbe_reinit_locked(adapter
);
2849 #ifdef CONFIG_IXGBE_DCB
2850 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter
*adapter
)
2853 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_DCB
];
2855 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
2859 adapter
->num_rx_queues
= f
->indices
;
2860 adapter
->num_tx_queues
= f
->indices
;
2868 * ixgbe_set_rss_queues: Allocate queues for RSS
2869 * @adapter: board private structure to initialize
2871 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
2872 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
2875 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter
*adapter
)
2878 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_RSS
];
2880 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
2882 adapter
->num_rx_queues
= f
->indices
;
2883 adapter
->num_tx_queues
= f
->indices
;
2894 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
2895 * @adapter: board private structure to initialize
2897 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
2898 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
2899 * rx queues out of the max number of rx queues, instead, it is used as the
2900 * index of the first rx queue used by FCoE.
2903 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter
*adapter
)
2906 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
2908 f
->indices
= min((int)num_online_cpus(), f
->indices
);
2909 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
2910 #ifdef CONFIG_IXGBE_DCB
2911 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
2912 DPRINTK(PROBE
, INFO
, "FCOE enabled with DCB \n");
2913 ixgbe_set_dcb_queues(adapter
);
2916 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
2917 DPRINTK(PROBE
, INFO
, "FCOE enabled with RSS \n");
2918 ixgbe_set_rss_queues(adapter
);
2920 /* adding FCoE rx rings to the end */
2921 f
->mask
= adapter
->num_rx_queues
;
2922 adapter
->num_rx_queues
+= f
->indices
;
2923 if (adapter
->num_tx_queues
== 0)
2924 adapter
->num_tx_queues
= f
->indices
;
2932 #endif /* IXGBE_FCOE */
2934 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
2935 * @adapter: board private structure to initialize
2937 * This is the top level queue allocation routine. The order here is very
2938 * important, starting with the "most" number of features turned on at once,
2939 * and ending with the smallest set of features. This way large combinations
2940 * can be allocated if they're turned on, and smaller combinations are the
2941 * fallthrough conditions.
2944 static void ixgbe_set_num_queues(struct ixgbe_adapter
*adapter
)
2947 if (ixgbe_set_fcoe_queues(adapter
))
2950 #endif /* IXGBE_FCOE */
2951 #ifdef CONFIG_IXGBE_DCB
2952 if (ixgbe_set_dcb_queues(adapter
))
2956 if (ixgbe_set_rss_queues(adapter
))
2959 /* fallback to base case */
2960 adapter
->num_rx_queues
= 1;
2961 adapter
->num_tx_queues
= 1;
2964 /* Notify the stack of the (possibly) reduced Tx Queue count. */
2965 adapter
->netdev
->real_num_tx_queues
= adapter
->num_tx_queues
;
2968 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter
*adapter
,
2971 int err
, vector_threshold
;
2973 /* We'll want at least 3 (vector_threshold):
2976 * 3) Other (Link Status Change, etc.)
2977 * 4) TCP Timer (optional)
2979 vector_threshold
= MIN_MSIX_COUNT
;
2981 /* The more we get, the more we will assign to Tx/Rx Cleanup
2982 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2983 * Right now, we simply care about how many we'll get; we'll
2984 * set them up later while requesting irq's.
2986 while (vectors
>= vector_threshold
) {
2987 err
= pci_enable_msix(adapter
->pdev
, adapter
->msix_entries
,
2989 if (!err
) /* Success in acquiring all requested vectors. */
2992 vectors
= 0; /* Nasty failure, quit now */
2993 else /* err == number of vectors we should try again with */
2997 if (vectors
< vector_threshold
) {
2998 /* Can't allocate enough MSI-X interrupts? Oh well.
2999 * This just means we'll go with either a single MSI
3000 * vector or fall back to legacy interrupts.
3002 DPRINTK(HW
, DEBUG
, "Unable to allocate MSI-X interrupts\n");
3003 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
3004 kfree(adapter
->msix_entries
);
3005 adapter
->msix_entries
= NULL
;
3007 adapter
->flags
|= IXGBE_FLAG_MSIX_ENABLED
; /* Woot! */
3009 * Adjust for only the vectors we'll use, which is minimum
3010 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3011 * vectors we were allocated.
3013 adapter
->num_msix_vectors
= min(vectors
,
3014 adapter
->max_msix_q_vectors
+ NON_Q_VECTORS
);
3019 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3020 * @adapter: board private structure to initialize
3022 * Cache the descriptor ring offsets for RSS to the assigned rings.
3025 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter
*adapter
)
3030 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3031 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3032 adapter
->rx_ring
[i
].reg_idx
= i
;
3033 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3034 adapter
->tx_ring
[i
].reg_idx
= i
;
3043 #ifdef CONFIG_IXGBE_DCB
3045 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3046 * @adapter: board private structure to initialize
3048 * Cache the descriptor ring offsets for DCB to the assigned rings.
3051 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter
*adapter
)
3055 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
3057 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3058 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
3059 /* the number of queues is assumed to be symmetric */
3060 for (i
= 0; i
< dcb_i
; i
++) {
3061 adapter
->rx_ring
[i
].reg_idx
= i
<< 3;
3062 adapter
->tx_ring
[i
].reg_idx
= i
<< 2;
3065 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
3068 * Tx TC0 starts at: descriptor queue 0
3069 * Tx TC1 starts at: descriptor queue 32
3070 * Tx TC2 starts at: descriptor queue 64
3071 * Tx TC3 starts at: descriptor queue 80
3072 * Tx TC4 starts at: descriptor queue 96
3073 * Tx TC5 starts at: descriptor queue 104
3074 * Tx TC6 starts at: descriptor queue 112
3075 * Tx TC7 starts at: descriptor queue 120
3077 * Rx TC0-TC7 are offset by 16 queues each
3079 for (i
= 0; i
< 3; i
++) {
3080 adapter
->tx_ring
[i
].reg_idx
= i
<< 5;
3081 adapter
->rx_ring
[i
].reg_idx
= i
<< 4;
3083 for ( ; i
< 5; i
++) {
3084 adapter
->tx_ring
[i
].reg_idx
=
3086 adapter
->rx_ring
[i
].reg_idx
= i
<< 4;
3088 for ( ; i
< dcb_i
; i
++) {
3089 adapter
->tx_ring
[i
].reg_idx
=
3091 adapter
->rx_ring
[i
].reg_idx
= i
<< 4;
3095 } else if (dcb_i
== 4) {
3097 * Tx TC0 starts at: descriptor queue 0
3098 * Tx TC1 starts at: descriptor queue 64
3099 * Tx TC2 starts at: descriptor queue 96
3100 * Tx TC3 starts at: descriptor queue 112
3102 * Rx TC0-TC3 are offset by 32 queues each
3104 adapter
->tx_ring
[0].reg_idx
= 0;
3105 adapter
->tx_ring
[1].reg_idx
= 64;
3106 adapter
->tx_ring
[2].reg_idx
= 96;
3107 adapter
->tx_ring
[3].reg_idx
= 112;
3108 for (i
= 0 ; i
< dcb_i
; i
++)
3109 adapter
->rx_ring
[i
].reg_idx
= i
<< 5;
3128 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3129 * @adapter: board private structure to initialize
3131 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3134 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter
*adapter
)
3138 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
3140 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
3141 #ifdef CONFIG_IXGBE_DCB
3142 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3143 ixgbe_cache_ring_dcb(adapter
);
3144 fcoe_i
= adapter
->rx_ring
[0].reg_idx
+ 1;
3146 #endif /* CONFIG_IXGBE_DCB */
3147 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3148 ixgbe_cache_ring_rss(adapter
);
3151 for (i
= 0; i
< f
->indices
; i
++, fcoe_i
++)
3152 adapter
->rx_ring
[f
->mask
+ i
].reg_idx
= fcoe_i
;
3158 #endif /* IXGBE_FCOE */
3160 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3161 * @adapter: board private structure to initialize
3163 * Once we know the feature-set enabled for the device, we'll cache
3164 * the register offset the descriptor ring is assigned to.
3166 * Note, the order the various feature calls is important. It must start with
3167 * the "most" features enabled at the same time, then trickle down to the
3168 * least amount of features turned on at once.
3170 static void ixgbe_cache_ring_register(struct ixgbe_adapter
*adapter
)
3172 /* start with default case */
3173 adapter
->rx_ring
[0].reg_idx
= 0;
3174 adapter
->tx_ring
[0].reg_idx
= 0;
3177 if (ixgbe_cache_ring_fcoe(adapter
))
3180 #endif /* IXGBE_FCOE */
3181 #ifdef CONFIG_IXGBE_DCB
3182 if (ixgbe_cache_ring_dcb(adapter
))
3186 if (ixgbe_cache_ring_rss(adapter
))
3191 * ixgbe_alloc_queues - Allocate memory for all rings
3192 * @adapter: board private structure to initialize
3194 * We allocate one ring per queue at run-time since we don't know the
3195 * number of queues at compile-time. The polling_netdev array is
3196 * intended for Multiqueue, but should work fine with a single queue.
3198 static int ixgbe_alloc_queues(struct ixgbe_adapter
*adapter
)
3202 adapter
->tx_ring
= kcalloc(adapter
->num_tx_queues
,
3203 sizeof(struct ixgbe_ring
), GFP_KERNEL
);
3204 if (!adapter
->tx_ring
)
3205 goto err_tx_ring_allocation
;
3207 adapter
->rx_ring
= kcalloc(adapter
->num_rx_queues
,
3208 sizeof(struct ixgbe_ring
), GFP_KERNEL
);
3209 if (!adapter
->rx_ring
)
3210 goto err_rx_ring_allocation
;
3212 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3213 adapter
->tx_ring
[i
].count
= adapter
->tx_ring_count
;
3214 adapter
->tx_ring
[i
].queue_index
= i
;
3217 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3218 adapter
->rx_ring
[i
].count
= adapter
->rx_ring_count
;
3219 adapter
->rx_ring
[i
].queue_index
= i
;
3222 ixgbe_cache_ring_register(adapter
);
3226 err_rx_ring_allocation
:
3227 kfree(adapter
->tx_ring
);
3228 err_tx_ring_allocation
:
3233 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3234 * @adapter: board private structure to initialize
3236 * Attempt to configure the interrupts using the best available
3237 * capabilities of the hardware and the kernel.
3239 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter
*adapter
)
3241 struct ixgbe_hw
*hw
= &adapter
->hw
;
3243 int vector
, v_budget
;
3246 * It's easy to be greedy for MSI-X vectors, but it really
3247 * doesn't do us much good if we have a lot more vectors
3248 * than CPU's. So let's be conservative and only ask for
3249 * (roughly) twice the number of vectors as there are CPU's.
3251 v_budget
= min(adapter
->num_rx_queues
+ adapter
->num_tx_queues
,
3252 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS
;
3255 * At the same time, hardware can only support a maximum of
3256 * hw.mac->max_msix_vectors vectors. With features
3257 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3258 * descriptor queues supported by our device. Thus, we cap it off in
3259 * those rare cases where the cpu count also exceeds our vector limit.
3261 v_budget
= min(v_budget
, (int)hw
->mac
.max_msix_vectors
);
3263 /* A failure in MSI-X entry allocation isn't fatal, but it does
3264 * mean we disable MSI-X capabilities of the adapter. */
3265 adapter
->msix_entries
= kcalloc(v_budget
,
3266 sizeof(struct msix_entry
), GFP_KERNEL
);
3267 if (adapter
->msix_entries
) {
3268 for (vector
= 0; vector
< v_budget
; vector
++)
3269 adapter
->msix_entries
[vector
].entry
= vector
;
3271 ixgbe_acquire_msix_vectors(adapter
, v_budget
);
3273 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
3277 adapter
->flags
&= ~IXGBE_FLAG_DCB_ENABLED
;
3278 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
3279 ixgbe_set_num_queues(adapter
);
3281 err
= pci_enable_msi(adapter
->pdev
);
3283 adapter
->flags
|= IXGBE_FLAG_MSI_ENABLED
;
3285 DPRINTK(HW
, DEBUG
, "Unable to allocate MSI interrupt, "
3286 "falling back to legacy. Error: %d\n", err
);
3296 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3297 * @adapter: board private structure to initialize
3299 * We allocate one q_vector per queue interrupt. If allocation fails we
3302 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter
*adapter
)
3304 int q_idx
, num_q_vectors
;
3305 struct ixgbe_q_vector
*q_vector
;
3307 int (*poll
)(struct napi_struct
*, int);
3309 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3310 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3311 napi_vectors
= adapter
->num_rx_queues
;
3312 poll
= &ixgbe_clean_rxonly
;
3319 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
3320 q_vector
= kzalloc(sizeof(struct ixgbe_q_vector
), GFP_KERNEL
);
3323 q_vector
->adapter
= adapter
;
3324 q_vector
->v_idx
= q_idx
;
3325 q_vector
->eitr
= adapter
->eitr_param
;
3326 if (q_idx
< napi_vectors
)
3327 netif_napi_add(adapter
->netdev
, &q_vector
->napi
,
3329 adapter
->q_vector
[q_idx
] = q_vector
;
3337 q_vector
= adapter
->q_vector
[q_idx
];
3338 netif_napi_del(&q_vector
->napi
);
3340 adapter
->q_vector
[q_idx
] = NULL
;
3346 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3347 * @adapter: board private structure to initialize
3349 * This function frees the memory allocated to the q_vectors. In addition if
3350 * NAPI is enabled it will delete any references to the NAPI struct prior
3351 * to freeing the q_vector.
3353 static void ixgbe_free_q_vectors(struct ixgbe_adapter
*adapter
)
3355 int q_idx
, num_q_vectors
;
3358 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3359 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3360 napi_vectors
= adapter
->num_rx_queues
;
3366 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
3367 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[q_idx
];
3369 adapter
->q_vector
[q_idx
] = NULL
;
3370 if (q_idx
< napi_vectors
)
3371 netif_napi_del(&q_vector
->napi
);
3376 void ixgbe_reset_interrupt_capability(struct ixgbe_adapter
*adapter
)
3378 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3379 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
3380 pci_disable_msix(adapter
->pdev
);
3381 kfree(adapter
->msix_entries
);
3382 adapter
->msix_entries
= NULL
;
3383 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
3384 adapter
->flags
&= ~IXGBE_FLAG_MSI_ENABLED
;
3385 pci_disable_msi(adapter
->pdev
);
3391 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3392 * @adapter: board private structure to initialize
3394 * We determine which interrupt scheme to use based on...
3395 * - Kernel support (MSI, MSI-X)
3396 * - which can be user-defined (via MODULE_PARAM)
3397 * - Hardware queue count (num_*_queues)
3398 * - defined by miscellaneous hardware support/features (RSS, etc.)
3400 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
)
3404 /* Number of supported queues */
3405 ixgbe_set_num_queues(adapter
);
3407 err
= ixgbe_set_interrupt_capability(adapter
);
3409 DPRINTK(PROBE
, ERR
, "Unable to setup interrupt capabilities\n");
3410 goto err_set_interrupt
;
3413 err
= ixgbe_alloc_q_vectors(adapter
);
3415 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for queue "
3417 goto err_alloc_q_vectors
;
3420 err
= ixgbe_alloc_queues(adapter
);
3422 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for queues\n");
3423 goto err_alloc_queues
;
3426 DPRINTK(DRV
, INFO
, "Multiqueue %s: Rx Queue count = %u, "
3427 "Tx Queue count = %u\n",
3428 (adapter
->num_rx_queues
> 1) ? "Enabled" :
3429 "Disabled", adapter
->num_rx_queues
, adapter
->num_tx_queues
);
3431 set_bit(__IXGBE_DOWN
, &adapter
->state
);
3436 ixgbe_free_q_vectors(adapter
);
3437 err_alloc_q_vectors
:
3438 ixgbe_reset_interrupt_capability(adapter
);
3444 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3445 * @adapter: board private structure to clear interrupt scheme on
3447 * We go through and clear interrupt specific resources and reset the structure
3448 * to pre-load conditions
3450 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
)
3452 kfree(adapter
->tx_ring
);
3453 kfree(adapter
->rx_ring
);
3454 adapter
->tx_ring
= NULL
;
3455 adapter
->rx_ring
= NULL
;
3457 ixgbe_free_q_vectors(adapter
);
3458 ixgbe_reset_interrupt_capability(adapter
);
3462 * ixgbe_sfp_timer - worker thread to find a missing module
3463 * @data: pointer to our adapter struct
3465 static void ixgbe_sfp_timer(unsigned long data
)
3467 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
3470 * Do the sfp_timer outside of interrupt context due to the
3471 * delays that sfp+ detection requires
3473 schedule_work(&adapter
->sfp_task
);
3477 * ixgbe_sfp_task - worker thread to find a missing module
3478 * @work: pointer to work_struct containing our data
3480 static void ixgbe_sfp_task(struct work_struct
*work
)
3482 struct ixgbe_adapter
*adapter
= container_of(work
,
3483 struct ixgbe_adapter
,
3485 struct ixgbe_hw
*hw
= &adapter
->hw
;
3487 if ((hw
->phy
.type
== ixgbe_phy_nl
) &&
3488 (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)) {
3489 s32 ret
= hw
->phy
.ops
.identify_sfp(hw
);
3492 ret
= hw
->phy
.ops
.reset(hw
);
3493 if (ret
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
3494 DPRINTK(PROBE
, ERR
, "failed to initialize because an "
3495 "unsupported SFP+ module type was detected.\n"
3496 "Reload the driver after installing a "
3497 "supported module.\n");
3498 unregister_netdev(adapter
->netdev
);
3500 DPRINTK(PROBE
, INFO
, "detected SFP+: %d\n",
3503 /* don't need this routine any more */
3504 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
3508 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
))
3509 mod_timer(&adapter
->sfp_timer
,
3510 round_jiffies(jiffies
+ (2 * HZ
)));
3514 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3515 * @adapter: board private structure to initialize
3517 * ixgbe_sw_init initializes the Adapter private data structure.
3518 * Fields are initialized based on PCI device information and
3519 * OS network device settings (MTU size).
3521 static int __devinit
ixgbe_sw_init(struct ixgbe_adapter
*adapter
)
3523 struct ixgbe_hw
*hw
= &adapter
->hw
;
3524 struct pci_dev
*pdev
= adapter
->pdev
;
3526 #ifdef CONFIG_IXGBE_DCB
3528 struct tc_configuration
*tc
;
3531 /* PCI config space info */
3533 hw
->vendor_id
= pdev
->vendor
;
3534 hw
->device_id
= pdev
->device
;
3535 hw
->revision_id
= pdev
->revision
;
3536 hw
->subsystem_vendor_id
= pdev
->subsystem_vendor
;
3537 hw
->subsystem_device_id
= pdev
->subsystem_device
;
3539 /* Set capability flags */
3540 rss
= min(IXGBE_MAX_RSS_INDICES
, (int)num_online_cpus());
3541 adapter
->ring_feature
[RING_F_RSS
].indices
= rss
;
3542 adapter
->flags
|= IXGBE_FLAG_RSS_ENABLED
;
3543 adapter
->ring_feature
[RING_F_DCB
].indices
= IXGBE_MAX_DCB_INDICES
;
3544 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
3545 if (hw
->device_id
== IXGBE_DEV_ID_82598AT
)
3546 adapter
->flags
|= IXGBE_FLAG_FAN_FAIL_CAPABLE
;
3547 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82598
;
3548 } else if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
3549 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82599
;
3550 adapter
->flags
|= IXGBE_FLAG_RSC_CAPABLE
;
3551 adapter
->flags
|= IXGBE_FLAG_RSC_ENABLED
;
3553 adapter
->flags
|= IXGBE_FLAG_FCOE_ENABLED
;
3554 adapter
->ring_feature
[RING_F_FCOE
].indices
= IXGBE_FCRETA_SIZE
;
3555 #endif /* IXGBE_FCOE */
3558 #ifdef CONFIG_IXGBE_DCB
3559 /* Configure DCB traffic classes */
3560 for (j
= 0; j
< MAX_TRAFFIC_CLASS
; j
++) {
3561 tc
= &adapter
->dcb_cfg
.tc_config
[j
];
3562 tc
->path
[DCB_TX_CONFIG
].bwg_id
= 0;
3563 tc
->path
[DCB_TX_CONFIG
].bwg_percent
= 12 + (j
& 1);
3564 tc
->path
[DCB_RX_CONFIG
].bwg_id
= 0;
3565 tc
->path
[DCB_RX_CONFIG
].bwg_percent
= 12 + (j
& 1);
3566 tc
->dcb_pfc
= pfc_disabled
;
3568 adapter
->dcb_cfg
.bw_percentage
[DCB_TX_CONFIG
][0] = 100;
3569 adapter
->dcb_cfg
.bw_percentage
[DCB_RX_CONFIG
][0] = 100;
3570 adapter
->dcb_cfg
.rx_pba_cfg
= pba_equal
;
3571 adapter
->dcb_cfg
.pfc_mode_enable
= false;
3572 adapter
->dcb_cfg
.round_robin_enable
= false;
3573 adapter
->dcb_set_bitmap
= 0x00;
3574 ixgbe_copy_dcb_cfg(&adapter
->dcb_cfg
, &adapter
->temp_dcb_cfg
,
3575 adapter
->ring_feature
[RING_F_DCB
].indices
);
3579 /* default flow control settings */
3580 hw
->fc
.requested_mode
= ixgbe_fc_full
;
3581 hw
->fc
.current_mode
= ixgbe_fc_full
; /* init for ethtool output */
3583 adapter
->last_lfc_mode
= hw
->fc
.current_mode
;
3585 hw
->fc
.high_water
= IXGBE_DEFAULT_FCRTH
;
3586 hw
->fc
.low_water
= IXGBE_DEFAULT_FCRTL
;
3587 hw
->fc
.pause_time
= IXGBE_DEFAULT_FCPAUSE
;
3588 hw
->fc
.send_xon
= true;
3589 hw
->fc
.disable_fc_autoneg
= false;
3591 /* enable itr by default in dynamic mode */
3592 adapter
->itr_setting
= 1;
3593 adapter
->eitr_param
= 20000;
3595 /* set defaults for eitr in MegaBytes */
3596 adapter
->eitr_low
= 10;
3597 adapter
->eitr_high
= 20;
3599 /* set default ring sizes */
3600 adapter
->tx_ring_count
= IXGBE_DEFAULT_TXD
;
3601 adapter
->rx_ring_count
= IXGBE_DEFAULT_RXD
;
3603 /* initialize eeprom parameters */
3604 if (ixgbe_init_eeprom_params_generic(hw
)) {
3605 dev_err(&pdev
->dev
, "EEPROM initialization failed\n");
3609 /* enable rx csum by default */
3610 adapter
->flags
|= IXGBE_FLAG_RX_CSUM_ENABLED
;
3612 set_bit(__IXGBE_DOWN
, &adapter
->state
);
3618 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3619 * @adapter: board private structure
3620 * @tx_ring: tx descriptor ring (for a specific queue) to setup
3622 * Return 0 on success, negative on failure
3624 int ixgbe_setup_tx_resources(struct ixgbe_adapter
*adapter
,
3625 struct ixgbe_ring
*tx_ring
)
3627 struct pci_dev
*pdev
= adapter
->pdev
;
3630 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
3631 tx_ring
->tx_buffer_info
= vmalloc(size
);
3632 if (!tx_ring
->tx_buffer_info
)
3634 memset(tx_ring
->tx_buffer_info
, 0, size
);
3636 /* round up to nearest 4K */
3637 tx_ring
->size
= tx_ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
3638 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
3640 tx_ring
->desc
= pci_alloc_consistent(pdev
, tx_ring
->size
,
3645 tx_ring
->next_to_use
= 0;
3646 tx_ring
->next_to_clean
= 0;
3647 tx_ring
->work_limit
= tx_ring
->count
;
3651 vfree(tx_ring
->tx_buffer_info
);
3652 tx_ring
->tx_buffer_info
= NULL
;
3653 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for the transmit "
3654 "descriptor ring\n");
3659 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3660 * @adapter: board private structure
3662 * If this function returns with an error, then it's possible one or
3663 * more of the rings is populated (while the rest are not). It is the
3664 * callers duty to clean those orphaned rings.
3666 * Return 0 on success, negative on failure
3668 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter
*adapter
)
3672 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3673 err
= ixgbe_setup_tx_resources(adapter
, &adapter
->tx_ring
[i
]);
3676 DPRINTK(PROBE
, ERR
, "Allocation for Tx Queue %u failed\n", i
);
3684 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3685 * @adapter: board private structure
3686 * @rx_ring: rx descriptor ring (for a specific queue) to setup
3688 * Returns 0 on success, negative on failure
3690 int ixgbe_setup_rx_resources(struct ixgbe_adapter
*adapter
,
3691 struct ixgbe_ring
*rx_ring
)
3693 struct pci_dev
*pdev
= adapter
->pdev
;
3696 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
3697 rx_ring
->rx_buffer_info
= vmalloc(size
);
3698 if (!rx_ring
->rx_buffer_info
) {
3700 "vmalloc allocation failed for the rx desc ring\n");
3703 memset(rx_ring
->rx_buffer_info
, 0, size
);
3705 /* Round up to nearest 4K */
3706 rx_ring
->size
= rx_ring
->count
* sizeof(union ixgbe_adv_rx_desc
);
3707 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
3709 rx_ring
->desc
= pci_alloc_consistent(pdev
, rx_ring
->size
, &rx_ring
->dma
);
3711 if (!rx_ring
->desc
) {
3713 "Memory allocation failed for the rx desc ring\n");
3714 vfree(rx_ring
->rx_buffer_info
);
3718 rx_ring
->next_to_clean
= 0;
3719 rx_ring
->next_to_use
= 0;
3728 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3729 * @adapter: board private structure
3731 * If this function returns with an error, then it's possible one or
3732 * more of the rings is populated (while the rest are not). It is the
3733 * callers duty to clean those orphaned rings.
3735 * Return 0 on success, negative on failure
3738 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter
*adapter
)
3742 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3743 err
= ixgbe_setup_rx_resources(adapter
, &adapter
->rx_ring
[i
]);
3746 DPRINTK(PROBE
, ERR
, "Allocation for Rx Queue %u failed\n", i
);
3754 * ixgbe_free_tx_resources - Free Tx Resources per Queue
3755 * @adapter: board private structure
3756 * @tx_ring: Tx descriptor ring for a specific queue
3758 * Free all transmit software resources
3760 void ixgbe_free_tx_resources(struct ixgbe_adapter
*adapter
,
3761 struct ixgbe_ring
*tx_ring
)
3763 struct pci_dev
*pdev
= adapter
->pdev
;
3765 ixgbe_clean_tx_ring(adapter
, tx_ring
);
3767 vfree(tx_ring
->tx_buffer_info
);
3768 tx_ring
->tx_buffer_info
= NULL
;
3770 pci_free_consistent(pdev
, tx_ring
->size
, tx_ring
->desc
, tx_ring
->dma
);
3772 tx_ring
->desc
= NULL
;
3776 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3777 * @adapter: board private structure
3779 * Free all transmit software resources
3781 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter
*adapter
)
3785 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3786 if (adapter
->tx_ring
[i
].desc
)
3787 ixgbe_free_tx_resources(adapter
, &adapter
->tx_ring
[i
]);
3791 * ixgbe_free_rx_resources - Free Rx Resources
3792 * @adapter: board private structure
3793 * @rx_ring: ring to clean the resources from
3795 * Free all receive software resources
3797 void ixgbe_free_rx_resources(struct ixgbe_adapter
*adapter
,
3798 struct ixgbe_ring
*rx_ring
)
3800 struct pci_dev
*pdev
= adapter
->pdev
;
3802 ixgbe_clean_rx_ring(adapter
, rx_ring
);
3804 vfree(rx_ring
->rx_buffer_info
);
3805 rx_ring
->rx_buffer_info
= NULL
;
3807 pci_free_consistent(pdev
, rx_ring
->size
, rx_ring
->desc
, rx_ring
->dma
);
3809 rx_ring
->desc
= NULL
;
3813 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3814 * @adapter: board private structure
3816 * Free all receive software resources
3818 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter
*adapter
)
3822 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3823 if (adapter
->rx_ring
[i
].desc
)
3824 ixgbe_free_rx_resources(adapter
, &adapter
->rx_ring
[i
]);
3828 * ixgbe_change_mtu - Change the Maximum Transfer Unit
3829 * @netdev: network interface device structure
3830 * @new_mtu: new value for maximum frame size
3832 * Returns 0 on success, negative on failure
3834 static int ixgbe_change_mtu(struct net_device
*netdev
, int new_mtu
)
3836 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3837 int max_frame
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
3839 /* MTU < 68 is an error and causes problems on some kernels */
3840 if ((new_mtu
< 68) || (max_frame
> IXGBE_MAX_JUMBO_FRAME_SIZE
))
3843 DPRINTK(PROBE
, INFO
, "changing MTU from %d to %d\n",
3844 netdev
->mtu
, new_mtu
);
3845 /* must set new MTU before calling down or up */
3846 netdev
->mtu
= new_mtu
;
3848 if (netif_running(netdev
))
3849 ixgbe_reinit_locked(adapter
);
3855 * ixgbe_open - Called when a network interface is made active
3856 * @netdev: network interface device structure
3858 * Returns 0 on success, negative value on failure
3860 * The open entry point is called when a network interface is made
3861 * active by the system (IFF_UP). At this point all resources needed
3862 * for transmit and receive operations are allocated, the interrupt
3863 * handler is registered with the OS, the watchdog timer is started,
3864 * and the stack is notified that the interface is ready.
3866 static int ixgbe_open(struct net_device
*netdev
)
3868 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3871 /* disallow open during test */
3872 if (test_bit(__IXGBE_TESTING
, &adapter
->state
))
3875 netif_carrier_off(netdev
);
3877 /* allocate transmit descriptors */
3878 err
= ixgbe_setup_all_tx_resources(adapter
);
3882 /* allocate receive descriptors */
3883 err
= ixgbe_setup_all_rx_resources(adapter
);
3887 ixgbe_configure(adapter
);
3889 err
= ixgbe_request_irq(adapter
);
3893 err
= ixgbe_up_complete(adapter
);
3897 netif_tx_start_all_queues(netdev
);
3902 ixgbe_release_hw_control(adapter
);
3903 ixgbe_free_irq(adapter
);
3906 ixgbe_free_all_rx_resources(adapter
);
3908 ixgbe_free_all_tx_resources(adapter
);
3909 ixgbe_reset(adapter
);
3915 * ixgbe_close - Disables a network interface
3916 * @netdev: network interface device structure
3918 * Returns 0, this is not allowed to fail
3920 * The close entry point is called when an interface is de-activated
3921 * by the OS. The hardware is still under the drivers control, but
3922 * needs to be disabled. A global MAC reset is issued to stop the
3923 * hardware, and all transmit and receive resources are freed.
3925 static int ixgbe_close(struct net_device
*netdev
)
3927 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3929 ixgbe_down(adapter
);
3930 ixgbe_free_irq(adapter
);
3932 ixgbe_free_all_tx_resources(adapter
);
3933 ixgbe_free_all_rx_resources(adapter
);
3935 ixgbe_release_hw_control(adapter
);
3941 static int ixgbe_resume(struct pci_dev
*pdev
)
3943 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3944 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3947 pci_set_power_state(pdev
, PCI_D0
);
3948 pci_restore_state(pdev
);
3950 err
= pci_enable_device_mem(pdev
);
3952 printk(KERN_ERR
"ixgbe: Cannot enable PCI device from "
3956 pci_set_master(pdev
);
3958 pci_wake_from_d3(pdev
, false);
3960 err
= ixgbe_init_interrupt_scheme(adapter
);
3962 printk(KERN_ERR
"ixgbe: Cannot initialize interrupts for "
3967 ixgbe_reset(adapter
);
3969 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
3971 if (netif_running(netdev
)) {
3972 err
= ixgbe_open(adapter
->netdev
);
3977 netif_device_attach(netdev
);
3981 #endif /* CONFIG_PM */
3983 static int __ixgbe_shutdown(struct pci_dev
*pdev
, bool *enable_wake
)
3985 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3986 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3987 struct ixgbe_hw
*hw
= &adapter
->hw
;
3989 u32 wufc
= adapter
->wol
;
3994 netif_device_detach(netdev
);
3996 if (netif_running(netdev
)) {
3997 ixgbe_down(adapter
);
3998 ixgbe_free_irq(adapter
);
3999 ixgbe_free_all_tx_resources(adapter
);
4000 ixgbe_free_all_rx_resources(adapter
);
4002 ixgbe_clear_interrupt_scheme(adapter
);
4005 retval
= pci_save_state(pdev
);
4011 ixgbe_set_rx_mode(netdev
);
4013 /* turn on all-multi mode if wake on multicast is enabled */
4014 if (wufc
& IXGBE_WUFC_MC
) {
4015 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
4016 fctrl
|= IXGBE_FCTRL_MPE
;
4017 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
4020 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
4021 ctrl
|= IXGBE_CTRL_GIO_DIS
;
4022 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
4024 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, wufc
);
4026 IXGBE_WRITE_REG(hw
, IXGBE_WUC
, 0);
4027 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, 0);
4030 if (wufc
&& hw
->mac
.type
== ixgbe_mac_82599EB
)
4031 pci_wake_from_d3(pdev
, true);
4033 pci_wake_from_d3(pdev
, false);
4035 *enable_wake
= !!wufc
;
4037 ixgbe_release_hw_control(adapter
);
4039 pci_disable_device(pdev
);
4045 static int ixgbe_suspend(struct pci_dev
*pdev
, pm_message_t state
)
4050 retval
= __ixgbe_shutdown(pdev
, &wake
);
4055 pci_prepare_to_sleep(pdev
);
4057 pci_wake_from_d3(pdev
, false);
4058 pci_set_power_state(pdev
, PCI_D3hot
);
4063 #endif /* CONFIG_PM */
4065 static void ixgbe_shutdown(struct pci_dev
*pdev
)
4069 __ixgbe_shutdown(pdev
, &wake
);
4071 if (system_state
== SYSTEM_POWER_OFF
) {
4072 pci_wake_from_d3(pdev
, wake
);
4073 pci_set_power_state(pdev
, PCI_D3hot
);
4078 * ixgbe_update_stats - Update the board statistics counters.
4079 * @adapter: board private structure
4081 void ixgbe_update_stats(struct ixgbe_adapter
*adapter
)
4083 struct ixgbe_hw
*hw
= &adapter
->hw
;
4085 u32 i
, missed_rx
= 0, mpc
, bprc
, lxon
, lxoff
, xon_off_tot
;
4087 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4089 for (i
= 0; i
< 16; i
++)
4090 adapter
->hw_rx_no_dma_resources
+=
4091 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
4092 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4093 rsc_count
+= adapter
->rx_ring
[i
].rsc_count
;
4094 adapter
->rsc_count
= rsc_count
;
4097 adapter
->stats
.crcerrs
+= IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
4098 for (i
= 0; i
< 8; i
++) {
4099 /* for packet buffers not used, the register should read 0 */
4100 mpc
= IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
4102 adapter
->stats
.mpc
[i
] += mpc
;
4103 total_mpc
+= adapter
->stats
.mpc
[i
];
4104 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
4105 adapter
->stats
.rnbc
[i
] += IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
4106 adapter
->stats
.qptc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
4107 adapter
->stats
.qbtc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
4108 adapter
->stats
.qprc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
4109 adapter
->stats
.qbrc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
4110 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4111 adapter
->stats
.pxonrxc
[i
] += IXGBE_READ_REG(hw
,
4112 IXGBE_PXONRXCNT(i
));
4113 adapter
->stats
.pxoffrxc
[i
] += IXGBE_READ_REG(hw
,
4114 IXGBE_PXOFFRXCNT(i
));
4115 adapter
->stats
.qprdc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
4117 adapter
->stats
.pxonrxc
[i
] += IXGBE_READ_REG(hw
,
4119 adapter
->stats
.pxoffrxc
[i
] += IXGBE_READ_REG(hw
,
4122 adapter
->stats
.pxontxc
[i
] += IXGBE_READ_REG(hw
,
4124 adapter
->stats
.pxofftxc
[i
] += IXGBE_READ_REG(hw
,
4127 adapter
->stats
.gprc
+= IXGBE_READ_REG(hw
, IXGBE_GPRC
);
4128 /* work around hardware counting issue */
4129 adapter
->stats
.gprc
-= missed_rx
;
4131 /* 82598 hardware only has a 32 bit counter in the high register */
4132 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4133 adapter
->stats
.gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCL
);
4134 IXGBE_READ_REG(hw
, IXGBE_GORCH
); /* to clear */
4135 adapter
->stats
.gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
4136 IXGBE_READ_REG(hw
, IXGBE_GOTCH
); /* to clear */
4137 adapter
->stats
.tor
+= IXGBE_READ_REG(hw
, IXGBE_TORL
);
4138 IXGBE_READ_REG(hw
, IXGBE_TORH
); /* to clear */
4139 adapter
->stats
.lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
4140 adapter
->stats
.lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
4142 adapter
->stats
.fccrc
+= IXGBE_READ_REG(hw
, IXGBE_FCCRC
);
4143 adapter
->stats
.fcoerpdc
+= IXGBE_READ_REG(hw
, IXGBE_FCOERPDC
);
4144 adapter
->stats
.fcoeprc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPRC
);
4145 adapter
->stats
.fcoeptc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPTC
);
4146 adapter
->stats
.fcoedwrc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWRC
);
4147 adapter
->stats
.fcoedwtc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWTC
);
4148 #endif /* IXGBE_FCOE */
4150 adapter
->stats
.lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
4151 adapter
->stats
.lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
4152 adapter
->stats
.gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCH
);
4153 adapter
->stats
.gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
4154 adapter
->stats
.tor
+= IXGBE_READ_REG(hw
, IXGBE_TORH
);
4156 bprc
= IXGBE_READ_REG(hw
, IXGBE_BPRC
);
4157 adapter
->stats
.bprc
+= bprc
;
4158 adapter
->stats
.mprc
+= IXGBE_READ_REG(hw
, IXGBE_MPRC
);
4159 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
4160 adapter
->stats
.mprc
-= bprc
;
4161 adapter
->stats
.roc
+= IXGBE_READ_REG(hw
, IXGBE_ROC
);
4162 adapter
->stats
.prc64
+= IXGBE_READ_REG(hw
, IXGBE_PRC64
);
4163 adapter
->stats
.prc127
+= IXGBE_READ_REG(hw
, IXGBE_PRC127
);
4164 adapter
->stats
.prc255
+= IXGBE_READ_REG(hw
, IXGBE_PRC255
);
4165 adapter
->stats
.prc511
+= IXGBE_READ_REG(hw
, IXGBE_PRC511
);
4166 adapter
->stats
.prc1023
+= IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
4167 adapter
->stats
.prc1522
+= IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
4168 adapter
->stats
.rlec
+= IXGBE_READ_REG(hw
, IXGBE_RLEC
);
4169 lxon
= IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
4170 adapter
->stats
.lxontxc
+= lxon
;
4171 lxoff
= IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
4172 adapter
->stats
.lxofftxc
+= lxoff
;
4173 adapter
->stats
.ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
4174 adapter
->stats
.gptc
+= IXGBE_READ_REG(hw
, IXGBE_GPTC
);
4175 adapter
->stats
.mptc
+= IXGBE_READ_REG(hw
, IXGBE_MPTC
);
4177 * 82598 errata - tx of flow control packets is included in tx counters
4179 xon_off_tot
= lxon
+ lxoff
;
4180 adapter
->stats
.gptc
-= xon_off_tot
;
4181 adapter
->stats
.mptc
-= xon_off_tot
;
4182 adapter
->stats
.gotc
-= (xon_off_tot
* (ETH_ZLEN
+ ETH_FCS_LEN
));
4183 adapter
->stats
.ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
4184 adapter
->stats
.rfc
+= IXGBE_READ_REG(hw
, IXGBE_RFC
);
4185 adapter
->stats
.rjc
+= IXGBE_READ_REG(hw
, IXGBE_RJC
);
4186 adapter
->stats
.tpr
+= IXGBE_READ_REG(hw
, IXGBE_TPR
);
4187 adapter
->stats
.ptc64
+= IXGBE_READ_REG(hw
, IXGBE_PTC64
);
4188 adapter
->stats
.ptc64
-= xon_off_tot
;
4189 adapter
->stats
.ptc127
+= IXGBE_READ_REG(hw
, IXGBE_PTC127
);
4190 adapter
->stats
.ptc255
+= IXGBE_READ_REG(hw
, IXGBE_PTC255
);
4191 adapter
->stats
.ptc511
+= IXGBE_READ_REG(hw
, IXGBE_PTC511
);
4192 adapter
->stats
.ptc1023
+= IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
4193 adapter
->stats
.ptc1522
+= IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
4194 adapter
->stats
.bptc
+= IXGBE_READ_REG(hw
, IXGBE_BPTC
);
4196 /* Fill out the OS statistics structure */
4197 adapter
->net_stats
.multicast
= adapter
->stats
.mprc
;
4200 adapter
->net_stats
.rx_errors
= adapter
->stats
.crcerrs
+
4201 adapter
->stats
.rlec
;
4202 adapter
->net_stats
.rx_dropped
= 0;
4203 adapter
->net_stats
.rx_length_errors
= adapter
->stats
.rlec
;
4204 adapter
->net_stats
.rx_crc_errors
= adapter
->stats
.crcerrs
;
4205 adapter
->net_stats
.rx_missed_errors
= total_mpc
;
4209 * ixgbe_watchdog - Timer Call-back
4210 * @data: pointer to adapter cast into an unsigned long
4212 static void ixgbe_watchdog(unsigned long data
)
4214 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
4215 struct ixgbe_hw
*hw
= &adapter
->hw
;
4217 /* Do the watchdog outside of interrupt context due to the lovely
4218 * delays that some of the newer hardware requires */
4219 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
4223 for (i
= 0; i
< adapter
->num_msix_vectors
- NON_Q_VECTORS
; i
++)
4224 eics
|= ((u64
)1 << i
);
4226 /* Cause software interrupt to ensure rx rings are cleaned */
4227 switch (hw
->mac
.type
) {
4228 case ixgbe_mac_82598EB
:
4229 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4230 IXGBE_WRITE_REG(hw
, IXGBE_EICS
, (u32
)eics
);
4233 * for legacy and MSI interrupts don't set any
4234 * bits that are enabled for EIAM, because this
4235 * operation would set *both* EIMS and EICS for
4238 IXGBE_WRITE_REG(hw
, IXGBE_EICS
,
4239 (IXGBE_EICS_TCP_TIMER
| IXGBE_EICS_OTHER
));
4242 case ixgbe_mac_82599EB
:
4243 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4244 IXGBE_WRITE_REG(hw
, IXGBE_EICS_EX(0),
4245 (u32
)(eics
& 0xFFFFFFFF));
4246 IXGBE_WRITE_REG(hw
, IXGBE_EICS_EX(1),
4250 * for legacy and MSI interrupts don't set any
4251 * bits that are enabled for EIAM, because this
4252 * operation would set *both* EIMS and EICS for
4255 IXGBE_WRITE_REG(hw
, IXGBE_EICS
,
4256 (IXGBE_EICS_TCP_TIMER
| IXGBE_EICS_OTHER
));
4262 /* Reset the timer */
4263 mod_timer(&adapter
->watchdog_timer
,
4264 round_jiffies(jiffies
+ 2 * HZ
));
4267 schedule_work(&adapter
->watchdog_task
);
4271 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4272 * @work: pointer to work_struct containing our data
4274 static void ixgbe_multispeed_fiber_task(struct work_struct
*work
)
4276 struct ixgbe_adapter
*adapter
= container_of(work
,
4277 struct ixgbe_adapter
,
4278 multispeed_fiber_task
);
4279 struct ixgbe_hw
*hw
= &adapter
->hw
;
4282 adapter
->flags
|= IXGBE_FLAG_IN_SFP_LINK_TASK
;
4283 if (hw
->mac
.ops
.get_link_capabilities
)
4284 hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
,
4286 if (hw
->mac
.ops
.setup_link_speed
)
4287 hw
->mac
.ops
.setup_link_speed(hw
, autoneg
, true, true);
4288 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
4289 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_LINK_TASK
;
4293 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4294 * @work: pointer to work_struct containing our data
4296 static void ixgbe_sfp_config_module_task(struct work_struct
*work
)
4298 struct ixgbe_adapter
*adapter
= container_of(work
,
4299 struct ixgbe_adapter
,
4300 sfp_config_module_task
);
4301 struct ixgbe_hw
*hw
= &adapter
->hw
;
4304 adapter
->flags
|= IXGBE_FLAG_IN_SFP_MOD_TASK
;
4305 err
= hw
->phy
.ops
.identify_sfp(hw
);
4306 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
4307 DPRINTK(PROBE
, ERR
, "PHY not supported on this NIC %d\n", err
);
4308 ixgbe_down(adapter
);
4311 hw
->mac
.ops
.setup_sfp(hw
);
4313 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
4314 /* This will also work for DA Twinax connections */
4315 schedule_work(&adapter
->multispeed_fiber_task
);
4316 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_MOD_TASK
;
4320 * ixgbe_watchdog_task - worker thread to bring link up
4321 * @work: pointer to work_struct containing our data
4323 static void ixgbe_watchdog_task(struct work_struct
*work
)
4325 struct ixgbe_adapter
*adapter
= container_of(work
,
4326 struct ixgbe_adapter
,
4328 struct net_device
*netdev
= adapter
->netdev
;
4329 struct ixgbe_hw
*hw
= &adapter
->hw
;
4330 u32 link_speed
= adapter
->link_speed
;
4331 bool link_up
= adapter
->link_up
;
4333 struct ixgbe_ring
*tx_ring
;
4334 int some_tx_pending
= 0;
4336 adapter
->flags
|= IXGBE_FLAG_IN_WATCHDOG_TASK
;
4338 if (adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
) {
4339 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
4342 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4343 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++)
4344 hw
->mac
.ops
.setup_fc(hw
, i
);
4346 hw
->mac
.ops
.setup_fc(hw
, 0);
4349 hw
->mac
.ops
.setup_fc(hw
, 0);
4354 time_after(jiffies
, (adapter
->link_check_timeout
+
4355 IXGBE_TRY_LINK_TIMEOUT
))) {
4356 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
4357 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMC_LSC
);
4359 adapter
->link_up
= link_up
;
4360 adapter
->link_speed
= link_speed
;
4364 if (!netif_carrier_ok(netdev
)) {
4365 bool flow_rx
, flow_tx
;
4367 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4368 u32 mflcn
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
4369 u32 fccfg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
4370 flow_rx
= (mflcn
& IXGBE_MFLCN_RFCE
);
4371 flow_tx
= (fccfg
& IXGBE_FCCFG_TFCE_802_3X
);
4373 u32 frctl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
4374 u32 rmcs
= IXGBE_READ_REG(hw
, IXGBE_RMCS
);
4375 flow_rx
= (frctl
& IXGBE_FCTRL_RFCE
);
4376 flow_tx
= (rmcs
& IXGBE_RMCS_TFCE_802_3X
);
4379 printk(KERN_INFO
"ixgbe: %s NIC Link is Up %s, "
4380 "Flow Control: %s\n",
4382 (link_speed
== IXGBE_LINK_SPEED_10GB_FULL
?
4384 (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
?
4385 "1 Gbps" : "unknown speed")),
4386 ((flow_rx
&& flow_tx
) ? "RX/TX" :
4388 (flow_tx
? "TX" : "None"))));
4390 netif_carrier_on(netdev
);
4392 /* Force detection of hung controller */
4393 adapter
->detect_tx_hung
= true;
4396 adapter
->link_up
= false;
4397 adapter
->link_speed
= 0;
4398 if (netif_carrier_ok(netdev
)) {
4399 printk(KERN_INFO
"ixgbe: %s NIC Link is Down\n",
4401 netif_carrier_off(netdev
);
4405 if (!netif_carrier_ok(netdev
)) {
4406 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4407 tx_ring
= &adapter
->tx_ring
[i
];
4408 if (tx_ring
->next_to_use
!= tx_ring
->next_to_clean
) {
4409 some_tx_pending
= 1;
4414 if (some_tx_pending
) {
4415 /* We've lost link, so the controller stops DMA,
4416 * but we've got queued Tx work that's never going
4417 * to get done, so reset controller to flush Tx.
4418 * (Do the reset outside of interrupt context).
4420 schedule_work(&adapter
->reset_task
);
4424 ixgbe_update_stats(adapter
);
4425 adapter
->flags
&= ~IXGBE_FLAG_IN_WATCHDOG_TASK
;
4428 static int ixgbe_tso(struct ixgbe_adapter
*adapter
,
4429 struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
4430 u32 tx_flags
, u8
*hdr_len
)
4432 struct ixgbe_adv_tx_context_desc
*context_desc
;
4435 struct ixgbe_tx_buffer
*tx_buffer_info
;
4436 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
;
4437 u32 mss_l4len_idx
, l4len
;
4439 if (skb_is_gso(skb
)) {
4440 if (skb_header_cloned(skb
)) {
4441 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
4445 l4len
= tcp_hdrlen(skb
);
4448 if (skb
->protocol
== htons(ETH_P_IP
)) {
4449 struct iphdr
*iph
= ip_hdr(skb
);
4452 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
4456 adapter
->hw_tso_ctxt
++;
4457 } else if (skb_shinfo(skb
)->gso_type
== SKB_GSO_TCPV6
) {
4458 ipv6_hdr(skb
)->payload_len
= 0;
4459 tcp_hdr(skb
)->check
=
4460 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
4461 &ipv6_hdr(skb
)->daddr
,
4463 adapter
->hw_tso6_ctxt
++;
4466 i
= tx_ring
->next_to_use
;
4468 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
4469 context_desc
= IXGBE_TX_CTXTDESC_ADV(*tx_ring
, i
);
4471 /* VLAN MACLEN IPLEN */
4472 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
4474 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
4475 vlan_macip_lens
|= ((skb_network_offset(skb
)) <<
4476 IXGBE_ADVTXD_MACLEN_SHIFT
);
4477 *hdr_len
+= skb_network_offset(skb
);
4479 (skb_transport_header(skb
) - skb_network_header(skb
));
4481 (skb_transport_header(skb
) - skb_network_header(skb
));
4482 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
4483 context_desc
->seqnum_seed
= 0;
4485 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4486 type_tucmd_mlhl
= (IXGBE_TXD_CMD_DEXT
|
4487 IXGBE_ADVTXD_DTYP_CTXT
);
4489 if (skb
->protocol
== htons(ETH_P_IP
))
4490 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
4491 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
4492 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
4496 (skb_shinfo(skb
)->gso_size
<< IXGBE_ADVTXD_MSS_SHIFT
);
4497 mss_l4len_idx
|= (l4len
<< IXGBE_ADVTXD_L4LEN_SHIFT
);
4498 /* use index 1 for TSO */
4499 mss_l4len_idx
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
4500 context_desc
->mss_l4len_idx
= cpu_to_le32(mss_l4len_idx
);
4502 tx_buffer_info
->time_stamp
= jiffies
;
4503 tx_buffer_info
->next_to_watch
= i
;
4506 if (i
== tx_ring
->count
)
4508 tx_ring
->next_to_use
= i
;
4515 static bool ixgbe_tx_csum(struct ixgbe_adapter
*adapter
,
4516 struct ixgbe_ring
*tx_ring
,
4517 struct sk_buff
*skb
, u32 tx_flags
)
4519 struct ixgbe_adv_tx_context_desc
*context_desc
;
4521 struct ixgbe_tx_buffer
*tx_buffer_info
;
4522 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
= 0;
4524 if (skb
->ip_summed
== CHECKSUM_PARTIAL
||
4525 (tx_flags
& IXGBE_TX_FLAGS_VLAN
)) {
4526 i
= tx_ring
->next_to_use
;
4527 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
4528 context_desc
= IXGBE_TX_CTXTDESC_ADV(*tx_ring
, i
);
4530 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
4532 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
4533 vlan_macip_lens
|= (skb_network_offset(skb
) <<
4534 IXGBE_ADVTXD_MACLEN_SHIFT
);
4535 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
4536 vlan_macip_lens
|= (skb_transport_header(skb
) -
4537 skb_network_header(skb
));
4539 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
4540 context_desc
->seqnum_seed
= 0;
4542 type_tucmd_mlhl
|= (IXGBE_TXD_CMD_DEXT
|
4543 IXGBE_ADVTXD_DTYP_CTXT
);
4545 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
4546 switch (skb
->protocol
) {
4547 case cpu_to_be16(ETH_P_IP
):
4548 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
4549 if (ip_hdr(skb
)->protocol
== IPPROTO_TCP
)
4551 IXGBE_ADVTXD_TUCMD_L4T_TCP
;
4552 else if (ip_hdr(skb
)->protocol
== IPPROTO_SCTP
)
4554 IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
4556 case cpu_to_be16(ETH_P_IPV6
):
4557 /* XXX what about other V6 headers?? */
4558 if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_TCP
)
4560 IXGBE_ADVTXD_TUCMD_L4T_TCP
;
4561 else if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_SCTP
)
4563 IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
4566 if (unlikely(net_ratelimit())) {
4567 DPRINTK(PROBE
, WARNING
,
4568 "partial checksum but proto=%x!\n",
4575 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
4576 /* use index zero for tx checksum offload */
4577 context_desc
->mss_l4len_idx
= 0;
4579 tx_buffer_info
->time_stamp
= jiffies
;
4580 tx_buffer_info
->next_to_watch
= i
;
4582 adapter
->hw_csum_tx_good
++;
4584 if (i
== tx_ring
->count
)
4586 tx_ring
->next_to_use
= i
;
4594 static int ixgbe_tx_map(struct ixgbe_adapter
*adapter
,
4595 struct ixgbe_ring
*tx_ring
,
4596 struct sk_buff
*skb
, u32 tx_flags
,
4599 struct ixgbe_tx_buffer
*tx_buffer_info
;
4601 unsigned int total
= skb
->len
;
4602 unsigned int offset
= 0, size
, count
= 0, i
;
4603 unsigned int nr_frags
= skb_shinfo(skb
)->nr_frags
;
4607 i
= tx_ring
->next_to_use
;
4609 if (skb_dma_map(&adapter
->pdev
->dev
, skb
, DMA_TO_DEVICE
)) {
4610 dev_err(&adapter
->pdev
->dev
, "TX DMA map failed\n");
4614 map
= skb_shinfo(skb
)->dma_maps
;
4616 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
)
4617 /* excluding fcoe_crc_eof for FCoE */
4618 total
-= sizeof(struct fcoe_crc_eof
);
4620 len
= min(skb_headlen(skb
), total
);
4622 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
4623 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
4625 tx_buffer_info
->length
= size
;
4626 tx_buffer_info
->dma
= map
[0] + offset
;
4627 tx_buffer_info
->time_stamp
= jiffies
;
4628 tx_buffer_info
->next_to_watch
= i
;
4637 if (i
== tx_ring
->count
)
4642 for (f
= 0; f
< nr_frags
; f
++) {
4643 struct skb_frag_struct
*frag
;
4645 frag
= &skb_shinfo(skb
)->frags
[f
];
4646 len
= min((unsigned int)frag
->size
, total
);
4651 if (i
== tx_ring
->count
)
4654 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
4655 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
4657 tx_buffer_info
->length
= size
;
4658 tx_buffer_info
->dma
= map
[f
+ 1] + offset
;
4659 tx_buffer_info
->time_stamp
= jiffies
;
4660 tx_buffer_info
->next_to_watch
= i
;
4671 tx_ring
->tx_buffer_info
[i
].skb
= skb
;
4672 tx_ring
->tx_buffer_info
[first
].next_to_watch
= i
;
4677 static void ixgbe_tx_queue(struct ixgbe_adapter
*adapter
,
4678 struct ixgbe_ring
*tx_ring
,
4679 int tx_flags
, int count
, u32 paylen
, u8 hdr_len
)
4681 union ixgbe_adv_tx_desc
*tx_desc
= NULL
;
4682 struct ixgbe_tx_buffer
*tx_buffer_info
;
4683 u32 olinfo_status
= 0, cmd_type_len
= 0;
4685 u32 txd_cmd
= IXGBE_TXD_CMD_EOP
| IXGBE_TXD_CMD_RS
| IXGBE_TXD_CMD_IFCS
;
4687 cmd_type_len
|= IXGBE_ADVTXD_DTYP_DATA
;
4689 cmd_type_len
|= IXGBE_ADVTXD_DCMD_IFCS
| IXGBE_ADVTXD_DCMD_DEXT
;
4691 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
4692 cmd_type_len
|= IXGBE_ADVTXD_DCMD_VLE
;
4694 if (tx_flags
& IXGBE_TX_FLAGS_TSO
) {
4695 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
4697 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
4698 IXGBE_ADVTXD_POPTS_SHIFT
;
4700 /* use index 1 context for tso */
4701 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
4702 if (tx_flags
& IXGBE_TX_FLAGS_IPV4
)
4703 olinfo_status
|= IXGBE_TXD_POPTS_IXSM
<<
4704 IXGBE_ADVTXD_POPTS_SHIFT
;
4706 } else if (tx_flags
& IXGBE_TX_FLAGS_CSUM
)
4707 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
4708 IXGBE_ADVTXD_POPTS_SHIFT
;
4710 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
4711 olinfo_status
|= IXGBE_ADVTXD_CC
;
4712 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
4713 if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
4714 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
4717 olinfo_status
|= ((paylen
- hdr_len
) << IXGBE_ADVTXD_PAYLEN_SHIFT
);
4719 i
= tx_ring
->next_to_use
;
4721 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
4722 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, i
);
4723 tx_desc
->read
.buffer_addr
= cpu_to_le64(tx_buffer_info
->dma
);
4724 tx_desc
->read
.cmd_type_len
=
4725 cpu_to_le32(cmd_type_len
| tx_buffer_info
->length
);
4726 tx_desc
->read
.olinfo_status
= cpu_to_le32(olinfo_status
);
4728 if (i
== tx_ring
->count
)
4732 tx_desc
->read
.cmd_type_len
|= cpu_to_le32(txd_cmd
);
4735 * Force memory writes to complete before letting h/w
4736 * know there are new descriptors to fetch. (Only
4737 * applicable for weak-ordered memory model archs,
4742 tx_ring
->next_to_use
= i
;
4743 writel(i
, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
4746 static int __ixgbe_maybe_stop_tx(struct net_device
*netdev
,
4747 struct ixgbe_ring
*tx_ring
, int size
)
4749 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4751 netif_stop_subqueue(netdev
, tx_ring
->queue_index
);
4752 /* Herbert's original patch had:
4753 * smp_mb__after_netif_stop_queue();
4754 * but since that doesn't exist yet, just open code it. */
4757 /* We need to check again in a case another CPU has just
4758 * made room available. */
4759 if (likely(IXGBE_DESC_UNUSED(tx_ring
) < size
))
4762 /* A reprieve! - use start_queue because it doesn't call schedule */
4763 netif_start_subqueue(netdev
, tx_ring
->queue_index
);
4764 ++adapter
->restart_queue
;
4768 static int ixgbe_maybe_stop_tx(struct net_device
*netdev
,
4769 struct ixgbe_ring
*tx_ring
, int size
)
4771 if (likely(IXGBE_DESC_UNUSED(tx_ring
) >= size
))
4773 return __ixgbe_maybe_stop_tx(netdev
, tx_ring
, size
);
4776 static u16
ixgbe_select_queue(struct net_device
*dev
, struct sk_buff
*skb
)
4778 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
4780 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
4781 return 0; /* All traffic should default to class 0 */
4783 return skb_tx_hash(dev
, skb
);
4786 static int ixgbe_xmit_frame(struct sk_buff
*skb
, struct net_device
*netdev
)
4788 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4789 struct ixgbe_ring
*tx_ring
;
4791 unsigned int tx_flags
= 0;
4797 r_idx
= skb
->queue_mapping
;
4798 tx_ring
= &adapter
->tx_ring
[r_idx
];
4800 if (adapter
->vlgrp
&& vlan_tx_tag_present(skb
)) {
4801 tx_flags
|= vlan_tx_tag_get(skb
);
4802 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4803 tx_flags
&= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK
;
4804 tx_flags
|= (skb
->queue_mapping
<< 13);
4806 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
4807 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
4808 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4809 tx_flags
|= (skb
->queue_mapping
<< 13);
4810 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
4811 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
4814 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
4815 (skb
->protocol
== htons(ETH_P_FCOE
)))
4816 tx_flags
|= IXGBE_TX_FLAGS_FCOE
;
4818 /* four things can cause us to need a context descriptor */
4819 if (skb_is_gso(skb
) ||
4820 (skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
4821 (tx_flags
& IXGBE_TX_FLAGS_VLAN
) ||
4822 (tx_flags
& IXGBE_TX_FLAGS_FCOE
))
4825 count
+= TXD_USE_COUNT(skb_headlen(skb
));
4826 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
4827 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
4829 if (ixgbe_maybe_stop_tx(netdev
, tx_ring
, count
)) {
4831 return NETDEV_TX_BUSY
;
4834 first
= tx_ring
->next_to_use
;
4835 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
4837 /* setup tx offload for FCoE */
4838 tso
= ixgbe_fso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
4840 dev_kfree_skb_any(skb
);
4841 return NETDEV_TX_OK
;
4844 tx_flags
|= IXGBE_TX_FLAGS_FSO
;
4845 #endif /* IXGBE_FCOE */
4847 if (skb
->protocol
== htons(ETH_P_IP
))
4848 tx_flags
|= IXGBE_TX_FLAGS_IPV4
;
4849 tso
= ixgbe_tso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
4851 dev_kfree_skb_any(skb
);
4852 return NETDEV_TX_OK
;
4856 tx_flags
|= IXGBE_TX_FLAGS_TSO
;
4857 else if (ixgbe_tx_csum(adapter
, tx_ring
, skb
, tx_flags
) &&
4858 (skb
->ip_summed
== CHECKSUM_PARTIAL
))
4859 tx_flags
|= IXGBE_TX_FLAGS_CSUM
;
4862 count
= ixgbe_tx_map(adapter
, tx_ring
, skb
, tx_flags
, first
);
4864 ixgbe_tx_queue(adapter
, tx_ring
, tx_flags
, count
, skb
->len
,
4866 netdev
->trans_start
= jiffies
;
4867 ixgbe_maybe_stop_tx(netdev
, tx_ring
, DESC_NEEDED
);
4870 dev_kfree_skb_any(skb
);
4871 tx_ring
->tx_buffer_info
[first
].time_stamp
= 0;
4872 tx_ring
->next_to_use
= first
;
4875 return NETDEV_TX_OK
;
4879 * ixgbe_get_stats - Get System Network Statistics
4880 * @netdev: network interface device structure
4882 * Returns the address of the device statistics structure.
4883 * The statistics are actually updated from the timer callback.
4885 static struct net_device_stats
*ixgbe_get_stats(struct net_device
*netdev
)
4887 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4889 /* only return the current stats */
4890 return &adapter
->net_stats
;
4894 * ixgbe_set_mac - Change the Ethernet Address of the NIC
4895 * @netdev: network interface device structure
4896 * @p: pointer to an address structure
4898 * Returns 0 on success, negative on failure
4900 static int ixgbe_set_mac(struct net_device
*netdev
, void *p
)
4902 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4903 struct ixgbe_hw
*hw
= &adapter
->hw
;
4904 struct sockaddr
*addr
= p
;
4906 if (!is_valid_ether_addr(addr
->sa_data
))
4907 return -EADDRNOTAVAIL
;
4909 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
4910 memcpy(hw
->mac
.addr
, addr
->sa_data
, netdev
->addr_len
);
4912 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, 0, IXGBE_RAH_AV
);
4918 ixgbe_mdio_read(struct net_device
*netdev
, int prtad
, int devad
, u16 addr
)
4920 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4921 struct ixgbe_hw
*hw
= &adapter
->hw
;
4925 if (prtad
!= hw
->phy
.mdio
.prtad
)
4927 rc
= hw
->phy
.ops
.read_reg(hw
, addr
, devad
, &value
);
4933 static int ixgbe_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
4934 u16 addr
, u16 value
)
4936 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4937 struct ixgbe_hw
*hw
= &adapter
->hw
;
4939 if (prtad
!= hw
->phy
.mdio
.prtad
)
4941 return hw
->phy
.ops
.write_reg(hw
, addr
, devad
, value
);
4944 static int ixgbe_ioctl(struct net_device
*netdev
, struct ifreq
*req
, int cmd
)
4946 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4948 return mdio_mii_ioctl(&adapter
->hw
.phy
.mdio
, if_mii(req
), cmd
);
4952 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
4953 * netdev->dev_addr_list
4954 * @netdev: network interface device structure
4956 * Returns non-zero on failure
4958 static int ixgbe_add_sanmac_netdev(struct net_device
*dev
)
4961 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
4962 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
4964 if (is_valid_ether_addr(mac
->san_addr
)) {
4966 err
= dev_addr_add(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
4973 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
4974 * netdev->dev_addr_list
4975 * @netdev: network interface device structure
4977 * Returns non-zero on failure
4979 static int ixgbe_del_sanmac_netdev(struct net_device
*dev
)
4982 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
4983 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
4985 if (is_valid_ether_addr(mac
->san_addr
)) {
4987 err
= dev_addr_del(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
4993 #ifdef CONFIG_NET_POLL_CONTROLLER
4995 * Polling 'interrupt' - used by things like netconsole to send skbs
4996 * without having to re-enable interrupts. It's not called while
4997 * the interrupt routine is executing.
4999 static void ixgbe_netpoll(struct net_device
*netdev
)
5001 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5003 disable_irq(adapter
->pdev
->irq
);
5004 adapter
->flags
|= IXGBE_FLAG_IN_NETPOLL
;
5005 ixgbe_intr(adapter
->pdev
->irq
, netdev
);
5006 adapter
->flags
&= ~IXGBE_FLAG_IN_NETPOLL
;
5007 enable_irq(adapter
->pdev
->irq
);
5011 static const struct net_device_ops ixgbe_netdev_ops
= {
5012 .ndo_open
= ixgbe_open
,
5013 .ndo_stop
= ixgbe_close
,
5014 .ndo_start_xmit
= ixgbe_xmit_frame
,
5015 .ndo_select_queue
= ixgbe_select_queue
,
5016 .ndo_get_stats
= ixgbe_get_stats
,
5017 .ndo_set_rx_mode
= ixgbe_set_rx_mode
,
5018 .ndo_set_multicast_list
= ixgbe_set_rx_mode
,
5019 .ndo_validate_addr
= eth_validate_addr
,
5020 .ndo_set_mac_address
= ixgbe_set_mac
,
5021 .ndo_change_mtu
= ixgbe_change_mtu
,
5022 .ndo_tx_timeout
= ixgbe_tx_timeout
,
5023 .ndo_vlan_rx_register
= ixgbe_vlan_rx_register
,
5024 .ndo_vlan_rx_add_vid
= ixgbe_vlan_rx_add_vid
,
5025 .ndo_vlan_rx_kill_vid
= ixgbe_vlan_rx_kill_vid
,
5026 .ndo_do_ioctl
= ixgbe_ioctl
,
5027 #ifdef CONFIG_NET_POLL_CONTROLLER
5028 .ndo_poll_controller
= ixgbe_netpoll
,
5031 .ndo_fcoe_ddp_setup
= ixgbe_fcoe_ddp_get
,
5032 .ndo_fcoe_ddp_done
= ixgbe_fcoe_ddp_put
,
5033 #endif /* IXGBE_FCOE */
5037 * ixgbe_probe - Device Initialization Routine
5038 * @pdev: PCI device information struct
5039 * @ent: entry in ixgbe_pci_tbl
5041 * Returns 0 on success, negative on failure
5043 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5044 * The OS initialization, configuring of the adapter private structure,
5045 * and a hardware reset occur.
5047 static int __devinit
ixgbe_probe(struct pci_dev
*pdev
,
5048 const struct pci_device_id
*ent
)
5050 struct net_device
*netdev
;
5051 struct ixgbe_adapter
*adapter
= NULL
;
5052 struct ixgbe_hw
*hw
;
5053 const struct ixgbe_info
*ii
= ixgbe_info_tbl
[ent
->driver_data
];
5054 static int cards_found
;
5055 int i
, err
, pci_using_dac
;
5061 err
= pci_enable_device_mem(pdev
);
5065 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) &&
5066 !pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64))) {
5069 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
5071 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
5073 dev_err(&pdev
->dev
, "No usable DMA "
5074 "configuration, aborting\n");
5081 err
= pci_request_selected_regions(pdev
, pci_select_bars(pdev
,
5082 IORESOURCE_MEM
), ixgbe_driver_name
);
5085 "pci_request_selected_regions failed 0x%x\n", err
);
5089 err
= pci_enable_pcie_error_reporting(pdev
);
5091 dev_err(&pdev
->dev
, "pci_enable_pcie_error_reporting failed "
5093 /* non-fatal, continue */
5096 pci_set_master(pdev
);
5097 pci_save_state(pdev
);
5099 netdev
= alloc_etherdev_mq(sizeof(struct ixgbe_adapter
), MAX_TX_QUEUES
);
5102 goto err_alloc_etherdev
;
5105 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
5107 pci_set_drvdata(pdev
, netdev
);
5108 adapter
= netdev_priv(netdev
);
5110 adapter
->netdev
= netdev
;
5111 adapter
->pdev
= pdev
;
5114 adapter
->msg_enable
= (1 << DEFAULT_DEBUG_LEVEL_SHIFT
) - 1;
5116 hw
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
5117 pci_resource_len(pdev
, 0));
5123 for (i
= 1; i
<= 5; i
++) {
5124 if (pci_resource_len(pdev
, i
) == 0)
5128 netdev
->netdev_ops
= &ixgbe_netdev_ops
;
5129 ixgbe_set_ethtool_ops(netdev
);
5130 netdev
->watchdog_timeo
= 5 * HZ
;
5131 strcpy(netdev
->name
, pci_name(pdev
));
5133 adapter
->bd_number
= cards_found
;
5136 memcpy(&hw
->mac
.ops
, ii
->mac_ops
, sizeof(hw
->mac
.ops
));
5137 hw
->mac
.type
= ii
->mac
;
5140 memcpy(&hw
->eeprom
.ops
, ii
->eeprom_ops
, sizeof(hw
->eeprom
.ops
));
5141 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
5142 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5143 if (!(eec
& (1 << 8)))
5144 hw
->eeprom
.ops
.read
= &ixgbe_read_eeprom_bit_bang_generic
;
5147 memcpy(&hw
->phy
.ops
, ii
->phy_ops
, sizeof(hw
->phy
.ops
));
5148 hw
->phy
.sfp_type
= ixgbe_sfp_type_unknown
;
5149 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5150 hw
->phy
.mdio
.prtad
= MDIO_PRTAD_NONE
;
5151 hw
->phy
.mdio
.mmds
= 0;
5152 hw
->phy
.mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
5153 hw
->phy
.mdio
.dev
= netdev
;
5154 hw
->phy
.mdio
.mdio_read
= ixgbe_mdio_read
;
5155 hw
->phy
.mdio
.mdio_write
= ixgbe_mdio_write
;
5157 /* set up this timer and work struct before calling get_invariants
5158 * which might start the timer
5160 init_timer(&adapter
->sfp_timer
);
5161 adapter
->sfp_timer
.function
= &ixgbe_sfp_timer
;
5162 adapter
->sfp_timer
.data
= (unsigned long) adapter
;
5164 INIT_WORK(&adapter
->sfp_task
, ixgbe_sfp_task
);
5166 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5167 INIT_WORK(&adapter
->multispeed_fiber_task
, ixgbe_multispeed_fiber_task
);
5169 /* a new SFP+ module arrival, called from GPI SDP2 context */
5170 INIT_WORK(&adapter
->sfp_config_module_task
,
5171 ixgbe_sfp_config_module_task
);
5173 ii
->get_invariants(hw
);
5175 /* setup the private structure */
5176 err
= ixgbe_sw_init(adapter
);
5181 * If there is a fan on this device and it has failed log the
5184 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
5185 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
5186 if (esdp
& IXGBE_ESDP_SDP1
)
5187 DPRINTK(PROBE
, CRIT
,
5188 "Fan has stopped, replace the adapter\n");
5191 /* reset_hw fills in the perm_addr as well */
5192 err
= hw
->mac
.ops
.reset_hw(hw
);
5193 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
&&
5194 hw
->mac
.type
== ixgbe_mac_82598EB
) {
5196 * Start a kernel thread to watch for a module to arrive.
5197 * Only do this for 82598, since 82599 will generate
5198 * interrupts on module arrival.
5200 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
5201 mod_timer(&adapter
->sfp_timer
,
5202 round_jiffies(jiffies
+ (2 * HZ
)));
5204 } else if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
5205 dev_err(&adapter
->pdev
->dev
, "failed to load because an "
5206 "unsupported SFP+ module type was detected.\n");
5209 dev_err(&adapter
->pdev
->dev
, "HW Init failed: %d\n", err
);
5213 netdev
->features
= NETIF_F_SG
|
5215 NETIF_F_HW_VLAN_TX
|
5216 NETIF_F_HW_VLAN_RX
|
5217 NETIF_F_HW_VLAN_FILTER
;
5219 netdev
->features
|= NETIF_F_IPV6_CSUM
;
5220 netdev
->features
|= NETIF_F_TSO
;
5221 netdev
->features
|= NETIF_F_TSO6
;
5222 netdev
->features
|= NETIF_F_GRO
;
5224 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
5225 netdev
->features
|= NETIF_F_SCTP_CSUM
;
5227 netdev
->vlan_features
|= NETIF_F_TSO
;
5228 netdev
->vlan_features
|= NETIF_F_TSO6
;
5229 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
5230 netdev
->vlan_features
|= NETIF_F_SG
;
5232 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
5233 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
5235 #ifdef CONFIG_IXGBE_DCB
5236 netdev
->dcbnl_ops
= &dcbnl_ops
;
5240 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
5241 if (hw
->mac
.ops
.get_device_caps
) {
5242 hw
->mac
.ops
.get_device_caps(hw
, &device_caps
);
5243 if (!(device_caps
& IXGBE_DEVICE_CAPS_FCOE_OFFLOADS
)) {
5244 netdev
->features
|= NETIF_F_FCOE_CRC
;
5245 netdev
->features
|= NETIF_F_FSO
;
5246 netdev
->fcoe_ddp_xid
= IXGBE_FCOE_DDP_MAX
- 1;
5248 adapter
->flags
&= ~IXGBE_FLAG_FCOE_ENABLED
;
5252 #endif /* IXGBE_FCOE */
5254 netdev
->features
|= NETIF_F_HIGHDMA
;
5256 if (adapter
->flags
& IXGBE_FLAG_RSC_ENABLED
)
5257 netdev
->features
|= NETIF_F_LRO
;
5259 /* make sure the EEPROM is good */
5260 if (hw
->eeprom
.ops
.validate_checksum(hw
, NULL
) < 0) {
5261 dev_err(&pdev
->dev
, "The EEPROM Checksum Is Not Valid\n");
5266 memcpy(netdev
->dev_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
5267 memcpy(netdev
->perm_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
5269 if (ixgbe_validate_mac_addr(netdev
->perm_addr
)) {
5270 dev_err(&pdev
->dev
, "invalid MAC address\n");
5275 init_timer(&adapter
->watchdog_timer
);
5276 adapter
->watchdog_timer
.function
= &ixgbe_watchdog
;
5277 adapter
->watchdog_timer
.data
= (unsigned long)adapter
;
5279 INIT_WORK(&adapter
->reset_task
, ixgbe_reset_task
);
5280 INIT_WORK(&adapter
->watchdog_task
, ixgbe_watchdog_task
);
5282 err
= ixgbe_init_interrupt_scheme(adapter
);
5286 switch (pdev
->device
) {
5287 case IXGBE_DEV_ID_82599_KX4
:
5288 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
5289 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
5295 device_init_wakeup(&adapter
->pdev
->dev
, true);
5296 device_set_wakeup_enable(&adapter
->pdev
->dev
, adapter
->wol
);
5298 /* pick up the PCI bus settings for reporting later */
5299 hw
->mac
.ops
.get_bus_info(hw
);
5301 /* print bus type/speed/width info */
5302 dev_info(&pdev
->dev
, "(PCI Express:%s:%s) %pM\n",
5303 ((hw
->bus
.speed
== ixgbe_bus_speed_5000
) ? "5.0Gb/s":
5304 (hw
->bus
.speed
== ixgbe_bus_speed_2500
) ? "2.5Gb/s":"Unknown"),
5305 ((hw
->bus
.width
== ixgbe_bus_width_pcie_x8
) ? "Width x8" :
5306 (hw
->bus
.width
== ixgbe_bus_width_pcie_x4
) ? "Width x4" :
5307 (hw
->bus
.width
== ixgbe_bus_width_pcie_x1
) ? "Width x1" :
5310 ixgbe_read_pba_num_generic(hw
, &part_num
);
5311 if (ixgbe_is_sfp(hw
) && hw
->phy
.sfp_type
!= ixgbe_sfp_type_not_present
)
5312 dev_info(&pdev
->dev
, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5313 hw
->mac
.type
, hw
->phy
.type
, hw
->phy
.sfp_type
,
5314 (part_num
>> 8), (part_num
& 0xff));
5316 dev_info(&pdev
->dev
, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5317 hw
->mac
.type
, hw
->phy
.type
,
5318 (part_num
>> 8), (part_num
& 0xff));
5320 if (hw
->bus
.width
<= ixgbe_bus_width_pcie_x4
) {
5321 dev_warn(&pdev
->dev
, "PCI-Express bandwidth available for "
5322 "this card is not sufficient for optimal "
5324 dev_warn(&pdev
->dev
, "For optimal performance a x8 "
5325 "PCI-Express slot is required.\n");
5328 /* save off EEPROM version number */
5329 hw
->eeprom
.ops
.read(hw
, 0x29, &adapter
->eeprom_version
);
5331 /* reset the hardware with the new settings */
5332 hw
->mac
.ops
.start_hw(hw
);
5334 strcpy(netdev
->name
, "eth%d");
5335 err
= register_netdev(netdev
);
5339 /* carrier off reporting is important to ethtool even BEFORE open */
5340 netif_carrier_off(netdev
);
5342 #ifdef CONFIG_IXGBE_DCA
5343 if (dca_add_requester(&pdev
->dev
) == 0) {
5344 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
5345 ixgbe_setup_dca(adapter
);
5348 /* add san mac addr to netdev */
5349 ixgbe_add_sanmac_netdev(netdev
);
5351 dev_info(&pdev
->dev
, "Intel(R) 10 Gigabit Network Connection\n");
5356 ixgbe_release_hw_control(adapter
);
5358 ixgbe_clear_interrupt_scheme(adapter
);
5361 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
5362 del_timer_sync(&adapter
->sfp_timer
);
5363 cancel_work_sync(&adapter
->sfp_task
);
5364 cancel_work_sync(&adapter
->multispeed_fiber_task
);
5365 cancel_work_sync(&adapter
->sfp_config_module_task
);
5366 iounmap(hw
->hw_addr
);
5368 free_netdev(netdev
);
5370 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
5374 pci_disable_device(pdev
);
5379 * ixgbe_remove - Device Removal Routine
5380 * @pdev: PCI device information struct
5382 * ixgbe_remove is called by the PCI subsystem to alert the driver
5383 * that it should release a PCI device. The could be caused by a
5384 * Hot-Plug event, or because the driver is going to be removed from
5387 static void __devexit
ixgbe_remove(struct pci_dev
*pdev
)
5389 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5390 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5393 set_bit(__IXGBE_DOWN
, &adapter
->state
);
5394 /* clear the module not found bit to make sure the worker won't
5397 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
5398 del_timer_sync(&adapter
->watchdog_timer
);
5400 del_timer_sync(&adapter
->sfp_timer
);
5401 cancel_work_sync(&adapter
->watchdog_task
);
5402 cancel_work_sync(&adapter
->sfp_task
);
5403 cancel_work_sync(&adapter
->multispeed_fiber_task
);
5404 cancel_work_sync(&adapter
->sfp_config_module_task
);
5405 flush_scheduled_work();
5407 #ifdef CONFIG_IXGBE_DCA
5408 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
5409 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
5410 dca_remove_requester(&pdev
->dev
);
5411 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
5416 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
5417 ixgbe_cleanup_fcoe(adapter
);
5419 #endif /* IXGBE_FCOE */
5421 /* remove the added san mac */
5422 ixgbe_del_sanmac_netdev(netdev
);
5424 if (netdev
->reg_state
== NETREG_REGISTERED
)
5425 unregister_netdev(netdev
);
5427 ixgbe_clear_interrupt_scheme(adapter
);
5429 ixgbe_release_hw_control(adapter
);
5431 iounmap(adapter
->hw
.hw_addr
);
5432 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
5435 DPRINTK(PROBE
, INFO
, "complete\n");
5437 free_netdev(netdev
);
5439 err
= pci_disable_pcie_error_reporting(pdev
);
5442 "pci_disable_pcie_error_reporting failed 0x%x\n", err
);
5444 pci_disable_device(pdev
);
5448 * ixgbe_io_error_detected - called when PCI error is detected
5449 * @pdev: Pointer to PCI device
5450 * @state: The current pci connection state
5452 * This function is called after a PCI bus error affecting
5453 * this device has been detected.
5455 static pci_ers_result_t
ixgbe_io_error_detected(struct pci_dev
*pdev
,
5456 pci_channel_state_t state
)
5458 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5459 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5461 netif_device_detach(netdev
);
5463 if (state
== pci_channel_io_perm_failure
)
5464 return PCI_ERS_RESULT_DISCONNECT
;
5466 if (netif_running(netdev
))
5467 ixgbe_down(adapter
);
5468 pci_disable_device(pdev
);
5470 /* Request a slot reset. */
5471 return PCI_ERS_RESULT_NEED_RESET
;
5475 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5476 * @pdev: Pointer to PCI device
5478 * Restart the card from scratch, as if from a cold-boot.
5480 static pci_ers_result_t
ixgbe_io_slot_reset(struct pci_dev
*pdev
)
5482 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5483 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5484 pci_ers_result_t result
;
5487 if (pci_enable_device_mem(pdev
)) {
5489 "Cannot re-enable PCI device after reset.\n");
5490 result
= PCI_ERS_RESULT_DISCONNECT
;
5492 pci_set_master(pdev
);
5493 pci_restore_state(pdev
);
5495 pci_wake_from_d3(pdev
, false);
5497 ixgbe_reset(adapter
);
5498 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
5499 result
= PCI_ERS_RESULT_RECOVERED
;
5502 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
5505 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err
);
5506 /* non-fatal, continue */
5513 * ixgbe_io_resume - called when traffic can start flowing again.
5514 * @pdev: Pointer to PCI device
5516 * This callback is called when the error recovery driver tells us that
5517 * its OK to resume normal operation.
5519 static void ixgbe_io_resume(struct pci_dev
*pdev
)
5521 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5522 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5524 if (netif_running(netdev
)) {
5525 if (ixgbe_up(adapter
)) {
5526 DPRINTK(PROBE
, INFO
, "ixgbe_up failed after reset\n");
5531 netif_device_attach(netdev
);
5534 static struct pci_error_handlers ixgbe_err_handler
= {
5535 .error_detected
= ixgbe_io_error_detected
,
5536 .slot_reset
= ixgbe_io_slot_reset
,
5537 .resume
= ixgbe_io_resume
,
5540 static struct pci_driver ixgbe_driver
= {
5541 .name
= ixgbe_driver_name
,
5542 .id_table
= ixgbe_pci_tbl
,
5543 .probe
= ixgbe_probe
,
5544 .remove
= __devexit_p(ixgbe_remove
),
5546 .suspend
= ixgbe_suspend
,
5547 .resume
= ixgbe_resume
,
5549 .shutdown
= ixgbe_shutdown
,
5550 .err_handler
= &ixgbe_err_handler
5554 * ixgbe_init_module - Driver Registration Routine
5556 * ixgbe_init_module is the first routine called when the driver is
5557 * loaded. All it does is register with the PCI subsystem.
5559 static int __init
ixgbe_init_module(void)
5562 printk(KERN_INFO
"%s: %s - version %s\n", ixgbe_driver_name
,
5563 ixgbe_driver_string
, ixgbe_driver_version
);
5565 printk(KERN_INFO
"%s: %s\n", ixgbe_driver_name
, ixgbe_copyright
);
5567 #ifdef CONFIG_IXGBE_DCA
5568 dca_register_notify(&dca_notifier
);
5571 ret
= pci_register_driver(&ixgbe_driver
);
5575 module_init(ixgbe_init_module
);
5578 * ixgbe_exit_module - Driver Exit Cleanup Routine
5580 * ixgbe_exit_module is called just before the driver is removed
5583 static void __exit
ixgbe_exit_module(void)
5585 #ifdef CONFIG_IXGBE_DCA
5586 dca_unregister_notify(&dca_notifier
);
5588 pci_unregister_driver(&ixgbe_driver
);
5591 #ifdef CONFIG_IXGBE_DCA
5592 static int ixgbe_notify_dca(struct notifier_block
*nb
, unsigned long event
,
5597 ret_val
= driver_for_each_device(&ixgbe_driver
.driver
, NULL
, &event
,
5598 __ixgbe_notify_dca
);
5600 return ret_val
? NOTIFY_BAD
: NOTIFY_DONE
;
5603 #endif /* CONFIG_IXGBE_DCA */
5606 * ixgbe_get_hw_dev_name - return device name string
5607 * used by hardware layer to print debugging information
5609 char *ixgbe_get_hw_dev_name(struct ixgbe_hw
*hw
)
5611 struct ixgbe_adapter
*adapter
= hw
->back
;
5612 return adapter
->netdev
->name
;
5616 module_exit(ixgbe_exit_module
);