2 * EDMA3 support for DaVinci
4 * Copyright (C) 2006-2009 Texas Instruments.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 #include <linux/err.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <linux/edma.h>
29 #include <linux/of_address.h>
30 #include <linux/of_device.h>
31 #include <linux/of_dma.h>
32 #include <linux/of_irq.h>
33 #include <linux/pm_runtime.h>
35 #include <linux/platform_data/edma.h>
37 /* Offsets matching "struct edmacc_param" */
40 #define PARM_A_B_CNT 0x08
42 #define PARM_SRC_DST_BIDX 0x10
43 #define PARM_LINK_BCNTRLD 0x14
44 #define PARM_SRC_DST_CIDX 0x18
45 #define PARM_CCNT 0x1c
47 #define PARM_SIZE 0x20
49 /* Offsets for EDMA CC global channel registers and their shadows */
50 #define SH_ER 0x00 /* 64 bits */
51 #define SH_ECR 0x08 /* 64 bits */
52 #define SH_ESR 0x10 /* 64 bits */
53 #define SH_CER 0x18 /* 64 bits */
54 #define SH_EER 0x20 /* 64 bits */
55 #define SH_EECR 0x28 /* 64 bits */
56 #define SH_EESR 0x30 /* 64 bits */
57 #define SH_SER 0x38 /* 64 bits */
58 #define SH_SECR 0x40 /* 64 bits */
59 #define SH_IER 0x50 /* 64 bits */
60 #define SH_IECR 0x58 /* 64 bits */
61 #define SH_IESR 0x60 /* 64 bits */
62 #define SH_IPR 0x68 /* 64 bits */
63 #define SH_ICR 0x70 /* 64 bits */
73 /* Offsets for EDMA CC global registers */
74 #define EDMA_REV 0x0000
75 #define EDMA_CCCFG 0x0004
76 #define EDMA_QCHMAP 0x0200 /* 8 registers */
77 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
78 #define EDMA_QDMAQNUM 0x0260
79 #define EDMA_QUETCMAP 0x0280
80 #define EDMA_QUEPRI 0x0284
81 #define EDMA_EMR 0x0300 /* 64 bits */
82 #define EDMA_EMCR 0x0308 /* 64 bits */
83 #define EDMA_QEMR 0x0310
84 #define EDMA_QEMCR 0x0314
85 #define EDMA_CCERR 0x0318
86 #define EDMA_CCERRCLR 0x031c
87 #define EDMA_EEVAL 0x0320
88 #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
89 #define EDMA_QRAE 0x0380 /* 4 registers */
90 #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
91 #define EDMA_QSTAT 0x0600 /* 2 registers */
92 #define EDMA_QWMTHRA 0x0620
93 #define EDMA_QWMTHRB 0x0624
94 #define EDMA_CCSTAT 0x0640
96 #define EDMA_M 0x1000 /* global channel registers */
97 #define EDMA_ECR 0x1008
98 #define EDMA_ECRH 0x100C
99 #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */
100 #define EDMA_PARM 0x4000 /* 128 param entries */
102 #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
104 #define EDMA_DCHMAP 0x0100 /* 64 registers */
107 #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
108 #define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
109 #define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
110 #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
111 #define CHMAP_EXIST BIT(24)
113 #define EDMA_MAX_DMACH 64
114 #define EDMA_MAX_PARAMENTRY 512
116 /*****************************************************************************/
118 static void __iomem
*edmacc_regs_base
[EDMA_MAX_CC
];
120 static inline unsigned int edma_read(unsigned ctlr
, int offset
)
122 return (unsigned int)__raw_readl(edmacc_regs_base
[ctlr
] + offset
);
125 static inline void edma_write(unsigned ctlr
, int offset
, int val
)
127 __raw_writel(val
, edmacc_regs_base
[ctlr
] + offset
);
129 static inline void edma_modify(unsigned ctlr
, int offset
, unsigned and,
132 unsigned val
= edma_read(ctlr
, offset
);
135 edma_write(ctlr
, offset
, val
);
137 static inline void edma_and(unsigned ctlr
, int offset
, unsigned and)
139 unsigned val
= edma_read(ctlr
, offset
);
141 edma_write(ctlr
, offset
, val
);
143 static inline void edma_or(unsigned ctlr
, int offset
, unsigned or)
145 unsigned val
= edma_read(ctlr
, offset
);
147 edma_write(ctlr
, offset
, val
);
149 static inline unsigned int edma_read_array(unsigned ctlr
, int offset
, int i
)
151 return edma_read(ctlr
, offset
+ (i
<< 2));
153 static inline void edma_write_array(unsigned ctlr
, int offset
, int i
,
156 edma_write(ctlr
, offset
+ (i
<< 2), val
);
158 static inline void edma_modify_array(unsigned ctlr
, int offset
, int i
,
159 unsigned and, unsigned or)
161 edma_modify(ctlr
, offset
+ (i
<< 2), and, or);
163 static inline void edma_or_array(unsigned ctlr
, int offset
, int i
, unsigned or)
165 edma_or(ctlr
, offset
+ (i
<< 2), or);
167 static inline void edma_or_array2(unsigned ctlr
, int offset
, int i
, int j
,
170 edma_or(ctlr
, offset
+ ((i
*2 + j
) << 2), or);
172 static inline void edma_write_array2(unsigned ctlr
, int offset
, int i
, int j
,
175 edma_write(ctlr
, offset
+ ((i
*2 + j
) << 2), val
);
177 static inline unsigned int edma_shadow0_read(unsigned ctlr
, int offset
)
179 return edma_read(ctlr
, EDMA_SHADOW0
+ offset
);
181 static inline unsigned int edma_shadow0_read_array(unsigned ctlr
, int offset
,
184 return edma_read(ctlr
, EDMA_SHADOW0
+ offset
+ (i
<< 2));
186 static inline void edma_shadow0_write(unsigned ctlr
, int offset
, unsigned val
)
188 edma_write(ctlr
, EDMA_SHADOW0
+ offset
, val
);
190 static inline void edma_shadow0_write_array(unsigned ctlr
, int offset
, int i
,
193 edma_write(ctlr
, EDMA_SHADOW0
+ offset
+ (i
<< 2), val
);
195 static inline unsigned int edma_parm_read(unsigned ctlr
, int offset
,
198 return edma_read(ctlr
, EDMA_PARM
+ offset
+ (param_no
<< 5));
200 static inline void edma_parm_write(unsigned ctlr
, int offset
, int param_no
,
203 edma_write(ctlr
, EDMA_PARM
+ offset
+ (param_no
<< 5), val
);
205 static inline void edma_parm_modify(unsigned ctlr
, int offset
, int param_no
,
206 unsigned and, unsigned or)
208 edma_modify(ctlr
, EDMA_PARM
+ offset
+ (param_no
<< 5), and, or);
210 static inline void edma_parm_and(unsigned ctlr
, int offset
, int param_no
,
213 edma_and(ctlr
, EDMA_PARM
+ offset
+ (param_no
<< 5), and);
215 static inline void edma_parm_or(unsigned ctlr
, int offset
, int param_no
,
218 edma_or(ctlr
, EDMA_PARM
+ offset
+ (param_no
<< 5), or);
221 static inline void set_bits(int offset
, int len
, unsigned long *p
)
223 for (; len
> 0; len
--)
224 set_bit(offset
+ (len
- 1), p
);
227 static inline void clear_bits(int offset
, int len
, unsigned long *p
)
229 for (; len
> 0; len
--)
230 clear_bit(offset
+ (len
- 1), p
);
233 /*****************************************************************************/
235 /* actual number of DMA channels and slots on this silicon */
237 /* how many dma resources of each type */
238 unsigned num_channels
;
242 enum dma_event_q default_queue
;
244 /* list of channels with no even trigger; terminated by "-1" */
247 /* The edma_inuse bit for each PaRAM slot is clear unless the
248 * channel is in use ... by ARM or DSP, for QDMA, or whatever.
250 DECLARE_BITMAP(edma_inuse
, EDMA_MAX_PARAMENTRY
);
252 /* The edma_unused bit for each channel is clear unless
253 * it is not being used on this platform. It uses a bit
254 * of SOC-specific initialization code.
256 DECLARE_BITMAP(edma_unused
, EDMA_MAX_DMACH
);
258 unsigned irq_res_start
;
259 unsigned irq_res_end
;
261 struct dma_interrupt_data
{
262 void (*callback
)(unsigned channel
, unsigned short ch_status
,
265 } intr_data
[EDMA_MAX_DMACH
];
268 static struct edma
*edma_cc
[EDMA_MAX_CC
];
269 static int arch_num_cc
;
271 /* dummy param set used to (re)initialize parameter RAM slots */
272 static const struct edmacc_param dummy_paramset
= {
273 .link_bcntrld
= 0xffff,
277 static const struct of_device_id edma_of_ids
[] = {
278 { .compatible
= "ti,edma3", },
282 /*****************************************************************************/
284 static void map_dmach_queue(unsigned ctlr
, unsigned ch_no
,
285 enum dma_event_q queue_no
)
287 int bit
= (ch_no
& 0x7) * 4;
289 /* default to low priority queue */
290 if (queue_no
== EVENTQ_DEFAULT
)
291 queue_no
= edma_cc
[ctlr
]->default_queue
;
294 edma_modify_array(ctlr
, EDMA_DMAQNUM
, (ch_no
>> 3),
295 ~(0x7 << bit
), queue_no
<< bit
);
298 static void __init
assign_priority_to_queue(unsigned ctlr
, int queue_no
,
301 int bit
= queue_no
* 4;
302 edma_modify(ctlr
, EDMA_QUEPRI
, ~(0x7 << bit
),
303 ((priority
& 0x7) << bit
));
307 * map_dmach_param - Maps channel number to param entry number
309 * This maps the dma channel number to param entry numberter. In
310 * other words using the DMA channel mapping registers a param entry
311 * can be mapped to any channel
313 * Callers are responsible for ensuring the channel mapping logic is
314 * included in that particular EDMA variant (Eg : dm646x)
317 static void __init
map_dmach_param(unsigned ctlr
)
320 for (i
= 0; i
< EDMA_MAX_DMACH
; i
++)
321 edma_write_array(ctlr
, EDMA_DCHMAP
, i
, (i
<< 5));
325 setup_dma_interrupt(unsigned lch
,
326 void (*callback
)(unsigned channel
, u16 ch_status
, void *data
),
331 ctlr
= EDMA_CTLR(lch
);
332 lch
= EDMA_CHAN_SLOT(lch
);
335 edma_shadow0_write_array(ctlr
, SH_IECR
, lch
>> 5,
338 edma_cc
[ctlr
]->intr_data
[lch
].callback
= callback
;
339 edma_cc
[ctlr
]->intr_data
[lch
].data
= data
;
342 edma_shadow0_write_array(ctlr
, SH_ICR
, lch
>> 5,
344 edma_shadow0_write_array(ctlr
, SH_IESR
, lch
>> 5,
349 static int irq2ctlr(int irq
)
351 if (irq
>= edma_cc
[0]->irq_res_start
&& irq
<= edma_cc
[0]->irq_res_end
)
353 else if (irq
>= edma_cc
[1]->irq_res_start
&&
354 irq
<= edma_cc
[1]->irq_res_end
)
360 /******************************************************************************
362 * DMA interrupt handler
364 *****************************************************************************/
365 static irqreturn_t
dma_irq_handler(int irq
, void *data
)
372 ctlr
= irq2ctlr(irq
);
376 dev_dbg(data
, "dma_irq_handler\n");
378 sh_ipr
= edma_shadow0_read_array(ctlr
, SH_IPR
, 0);
380 sh_ipr
= edma_shadow0_read_array(ctlr
, SH_IPR
, 1);
383 sh_ier
= edma_shadow0_read_array(ctlr
, SH_IER
, 1);
386 sh_ier
= edma_shadow0_read_array(ctlr
, SH_IER
, 0);
394 dev_dbg(data
, "IPR%d %08x\n", bank
, sh_ipr
);
396 slot
= __ffs(sh_ipr
);
397 sh_ipr
&= ~(BIT(slot
));
399 if (sh_ier
& BIT(slot
)) {
400 channel
= (bank
<< 5) | slot
;
401 /* Clear the corresponding IPR bits */
402 edma_shadow0_write_array(ctlr
, SH_ICR
, bank
,
404 if (edma_cc
[ctlr
]->intr_data
[channel
].callback
)
405 edma_cc
[ctlr
]->intr_data
[channel
].callback(
406 channel
, EDMA_DMA_COMPLETE
,
407 edma_cc
[ctlr
]->intr_data
[channel
].data
);
411 edma_shadow0_write(ctlr
, SH_IEVAL
, 1);
415 /******************************************************************************
417 * DMA error interrupt handler
419 *****************************************************************************/
420 static irqreturn_t
dma_ccerr_handler(int irq
, void *data
)
424 unsigned int cnt
= 0;
426 ctlr
= irq2ctlr(irq
);
430 dev_dbg(data
, "dma_ccerr_handler\n");
432 if ((edma_read_array(ctlr
, EDMA_EMR
, 0) == 0) &&
433 (edma_read_array(ctlr
, EDMA_EMR
, 1) == 0) &&
434 (edma_read(ctlr
, EDMA_QEMR
) == 0) &&
435 (edma_read(ctlr
, EDMA_CCERR
) == 0))
440 if (edma_read_array(ctlr
, EDMA_EMR
, 0))
442 else if (edma_read_array(ctlr
, EDMA_EMR
, 1))
445 dev_dbg(data
, "EMR%d %08x\n", j
,
446 edma_read_array(ctlr
, EDMA_EMR
, j
));
447 for (i
= 0; i
< 32; i
++) {
448 int k
= (j
<< 5) + i
;
449 if (edma_read_array(ctlr
, EDMA_EMR
, j
) &
451 /* Clear the corresponding EMR bits */
452 edma_write_array(ctlr
, EDMA_EMCR
, j
,
455 edma_shadow0_write_array(ctlr
, SH_SECR
,
457 if (edma_cc
[ctlr
]->intr_data
[k
].
459 edma_cc
[ctlr
]->intr_data
[k
].
462 edma_cc
[ctlr
]->intr_data
467 } else if (edma_read(ctlr
, EDMA_QEMR
)) {
468 dev_dbg(data
, "QEMR %02x\n",
469 edma_read(ctlr
, EDMA_QEMR
));
470 for (i
= 0; i
< 8; i
++) {
471 if (edma_read(ctlr
, EDMA_QEMR
) & BIT(i
)) {
472 /* Clear the corresponding IPR bits */
473 edma_write(ctlr
, EDMA_QEMCR
, BIT(i
));
474 edma_shadow0_write(ctlr
, SH_QSECR
,
477 /* NOTE: not reported!! */
480 } else if (edma_read(ctlr
, EDMA_CCERR
)) {
481 dev_dbg(data
, "CCERR %08x\n",
482 edma_read(ctlr
, EDMA_CCERR
));
483 /* FIXME: CCERR.BIT(16) ignored! much better
484 * to just write CCERRCLR with CCERR value...
486 for (i
= 0; i
< 8; i
++) {
487 if (edma_read(ctlr
, EDMA_CCERR
) & BIT(i
)) {
488 /* Clear the corresponding IPR bits */
489 edma_write(ctlr
, EDMA_CCERRCLR
, BIT(i
));
491 /* NOTE: not reported!! */
495 if ((edma_read_array(ctlr
, EDMA_EMR
, 0) == 0) &&
496 (edma_read_array(ctlr
, EDMA_EMR
, 1) == 0) &&
497 (edma_read(ctlr
, EDMA_QEMR
) == 0) &&
498 (edma_read(ctlr
, EDMA_CCERR
) == 0))
504 edma_write(ctlr
, EDMA_EEVAL
, 1);
508 static int reserve_contiguous_slots(int ctlr
, unsigned int id
,
509 unsigned int num_slots
,
510 unsigned int start_slot
)
513 unsigned int count
= num_slots
;
514 int stop_slot
= start_slot
;
515 DECLARE_BITMAP(tmp_inuse
, EDMA_MAX_PARAMENTRY
);
517 for (i
= start_slot
; i
< edma_cc
[ctlr
]->num_slots
; ++i
) {
518 j
= EDMA_CHAN_SLOT(i
);
519 if (!test_and_set_bit(j
, edma_cc
[ctlr
]->edma_inuse
)) {
520 /* Record our current beginning slot */
521 if (count
== num_slots
)
525 set_bit(j
, tmp_inuse
);
530 clear_bit(j
, tmp_inuse
);
532 if (id
== EDMA_CONT_PARAMS_FIXED_EXACT
) {
542 * We have to clear any bits that we set
543 * if we run out parameter RAM slots, i.e we do find a set
544 * of contiguous parameter RAM slots but do not find the exact number
545 * requested as we may reach the total number of parameter RAM slots
547 if (i
== edma_cc
[ctlr
]->num_slots
)
551 for_each_set_bit_from(j
, tmp_inuse
, stop_slot
)
552 clear_bit(j
, edma_cc
[ctlr
]->edma_inuse
);
557 for (j
= i
- num_slots
+ 1; j
<= i
; ++j
)
558 memcpy_toio(edmacc_regs_base
[ctlr
] + PARM_OFFSET(j
),
559 &dummy_paramset
, PARM_SIZE
);
561 return EDMA_CTLR_CHAN(ctlr
, i
- num_slots
+ 1);
564 static int prepare_unused_channel_list(struct device
*dev
, void *data
)
566 struct platform_device
*pdev
= to_platform_device(dev
);
568 struct of_phandle_args dma_spec
;
571 count
= of_property_count_strings(dev
->of_node
, "dma-names");
574 for (i
= 0; i
< count
; i
++) {
575 if (of_parse_phandle_with_args(dev
->of_node
, "dmas",
580 if (!of_match_node(edma_of_ids
, dma_spec
.np
)) {
581 of_node_put(dma_spec
.np
);
585 clear_bit(EDMA_CHAN_SLOT(dma_spec
.args
[0]),
586 edma_cc
[0]->edma_unused
);
587 of_node_put(dma_spec
.np
);
592 /* For non-OF case */
593 for (i
= 0; i
< pdev
->num_resources
; i
++) {
594 if ((pdev
->resource
[i
].flags
& IORESOURCE_DMA
) &&
595 (int)pdev
->resource
[i
].start
>= 0) {
596 ctlr
= EDMA_CTLR(pdev
->resource
[i
].start
);
597 clear_bit(EDMA_CHAN_SLOT(pdev
->resource
[i
].start
),
598 edma_cc
[ctlr
]->edma_unused
);
605 /*-----------------------------------------------------------------------*/
607 static bool unused_chan_list_done
;
609 /* Resource alloc/free: dma channels, parameter RAM slots */
612 * edma_alloc_channel - allocate DMA channel and paired parameter RAM
613 * @channel: specific channel to allocate; negative for "any unmapped channel"
614 * @callback: optional; to be issued on DMA completion or errors
615 * @data: passed to callback
616 * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
617 * Controller (TC) executes requests using this channel. Use
618 * EVENTQ_DEFAULT unless you really need a high priority queue.
620 * This allocates a DMA channel and its associated parameter RAM slot.
621 * The parameter RAM is initialized to hold a dummy transfer.
623 * Normal use is to pass a specific channel number as @channel, to make
624 * use of hardware events mapped to that channel. When the channel will
625 * be used only for software triggering or event chaining, channels not
626 * mapped to hardware events (or mapped to unused events) are preferable.
628 * DMA transfers start from a channel using edma_start(), or by
629 * chaining. When the transfer described in that channel's parameter RAM
630 * slot completes, that slot's data may be reloaded through a link.
632 * DMA errors are only reported to the @callback associated with the
633 * channel driving that transfer, but transfer completion callbacks can
634 * be sent to another channel under control of the TCC field in
635 * the option word of the transfer's parameter RAM set. Drivers must not
636 * use DMA transfer completion callbacks for channels they did not allocate.
637 * (The same applies to TCC codes used in transfer chaining.)
639 * Returns the number of the channel, else negative errno.
641 int edma_alloc_channel(int channel
,
642 void (*callback
)(unsigned channel
, u16 ch_status
, void *data
),
644 enum dma_event_q eventq_no
)
646 unsigned i
, done
= 0, ctlr
= 0;
649 if (!unused_chan_list_done
) {
651 * Scan all the platform devices to find out the EDMA channels
652 * used and clear them in the unused list, making the rest
653 * available for ARM usage.
655 ret
= bus_for_each_dev(&platform_bus_type
, NULL
, NULL
,
656 prepare_unused_channel_list
);
660 unused_chan_list_done
= true;
664 ctlr
= EDMA_CTLR(channel
);
665 channel
= EDMA_CHAN_SLOT(channel
);
669 for (i
= 0; i
< arch_num_cc
; i
++) {
672 channel
= find_next_bit(edma_cc
[i
]->edma_unused
,
673 edma_cc
[i
]->num_channels
,
675 if (channel
== edma_cc
[i
]->num_channels
)
677 if (!test_and_set_bit(channel
,
678 edma_cc
[i
]->edma_inuse
)) {
690 } else if (channel
>= edma_cc
[ctlr
]->num_channels
) {
692 } else if (test_and_set_bit(channel
, edma_cc
[ctlr
]->edma_inuse
)) {
696 /* ensure access through shadow region 0 */
697 edma_or_array2(ctlr
, EDMA_DRAE
, 0, channel
>> 5, BIT(channel
& 0x1f));
699 /* ensure no events are pending */
700 edma_stop(EDMA_CTLR_CHAN(ctlr
, channel
));
701 memcpy_toio(edmacc_regs_base
[ctlr
] + PARM_OFFSET(channel
),
702 &dummy_paramset
, PARM_SIZE
);
705 setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr
, channel
),
708 map_dmach_queue(ctlr
, channel
, eventq_no
);
710 return EDMA_CTLR_CHAN(ctlr
, channel
);
712 EXPORT_SYMBOL(edma_alloc_channel
);
716 * edma_free_channel - deallocate DMA channel
717 * @channel: dma channel returned from edma_alloc_channel()
719 * This deallocates the DMA channel and associated parameter RAM slot
720 * allocated by edma_alloc_channel().
722 * Callers are responsible for ensuring the channel is inactive, and
723 * will not be reactivated by linking, chaining, or software calls to
726 void edma_free_channel(unsigned channel
)
730 ctlr
= EDMA_CTLR(channel
);
731 channel
= EDMA_CHAN_SLOT(channel
);
733 if (channel
>= edma_cc
[ctlr
]->num_channels
)
736 setup_dma_interrupt(channel
, NULL
, NULL
);
737 /* REVISIT should probably take out of shadow region 0 */
739 memcpy_toio(edmacc_regs_base
[ctlr
] + PARM_OFFSET(channel
),
740 &dummy_paramset
, PARM_SIZE
);
741 clear_bit(channel
, edma_cc
[ctlr
]->edma_inuse
);
743 EXPORT_SYMBOL(edma_free_channel
);
746 * edma_alloc_slot - allocate DMA parameter RAM
747 * @slot: specific slot to allocate; negative for "any unused slot"
749 * This allocates a parameter RAM slot, initializing it to hold a
750 * dummy transfer. Slots allocated using this routine have not been
751 * mapped to a hardware DMA channel, and will normally be used by
752 * linking to them from a slot associated with a DMA channel.
754 * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
755 * slots may be allocated on behalf of DSP firmware.
757 * Returns the number of the slot, else negative errno.
759 int edma_alloc_slot(unsigned ctlr
, int slot
)
765 slot
= EDMA_CHAN_SLOT(slot
);
768 slot
= edma_cc
[ctlr
]->num_channels
;
770 slot
= find_next_zero_bit(edma_cc
[ctlr
]->edma_inuse
,
771 edma_cc
[ctlr
]->num_slots
, slot
);
772 if (slot
== edma_cc
[ctlr
]->num_slots
)
774 if (!test_and_set_bit(slot
, edma_cc
[ctlr
]->edma_inuse
))
777 } else if (slot
< edma_cc
[ctlr
]->num_channels
||
778 slot
>= edma_cc
[ctlr
]->num_slots
) {
780 } else if (test_and_set_bit(slot
, edma_cc
[ctlr
]->edma_inuse
)) {
784 memcpy_toio(edmacc_regs_base
[ctlr
] + PARM_OFFSET(slot
),
785 &dummy_paramset
, PARM_SIZE
);
787 return EDMA_CTLR_CHAN(ctlr
, slot
);
789 EXPORT_SYMBOL(edma_alloc_slot
);
792 * edma_free_slot - deallocate DMA parameter RAM
793 * @slot: parameter RAM slot returned from edma_alloc_slot()
795 * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
796 * Callers are responsible for ensuring the slot is inactive, and will
799 void edma_free_slot(unsigned slot
)
803 ctlr
= EDMA_CTLR(slot
);
804 slot
= EDMA_CHAN_SLOT(slot
);
806 if (slot
< edma_cc
[ctlr
]->num_channels
||
807 slot
>= edma_cc
[ctlr
]->num_slots
)
810 memcpy_toio(edmacc_regs_base
[ctlr
] + PARM_OFFSET(slot
),
811 &dummy_paramset
, PARM_SIZE
);
812 clear_bit(slot
, edma_cc
[ctlr
]->edma_inuse
);
814 EXPORT_SYMBOL(edma_free_slot
);
818 * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
819 * The API will return the starting point of a set of
820 * contiguous parameter RAM slots that have been requested
822 * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
823 * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
824 * @count: number of contiguous Paramter RAM slots
825 * @slot - the start value of Parameter RAM slot that should be passed if id
826 * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
828 * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
829 * contiguous Parameter RAM slots from parameter RAM 64 in the case of
830 * DaVinci SOCs and 32 in the case of DA8xx SOCs.
832 * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
833 * set of contiguous parameter RAM slots from the "slot" that is passed as an
834 * argument to the API.
836 * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
837 * starts looking for a set of contiguous parameter RAMs from the "slot"
838 * that is passed as an argument to the API. On failure the API will try to
839 * find a set of contiguous Parameter RAM slots from the remaining Parameter
842 int edma_alloc_cont_slots(unsigned ctlr
, unsigned int id
, int slot
, int count
)
845 * The start slot requested should be greater than
846 * the number of channels and lesser than the total number
849 if ((id
!= EDMA_CONT_PARAMS_ANY
) &&
850 (slot
< edma_cc
[ctlr
]->num_channels
||
851 slot
>= edma_cc
[ctlr
]->num_slots
))
855 * The number of parameter RAM slots requested cannot be less than 1
856 * and cannot be more than the number of slots minus the number of
859 if (count
< 1 || count
>
860 (edma_cc
[ctlr
]->num_slots
- edma_cc
[ctlr
]->num_channels
))
864 case EDMA_CONT_PARAMS_ANY
:
865 return reserve_contiguous_slots(ctlr
, id
, count
,
866 edma_cc
[ctlr
]->num_channels
);
867 case EDMA_CONT_PARAMS_FIXED_EXACT
:
868 case EDMA_CONT_PARAMS_FIXED_NOT_EXACT
:
869 return reserve_contiguous_slots(ctlr
, id
, count
, slot
);
875 EXPORT_SYMBOL(edma_alloc_cont_slots
);
878 * edma_free_cont_slots - deallocate DMA parameter RAM slots
879 * @slot: first parameter RAM of a set of parameter RAM slots to be freed
880 * @count: the number of contiguous parameter RAM slots to be freed
882 * This deallocates the parameter RAM slots allocated by
883 * edma_alloc_cont_slots.
884 * Callers/applications need to keep track of sets of contiguous
885 * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
887 * Callers are responsible for ensuring the slots are inactive, and will
890 int edma_free_cont_slots(unsigned slot
, int count
)
892 unsigned ctlr
, slot_to_free
;
895 ctlr
= EDMA_CTLR(slot
);
896 slot
= EDMA_CHAN_SLOT(slot
);
898 if (slot
< edma_cc
[ctlr
]->num_channels
||
899 slot
>= edma_cc
[ctlr
]->num_slots
||
903 for (i
= slot
; i
< slot
+ count
; ++i
) {
905 slot_to_free
= EDMA_CHAN_SLOT(i
);
907 memcpy_toio(edmacc_regs_base
[ctlr
] + PARM_OFFSET(slot_to_free
),
908 &dummy_paramset
, PARM_SIZE
);
909 clear_bit(slot_to_free
, edma_cc
[ctlr
]->edma_inuse
);
914 EXPORT_SYMBOL(edma_free_cont_slots
);
916 /*-----------------------------------------------------------------------*/
918 /* Parameter RAM operations (i) -- read/write partial slots */
921 * edma_set_src - set initial DMA source address in parameter RAM slot
922 * @slot: parameter RAM slot being configured
923 * @src_port: physical address of source (memory, controller FIFO, etc)
924 * @addressMode: INCR, except in very rare cases
925 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
926 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
928 * Note that the source address is modified during the DMA transfer
929 * according to edma_set_src_index().
931 void edma_set_src(unsigned slot
, dma_addr_t src_port
,
932 enum address_mode mode
, enum fifo_width width
)
936 ctlr
= EDMA_CTLR(slot
);
937 slot
= EDMA_CHAN_SLOT(slot
);
939 if (slot
< edma_cc
[ctlr
]->num_slots
) {
940 unsigned int i
= edma_parm_read(ctlr
, PARM_OPT
, slot
);
943 /* set SAM and program FWID */
944 i
= (i
& ~(EDMA_FWID
)) | (SAM
| ((width
& 0x7) << 8));
949 edma_parm_write(ctlr
, PARM_OPT
, slot
, i
);
951 /* set the source port address
952 in source register of param structure */
953 edma_parm_write(ctlr
, PARM_SRC
, slot
, src_port
);
956 EXPORT_SYMBOL(edma_set_src
);
959 * edma_set_dest - set initial DMA destination address in parameter RAM slot
960 * @slot: parameter RAM slot being configured
961 * @dest_port: physical address of destination (memory, controller FIFO, etc)
962 * @addressMode: INCR, except in very rare cases
963 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
964 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
966 * Note that the destination address is modified during the DMA transfer
967 * according to edma_set_dest_index().
969 void edma_set_dest(unsigned slot
, dma_addr_t dest_port
,
970 enum address_mode mode
, enum fifo_width width
)
974 ctlr
= EDMA_CTLR(slot
);
975 slot
= EDMA_CHAN_SLOT(slot
);
977 if (slot
< edma_cc
[ctlr
]->num_slots
) {
978 unsigned int i
= edma_parm_read(ctlr
, PARM_OPT
, slot
);
981 /* set DAM and program FWID */
982 i
= (i
& ~(EDMA_FWID
)) | (DAM
| ((width
& 0x7) << 8));
987 edma_parm_write(ctlr
, PARM_OPT
, slot
, i
);
988 /* set the destination port address
989 in dest register of param structure */
990 edma_parm_write(ctlr
, PARM_DST
, slot
, dest_port
);
993 EXPORT_SYMBOL(edma_set_dest
);
996 * edma_get_position - returns the current transfer point
997 * @slot: parameter RAM slot being examined
998 * @dst: true selects the dest position, false the source
1000 * Returns the position of the current active slot
1002 dma_addr_t
edma_get_position(unsigned slot
, bool dst
)
1004 u32 offs
, ctlr
= EDMA_CTLR(slot
);
1006 slot
= EDMA_CHAN_SLOT(slot
);
1008 offs
= PARM_OFFSET(slot
);
1009 offs
+= dst
? PARM_DST
: PARM_SRC
;
1011 return edma_read(ctlr
, offs
);
1015 * edma_set_src_index - configure DMA source address indexing
1016 * @slot: parameter RAM slot being configured
1017 * @src_bidx: byte offset between source arrays in a frame
1018 * @src_cidx: byte offset between source frames in a block
1020 * Offsets are specified to support either contiguous or discontiguous
1021 * memory transfers, or repeated access to a hardware register, as needed.
1022 * When accessing hardware registers, both offsets are normally zero.
1024 void edma_set_src_index(unsigned slot
, s16 src_bidx
, s16 src_cidx
)
1028 ctlr
= EDMA_CTLR(slot
);
1029 slot
= EDMA_CHAN_SLOT(slot
);
1031 if (slot
< edma_cc
[ctlr
]->num_slots
) {
1032 edma_parm_modify(ctlr
, PARM_SRC_DST_BIDX
, slot
,
1033 0xffff0000, src_bidx
);
1034 edma_parm_modify(ctlr
, PARM_SRC_DST_CIDX
, slot
,
1035 0xffff0000, src_cidx
);
1038 EXPORT_SYMBOL(edma_set_src_index
);
1041 * edma_set_dest_index - configure DMA destination address indexing
1042 * @slot: parameter RAM slot being configured
1043 * @dest_bidx: byte offset between destination arrays in a frame
1044 * @dest_cidx: byte offset between destination frames in a block
1046 * Offsets are specified to support either contiguous or discontiguous
1047 * memory transfers, or repeated access to a hardware register, as needed.
1048 * When accessing hardware registers, both offsets are normally zero.
1050 void edma_set_dest_index(unsigned slot
, s16 dest_bidx
, s16 dest_cidx
)
1054 ctlr
= EDMA_CTLR(slot
);
1055 slot
= EDMA_CHAN_SLOT(slot
);
1057 if (slot
< edma_cc
[ctlr
]->num_slots
) {
1058 edma_parm_modify(ctlr
, PARM_SRC_DST_BIDX
, slot
,
1059 0x0000ffff, dest_bidx
<< 16);
1060 edma_parm_modify(ctlr
, PARM_SRC_DST_CIDX
, slot
,
1061 0x0000ffff, dest_cidx
<< 16);
1064 EXPORT_SYMBOL(edma_set_dest_index
);
1067 * edma_set_transfer_params - configure DMA transfer parameters
1068 * @slot: parameter RAM slot being configured
1069 * @acnt: how many bytes per array (at least one)
1070 * @bcnt: how many arrays per frame (at least one)
1071 * @ccnt: how many frames per block (at least one)
1072 * @bcnt_rld: used only for A-Synchronized transfers; this specifies
1073 * the value to reload into bcnt when it decrements to zero
1074 * @sync_mode: ASYNC or ABSYNC
1076 * See the EDMA3 documentation to understand how to configure and link
1077 * transfers using the fields in PaRAM slots. If you are not doing it
1078 * all at once with edma_write_slot(), you will use this routine
1079 * plus two calls each for source and destination, setting the initial
1080 * address and saying how to index that address.
1082 * An example of an A-Synchronized transfer is a serial link using a
1083 * single word shift register. In that case, @acnt would be equal to
1084 * that word size; the serial controller issues a DMA synchronization
1085 * event to transfer each word, and memory access by the DMA transfer
1086 * controller will be word-at-a-time.
1088 * An example of an AB-Synchronized transfer is a device using a FIFO.
1089 * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
1090 * The controller with the FIFO issues DMA synchronization events when
1091 * the FIFO threshold is reached, and the DMA transfer controller will
1092 * transfer one frame to (or from) the FIFO. It will probably use
1093 * efficient burst modes to access memory.
1095 void edma_set_transfer_params(unsigned slot
,
1096 u16 acnt
, u16 bcnt
, u16 ccnt
,
1097 u16 bcnt_rld
, enum sync_dimension sync_mode
)
1101 ctlr
= EDMA_CTLR(slot
);
1102 slot
= EDMA_CHAN_SLOT(slot
);
1104 if (slot
< edma_cc
[ctlr
]->num_slots
) {
1105 edma_parm_modify(ctlr
, PARM_LINK_BCNTRLD
, slot
,
1106 0x0000ffff, bcnt_rld
<< 16);
1107 if (sync_mode
== ASYNC
)
1108 edma_parm_and(ctlr
, PARM_OPT
, slot
, ~SYNCDIM
);
1110 edma_parm_or(ctlr
, PARM_OPT
, slot
, SYNCDIM
);
1111 /* Set the acount, bcount, ccount registers */
1112 edma_parm_write(ctlr
, PARM_A_B_CNT
, slot
, (bcnt
<< 16) | acnt
);
1113 edma_parm_write(ctlr
, PARM_CCNT
, slot
, ccnt
);
1116 EXPORT_SYMBOL(edma_set_transfer_params
);
1119 * edma_link - link one parameter RAM slot to another
1120 * @from: parameter RAM slot originating the link
1121 * @to: parameter RAM slot which is the link target
1123 * The originating slot should not be part of any active DMA transfer.
1125 void edma_link(unsigned from
, unsigned to
)
1127 unsigned ctlr_from
, ctlr_to
;
1129 ctlr_from
= EDMA_CTLR(from
);
1130 from
= EDMA_CHAN_SLOT(from
);
1131 ctlr_to
= EDMA_CTLR(to
);
1132 to
= EDMA_CHAN_SLOT(to
);
1134 if (from
>= edma_cc
[ctlr_from
]->num_slots
)
1136 if (to
>= edma_cc
[ctlr_to
]->num_slots
)
1138 edma_parm_modify(ctlr_from
, PARM_LINK_BCNTRLD
, from
, 0xffff0000,
1141 EXPORT_SYMBOL(edma_link
);
1144 * edma_unlink - cut link from one parameter RAM slot
1145 * @from: parameter RAM slot originating the link
1147 * The originating slot should not be part of any active DMA transfer.
1148 * Its link is set to 0xffff.
1150 void edma_unlink(unsigned from
)
1154 ctlr
= EDMA_CTLR(from
);
1155 from
= EDMA_CHAN_SLOT(from
);
1157 if (from
>= edma_cc
[ctlr
]->num_slots
)
1159 edma_parm_or(ctlr
, PARM_LINK_BCNTRLD
, from
, 0xffff);
1161 EXPORT_SYMBOL(edma_unlink
);
1163 /*-----------------------------------------------------------------------*/
1165 /* Parameter RAM operations (ii) -- read/write whole parameter sets */
1168 * edma_write_slot - write parameter RAM data for slot
1169 * @slot: number of parameter RAM slot being modified
1170 * @param: data to be written into parameter RAM slot
1172 * Use this to assign all parameters of a transfer at once. This
1173 * allows more efficient setup of transfers than issuing multiple
1174 * calls to set up those parameters in small pieces, and provides
1175 * complete control over all transfer options.
1177 void edma_write_slot(unsigned slot
, const struct edmacc_param
*param
)
1181 ctlr
= EDMA_CTLR(slot
);
1182 slot
= EDMA_CHAN_SLOT(slot
);
1184 if (slot
>= edma_cc
[ctlr
]->num_slots
)
1186 memcpy_toio(edmacc_regs_base
[ctlr
] + PARM_OFFSET(slot
), param
,
1189 EXPORT_SYMBOL(edma_write_slot
);
1192 * edma_read_slot - read parameter RAM data from slot
1193 * @slot: number of parameter RAM slot being copied
1194 * @param: where to store copy of parameter RAM data
1196 * Use this to read data from a parameter RAM slot, perhaps to
1197 * save them as a template for later reuse.
1199 void edma_read_slot(unsigned slot
, struct edmacc_param
*param
)
1203 ctlr
= EDMA_CTLR(slot
);
1204 slot
= EDMA_CHAN_SLOT(slot
);
1206 if (slot
>= edma_cc
[ctlr
]->num_slots
)
1208 memcpy_fromio(param
, edmacc_regs_base
[ctlr
] + PARM_OFFSET(slot
),
1211 EXPORT_SYMBOL(edma_read_slot
);
1213 /*-----------------------------------------------------------------------*/
1215 /* Various EDMA channel control operations */
1218 * edma_pause - pause dma on a channel
1219 * @channel: on which edma_start() has been called
1221 * This temporarily disables EDMA hardware events on the specified channel,
1222 * preventing them from triggering new transfers on its behalf
1224 void edma_pause(unsigned channel
)
1228 ctlr
= EDMA_CTLR(channel
);
1229 channel
= EDMA_CHAN_SLOT(channel
);
1231 if (channel
< edma_cc
[ctlr
]->num_channels
) {
1232 unsigned int mask
= BIT(channel
& 0x1f);
1234 edma_shadow0_write_array(ctlr
, SH_EECR
, channel
>> 5, mask
);
1237 EXPORT_SYMBOL(edma_pause
);
1240 * edma_resume - resumes dma on a paused channel
1241 * @channel: on which edma_pause() has been called
1243 * This re-enables EDMA hardware events on the specified channel.
1245 void edma_resume(unsigned channel
)
1249 ctlr
= EDMA_CTLR(channel
);
1250 channel
= EDMA_CHAN_SLOT(channel
);
1252 if (channel
< edma_cc
[ctlr
]->num_channels
) {
1253 unsigned int mask
= BIT(channel
& 0x1f);
1255 edma_shadow0_write_array(ctlr
, SH_EESR
, channel
>> 5, mask
);
1258 EXPORT_SYMBOL(edma_resume
);
1260 int edma_trigger_channel(unsigned channel
)
1265 ctlr
= EDMA_CTLR(channel
);
1266 channel
= EDMA_CHAN_SLOT(channel
);
1267 mask
= BIT(channel
& 0x1f);
1269 edma_shadow0_write_array(ctlr
, SH_ESR
, (channel
>> 5), mask
);
1271 pr_debug("EDMA: ESR%d %08x\n", (channel
>> 5),
1272 edma_shadow0_read_array(ctlr
, SH_ESR
, (channel
>> 5)));
1275 EXPORT_SYMBOL(edma_trigger_channel
);
1278 * edma_start - start dma on a channel
1279 * @channel: channel being activated
1281 * Channels with event associations will be triggered by their hardware
1282 * events, and channels without such associations will be triggered by
1283 * software. (At this writing there is no interface for using software
1284 * triggers except with channels that don't support hardware triggers.)
1286 * Returns zero on success, else negative errno.
1288 int edma_start(unsigned channel
)
1292 ctlr
= EDMA_CTLR(channel
);
1293 channel
= EDMA_CHAN_SLOT(channel
);
1295 if (channel
< edma_cc
[ctlr
]->num_channels
) {
1296 int j
= channel
>> 5;
1297 unsigned int mask
= BIT(channel
& 0x1f);
1299 /* EDMA channels without event association */
1300 if (test_bit(channel
, edma_cc
[ctlr
]->edma_unused
)) {
1301 pr_debug("EDMA: ESR%d %08x\n", j
,
1302 edma_shadow0_read_array(ctlr
, SH_ESR
, j
));
1303 edma_shadow0_write_array(ctlr
, SH_ESR
, j
, mask
);
1307 /* EDMA channel with event association */
1308 pr_debug("EDMA: ER%d %08x\n", j
,
1309 edma_shadow0_read_array(ctlr
, SH_ER
, j
));
1310 /* Clear any pending event or error */
1311 edma_write_array(ctlr
, EDMA_ECR
, j
, mask
);
1312 edma_write_array(ctlr
, EDMA_EMCR
, j
, mask
);
1314 edma_shadow0_write_array(ctlr
, SH_SECR
, j
, mask
);
1315 edma_shadow0_write_array(ctlr
, SH_EESR
, j
, mask
);
1316 pr_debug("EDMA: EER%d %08x\n", j
,
1317 edma_shadow0_read_array(ctlr
, SH_EER
, j
));
1323 EXPORT_SYMBOL(edma_start
);
1326 * edma_stop - stops dma on the channel passed
1327 * @channel: channel being deactivated
1329 * When @lch is a channel, any active transfer is paused and
1330 * all pending hardware events are cleared. The current transfer
1331 * may not be resumed, and the channel's Parameter RAM should be
1332 * reinitialized before being reused.
1334 void edma_stop(unsigned channel
)
1338 ctlr
= EDMA_CTLR(channel
);
1339 channel
= EDMA_CHAN_SLOT(channel
);
1341 if (channel
< edma_cc
[ctlr
]->num_channels
) {
1342 int j
= channel
>> 5;
1343 unsigned int mask
= BIT(channel
& 0x1f);
1345 edma_shadow0_write_array(ctlr
, SH_EECR
, j
, mask
);
1346 edma_shadow0_write_array(ctlr
, SH_ECR
, j
, mask
);
1347 edma_shadow0_write_array(ctlr
, SH_SECR
, j
, mask
);
1348 edma_write_array(ctlr
, EDMA_EMCR
, j
, mask
);
1350 pr_debug("EDMA: EER%d %08x\n", j
,
1351 edma_shadow0_read_array(ctlr
, SH_EER
, j
));
1353 /* REVISIT: consider guarding against inappropriate event
1354 * chaining by overwriting with dummy_paramset.
1358 EXPORT_SYMBOL(edma_stop
);
1360 /******************************************************************************
1362 * It cleans ParamEntry qand bring back EDMA to initial state if media has
1363 * been removed before EDMA has finished.It is usedful for removable media.
1365 * ch_no - channel no
1367 * Return: zero on success, or corresponding error no on failure
1369 * FIXME this should not be needed ... edma_stop() should suffice.
1371 *****************************************************************************/
1373 void edma_clean_channel(unsigned channel
)
1377 ctlr
= EDMA_CTLR(channel
);
1378 channel
= EDMA_CHAN_SLOT(channel
);
1380 if (channel
< edma_cc
[ctlr
]->num_channels
) {
1381 int j
= (channel
>> 5);
1382 unsigned int mask
= BIT(channel
& 0x1f);
1384 pr_debug("EDMA: EMR%d %08x\n", j
,
1385 edma_read_array(ctlr
, EDMA_EMR
, j
));
1386 edma_shadow0_write_array(ctlr
, SH_ECR
, j
, mask
);
1387 /* Clear the corresponding EMR bits */
1388 edma_write_array(ctlr
, EDMA_EMCR
, j
, mask
);
1390 edma_shadow0_write_array(ctlr
, SH_SECR
, j
, mask
);
1391 edma_write(ctlr
, EDMA_CCERRCLR
, BIT(16) | BIT(1) | BIT(0));
1394 EXPORT_SYMBOL(edma_clean_channel
);
1397 * edma_clear_event - clear an outstanding event on the DMA channel
1399 * channel - channel number
1401 void edma_clear_event(unsigned channel
)
1405 ctlr
= EDMA_CTLR(channel
);
1406 channel
= EDMA_CHAN_SLOT(channel
);
1408 if (channel
>= edma_cc
[ctlr
]->num_channels
)
1411 edma_write(ctlr
, EDMA_ECR
, BIT(channel
));
1413 edma_write(ctlr
, EDMA_ECRH
, BIT(channel
- 32));
1415 EXPORT_SYMBOL(edma_clear_event
);
1418 * edma_assign_channel_eventq - move given channel to desired eventq
1420 * channel - channel number
1421 * eventq_no - queue to move the channel
1423 * Can be used to move a channel to a selected event queue.
1425 void edma_assign_channel_eventq(unsigned channel
, enum dma_event_q eventq_no
)
1429 ctlr
= EDMA_CTLR(channel
);
1430 channel
= EDMA_CHAN_SLOT(channel
);
1432 if (channel
>= edma_cc
[ctlr
]->num_channels
)
1435 /* default to low priority queue */
1436 if (eventq_no
== EVENTQ_DEFAULT
)
1437 eventq_no
= edma_cc
[ctlr
]->default_queue
;
1438 if (eventq_no
>= edma_cc
[ctlr
]->num_tc
)
1441 map_dmach_queue(ctlr
, channel
, eventq_no
);
1443 EXPORT_SYMBOL(edma_assign_channel_eventq
);
1445 static int edma_setup_from_hw(struct device
*dev
, struct edma_soc_info
*pdata
,
1446 struct edma
*edma_cc
)
1450 s8 (*queue_priority_map
)[2];
1452 /* Decode the eDMA3 configuration from CCCFG register */
1453 cccfg
= edma_read(0, EDMA_CCCFG
);
1455 value
= GET_NUM_REGN(cccfg
);
1456 edma_cc
->num_region
= BIT(value
);
1458 value
= GET_NUM_DMACH(cccfg
);
1459 edma_cc
->num_channels
= BIT(value
+ 1);
1461 value
= GET_NUM_PAENTRY(cccfg
);
1462 edma_cc
->num_slots
= BIT(value
+ 4);
1464 value
= GET_NUM_EVQUE(cccfg
);
1465 edma_cc
->num_tc
= value
+ 1;
1467 dev_dbg(dev
, "eDMA3 HW configuration (cccfg: 0x%08x):\n", cccfg
);
1468 dev_dbg(dev
, "num_region: %u\n", edma_cc
->num_region
);
1469 dev_dbg(dev
, "num_channel: %u\n", edma_cc
->num_channels
);
1470 dev_dbg(dev
, "num_slot: %u\n", edma_cc
->num_slots
);
1471 dev_dbg(dev
, "num_tc: %u\n", edma_cc
->num_tc
);
1473 /* Nothing need to be done if queue priority is provided */
1474 if (pdata
->queue_priority_mapping
)
1478 * Configure TC/queue priority as follows:
1483 * The meaning of priority numbers: 0 highest priority, 7 lowest
1484 * priority. So Q0 is the highest priority queue and the last queue has
1485 * the lowest priority.
1487 queue_priority_map
= devm_kzalloc(dev
,
1488 (edma_cc
->num_tc
+ 1) * sizeof(s8
),
1490 if (!queue_priority_map
)
1493 for (i
= 0; i
< edma_cc
->num_tc
; i
++) {
1494 queue_priority_map
[i
][0] = i
;
1495 queue_priority_map
[i
][1] = i
;
1497 queue_priority_map
[i
][0] = -1;
1498 queue_priority_map
[i
][1] = -1;
1500 pdata
->queue_priority_mapping
= queue_priority_map
;
1501 /* Default queue has the lowest priority */
1502 pdata
->default_queue
= i
- 1;
1507 #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)
1509 static int edma_xbar_event_map(struct device
*dev
, struct device_node
*node
,
1510 struct edma_soc_info
*pdata
, size_t sz
)
1512 const char pname
[] = "ti,edma-xbar-event-map";
1513 struct resource res
;
1515 s16 (*xbar_chans
)[2];
1516 size_t nelm
= sz
/ sizeof(s16
);
1517 u32 shift
, offset
, mux
;
1520 xbar_chans
= devm_kzalloc(dev
, (nelm
+ 2) * sizeof(s16
), GFP_KERNEL
);
1524 ret
= of_address_to_resource(node
, 1, &res
);
1528 xbar
= devm_ioremap(dev
, res
.start
, resource_size(&res
));
1532 ret
= of_property_read_u16_array(node
, pname
, (u16
*)xbar_chans
, nelm
);
1536 /* Invalidate last entry for the other user of this mess */
1538 xbar_chans
[nelm
][0] = xbar_chans
[nelm
][1] = -1;
1540 for (i
= 0; i
< nelm
; i
++) {
1541 shift
= (xbar_chans
[i
][1] & 0x03) << 3;
1542 offset
= xbar_chans
[i
][1] & 0xfffffffc;
1543 mux
= readl(xbar
+ offset
);
1544 mux
&= ~(0xff << shift
);
1545 mux
|= xbar_chans
[i
][0] << shift
;
1546 writel(mux
, (xbar
+ offset
));
1549 pdata
->xbar_chans
= (const s16 (*)[2]) xbar_chans
;
1553 static int edma_of_parse_dt(struct device
*dev
,
1554 struct device_node
*node
,
1555 struct edma_soc_info
*pdata
)
1558 struct property
*prop
;
1560 struct edma_rsv_info
*rsv_info
;
1562 rsv_info
= devm_kzalloc(dev
, sizeof(struct edma_rsv_info
), GFP_KERNEL
);
1565 pdata
->rsv
= rsv_info
;
1567 prop
= of_find_property(node
, "ti,edma-xbar-event-map", &sz
);
1569 ret
= edma_xbar_event_map(dev
, node
, pdata
, sz
);
1574 static struct of_dma_filter_info edma_filter_info
= {
1575 .filter_fn
= edma_filter_fn
,
1578 static struct edma_soc_info
*edma_setup_info_from_dt(struct device
*dev
,
1579 struct device_node
*node
)
1581 struct edma_soc_info
*info
;
1584 info
= devm_kzalloc(dev
, sizeof(struct edma_soc_info
), GFP_KERNEL
);
1586 return ERR_PTR(-ENOMEM
);
1588 ret
= edma_of_parse_dt(dev
, node
, info
);
1590 return ERR_PTR(ret
);
1592 dma_cap_set(DMA_SLAVE
, edma_filter_info
.dma_cap
);
1593 dma_cap_set(DMA_CYCLIC
, edma_filter_info
.dma_cap
);
1594 of_dma_controller_register(dev
->of_node
, of_dma_simple_xlate
,
1600 static struct edma_soc_info
*edma_setup_info_from_dt(struct device
*dev
,
1601 struct device_node
*node
)
1603 return ERR_PTR(-ENOSYS
);
1607 static int edma_probe(struct platform_device
*pdev
)
1609 struct edma_soc_info
**info
= pdev
->dev
.platform_data
;
1610 struct edma_soc_info
*ninfo
[EDMA_MAX_CC
] = {NULL
};
1611 s8 (*queue_priority_mapping
)[2];
1612 int i
, j
, off
, ln
, found
= 0;
1614 const s16 (*rsv_chans
)[2];
1615 const s16 (*rsv_slots
)[2];
1616 const s16 (*xbar_chans
)[2];
1617 int irq
[EDMA_MAX_CC
] = {0, 0};
1618 int err_irq
[EDMA_MAX_CC
] = {0, 0};
1619 struct resource
*r
[EDMA_MAX_CC
] = {NULL
};
1620 struct resource res
[EDMA_MAX_CC
];
1622 struct device_node
*node
= pdev
->dev
.of_node
;
1623 struct device
*dev
= &pdev
->dev
;
1627 /* Check if this is a second instance registered */
1629 dev_err(dev
, "only one EDMA instance is supported via DT\n");
1633 ninfo
[0] = edma_setup_info_from_dt(dev
, node
);
1634 if (IS_ERR(ninfo
[0])) {
1635 dev_err(dev
, "failed to get DT data\n");
1636 return PTR_ERR(ninfo
[0]);
1645 pm_runtime_enable(dev
);
1646 ret
= pm_runtime_get_sync(dev
);
1648 dev_err(dev
, "pm_runtime_get_sync() failed\n");
1652 for (j
= 0; j
< EDMA_MAX_CC
; j
++) {
1659 ret
= of_address_to_resource(node
, j
, &res
[j
]);
1663 sprintf(res_name
, "edma_cc%d", j
);
1664 r
[j
] = platform_get_resource_byname(pdev
,
1677 edmacc_regs_base
[j
] = devm_ioremap_resource(&pdev
->dev
, r
[j
]);
1678 if (IS_ERR(edmacc_regs_base
[j
]))
1679 return PTR_ERR(edmacc_regs_base
[j
]);
1681 edma_cc
[j
] = devm_kzalloc(&pdev
->dev
, sizeof(struct edma
),
1686 /* Get eDMA3 configuration from IP */
1687 ret
= edma_setup_from_hw(dev
, info
[j
], edma_cc
[j
]);
1691 edma_cc
[j
]->default_queue
= info
[j
]->default_queue
;
1693 dev_dbg(&pdev
->dev
, "DMA REG BASE ADDR=%p\n",
1694 edmacc_regs_base
[j
]);
1696 for (i
= 0; i
< edma_cc
[j
]->num_slots
; i
++)
1697 memcpy_toio(edmacc_regs_base
[j
] + PARM_OFFSET(i
),
1698 &dummy_paramset
, PARM_SIZE
);
1700 /* Mark all channels as unused */
1701 memset(edma_cc
[j
]->edma_unused
, 0xff,
1702 sizeof(edma_cc
[j
]->edma_unused
));
1706 /* Clear the reserved channels in unused list */
1707 rsv_chans
= info
[j
]->rsv
->rsv_chans
;
1709 for (i
= 0; rsv_chans
[i
][0] != -1; i
++) {
1710 off
= rsv_chans
[i
][0];
1711 ln
= rsv_chans
[i
][1];
1713 edma_cc
[j
]->edma_unused
);
1717 /* Set the reserved slots in inuse list */
1718 rsv_slots
= info
[j
]->rsv
->rsv_slots
;
1720 for (i
= 0; rsv_slots
[i
][0] != -1; i
++) {
1721 off
= rsv_slots
[i
][0];
1722 ln
= rsv_slots
[i
][1];
1724 edma_cc
[j
]->edma_inuse
);
1729 /* Clear the xbar mapped channels in unused list */
1730 xbar_chans
= info
[j
]->xbar_chans
;
1732 for (i
= 0; xbar_chans
[i
][1] != -1; i
++) {
1733 off
= xbar_chans
[i
][1];
1735 edma_cc
[j
]->edma_unused
);
1740 irq
[j
] = irq_of_parse_and_map(node
, 0);
1741 err_irq
[j
] = irq_of_parse_and_map(node
, 2);
1745 sprintf(irq_name
, "edma%d", j
);
1746 irq
[j
] = platform_get_irq_byname(pdev
, irq_name
);
1748 sprintf(irq_name
, "edma%d_err", j
);
1749 err_irq
[j
] = platform_get_irq_byname(pdev
, irq_name
);
1751 edma_cc
[j
]->irq_res_start
= irq
[j
];
1752 edma_cc
[j
]->irq_res_end
= err_irq
[j
];
1754 status
= devm_request_irq(dev
, irq
[j
], dma_irq_handler
, 0,
1758 "devm_request_irq %d failed --> %d\n",
1763 status
= devm_request_irq(dev
, err_irq
[j
], dma_ccerr_handler
, 0,
1767 "devm_request_irq %d failed --> %d\n",
1768 err_irq
[j
], status
);
1772 for (i
= 0; i
< edma_cc
[j
]->num_channels
; i
++)
1773 map_dmach_queue(j
, i
, info
[j
]->default_queue
);
1775 queue_priority_mapping
= info
[j
]->queue_priority_mapping
;
1777 /* Event queue priority mapping */
1778 for (i
= 0; queue_priority_mapping
[i
][0] != -1; i
++)
1779 assign_priority_to_queue(j
,
1780 queue_priority_mapping
[i
][0],
1781 queue_priority_mapping
[i
][1]);
1783 /* Map the channel to param entry if channel mapping logic
1786 if (edma_read(j
, EDMA_CCCFG
) & CHMAP_EXIST
)
1789 for (i
= 0; i
< edma_cc
[j
]->num_region
; i
++) {
1790 edma_write_array2(j
, EDMA_DRAE
, i
, 0, 0x0);
1791 edma_write_array2(j
, EDMA_DRAE
, i
, 1, 0x0);
1792 edma_write_array(j
, EDMA_QRAE
, i
, 0x0);
1800 static struct platform_driver edma_driver
= {
1803 .of_match_table
= edma_of_ids
,
1805 .probe
= edma_probe
,
1808 static int __init
edma_init(void)
1810 return platform_driver_probe(&edma_driver
, edma_probe
);
1812 arch_initcall(edma_init
);