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fbdev: sh_mobile_hdmi: enable "external" mode
[linux-2.6/btrfs-unstable.git] / drivers / video / sh_mobile_hdmi.c
bloba8cf9a510f30f4f2348e766c18fdf06aae9ac446
1 /*
2 * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
3 * for SLISHDMI13T and SLIPHDMIT IP cores
4 *
5 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/clk.h>
13 #include <linux/console.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/slab.h>
23 #include <linux/types.h>
24 #include <linux/workqueue.h>
25
26 #include <video/sh_mobile_hdmi.h>
27 #include <video/sh_mobile_lcdc.h>
28
29 #define HDMI_SYSTEM_CTRL 0x00 /* System control */
30 #define HDMI_L_R_DATA_SWAP_CTRL_RPKT 0x01 /* L/R data swap control,
31 bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
32 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8 0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
33 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0 0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
34 #define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS 0x04 /* SPDIF audio sampling frequency,
35 bits 19..16 of Internal CTS */
36 #define HDMI_INTERNAL_CTS_15_8 0x05 /* bits 15..8 of Internal CTS */
37 #define HDMI_INTERNAL_CTS_7_0 0x06 /* bits 7..0 of Internal CTS */
38 #define HDMI_EXTERNAL_CTS_19_16 0x07 /* External CTS */
39 #define HDMI_EXTERNAL_CTS_15_8 0x08 /* External CTS */
40 #define HDMI_EXTERNAL_CTS_7_0 0x09 /* External CTS */
41 #define HDMI_AUDIO_SETTING_1 0x0A /* Audio setting.1 */
42 #define HDMI_AUDIO_SETTING_2 0x0B /* Audio setting.2 */
43 #define HDMI_I2S_AUDIO_SET 0x0C /* I2S audio setting */
44 #define HDMI_DSD_AUDIO_SET 0x0D /* DSD audio setting */
45 #define HDMI_DEBUG_MONITOR_1 0x0E /* Debug monitor.1 */
46 #define HDMI_DEBUG_MONITOR_2 0x0F /* Debug monitor.2 */
47 #define HDMI_I2S_INPUT_PIN_SWAP 0x10 /* I2S input pin swap */
48 #define HDMI_AUDIO_STATUS_BITS_SETTING_1 0x11 /* Audio status bits setting.1 */
49 #define HDMI_AUDIO_STATUS_BITS_SETTING_2 0x12 /* Audio status bits setting.2 */
50 #define HDMI_CATEGORY_CODE 0x13 /* Category code */
51 #define HDMI_SOURCE_NUM_AUDIO_WORD_LEN 0x14 /* Source number/Audio word length */
52 #define HDMI_AUDIO_VIDEO_SETTING_1 0x15 /* Audio/Video setting.1 */
53 #define HDMI_VIDEO_SETTING_1 0x16 /* Video setting.1 */
54 #define HDMI_DEEP_COLOR_MODES 0x17 /* Deep Color Modes */
55
56 /* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
57 #define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS 0x18
58
59 #define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS 0x30 /* External video parameter settings */
60 #define HDMI_EXTERNAL_H_TOTAL_7_0 0x31 /* External horizontal total (LSB) */
61 #define HDMI_EXTERNAL_H_TOTAL_11_8 0x32 /* External horizontal total (MSB) */
62 #define HDMI_EXTERNAL_H_BLANK_7_0 0x33 /* External horizontal blank (LSB) */
63 #define HDMI_EXTERNAL_H_BLANK_9_8 0x34 /* External horizontal blank (MSB) */
64 #define HDMI_EXTERNAL_H_DELAY_7_0 0x35 /* External horizontal delay (LSB) */
65 #define HDMI_EXTERNAL_H_DELAY_9_8 0x36 /* External horizontal delay (MSB) */
66 #define HDMI_EXTERNAL_H_DURATION_7_0 0x37 /* External horizontal duration (LSB) */
67 #define HDMI_EXTERNAL_H_DURATION_9_8 0x38 /* External horizontal duration (MSB) */
68 #define HDMI_EXTERNAL_V_TOTAL_7_0 0x39 /* External vertical total (LSB) */
69 #define HDMI_EXTERNAL_V_TOTAL_9_8 0x3A /* External vertical total (MSB) */
70 #define HDMI_AUDIO_VIDEO_SETTING_2 0x3B /* Audio/Video setting.2 */
71 #define HDMI_EXTERNAL_V_BLANK 0x3D /* External vertical blank */
72 #define HDMI_EXTERNAL_V_DELAY 0x3E /* External vertical delay */
73 #define HDMI_EXTERNAL_V_DURATION 0x3F /* External vertical duration */
74 #define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL 0x40 /* Control packet manual send control */
75 #define HDMI_CTRL_PKT_AUTO_SEND 0x41 /* Control packet auto send with VSYNC control */
76 #define HDMI_AUTO_CHECKSUM_OPTION 0x42 /* Auto checksum option */
77 #define HDMI_VIDEO_SETTING_2 0x45 /* Video setting.2 */
78 #define HDMI_OUTPUT_OPTION 0x46 /* Output option */
79 #define HDMI_SLIPHDMIT_PARAM_OPTION 0x51 /* SLIPHDMIT parameter option */
80 #define HDMI_HSYNC_PMENT_AT_EMB_7_0 0x52 /* HSYNC placement at embedded sync (LSB) */
81 #define HDMI_HSYNC_PMENT_AT_EMB_15_8 0x53 /* HSYNC placement at embedded sync (MSB) */
82 #define HDMI_VSYNC_PMENT_AT_EMB_7_0 0x54 /* VSYNC placement at embedded sync (LSB) */
83 #define HDMI_VSYNC_PMENT_AT_EMB_14_8 0x55 /* VSYNC placement at embedded sync (MSB) */
84 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_1 0x56 /* SLIPHDMIT parameter settings.1 */
85 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_2 0x57 /* SLIPHDMIT parameter settings.2 */
86 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_3 0x58 /* SLIPHDMIT parameter settings.3 */
87 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_5 0x59 /* SLIPHDMIT parameter settings.5 */
88 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_6 0x5A /* SLIPHDMIT parameter settings.6 */
89 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_7 0x5B /* SLIPHDMIT parameter settings.7 */
90 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_8 0x5C /* SLIPHDMIT parameter settings.8 */
91 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_9 0x5D /* SLIPHDMIT parameter settings.9 */
92 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_10 0x5E /* SLIPHDMIT parameter settings.10 */
93 #define HDMI_CTRL_PKT_BUF_INDEX 0x5F /* Control packet buffer index */
94 #define HDMI_CTRL_PKT_BUF_ACCESS_HB0 0x60 /* Control packet data buffer access window - HB0 */
95 #define HDMI_CTRL_PKT_BUF_ACCESS_HB1 0x61 /* Control packet data buffer access window - HB1 */
96 #define HDMI_CTRL_PKT_BUF_ACCESS_HB2 0x62 /* Control packet data buffer access window - HB2 */
97 #define HDMI_CTRL_PKT_BUF_ACCESS_PB0 0x63 /* Control packet data buffer access window - PB0 */
98 #define HDMI_CTRL_PKT_BUF_ACCESS_PB1 0x64 /* Control packet data buffer access window - PB1 */
99 #define HDMI_CTRL_PKT_BUF_ACCESS_PB2 0x65 /* Control packet data buffer access window - PB2 */
100 #define HDMI_CTRL_PKT_BUF_ACCESS_PB3 0x66 /* Control packet data buffer access window - PB3 */
101 #define HDMI_CTRL_PKT_BUF_ACCESS_PB4 0x67 /* Control packet data buffer access window - PB4 */
102 #define HDMI_CTRL_PKT_BUF_ACCESS_PB5 0x68 /* Control packet data buffer access window - PB5 */
103 #define HDMI_CTRL_PKT_BUF_ACCESS_PB6 0x69 /* Control packet data buffer access window - PB6 */
104 #define HDMI_CTRL_PKT_BUF_ACCESS_PB7 0x6A /* Control packet data buffer access window - PB7 */
105 #define HDMI_CTRL_PKT_BUF_ACCESS_PB8 0x6B /* Control packet data buffer access window - PB8 */
106 #define HDMI_CTRL_PKT_BUF_ACCESS_PB9 0x6C /* Control packet data buffer access window - PB9 */
107 #define HDMI_CTRL_PKT_BUF_ACCESS_PB10 0x6D /* Control packet data buffer access window - PB10 */
108 #define HDMI_CTRL_PKT_BUF_ACCESS_PB11 0x6E /* Control packet data buffer access window - PB11 */
109 #define HDMI_CTRL_PKT_BUF_ACCESS_PB12 0x6F /* Control packet data buffer access window - PB12 */
110 #define HDMI_CTRL_PKT_BUF_ACCESS_PB13 0x70 /* Control packet data buffer access window - PB13 */
111 #define HDMI_CTRL_PKT_BUF_ACCESS_PB14 0x71 /* Control packet data buffer access window - PB14 */
112 #define HDMI_CTRL_PKT_BUF_ACCESS_PB15 0x72 /* Control packet data buffer access window - PB15 */
113 #define HDMI_CTRL_PKT_BUF_ACCESS_PB16 0x73 /* Control packet data buffer access window - PB16 */
114 #define HDMI_CTRL_PKT_BUF_ACCESS_PB17 0x74 /* Control packet data buffer access window - PB17 */
115 #define HDMI_CTRL_PKT_BUF_ACCESS_PB18 0x75 /* Control packet data buffer access window - PB18 */
116 #define HDMI_CTRL_PKT_BUF_ACCESS_PB19 0x76 /* Control packet data buffer access window - PB19 */
117 #define HDMI_CTRL_PKT_BUF_ACCESS_PB20 0x77 /* Control packet data buffer access window - PB20 */
118 #define HDMI_CTRL_PKT_BUF_ACCESS_PB21 0x78 /* Control packet data buffer access window - PB21 */
119 #define HDMI_CTRL_PKT_BUF_ACCESS_PB22 0x79 /* Control packet data buffer access window - PB22 */
120 #define HDMI_CTRL_PKT_BUF_ACCESS_PB23 0x7A /* Control packet data buffer access window - PB23 */
121 #define HDMI_CTRL_PKT_BUF_ACCESS_PB24 0x7B /* Control packet data buffer access window - PB24 */
122 #define HDMI_CTRL_PKT_BUF_ACCESS_PB25 0x7C /* Control packet data buffer access window - PB25 */
123 #define HDMI_CTRL_PKT_BUF_ACCESS_PB26 0x7D /* Control packet data buffer access window - PB26 */
124 #define HDMI_CTRL_PKT_BUF_ACCESS_PB27 0x7E /* Control packet data buffer access window - PB27 */
125 #define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW 0x80 /* EDID/KSV FIFO access window */
126 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0 0x81 /* DDC bus access frequency control (LSB) */
127 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8 0x82 /* DDC bus access frequency control (MSB) */
128 #define HDMI_INTERRUPT_MASK_1 0x92 /* Interrupt mask.1 */
129 #define HDMI_INTERRUPT_MASK_2 0x93 /* Interrupt mask.2 */
130 #define HDMI_INTERRUPT_STATUS_1 0x94 /* Interrupt status.1 */
131 #define HDMI_INTERRUPT_STATUS_2 0x95 /* Interrupt status.2 */
132 #define HDMI_INTERRUPT_MASK_3 0x96 /* Interrupt mask.3 */
133 #define HDMI_INTERRUPT_MASK_4 0x97 /* Interrupt mask.4 */
134 #define HDMI_INTERRUPT_STATUS_3 0x98 /* Interrupt status.3 */
135 #define HDMI_INTERRUPT_STATUS_4 0x99 /* Interrupt status.4 */
136 #define HDMI_SOFTWARE_HDCP_CONTROL_1 0x9A /* Software HDCP control.1 */
137 #define HDMI_FRAME_COUNTER 0x9C /* Frame counter */
138 #define HDMI_FRAME_COUNTER_FOR_RI_CHECK 0x9D /* Frame counter for Ri check */
139 #define HDMI_HDCP_CONTROL 0xAF /* HDCP control */
140 #define HDMI_RI_FRAME_COUNT_REGISTER 0xB2 /* Ri frame count register */
141 #define HDMI_DDC_BUS_CONTROL 0xB7 /* DDC bus control */
142 #define HDMI_HDCP_STATUS 0xB8 /* HDCP status */
143 #define HDMI_SHA0 0xB9 /* sha0 */
144 #define HDMI_SHA1 0xBA /* sha1 */
145 #define HDMI_SHA2 0xBB /* sha2 */
146 #define HDMI_SHA3 0xBC /* sha3 */
147 #define HDMI_SHA4 0xBD /* sha4 */
148 #define HDMI_BCAPS_READ 0xBE /* BCAPS read / debug */
149 #define HDMI_AKSV_BKSV_7_0_MONITOR 0xBF /* AKSV/BKSV[7:0] monitor */
150 #define HDMI_AKSV_BKSV_15_8_MONITOR 0xC0 /* AKSV/BKSV[15:8] monitor */
151 #define HDMI_AKSV_BKSV_23_16_MONITOR 0xC1 /* AKSV/BKSV[23:16] monitor */
152 #define HDMI_AKSV_BKSV_31_24_MONITOR 0xC2 /* AKSV/BKSV[31:24] monitor */
153 #define HDMI_AKSV_BKSV_39_32_MONITOR 0xC3 /* AKSV/BKSV[39:32] monitor */
154 #define HDMI_EDID_SEGMENT_POINTER 0xC4 /* EDID segment pointer */
155 #define HDMI_EDID_WORD_ADDRESS 0xC5 /* EDID word address */
156 #define HDMI_EDID_DATA_FIFO_ADDRESS 0xC6 /* EDID data FIFO address */
157 #define HDMI_NUM_OF_HDMI_DEVICES 0xC7 /* Number of HDMI devices */
158 #define HDMI_HDCP_ERROR_CODE 0xC8 /* HDCP error code */
159 #define HDMI_100MS_TIMER_SET 0xC9 /* 100ms timer setting */
160 #define HDMI_5SEC_TIMER_SET 0xCA /* 5sec timer setting */
161 #define HDMI_RI_READ_COUNT 0xCB /* Ri read count */
162 #define HDMI_AN_SEED 0xCC /* An seed */
163 #define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED 0xCD /* Maximum number of receivers allowed */
164 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1 0xCE /* HDCP memory access control.1 */
165 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2 0xCF /* HDCP memory access control.2 */
166 #define HDMI_HDCP_CONTROL_2 0xD0 /* HDCP Control 2 */
167 #define HDMI_HDCP_KEY_MEMORY_CONTROL 0xD2 /* HDCP Key Memory Control */
168 #define HDMI_COLOR_SPACE_CONV_CONFIG_1 0xD3 /* Color space conversion configuration.1 */
169 #define HDMI_VIDEO_SETTING_3 0xD4 /* Video setting.3 */
170 #define HDMI_RI_7_0 0xD5 /* Ri[7:0] */
171 #define HDMI_RI_15_8 0xD6 /* Ri[15:8] */
172 #define HDMI_PJ 0xD7 /* Pj */
173 #define HDMI_SHA_RD 0xD8 /* sha_rd */
174 #define HDMI_RI_7_0_SAVED 0xD9 /* Ri[7:0] saved */
175 #define HDMI_RI_15_8_SAVED 0xDA /* Ri[15:8] saved */
176 #define HDMI_PJ_SAVED 0xDB /* Pj saved */
177 #define HDMI_NUM_OF_DEVICES 0xDC /* Number of devices */
178 #define HDMI_HOT_PLUG_MSENS_STATUS 0xDF /* Hot plug/MSENS status */
179 #define HDMI_BCAPS_WRITE 0xE0 /* bcaps */
180 #define HDMI_BSTAT_7_0 0xE1 /* bstat[7:0] */
181 #define HDMI_BSTAT_15_8 0xE2 /* bstat[15:8] */
182 #define HDMI_BKSV_7_0 0xE3 /* bksv[7:0] */
183 #define HDMI_BKSV_15_8 0xE4 /* bksv[15:8] */
184 #define HDMI_BKSV_23_16 0xE5 /* bksv[23:16] */
185 #define HDMI_BKSV_31_24 0xE6 /* bksv[31:24] */
186 #define HDMI_BKSV_39_32 0xE7 /* bksv[39:32] */
187 #define HDMI_AN_7_0 0xE8 /* An[7:0] */
188 #define HDMI_AN_15_8 0xE9 /* An [15:8] */
189 #define HDMI_AN_23_16 0xEA /* An [23:16] */
190 #define HDMI_AN_31_24 0xEB /* An [31:24] */
191 #define HDMI_AN_39_32 0xEC /* An [39:32] */
192 #define HDMI_AN_47_40 0xED /* An [47:40] */
193 #define HDMI_AN_55_48 0xEE /* An [55:48] */
194 #define HDMI_AN_63_56 0xEF /* An [63:56] */
195 #define HDMI_PRODUCT_ID 0xF0 /* Product ID */
196 #define HDMI_REVISION_ID 0xF1 /* Revision ID */
197 #define HDMI_TEST_MODE 0xFE /* Test mode */
198
199 enum hotplug_state {
200 HDMI_HOTPLUG_DISCONNECTED,
201 HDMI_HOTPLUG_CONNECTED,
202 HDMI_HOTPLUG_EDID_DONE,
203 };
204
205 struct sh_hdmi {
206 void __iomem *base;
207 enum hotplug_state hp_state;
208 bool preprogrammed_mode; /* use a pre-programmed VIC or the external mode */
209 struct clk *hdmi_clk;
210 struct device *dev;
211 struct fb_info *info;
212 struct delayed_work edid_work;
213 struct fb_var_screeninfo var;
214 };
215
216 static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
217 {
218 iowrite8(data, hdmi->base + reg);
219 }
220
221 static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
222 {
223 return ioread8(hdmi->base + reg);
224 }
225
226 /* External video parameter settings */
227 static void hdmi_external_video_param(struct sh_hdmi *hdmi)
228 {
229 struct fb_var_screeninfo *var = &hdmi->var;
230 u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
231 u8 sync = 0;
232
233 htotal = var->xres + var->right_margin + var->left_margin + var->hsync_len;
234
235 hdelay = var->hsync_len + var->left_margin;
236 hblank = var->right_margin + hdelay;
237
238 /*
239 * Vertical timing looks a bit different in Figure 18,
240 * but let's try the same first by setting offset = 0
241 */
242 vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
243
244 vdelay = var->vsync_len + var->upper_margin;
245 vblank = var->lower_margin + vdelay;
246 voffset = min(var->upper_margin / 2, 6U);
247
248 /*
249 * [3]: VSYNC polarity: Positive
250 * [2]: HSYNC polarity: Positive
251 * [1]: Interlace/Progressive: Progressive
252 * [0]: External video settings enable: used.
253 */
254 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
255 sync |= 4;
256 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
257 sync |= 8;
258
259 pr_debug("H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
260 htotal, hblank, hdelay, var->hsync_len,
261 vtotal, vblank, vdelay, var->vsync_len, sync);
262
263 hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
264
265 hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
266 hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
267
268 hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
269 hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
270
271 hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
272 hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
273
274 hdmi_write(hdmi, var->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
275 hdmi_write(hdmi, var->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
276
277 hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
278 hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
279
280 hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
281
282 hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
283
284 hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
285
286 /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */
287 if (!hdmi->preprogrammed_mode)
288 hdmi_write(hdmi, sync | 1 | (voffset << 4),
289 HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
290 }
291
292 /**
293 * sh_hdmi_video_config()
294 */
295 static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
296 {
297 /*
298 * [7:4]: Audio sampling frequency: 48kHz
299 * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
300 * [0]: Internal/External DE select: internal
301 */
302 hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
303
304 /*
305 * [7:6]: Video output format: RGB 4:4:4
306 * [5:4]: Input video data width: 8 bit
307 * [3:1]: EAV/SAV location: channel 1
308 * [0]: Video input color space: RGB
309 */
310 hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
311
312 /*
313 * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
314 * left at 0 by default, this configures 24bpp and sets the Color Depth
315 * (CD) field in the General Control Packet
316 */
317 hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
318 }
319
320 /**
321 * sh_hdmi_audio_config()
322 */
323 static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
324 {
325 /*
326 * [7:4] L/R data swap control
327 * [3:0] appropriate N[19:16]
328 */
329 hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
330 /* appropriate N[15:8] */
331 hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
332 /* appropriate N[7:0] */
333 hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
334
335 /* [7:4] 48 kHz SPDIF not used */
336 hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
337
338 /*
339 * [6:5] set required down sampling rate if required
340 * [4:3] set required audio source
341 */
342 hdmi_write(hdmi, 0x00, HDMI_AUDIO_SETTING_1);
343
344 /* [3:0] set sending channel number for channel status */
345 hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
346
347 /*
348 * [5:2] set valid I2S source input pin
349 * [1:0] set input I2S source mode
350 */
351 hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
352
353 /* [7:4] set valid DSD source input pin */
354 hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
355
356 /* [7:0] set appropriate I2S input pin swap settings if required */
357 hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
358
359 /*
360 * [7] set validity bit for channel status
361 * [3:0] set original sample frequency for channel status
362 */
363 hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
364
365 /*
366 * [7] set value for channel status
367 * [6] set value for channel status
368 * [5] set copyright bit for channel status
369 * [4:2] set additional information for channel status
370 * [1:0] set clock accuracy for channel status
371 */
372 hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
373
374 /* [7:0] set category code for channel status */
375 hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
376
377 /*
378 * [7:4] set source number for channel status
379 * [3:0] set word length for channel status
380 */
381 hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
382
383 /* [7:4] set sample frequency for channel status */
384 hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
385 }
386
387 /**
388 * sh_hdmi_phy_config() - configure the HDMI PHY for the used video mode
389 */
390 static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
391 {
392 if (hdmi->var.yres > 480) {
393 /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
394 /*
395 * [1:0] Speed_A
396 * [3:2] Speed_B
397 * [4] PLLA_Bypass
398 * [6] DRV_TEST_EN
399 * [7] DRV_TEST_IN
400 */
401 hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
402 /* PLLB_CONFIG[17], PLLA_CONFIG[17] - not in PHY datasheet */
403 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
404 /*
405 * [2:0] BGR_I_OFFSET
406 * [6:4] BGR_V_OFFSET
407 */
408 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
409 /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
410 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
411 /*
412 * PLLA_CONFIG[15:8]: regulator voltage[0], CP current,
413 * LPF capacitance, LPF resistance[1]
414 */
415 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
416 /* PLLB_CONFIG[7:0]: LPF resistance[0], VCO offset, VCO gain */
417 hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
418 /*
419 * PLLB_CONFIG[15:8]: regulator voltage[0], CP current,
420 * LPF capacitance, LPF resistance[1]
421 */
422 hdmi_write(hdmi, 0x0E, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
423 /* DRV_CONFIG, PE_CONFIG */
424 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
425 /*
426 * [2:0] AMON_SEL (4 == LPF voltage)
427 * [4] PLLA_CONFIG[16]
428 * [5] PLLB_CONFIG[16]
429 */
430 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
431 } else {
432 /* for 480p8bit 27MHz */
433 hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
434 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
435 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
436 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
437 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
438 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
439 hdmi_write(hdmi, 0x0F, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
440 hdmi_write(hdmi, 0x20, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
441 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
442 }
443 }
444
445 /**
446 * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
447 */
448 static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
449 {
450 u8 vic;
451
452 /* AVI InfoFrame */
453 hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
454
455 /* Packet Type = 0x82 */
456 hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
457
458 /* Version = 0x02 */
459 hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
460
461 /* Length = 13 (0x0D) */
462 hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
463
464 /* N. A. Checksum */
465 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
466
467 /*
468 * Y = RGB
469 * A0 = No Data
470 * B = Bar Data not valid
471 * S = No Data
472 */
473 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
474
475 /*
476 * C = No Data
477 * M = 16:9 Picture Aspect Ratio
478 * R = Same as picture aspect ratio
479 */
480 hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
481
482 /*
483 * ITC = No Data
484 * EC = xvYCC601
485 * Q = Default (depends on video format)
486 * SC = No Known non_uniform Scaling
487 */
488 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
489
490 /*
491 * VIC = 1280 x 720p: ignored if external config is used
492 * Send 2 for 720 x 480p, 16 for 1080p, ignored in external mode
493 */
494 if (hdmi->var.yres == 1080 && hdmi->var.xres == 1920)
495 vic = 16;
496 else if (hdmi->var.yres == 480 && hdmi->var.xres == 720)
497 vic = 2;
498 else
499 vic = 4;
500 hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
501
502 /* PR = No Repetition */
503 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
504
505 /* Line Number of End of Top Bar (lower 8 bits) */
506 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
507
508 /* Line Number of End of Top Bar (upper 8 bits) */
509 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
510
511 /* Line Number of Start of Bottom Bar (lower 8 bits) */
512 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
513
514 /* Line Number of Start of Bottom Bar (upper 8 bits) */
515 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
516
517 /* Pixel Number of End of Left Bar (lower 8 bits) */
518 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
519
520 /* Pixel Number of End of Left Bar (upper 8 bits) */
521 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
522
523 /* Pixel Number of Start of Right Bar (lower 8 bits) */
524 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
525
526 /* Pixel Number of Start of Right Bar (upper 8 bits) */
527 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
528 }
529
530 /**
531 * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
532 */
533 static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
534 {
535 /* Audio InfoFrame */
536 hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
537
538 /* Packet Type = 0x84 */
539 hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
540
541 /* Version Number = 0x01 */
542 hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
543
544 /* 0 Length = 10 (0x0A) */
545 hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
546
547 /* n. a. Checksum */
548 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
549
550 /* Audio Channel Count = Refer to Stream Header */
551 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
552
553 /* Refer to Stream Header */
554 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
555
556 /* Format depends on coding type (i.e. CT0...CT3) */
557 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
558
559 /* Speaker Channel Allocation = Front Right + Front Left */
560 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
561
562 /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
563 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
564
565 /* Reserved (0) */
566 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
567 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
568 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
569 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
570 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
571 }
572
573 /**
574 * sh_hdmi_configure() - Initialise HDMI for output
575 */
576 static void sh_hdmi_configure(struct sh_hdmi *hdmi)
577 {
578 /* Configure video format */
579 sh_hdmi_video_config(hdmi);
580
581 /* Configure audio format */
582 sh_hdmi_audio_config(hdmi);
583
584 /* Configure PHY */
585 sh_hdmi_phy_config(hdmi);
586
587 /* Auxiliary Video Information (AVI) InfoFrame */
588 sh_hdmi_avi_infoframe_setup(hdmi);
589
590 /* Audio InfoFrame */
591 sh_hdmi_audio_infoframe_setup(hdmi);
592
593 /*
594 * Control packet auto send with VSYNC control: auto send
595 * General control, Gamut metadata, ISRC, and ACP packets
596 */
597 hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
598
599 /* FIXME */
600 msleep(10);
601
602 /* PS mode b->d, reset PLLA and PLLB */
603 hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL);
604
605 udelay(10);
606
607 hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
608 }
609
610 static void sh_hdmi_read_edid(struct sh_hdmi *hdmi)
611 {
612 struct fb_var_screeninfo tmpvar;
613 /* TODO: When we are ready to use EDID, use this to fill &hdmi->var */
614 struct fb_var_screeninfo *var = &tmpvar;
615 int i;
616 u8 edid[128];
617
618 /* Read EDID */
619 pr_debug("Read back EDID code:");
620 for (i = 0; i < 128; i++) {
621 edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
622 #ifdef DEBUG
623 if ((i % 16) == 0) {
624 printk(KERN_CONT "\n");
625 printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
626 } else {
627 printk(KERN_CONT " %02X", edid[i]);
628 }
629 #endif
630 }
631 #ifdef DEBUG
632 printk(KERN_CONT "\n");
633 #endif
634 fb_parse_edid(edid, var);
635 pr_debug("%u-%u-%u-%u x %u-%u-%u-%u @ %lu kHz monitor detected\n",
636 var->left_margin, var->xres, var->right_margin, var->hsync_len,
637 var->upper_margin, var->yres, var->lower_margin, var->vsync_len,
638 PICOS2KHZ(var->pixclock));
639
640 if ((hdmi->var.xres == 720 && hdmi->var.yres == 480) ||
641 (hdmi->var.xres == 1280 && hdmi->var.yres == 720) ||
642 (hdmi->var.xres == 1920 && hdmi->var.yres == 1080))
643 hdmi->preprogrammed_mode = true;
644 else
645 hdmi->preprogrammed_mode = false;
646
647 hdmi_external_video_param(hdmi);
648 }
649
650 static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
651 {
652 struct sh_hdmi *hdmi = dev_id;
653 u8 status1, status2, mask1, mask2;
654
655 /* mode_b and PLLA and PLLB reset */
656 hdmi_write(hdmi, 0x2C, HDMI_SYSTEM_CTRL);
657
658 /* How long shall reset be held? */
659 udelay(10);
660
661 /* mode_b and PLLA and PLLB reset release */
662 hdmi_write(hdmi, 0x20, HDMI_SYSTEM_CTRL);
663
664 status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
665 status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
666
667 mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
668 mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
669
670 /* Correct would be to ack only set bits, but the datasheet requires 0xff */
671 hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
672 hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
673
674 if (printk_ratelimit())
675 pr_debug("IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
676 irq, status1, mask1, status2, mask2);
677
678 if (!((status1 & mask1) | (status2 & mask2))) {
679 return IRQ_NONE;
680 } else if (status1 & 0xc0) {
681 u8 msens;
682
683 /* Datasheet specifies 10ms... */
684 udelay(500);
685
686 msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
687 pr_debug("MSENS 0x%x\n", msens);
688 /* Check, if hot plug & MSENS pin status are both high */
689 if ((msens & 0xC0) == 0xC0) {
690 /* Display plug in */
691 hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
692
693 /* Set EDID word address */
694 hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
695 /* Set EDID segment pointer */
696 hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
697 /* Enable EDID interrupt */
698 hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
699 } else if (!(status1 & 0x80)) {
700 /* Display unplug, beware multiple interrupts */
701 if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED)
702 schedule_delayed_work(&hdmi->edid_work, 0);
703
704 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
705 /* display_off will switch back to mode_a */
706 }
707 } else if (status1 & 2) {
708 /* EDID error interrupt: retry */
709 /* Set EDID word address */
710 hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
711 /* Set EDID segment pointer */
712 hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
713 } else if (status1 & 4) {
714 /* Disable EDID interrupt */
715 hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
716 hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
717 schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
718 }
719
720 return IRQ_HANDLED;
721 }
722
723 static void hdmi_display_on(void *arg, struct fb_info *info)
724 {
725 struct sh_hdmi *hdmi = arg;
726 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
727
728 pr_debug("%s(%p): state %x\n", __func__, pdata->lcd_dev, info->state);
729 /*
730 * FIXME: not a good place to store fb_info. And we cannot nullify it
731 * even on monitor disconnect. What should the lifecycle be?
732 */
733 hdmi->info = info;
734 switch (hdmi->hp_state) {
735 case HDMI_HOTPLUG_EDID_DONE:
736 /* PS mode d->e. All functions are active */
737 hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL);
738 pr_debug("HDMI running\n");
739 break;
740 case HDMI_HOTPLUG_DISCONNECTED:
741 info->state = FBINFO_STATE_SUSPENDED;
742 default:
743 hdmi->var = info->var;
744 }
745 }
746
747 static void hdmi_display_off(void *arg)
748 {
749 struct sh_hdmi *hdmi = arg;
750 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
751
752 pr_debug("%s(%p)\n", __func__, pdata->lcd_dev);
753 /* PS mode e->a */
754 hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
755 }
756
757 /* Hotplug interrupt occurred, read EDID */
758 static void edid_work_fn(struct work_struct *work)
759 {
760 struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
761 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
762
763 pr_debug("%s(%p): begin, hotplug status %d\n", __func__,
764 pdata->lcd_dev, hdmi->hp_state);
765
766 if (!pdata->lcd_dev)
767 return;
768
769 if (hdmi->hp_state == HDMI_HOTPLUG_EDID_DONE) {
770 pm_runtime_get_sync(hdmi->dev);
771 /* A device has been plugged in */
772 sh_hdmi_read_edid(hdmi);
773 msleep(10);
774 sh_hdmi_configure(hdmi);
775 /* Switched to another (d) power-save mode */
776 msleep(10);
777
778 if (!hdmi->info)
779 return;
780
781 acquire_console_sem();
782
783 /* HDMI plug in */
784 hdmi->info->var = hdmi->var;
785 if (hdmi->info->state != FBINFO_STATE_RUNNING)
786 fb_set_suspend(hdmi->info, 0);
787 else
788 hdmi_display_on(hdmi, hdmi->info);
789
790 release_console_sem();
791 } else {
792 if (!hdmi->info)
793 return;
794
795 acquire_console_sem();
796
797 /* HDMI disconnect */
798 fb_set_suspend(hdmi->info, 1);
799
800 release_console_sem();
801 pm_runtime_put(hdmi->dev);
802 }
803
804 pr_debug("%s(%p): end\n", __func__, pdata->lcd_dev);
805 }
806
807 static int __init sh_hdmi_probe(struct platform_device *pdev)
808 {
809 struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
810 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
811 int irq = platform_get_irq(pdev, 0), ret;
812 struct sh_hdmi *hdmi;
813 long rate;
814
815 if (!res || !pdata || irq < 0)
816 return -ENODEV;
817
818 hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
819 if (!hdmi) {
820 dev_err(&pdev->dev, "Cannot allocate device data\n");
821 return -ENOMEM;
822 }
823
824 hdmi->dev = &pdev->dev;
825
826 hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
827 if (IS_ERR(hdmi->hdmi_clk)) {
828 ret = PTR_ERR(hdmi->hdmi_clk);
829 dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
830 goto egetclk;
831 }
832
833 /* TODO: reconfigure the clock on monitor plug in */
834 rate = PICOS2KHZ(pdata->lcd_chan->lcd_cfg[0].pixclock) * 1000;
835
836 rate = clk_round_rate(hdmi->hdmi_clk, rate);
837 if (rate < 0) {
838 ret = rate;
839 dev_err(&pdev->dev, "Cannot get suitable rate: %ld\n", rate);
840 goto erate;
841 }
842
843 ret = clk_set_rate(hdmi->hdmi_clk, rate);
844 if (ret < 0) {
845 dev_err(&pdev->dev, "Cannot set rate %ld: %d\n", rate, ret);
846 goto erate;
847 }
848
849 pr_debug("HDMI set frequency %lu\n", rate);
850
851 ret = clk_enable(hdmi->hdmi_clk);
852 if (ret < 0) {
853 dev_err(&pdev->dev, "Cannot enable clock: %d\n", ret);
854 goto eclkenable;
855 }
856
857 dev_info(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
858
859 if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
860 dev_err(&pdev->dev, "HDMI register region already claimed\n");
861 ret = -EBUSY;
862 goto ereqreg;
863 }
864
865 hdmi->base = ioremap(res->start, resource_size(res));
866 if (!hdmi->base) {
867 dev_err(&pdev->dev, "HDMI register region already claimed\n");
868 ret = -ENOMEM;
869 goto emap;
870 }
871
872 platform_set_drvdata(pdev, hdmi);
873
874 #if 1
875 /* Product and revision IDs are 0 in sh-mobile version */
876 dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
877 hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
878 #endif
879
880 /* Set up LCDC callbacks */
881 pdata->lcd_chan->board_cfg.board_data = hdmi;
882 pdata->lcd_chan->board_cfg.display_on = hdmi_display_on;
883 pdata->lcd_chan->board_cfg.display_off = hdmi_display_off;
884
885 INIT_DELAYED_WORK(&hdmi->edid_work, edid_work_fn);
886
887 pm_runtime_enable(&pdev->dev);
888 pm_runtime_resume(&pdev->dev);
889
890 ret = request_irq(irq, sh_hdmi_hotplug, 0,
891 dev_name(&pdev->dev), hdmi);
892 if (ret < 0) {
893 dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
894 goto ereqirq;
895 }
896
897 return 0;
898
899 ereqirq:
900 pm_runtime_disable(&pdev->dev);
901 iounmap(hdmi->base);
902 emap:
903 release_mem_region(res->start, resource_size(res));
904 ereqreg:
905 clk_disable(hdmi->hdmi_clk);
906 eclkenable:
907 erate:
908 clk_put(hdmi->hdmi_clk);
909 egetclk:
910 kfree(hdmi);
911
912 return ret;
913 }
914
915 static int __exit sh_hdmi_remove(struct platform_device *pdev)
916 {
917 struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
918 struct sh_hdmi *hdmi = platform_get_drvdata(pdev);
919 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
920 int irq = platform_get_irq(pdev, 0);
921
922 pdata->lcd_chan->board_cfg.display_on = NULL;
923 pdata->lcd_chan->board_cfg.display_off = NULL;
924 pdata->lcd_chan->board_cfg.board_data = NULL;
925
926 free_irq(irq, hdmi);
927 pm_runtime_disable(&pdev->dev);
928 cancel_delayed_work_sync(&hdmi->edid_work);
929 clk_disable(hdmi->hdmi_clk);
930 clk_put(hdmi->hdmi_clk);
931 iounmap(hdmi->base);
932 release_mem_region(res->start, resource_size(res));
933 kfree(hdmi);
934
935 return 0;
936 }
937
938 static struct platform_driver sh_hdmi_driver = {
939 .remove = __exit_p(sh_hdmi_remove),
940 .driver = {
941 .name = "sh-mobile-hdmi",
942 },
943 };
944
945 static int __init sh_hdmi_init(void)
946 {
947 return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe);
948 }
949 module_init(sh_hdmi_init);
950
951 static void __exit sh_hdmi_exit(void)
952 {
953 platform_driver_unregister(&sh_hdmi_driver);
954 }
955 module_exit(sh_hdmi_exit);
956
957 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
958 MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
959 MODULE_LICENSE("GPL v2");
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