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bnxt_en: Update firmware interface to 1.9.0.
[linux-2.6/btrfs-unstable.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
blob3015d863bc8c0d195a60a63b5fb518d65ba57a2c
1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2018 Broadcom Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
11 #include <linux/module.h>
12
13 #include <linux/stringify.h>
14 #include <linux/kernel.h>
15 #include <linux/timer.h>
16 #include <linux/errno.h>
17 #include <linux/ioport.h>
18 #include <linux/slab.h>
19 #include <linux/vmalloc.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/bitops.h>
27 #include <linux/io.h>
28 #include <linux/irq.h>
29 #include <linux/delay.h>
30 #include <asm/byteorder.h>
31 #include <asm/page.h>
32 #include <linux/time.h>
33 #include <linux/mii.h>
34 #include <linux/if.h>
35 #include <linux/if_vlan.h>
36 #include <linux/if_bridge.h>
37 #include <linux/rtc.h>
38 #include <linux/bpf.h>
39 #include <net/ip.h>
40 #include <net/tcp.h>
41 #include <net/udp.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <net/udp_tunnel.h>
45 #include <linux/workqueue.h>
46 #include <linux/prefetch.h>
47 #include <linux/cache.h>
48 #include <linux/log2.h>
49 #include <linux/aer.h>
50 #include <linux/bitmap.h>
51 #include <linux/cpu_rmap.h>
52 #include <linux/cpumask.h>
53 #include <net/pkt_cls.h>
54
55 #include "bnxt_hsi.h"
56 #include "bnxt.h"
57 #include "bnxt_ulp.h"
58 #include "bnxt_sriov.h"
59 #include "bnxt_ethtool.h"
60 #include "bnxt_dcb.h"
61 #include "bnxt_xdp.h"
62 #include "bnxt_vfr.h"
63 #include "bnxt_tc.h"
64 #include "bnxt_devlink.h"
65
66 #define BNXT_TX_TIMEOUT (5 * HZ)
67
68 static const char version[] =
69 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
70
71 MODULE_LICENSE("GPL");
72 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
73 MODULE_VERSION(DRV_MODULE_VERSION);
74
75 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
76 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
77 #define BNXT_RX_COPY_THRESH 256
78
79 #define BNXT_TX_PUSH_THRESH 164
80
81 enum board_idx {
82 BCM57301,
83 BCM57302,
84 BCM57304,
85 BCM57417_NPAR,
86 BCM58700,
87 BCM57311,
88 BCM57312,
89 BCM57402,
90 BCM57404,
91 BCM57406,
92 BCM57402_NPAR,
93 BCM57407,
94 BCM57412,
95 BCM57414,
96 BCM57416,
97 BCM57417,
98 BCM57412_NPAR,
99 BCM57314,
100 BCM57417_SFP,
101 BCM57416_SFP,
102 BCM57404_NPAR,
103 BCM57406_NPAR,
104 BCM57407_SFP,
105 BCM57407_NPAR,
106 BCM57414_NPAR,
107 BCM57416_NPAR,
108 BCM57452,
109 BCM57454,
110 BCM58802,
111 BCM58804,
112 BCM58808,
113 NETXTREME_E_VF,
114 NETXTREME_C_VF,
115 NETXTREME_S_VF,
116 };
117
118 /* indexed by enum above */
119 static const struct {
120 char *name;
121 } board_info[] = {
122 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
123 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
124 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
125 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
126 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
127 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
128 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
129 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
130 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
131 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
132 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
133 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
134 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
135 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
136 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
137 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
138 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
139 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
140 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
141 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
142 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
143 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
144 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
145 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
146 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
147 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
148 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
149 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
150 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
151 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
152 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
153 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
154 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
155 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
156 };
157
158 static const struct pci_device_id bnxt_pci_tbl[] = {
159 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
160 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
161 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
162 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
163 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
164 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
165 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
166 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
167 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
168 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
169 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
170 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
171 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
172 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
173 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
174 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
175 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
176 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
177 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
178 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
179 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
180 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
181 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
182 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
183 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
184 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
185 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
186 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
187 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
188 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
189 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
190 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
191 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
192 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
193 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
194 #ifdef CONFIG_BNXT_SRIOV
195 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
196 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
197 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
198 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
199 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
200 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
201 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
202 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
203 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
204 #endif
205 { 0 }
206 };
207
208 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
209
210 static const u16 bnxt_vf_req_snif[] = {
211 HWRM_FUNC_CFG,
212 HWRM_PORT_PHY_QCFG,
213 HWRM_CFA_L2_FILTER_ALLOC,
214 };
215
216 static const u16 bnxt_async_events_arr[] = {
217 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
218 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
219 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
220 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
221 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
222 };
223
224 static struct workqueue_struct *bnxt_pf_wq;
225
226 static bool bnxt_vf_pciid(enum board_idx idx)
227 {
228 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
229 idx == NETXTREME_S_VF);
230 }
231
232 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
233 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
234 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
235
236 #define BNXT_CP_DB_REARM(db, raw_cons) \
237 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
238
239 #define BNXT_CP_DB(db, raw_cons) \
240 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
241
242 #define BNXT_CP_DB_IRQ_DIS(db) \
243 writel(DB_CP_IRQ_DIS_FLAGS, db)
244
245 const u16 bnxt_lhint_arr[] = {
246 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
247 TX_BD_FLAGS_LHINT_512_TO_1023,
248 TX_BD_FLAGS_LHINT_1024_TO_2047,
249 TX_BD_FLAGS_LHINT_1024_TO_2047,
250 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
251 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
252 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
253 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
254 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
255 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
256 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
257 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
258 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
259 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
260 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
261 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
262 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
263 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
264 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
265 };
266
267 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
268 {
269 struct metadata_dst *md_dst = skb_metadata_dst(skb);
270
271 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
272 return 0;
273
274 return md_dst->u.port_info.port_id;
275 }
276
277 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
278 {
279 struct bnxt *bp = netdev_priv(dev);
280 struct tx_bd *txbd;
281 struct tx_bd_ext *txbd1;
282 struct netdev_queue *txq;
283 int i;
284 dma_addr_t mapping;
285 unsigned int length, pad = 0;
286 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
287 u16 prod, last_frag;
288 struct pci_dev *pdev = bp->pdev;
289 struct bnxt_tx_ring_info *txr;
290 struct bnxt_sw_tx_bd *tx_buf;
291
292 i = skb_get_queue_mapping(skb);
293 if (unlikely(i >= bp->tx_nr_rings)) {
294 dev_kfree_skb_any(skb);
295 return NETDEV_TX_OK;
296 }
297
298 txq = netdev_get_tx_queue(dev, i);
299 txr = &bp->tx_ring[bp->tx_ring_map[i]];
300 prod = txr->tx_prod;
301
302 free_size = bnxt_tx_avail(bp, txr);
303 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
304 netif_tx_stop_queue(txq);
305 return NETDEV_TX_BUSY;
306 }
307
308 length = skb->len;
309 len = skb_headlen(skb);
310 last_frag = skb_shinfo(skb)->nr_frags;
311
312 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
313
314 txbd->tx_bd_opaque = prod;
315
316 tx_buf = &txr->tx_buf_ring[prod];
317 tx_buf->skb = skb;
318 tx_buf->nr_frags = last_frag;
319
320 vlan_tag_flags = 0;
321 cfa_action = bnxt_xmit_get_cfa_action(skb);
322 if (skb_vlan_tag_present(skb)) {
323 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
324 skb_vlan_tag_get(skb);
325 /* Currently supports 8021Q, 8021AD vlan offloads
326 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
327 */
328 if (skb->vlan_proto == htons(ETH_P_8021Q))
329 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
330 }
331
332 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
333 struct tx_push_buffer *tx_push_buf = txr->tx_push;
334 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
335 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
336 void *pdata = tx_push_buf->data;
337 u64 *end;
338 int j, push_len;
339
340 /* Set COAL_NOW to be ready quickly for the next push */
341 tx_push->tx_bd_len_flags_type =
342 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
343 TX_BD_TYPE_LONG_TX_BD |
344 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
345 TX_BD_FLAGS_COAL_NOW |
346 TX_BD_FLAGS_PACKET_END |
347 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
348
349 if (skb->ip_summed == CHECKSUM_PARTIAL)
350 tx_push1->tx_bd_hsize_lflags =
351 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
352 else
353 tx_push1->tx_bd_hsize_lflags = 0;
354
355 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
356 tx_push1->tx_bd_cfa_action =
357 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
358
359 end = pdata + length;
360 end = PTR_ALIGN(end, 8) - 1;
361 *end = 0;
362
363 skb_copy_from_linear_data(skb, pdata, len);
364 pdata += len;
365 for (j = 0; j < last_frag; j++) {
366 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
367 void *fptr;
368
369 fptr = skb_frag_address_safe(frag);
370 if (!fptr)
371 goto normal_tx;
372
373 memcpy(pdata, fptr, skb_frag_size(frag));
374 pdata += skb_frag_size(frag);
375 }
376
377 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
378 txbd->tx_bd_haddr = txr->data_mapping;
379 prod = NEXT_TX(prod);
380 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
381 memcpy(txbd, tx_push1, sizeof(*txbd));
382 prod = NEXT_TX(prod);
383 tx_push->doorbell =
384 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
385 txr->tx_prod = prod;
386
387 tx_buf->is_push = 1;
388 netdev_tx_sent_queue(txq, skb->len);
389 wmb(); /* Sync is_push and byte queue before pushing data */
390
391 push_len = (length + sizeof(*tx_push) + 7) / 8;
392 if (push_len > 16) {
393 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
394 __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
395 (push_len - 16) << 1);
396 } else {
397 __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
398 push_len);
399 }
400
401 goto tx_done;
402 }
403
404 normal_tx:
405 if (length < BNXT_MIN_PKT_SIZE) {
406 pad = BNXT_MIN_PKT_SIZE - length;
407 if (skb_pad(skb, pad)) {
408 /* SKB already freed. */
409 tx_buf->skb = NULL;
410 return NETDEV_TX_OK;
411 }
412 length = BNXT_MIN_PKT_SIZE;
413 }
414
415 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
416
417 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
418 dev_kfree_skb_any(skb);
419 tx_buf->skb = NULL;
420 return NETDEV_TX_OK;
421 }
422
423 dma_unmap_addr_set(tx_buf, mapping, mapping);
424 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
425 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
426
427 txbd->tx_bd_haddr = cpu_to_le64(mapping);
428
429 prod = NEXT_TX(prod);
430 txbd1 = (struct tx_bd_ext *)
431 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
432
433 txbd1->tx_bd_hsize_lflags = 0;
434 if (skb_is_gso(skb)) {
435 u32 hdr_len;
436
437 if (skb->encapsulation)
438 hdr_len = skb_inner_network_offset(skb) +
439 skb_inner_network_header_len(skb) +
440 inner_tcp_hdrlen(skb);
441 else
442 hdr_len = skb_transport_offset(skb) +
443 tcp_hdrlen(skb);
444
445 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
446 TX_BD_FLAGS_T_IPID |
447 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
448 length = skb_shinfo(skb)->gso_size;
449 txbd1->tx_bd_mss = cpu_to_le32(length);
450 length += hdr_len;
451 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
452 txbd1->tx_bd_hsize_lflags =
453 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
454 txbd1->tx_bd_mss = 0;
455 }
456
457 length >>= 9;
458 flags |= bnxt_lhint_arr[length];
459 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
460
461 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
462 txbd1->tx_bd_cfa_action =
463 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
464 for (i = 0; i < last_frag; i++) {
465 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
466
467 prod = NEXT_TX(prod);
468 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
469
470 len = skb_frag_size(frag);
471 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
472 DMA_TO_DEVICE);
473
474 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
475 goto tx_dma_error;
476
477 tx_buf = &txr->tx_buf_ring[prod];
478 dma_unmap_addr_set(tx_buf, mapping, mapping);
479
480 txbd->tx_bd_haddr = cpu_to_le64(mapping);
481
482 flags = len << TX_BD_LEN_SHIFT;
483 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
484 }
485
486 flags &= ~TX_BD_LEN;
487 txbd->tx_bd_len_flags_type =
488 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
489 TX_BD_FLAGS_PACKET_END);
490
491 netdev_tx_sent_queue(txq, skb->len);
492
493 /* Sync BD data before updating doorbell */
494 wmb();
495
496 prod = NEXT_TX(prod);
497 txr->tx_prod = prod;
498
499 if (!skb->xmit_more || netif_xmit_stopped(txq))
500 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
501
502 tx_done:
503
504 mmiowb();
505
506 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
507 if (skb->xmit_more && !tx_buf->is_push)
508 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
509
510 netif_tx_stop_queue(txq);
511
512 /* netif_tx_stop_queue() must be done before checking
513 * tx index in bnxt_tx_avail() below, because in
514 * bnxt_tx_int(), we update tx index before checking for
515 * netif_tx_queue_stopped().
516 */
517 smp_mb();
518 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
519 netif_tx_wake_queue(txq);
520 }
521 return NETDEV_TX_OK;
522
523 tx_dma_error:
524 last_frag = i;
525
526 /* start back at beginning and unmap skb */
527 prod = txr->tx_prod;
528 tx_buf = &txr->tx_buf_ring[prod];
529 tx_buf->skb = NULL;
530 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
531 skb_headlen(skb), PCI_DMA_TODEVICE);
532 prod = NEXT_TX(prod);
533
534 /* unmap remaining mapped pages */
535 for (i = 0; i < last_frag; i++) {
536 prod = NEXT_TX(prod);
537 tx_buf = &txr->tx_buf_ring[prod];
538 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
539 skb_frag_size(&skb_shinfo(skb)->frags[i]),
540 PCI_DMA_TODEVICE);
541 }
542
543 dev_kfree_skb_any(skb);
544 return NETDEV_TX_OK;
545 }
546
547 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
548 {
549 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
550 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
551 u16 cons = txr->tx_cons;
552 struct pci_dev *pdev = bp->pdev;
553 int i;
554 unsigned int tx_bytes = 0;
555
556 for (i = 0; i < nr_pkts; i++) {
557 struct bnxt_sw_tx_bd *tx_buf;
558 struct sk_buff *skb;
559 int j, last;
560
561 tx_buf = &txr->tx_buf_ring[cons];
562 cons = NEXT_TX(cons);
563 skb = tx_buf->skb;
564 tx_buf->skb = NULL;
565
566 if (tx_buf->is_push) {
567 tx_buf->is_push = 0;
568 goto next_tx_int;
569 }
570
571 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
572 skb_headlen(skb), PCI_DMA_TODEVICE);
573 last = tx_buf->nr_frags;
574
575 for (j = 0; j < last; j++) {
576 cons = NEXT_TX(cons);
577 tx_buf = &txr->tx_buf_ring[cons];
578 dma_unmap_page(
579 &pdev->dev,
580 dma_unmap_addr(tx_buf, mapping),
581 skb_frag_size(&skb_shinfo(skb)->frags[j]),
582 PCI_DMA_TODEVICE);
583 }
584
585 next_tx_int:
586 cons = NEXT_TX(cons);
587
588 tx_bytes += skb->len;
589 dev_kfree_skb_any(skb);
590 }
591
592 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
593 txr->tx_cons = cons;
594
595 /* Need to make the tx_cons update visible to bnxt_start_xmit()
596 * before checking for netif_tx_queue_stopped(). Without the
597 * memory barrier, there is a small possibility that bnxt_start_xmit()
598 * will miss it and cause the queue to be stopped forever.
599 */
600 smp_mb();
601
602 if (unlikely(netif_tx_queue_stopped(txq)) &&
603 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
604 __netif_tx_lock(txq, smp_processor_id());
605 if (netif_tx_queue_stopped(txq) &&
606 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
607 txr->dev_state != BNXT_DEV_STATE_CLOSING)
608 netif_tx_wake_queue(txq);
609 __netif_tx_unlock(txq);
610 }
611 }
612
613 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
614 gfp_t gfp)
615 {
616 struct device *dev = &bp->pdev->dev;
617 struct page *page;
618
619 page = alloc_page(gfp);
620 if (!page)
621 return NULL;
622
623 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
624 DMA_ATTR_WEAK_ORDERING);
625 if (dma_mapping_error(dev, *mapping)) {
626 __free_page(page);
627 return NULL;
628 }
629 *mapping += bp->rx_dma_offset;
630 return page;
631 }
632
633 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
634 gfp_t gfp)
635 {
636 u8 *data;
637 struct pci_dev *pdev = bp->pdev;
638
639 data = kmalloc(bp->rx_buf_size, gfp);
640 if (!data)
641 return NULL;
642
643 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
644 bp->rx_buf_use_size, bp->rx_dir,
645 DMA_ATTR_WEAK_ORDERING);
646
647 if (dma_mapping_error(&pdev->dev, *mapping)) {
648 kfree(data);
649 data = NULL;
650 }
651 return data;
652 }
653
654 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
655 u16 prod, gfp_t gfp)
656 {
657 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
658 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
659 dma_addr_t mapping;
660
661 if (BNXT_RX_PAGE_MODE(bp)) {
662 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
663
664 if (!page)
665 return -ENOMEM;
666
667 rx_buf->data = page;
668 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
669 } else {
670 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
671
672 if (!data)
673 return -ENOMEM;
674
675 rx_buf->data = data;
676 rx_buf->data_ptr = data + bp->rx_offset;
677 }
678 rx_buf->mapping = mapping;
679
680 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
681 return 0;
682 }
683
684 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
685 {
686 u16 prod = rxr->rx_prod;
687 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
688 struct rx_bd *cons_bd, *prod_bd;
689
690 prod_rx_buf = &rxr->rx_buf_ring[prod];
691 cons_rx_buf = &rxr->rx_buf_ring[cons];
692
693 prod_rx_buf->data = data;
694 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
695
696 prod_rx_buf->mapping = cons_rx_buf->mapping;
697
698 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
699 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
700
701 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
702 }
703
704 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
705 {
706 u16 next, max = rxr->rx_agg_bmap_size;
707
708 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
709 if (next >= max)
710 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
711 return next;
712 }
713
714 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
715 struct bnxt_rx_ring_info *rxr,
716 u16 prod, gfp_t gfp)
717 {
718 struct rx_bd *rxbd =
719 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
720 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
721 struct pci_dev *pdev = bp->pdev;
722 struct page *page;
723 dma_addr_t mapping;
724 u16 sw_prod = rxr->rx_sw_agg_prod;
725 unsigned int offset = 0;
726
727 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
728 page = rxr->rx_page;
729 if (!page) {
730 page = alloc_page(gfp);
731 if (!page)
732 return -ENOMEM;
733 rxr->rx_page = page;
734 rxr->rx_page_offset = 0;
735 }
736 offset = rxr->rx_page_offset;
737 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
738 if (rxr->rx_page_offset == PAGE_SIZE)
739 rxr->rx_page = NULL;
740 else
741 get_page(page);
742 } else {
743 page = alloc_page(gfp);
744 if (!page)
745 return -ENOMEM;
746 }
747
748 mapping = dma_map_page_attrs(&pdev->dev, page, offset,
749 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
750 DMA_ATTR_WEAK_ORDERING);
751 if (dma_mapping_error(&pdev->dev, mapping)) {
752 __free_page(page);
753 return -EIO;
754 }
755
756 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
757 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
758
759 __set_bit(sw_prod, rxr->rx_agg_bmap);
760 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
761 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
762
763 rx_agg_buf->page = page;
764 rx_agg_buf->offset = offset;
765 rx_agg_buf->mapping = mapping;
766 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
767 rxbd->rx_bd_opaque = sw_prod;
768 return 0;
769 }
770
771 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
772 u32 agg_bufs)
773 {
774 struct bnxt *bp = bnapi->bp;
775 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
776 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
777 u16 prod = rxr->rx_agg_prod;
778 u16 sw_prod = rxr->rx_sw_agg_prod;
779 u32 i;
780
781 for (i = 0; i < agg_bufs; i++) {
782 u16 cons;
783 struct rx_agg_cmp *agg;
784 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
785 struct rx_bd *prod_bd;
786 struct page *page;
787
788 agg = (struct rx_agg_cmp *)
789 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
790 cons = agg->rx_agg_cmp_opaque;
791 __clear_bit(cons, rxr->rx_agg_bmap);
792
793 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
794 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
795
796 __set_bit(sw_prod, rxr->rx_agg_bmap);
797 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
798 cons_rx_buf = &rxr->rx_agg_ring[cons];
799
800 /* It is possible for sw_prod to be equal to cons, so
801 * set cons_rx_buf->page to NULL first.
802 */
803 page = cons_rx_buf->page;
804 cons_rx_buf->page = NULL;
805 prod_rx_buf->page = page;
806 prod_rx_buf->offset = cons_rx_buf->offset;
807
808 prod_rx_buf->mapping = cons_rx_buf->mapping;
809
810 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
811
812 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
813 prod_bd->rx_bd_opaque = sw_prod;
814
815 prod = NEXT_RX_AGG(prod);
816 sw_prod = NEXT_RX_AGG(sw_prod);
817 cp_cons = NEXT_CMP(cp_cons);
818 }
819 rxr->rx_agg_prod = prod;
820 rxr->rx_sw_agg_prod = sw_prod;
821 }
822
823 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
824 struct bnxt_rx_ring_info *rxr,
825 u16 cons, void *data, u8 *data_ptr,
826 dma_addr_t dma_addr,
827 unsigned int offset_and_len)
828 {
829 unsigned int payload = offset_and_len >> 16;
830 unsigned int len = offset_and_len & 0xffff;
831 struct skb_frag_struct *frag;
832 struct page *page = data;
833 u16 prod = rxr->rx_prod;
834 struct sk_buff *skb;
835 int off, err;
836
837 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
838 if (unlikely(err)) {
839 bnxt_reuse_rx_data(rxr, cons, data);
840 return NULL;
841 }
842 dma_addr -= bp->rx_dma_offset;
843 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
844 DMA_ATTR_WEAK_ORDERING);
845
846 if (unlikely(!payload))
847 payload = eth_get_headlen(data_ptr, len);
848
849 skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
850 if (!skb) {
851 __free_page(page);
852 return NULL;
853 }
854
855 off = (void *)data_ptr - page_address(page);
856 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
857 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
858 payload + NET_IP_ALIGN);
859
860 frag = &skb_shinfo(skb)->frags[0];
861 skb_frag_size_sub(frag, payload);
862 frag->page_offset += payload;
863 skb->data_len -= payload;
864 skb->tail += payload;
865
866 return skb;
867 }
868
869 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
870 struct bnxt_rx_ring_info *rxr, u16 cons,
871 void *data, u8 *data_ptr,
872 dma_addr_t dma_addr,
873 unsigned int offset_and_len)
874 {
875 u16 prod = rxr->rx_prod;
876 struct sk_buff *skb;
877 int err;
878
879 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
880 if (unlikely(err)) {
881 bnxt_reuse_rx_data(rxr, cons, data);
882 return NULL;
883 }
884
885 skb = build_skb(data, 0);
886 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
887 bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
888 if (!skb) {
889 kfree(data);
890 return NULL;
891 }
892
893 skb_reserve(skb, bp->rx_offset);
894 skb_put(skb, offset_and_len & 0xffff);
895 return skb;
896 }
897
898 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
899 struct sk_buff *skb, u16 cp_cons,
900 u32 agg_bufs)
901 {
902 struct pci_dev *pdev = bp->pdev;
903 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
904 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
905 u16 prod = rxr->rx_agg_prod;
906 u32 i;
907
908 for (i = 0; i < agg_bufs; i++) {
909 u16 cons, frag_len;
910 struct rx_agg_cmp *agg;
911 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
912 struct page *page;
913 dma_addr_t mapping;
914
915 agg = (struct rx_agg_cmp *)
916 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
917 cons = agg->rx_agg_cmp_opaque;
918 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
919 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
920
921 cons_rx_buf = &rxr->rx_agg_ring[cons];
922 skb_fill_page_desc(skb, i, cons_rx_buf->page,
923 cons_rx_buf->offset, frag_len);
924 __clear_bit(cons, rxr->rx_agg_bmap);
925
926 /* It is possible for bnxt_alloc_rx_page() to allocate
927 * a sw_prod index that equals the cons index, so we
928 * need to clear the cons entry now.
929 */
930 mapping = cons_rx_buf->mapping;
931 page = cons_rx_buf->page;
932 cons_rx_buf->page = NULL;
933
934 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
935 struct skb_shared_info *shinfo;
936 unsigned int nr_frags;
937
938 shinfo = skb_shinfo(skb);
939 nr_frags = --shinfo->nr_frags;
940 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
941
942 dev_kfree_skb(skb);
943
944 cons_rx_buf->page = page;
945
946 /* Update prod since possibly some pages have been
947 * allocated already.
948 */
949 rxr->rx_agg_prod = prod;
950 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
951 return NULL;
952 }
953
954 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
955 PCI_DMA_FROMDEVICE,
956 DMA_ATTR_WEAK_ORDERING);
957
958 skb->data_len += frag_len;
959 skb->len += frag_len;
960 skb->truesize += PAGE_SIZE;
961
962 prod = NEXT_RX_AGG(prod);
963 cp_cons = NEXT_CMP(cp_cons);
964 }
965 rxr->rx_agg_prod = prod;
966 return skb;
967 }
968
969 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
970 u8 agg_bufs, u32 *raw_cons)
971 {
972 u16 last;
973 struct rx_agg_cmp *agg;
974
975 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
976 last = RING_CMP(*raw_cons);
977 agg = (struct rx_agg_cmp *)
978 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
979 return RX_AGG_CMP_VALID(agg, *raw_cons);
980 }
981
982 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
983 unsigned int len,
984 dma_addr_t mapping)
985 {
986 struct bnxt *bp = bnapi->bp;
987 struct pci_dev *pdev = bp->pdev;
988 struct sk_buff *skb;
989
990 skb = napi_alloc_skb(&bnapi->napi, len);
991 if (!skb)
992 return NULL;
993
994 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
995 bp->rx_dir);
996
997 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
998 len + NET_IP_ALIGN);
999
1000 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1001 bp->rx_dir);
1002
1003 skb_put(skb, len);
1004 return skb;
1005 }
1006
1007 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
1008 u32 *raw_cons, void *cmp)
1009 {
1010 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1011 struct rx_cmp *rxcmp = cmp;
1012 u32 tmp_raw_cons = *raw_cons;
1013 u8 cmp_type, agg_bufs = 0;
1014
1015 cmp_type = RX_CMP_TYPE(rxcmp);
1016
1017 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1018 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1019 RX_CMP_AGG_BUFS) >>
1020 RX_CMP_AGG_BUFS_SHIFT;
1021 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1022 struct rx_tpa_end_cmp *tpa_end = cmp;
1023
1024 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1025 RX_TPA_END_CMP_AGG_BUFS) >>
1026 RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1027 }
1028
1029 if (agg_bufs) {
1030 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1031 return -EBUSY;
1032 }
1033 *raw_cons = tmp_raw_cons;
1034 return 0;
1035 }
1036
1037 static void bnxt_queue_sp_work(struct bnxt *bp)
1038 {
1039 if (BNXT_PF(bp))
1040 queue_work(bnxt_pf_wq, &bp->sp_task);
1041 else
1042 schedule_work(&bp->sp_task);
1043 }
1044
1045 static void bnxt_cancel_sp_work(struct bnxt *bp)
1046 {
1047 if (BNXT_PF(bp))
1048 flush_workqueue(bnxt_pf_wq);
1049 else
1050 cancel_work_sync(&bp->sp_task);
1051 }
1052
1053 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1054 {
1055 if (!rxr->bnapi->in_reset) {
1056 rxr->bnapi->in_reset = true;
1057 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1058 bnxt_queue_sp_work(bp);
1059 }
1060 rxr->rx_next_cons = 0xffff;
1061 }
1062
1063 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1064 struct rx_tpa_start_cmp *tpa_start,
1065 struct rx_tpa_start_cmp_ext *tpa_start1)
1066 {
1067 u8 agg_id = TPA_START_AGG_ID(tpa_start);
1068 u16 cons, prod;
1069 struct bnxt_tpa_info *tpa_info;
1070 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1071 struct rx_bd *prod_bd;
1072 dma_addr_t mapping;
1073
1074 cons = tpa_start->rx_tpa_start_cmp_opaque;
1075 prod = rxr->rx_prod;
1076 cons_rx_buf = &rxr->rx_buf_ring[cons];
1077 prod_rx_buf = &rxr->rx_buf_ring[prod];
1078 tpa_info = &rxr->rx_tpa[agg_id];
1079
1080 if (unlikely(cons != rxr->rx_next_cons)) {
1081 bnxt_sched_reset(bp, rxr);
1082 return;
1083 }
1084 /* Store cfa_code in tpa_info to use in tpa_end
1085 * completion processing.
1086 */
1087 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1088 prod_rx_buf->data = tpa_info->data;
1089 prod_rx_buf->data_ptr = tpa_info->data_ptr;
1090
1091 mapping = tpa_info->mapping;
1092 prod_rx_buf->mapping = mapping;
1093
1094 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1095
1096 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1097
1098 tpa_info->data = cons_rx_buf->data;
1099 tpa_info->data_ptr = cons_rx_buf->data_ptr;
1100 cons_rx_buf->data = NULL;
1101 tpa_info->mapping = cons_rx_buf->mapping;
1102
1103 tpa_info->len =
1104 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1105 RX_TPA_START_CMP_LEN_SHIFT;
1106 if (likely(TPA_START_HASH_VALID(tpa_start))) {
1107 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1108
1109 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1110 tpa_info->gso_type = SKB_GSO_TCPV4;
1111 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1112 if (hash_type == 3)
1113 tpa_info->gso_type = SKB_GSO_TCPV6;
1114 tpa_info->rss_hash =
1115 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1116 } else {
1117 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1118 tpa_info->gso_type = 0;
1119 if (netif_msg_rx_err(bp))
1120 netdev_warn(bp->dev, "TPA packet without valid hash\n");
1121 }
1122 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1123 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1124 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1125
1126 rxr->rx_prod = NEXT_RX(prod);
1127 cons = NEXT_RX(cons);
1128 rxr->rx_next_cons = NEXT_RX(cons);
1129 cons_rx_buf = &rxr->rx_buf_ring[cons];
1130
1131 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1132 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1133 cons_rx_buf->data = NULL;
1134 }
1135
1136 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1137 u16 cp_cons, u32 agg_bufs)
1138 {
1139 if (agg_bufs)
1140 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1141 }
1142
1143 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1144 int payload_off, int tcp_ts,
1145 struct sk_buff *skb)
1146 {
1147 #ifdef CONFIG_INET
1148 struct tcphdr *th;
1149 int len, nw_off;
1150 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1151 u32 hdr_info = tpa_info->hdr_info;
1152 bool loopback = false;
1153
1154 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1155 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1156 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1157
1158 /* If the packet is an internal loopback packet, the offsets will
1159 * have an extra 4 bytes.
1160 */
1161 if (inner_mac_off == 4) {
1162 loopback = true;
1163 } else if (inner_mac_off > 4) {
1164 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1165 ETH_HLEN - 2));
1166
1167 /* We only support inner iPv4/ipv6. If we don't see the
1168 * correct protocol ID, it must be a loopback packet where
1169 * the offsets are off by 4.
1170 */
1171 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1172 loopback = true;
1173 }
1174 if (loopback) {
1175 /* internal loopback packet, subtract all offsets by 4 */
1176 inner_ip_off -= 4;
1177 inner_mac_off -= 4;
1178 outer_ip_off -= 4;
1179 }
1180
1181 nw_off = inner_ip_off - ETH_HLEN;
1182 skb_set_network_header(skb, nw_off);
1183 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1184 struct ipv6hdr *iph = ipv6_hdr(skb);
1185
1186 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1187 len = skb->len - skb_transport_offset(skb);
1188 th = tcp_hdr(skb);
1189 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1190 } else {
1191 struct iphdr *iph = ip_hdr(skb);
1192
1193 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1194 len = skb->len - skb_transport_offset(skb);
1195 th = tcp_hdr(skb);
1196 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1197 }
1198
1199 if (inner_mac_off) { /* tunnel */
1200 struct udphdr *uh = NULL;
1201 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1202 ETH_HLEN - 2));
1203
1204 if (proto == htons(ETH_P_IP)) {
1205 struct iphdr *iph = (struct iphdr *)skb->data;
1206
1207 if (iph->protocol == IPPROTO_UDP)
1208 uh = (struct udphdr *)(iph + 1);
1209 } else {
1210 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1211
1212 if (iph->nexthdr == IPPROTO_UDP)
1213 uh = (struct udphdr *)(iph + 1);
1214 }
1215 if (uh) {
1216 if (uh->check)
1217 skb_shinfo(skb)->gso_type |=
1218 SKB_GSO_UDP_TUNNEL_CSUM;
1219 else
1220 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1221 }
1222 }
1223 #endif
1224 return skb;
1225 }
1226
1227 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1228 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1229
1230 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1231 int payload_off, int tcp_ts,
1232 struct sk_buff *skb)
1233 {
1234 #ifdef CONFIG_INET
1235 struct tcphdr *th;
1236 int len, nw_off, tcp_opt_len = 0;
1237
1238 if (tcp_ts)
1239 tcp_opt_len = 12;
1240
1241 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1242 struct iphdr *iph;
1243
1244 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1245 ETH_HLEN;
1246 skb_set_network_header(skb, nw_off);
1247 iph = ip_hdr(skb);
1248 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1249 len = skb->len - skb_transport_offset(skb);
1250 th = tcp_hdr(skb);
1251 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1252 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1253 struct ipv6hdr *iph;
1254
1255 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1256 ETH_HLEN;
1257 skb_set_network_header(skb, nw_off);
1258 iph = ipv6_hdr(skb);
1259 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1260 len = skb->len - skb_transport_offset(skb);
1261 th = tcp_hdr(skb);
1262 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1263 } else {
1264 dev_kfree_skb_any(skb);
1265 return NULL;
1266 }
1267
1268 if (nw_off) { /* tunnel */
1269 struct udphdr *uh = NULL;
1270
1271 if (skb->protocol == htons(ETH_P_IP)) {
1272 struct iphdr *iph = (struct iphdr *)skb->data;
1273
1274 if (iph->protocol == IPPROTO_UDP)
1275 uh = (struct udphdr *)(iph + 1);
1276 } else {
1277 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1278
1279 if (iph->nexthdr == IPPROTO_UDP)
1280 uh = (struct udphdr *)(iph + 1);
1281 }
1282 if (uh) {
1283 if (uh->check)
1284 skb_shinfo(skb)->gso_type |=
1285 SKB_GSO_UDP_TUNNEL_CSUM;
1286 else
1287 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1288 }
1289 }
1290 #endif
1291 return skb;
1292 }
1293
1294 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1295 struct bnxt_tpa_info *tpa_info,
1296 struct rx_tpa_end_cmp *tpa_end,
1297 struct rx_tpa_end_cmp_ext *tpa_end1,
1298 struct sk_buff *skb)
1299 {
1300 #ifdef CONFIG_INET
1301 int payload_off;
1302 u16 segs;
1303
1304 segs = TPA_END_TPA_SEGS(tpa_end);
1305 if (segs == 1)
1306 return skb;
1307
1308 NAPI_GRO_CB(skb)->count = segs;
1309 skb_shinfo(skb)->gso_size =
1310 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1311 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1312 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1313 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1314 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1315 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1316 if (likely(skb))
1317 tcp_gro_complete(skb);
1318 #endif
1319 return skb;
1320 }
1321
1322 /* Given the cfa_code of a received packet determine which
1323 * netdev (vf-rep or PF) the packet is destined to.
1324 */
1325 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1326 {
1327 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1328
1329 /* if vf-rep dev is NULL, the must belongs to the PF */
1330 return dev ? dev : bp->dev;
1331 }
1332
1333 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1334 struct bnxt_napi *bnapi,
1335 u32 *raw_cons,
1336 struct rx_tpa_end_cmp *tpa_end,
1337 struct rx_tpa_end_cmp_ext *tpa_end1,
1338 u8 *event)
1339 {
1340 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1341 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1342 u8 agg_id = TPA_END_AGG_ID(tpa_end);
1343 u8 *data_ptr, agg_bufs;
1344 u16 cp_cons = RING_CMP(*raw_cons);
1345 unsigned int len;
1346 struct bnxt_tpa_info *tpa_info;
1347 dma_addr_t mapping;
1348 struct sk_buff *skb;
1349 void *data;
1350
1351 if (unlikely(bnapi->in_reset)) {
1352 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1353
1354 if (rc < 0)
1355 return ERR_PTR(-EBUSY);
1356 return NULL;
1357 }
1358
1359 tpa_info = &rxr->rx_tpa[agg_id];
1360 data = tpa_info->data;
1361 data_ptr = tpa_info->data_ptr;
1362 prefetch(data_ptr);
1363 len = tpa_info->len;
1364 mapping = tpa_info->mapping;
1365
1366 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1367 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1368
1369 if (agg_bufs) {
1370 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1371 return ERR_PTR(-EBUSY);
1372
1373 *event |= BNXT_AGG_EVENT;
1374 cp_cons = NEXT_CMP(cp_cons);
1375 }
1376
1377 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1378 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1379 if (agg_bufs > MAX_SKB_FRAGS)
1380 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1381 agg_bufs, (int)MAX_SKB_FRAGS);
1382 return NULL;
1383 }
1384
1385 if (len <= bp->rx_copy_thresh) {
1386 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1387 if (!skb) {
1388 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1389 return NULL;
1390 }
1391 } else {
1392 u8 *new_data;
1393 dma_addr_t new_mapping;
1394
1395 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1396 if (!new_data) {
1397 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1398 return NULL;
1399 }
1400
1401 tpa_info->data = new_data;
1402 tpa_info->data_ptr = new_data + bp->rx_offset;
1403 tpa_info->mapping = new_mapping;
1404
1405 skb = build_skb(data, 0);
1406 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1407 bp->rx_buf_use_size, bp->rx_dir,
1408 DMA_ATTR_WEAK_ORDERING);
1409
1410 if (!skb) {
1411 kfree(data);
1412 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1413 return NULL;
1414 }
1415 skb_reserve(skb, bp->rx_offset);
1416 skb_put(skb, len);
1417 }
1418
1419 if (agg_bufs) {
1420 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1421 if (!skb) {
1422 /* Page reuse already handled by bnxt_rx_pages(). */
1423 return NULL;
1424 }
1425 }
1426
1427 skb->protocol =
1428 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1429
1430 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1431 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1432
1433 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1434 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1435 u16 vlan_proto = tpa_info->metadata >>
1436 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1437 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK;
1438
1439 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1440 }
1441
1442 skb_checksum_none_assert(skb);
1443 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1444 skb->ip_summed = CHECKSUM_UNNECESSARY;
1445 skb->csum_level =
1446 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1447 }
1448
1449 if (TPA_END_GRO(tpa_end))
1450 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1451
1452 return skb;
1453 }
1454
1455 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1456 struct sk_buff *skb)
1457 {
1458 if (skb->dev != bp->dev) {
1459 /* this packet belongs to a vf-rep */
1460 bnxt_vf_rep_rx(bp, skb);
1461 return;
1462 }
1463 skb_record_rx_queue(skb, bnapi->index);
1464 napi_gro_receive(&bnapi->napi, skb);
1465 }
1466
1467 /* returns the following:
1468 * 1 - 1 packet successfully received
1469 * 0 - successful TPA_START, packet not completed yet
1470 * -EBUSY - completion ring does not have all the agg buffers yet
1471 * -ENOMEM - packet aborted due to out of memory
1472 * -EIO - packet aborted due to hw error indicated in BD
1473 */
1474 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1475 u8 *event)
1476 {
1477 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1478 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1479 struct net_device *dev = bp->dev;
1480 struct rx_cmp *rxcmp;
1481 struct rx_cmp_ext *rxcmp1;
1482 u32 tmp_raw_cons = *raw_cons;
1483 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1484 struct bnxt_sw_rx_bd *rx_buf;
1485 unsigned int len;
1486 u8 *data_ptr, agg_bufs, cmp_type;
1487 dma_addr_t dma_addr;
1488 struct sk_buff *skb;
1489 void *data;
1490 int rc = 0;
1491 u32 misc;
1492
1493 rxcmp = (struct rx_cmp *)
1494 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1495
1496 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1497 cp_cons = RING_CMP(tmp_raw_cons);
1498 rxcmp1 = (struct rx_cmp_ext *)
1499 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1500
1501 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1502 return -EBUSY;
1503
1504 cmp_type = RX_CMP_TYPE(rxcmp);
1505
1506 prod = rxr->rx_prod;
1507
1508 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1509 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1510 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1511
1512 *event |= BNXT_RX_EVENT;
1513 goto next_rx_no_prod_no_len;
1514
1515 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1516 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1517 (struct rx_tpa_end_cmp *)rxcmp,
1518 (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1519
1520 if (IS_ERR(skb))
1521 return -EBUSY;
1522
1523 rc = -ENOMEM;
1524 if (likely(skb)) {
1525 bnxt_deliver_skb(bp, bnapi, skb);
1526 rc = 1;
1527 }
1528 *event |= BNXT_RX_EVENT;
1529 goto next_rx_no_prod_no_len;
1530 }
1531
1532 cons = rxcmp->rx_cmp_opaque;
1533 rx_buf = &rxr->rx_buf_ring[cons];
1534 data = rx_buf->data;
1535 data_ptr = rx_buf->data_ptr;
1536 if (unlikely(cons != rxr->rx_next_cons)) {
1537 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1538
1539 bnxt_sched_reset(bp, rxr);
1540 return rc1;
1541 }
1542 prefetch(data_ptr);
1543
1544 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1545 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1546
1547 if (agg_bufs) {
1548 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1549 return -EBUSY;
1550
1551 cp_cons = NEXT_CMP(cp_cons);
1552 *event |= BNXT_AGG_EVENT;
1553 }
1554 *event |= BNXT_RX_EVENT;
1555
1556 rx_buf->data = NULL;
1557 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1558 bnxt_reuse_rx_data(rxr, cons, data);
1559 if (agg_bufs)
1560 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1561
1562 rc = -EIO;
1563 goto next_rx;
1564 }
1565
1566 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1567 dma_addr = rx_buf->mapping;
1568
1569 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1570 rc = 1;
1571 goto next_rx;
1572 }
1573
1574 if (len <= bp->rx_copy_thresh) {
1575 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1576 bnxt_reuse_rx_data(rxr, cons, data);
1577 if (!skb) {
1578 rc = -ENOMEM;
1579 goto next_rx;
1580 }
1581 } else {
1582 u32 payload;
1583
1584 if (rx_buf->data_ptr == data_ptr)
1585 payload = misc & RX_CMP_PAYLOAD_OFFSET;
1586 else
1587 payload = 0;
1588 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1589 payload | len);
1590 if (!skb) {
1591 rc = -ENOMEM;
1592 goto next_rx;
1593 }
1594 }
1595
1596 if (agg_bufs) {
1597 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1598 if (!skb) {
1599 rc = -ENOMEM;
1600 goto next_rx;
1601 }
1602 }
1603
1604 if (RX_CMP_HASH_VALID(rxcmp)) {
1605 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1606 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1607
1608 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1609 if (hash_type != 1 && hash_type != 3)
1610 type = PKT_HASH_TYPE_L3;
1611 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1612 }
1613
1614 cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1615 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1616
1617 if ((rxcmp1->rx_cmp_flags2 &
1618 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1619 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1620 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1621 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK;
1622 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1623
1624 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1625 }
1626
1627 skb_checksum_none_assert(skb);
1628 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1629 if (dev->features & NETIF_F_RXCSUM) {
1630 skb->ip_summed = CHECKSUM_UNNECESSARY;
1631 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1632 }
1633 } else {
1634 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1635 if (dev->features & NETIF_F_RXCSUM)
1636 cpr->rx_l4_csum_errors++;
1637 }
1638 }
1639
1640 bnxt_deliver_skb(bp, bnapi, skb);
1641 rc = 1;
1642
1643 next_rx:
1644 rxr->rx_prod = NEXT_RX(prod);
1645 rxr->rx_next_cons = NEXT_RX(cons);
1646
1647 cpr->rx_packets += 1;
1648 cpr->rx_bytes += len;
1649
1650 next_rx_no_prod_no_len:
1651 *raw_cons = tmp_raw_cons;
1652
1653 return rc;
1654 }
1655
1656 /* In netpoll mode, if we are using a combined completion ring, we need to
1657 * discard the rx packets and recycle the buffers.
1658 */
1659 static int bnxt_force_rx_discard(struct bnxt *bp, struct bnxt_napi *bnapi,
1660 u32 *raw_cons, u8 *event)
1661 {
1662 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1663 u32 tmp_raw_cons = *raw_cons;
1664 struct rx_cmp_ext *rxcmp1;
1665 struct rx_cmp *rxcmp;
1666 u16 cp_cons;
1667 u8 cmp_type;
1668
1669 cp_cons = RING_CMP(tmp_raw_cons);
1670 rxcmp = (struct rx_cmp *)
1671 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1672
1673 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1674 cp_cons = RING_CMP(tmp_raw_cons);
1675 rxcmp1 = (struct rx_cmp_ext *)
1676 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1677
1678 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1679 return -EBUSY;
1680
1681 cmp_type = RX_CMP_TYPE(rxcmp);
1682 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1683 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1684 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1685 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1686 struct rx_tpa_end_cmp_ext *tpa_end1;
1687
1688 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1689 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1690 cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1691 }
1692 return bnxt_rx_pkt(bp, bnapi, raw_cons, event);
1693 }
1694
1695 #define BNXT_GET_EVENT_PORT(data) \
1696 ((data) & \
1697 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1698
1699 static int bnxt_async_event_process(struct bnxt *bp,
1700 struct hwrm_async_event_cmpl *cmpl)
1701 {
1702 u16 event_id = le16_to_cpu(cmpl->event_id);
1703
1704 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1705 switch (event_id) {
1706 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1707 u32 data1 = le32_to_cpu(cmpl->event_data1);
1708 struct bnxt_link_info *link_info = &bp->link_info;
1709
1710 if (BNXT_VF(bp))
1711 goto async_event_process_exit;
1712
1713 /* print unsupported speed warning in forced speed mode only */
1714 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1715 (data1 & 0x20000)) {
1716 u16 fw_speed = link_info->force_link_speed;
1717 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1718
1719 if (speed != SPEED_UNKNOWN)
1720 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1721 speed);
1722 }
1723 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1724 /* fall thru */
1725 }
1726 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1727 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1728 break;
1729 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1730 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1731 break;
1732 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1733 u32 data1 = le32_to_cpu(cmpl->event_data1);
1734 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1735
1736 if (BNXT_VF(bp))
1737 break;
1738
1739 if (bp->pf.port_id != port_id)
1740 break;
1741
1742 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1743 break;
1744 }
1745 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1746 if (BNXT_PF(bp))
1747 goto async_event_process_exit;
1748 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1749 break;
1750 default:
1751 goto async_event_process_exit;
1752 }
1753 bnxt_queue_sp_work(bp);
1754 async_event_process_exit:
1755 bnxt_ulp_async_events(bp, cmpl);
1756 return 0;
1757 }
1758
1759 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1760 {
1761 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1762 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1763 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1764 (struct hwrm_fwd_req_cmpl *)txcmp;
1765
1766 switch (cmpl_type) {
1767 case CMPL_BASE_TYPE_HWRM_DONE:
1768 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1769 if (seq_id == bp->hwrm_intr_seq_id)
1770 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1771 else
1772 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1773 break;
1774
1775 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1776 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1777
1778 if ((vf_id < bp->pf.first_vf_id) ||
1779 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1780 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1781 vf_id);
1782 return -EINVAL;
1783 }
1784
1785 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1786 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1787 bnxt_queue_sp_work(bp);
1788 break;
1789
1790 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1791 bnxt_async_event_process(bp,
1792 (struct hwrm_async_event_cmpl *)txcmp);
1793
1794 default:
1795 break;
1796 }
1797
1798 return 0;
1799 }
1800
1801 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1802 {
1803 struct bnxt_napi *bnapi = dev_instance;
1804 struct bnxt *bp = bnapi->bp;
1805 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1806 u32 cons = RING_CMP(cpr->cp_raw_cons);
1807
1808 cpr->event_ctr++;
1809 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1810 napi_schedule(&bnapi->napi);
1811 return IRQ_HANDLED;
1812 }
1813
1814 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1815 {
1816 u32 raw_cons = cpr->cp_raw_cons;
1817 u16 cons = RING_CMP(raw_cons);
1818 struct tx_cmp *txcmp;
1819
1820 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1821
1822 return TX_CMP_VALID(txcmp, raw_cons);
1823 }
1824
1825 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1826 {
1827 struct bnxt_napi *bnapi = dev_instance;
1828 struct bnxt *bp = bnapi->bp;
1829 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1830 u32 cons = RING_CMP(cpr->cp_raw_cons);
1831 u32 int_status;
1832
1833 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1834
1835 if (!bnxt_has_work(bp, cpr)) {
1836 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1837 /* return if erroneous interrupt */
1838 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1839 return IRQ_NONE;
1840 }
1841
1842 /* disable ring IRQ */
1843 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1844
1845 /* Return here if interrupt is shared and is disabled. */
1846 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1847 return IRQ_HANDLED;
1848
1849 napi_schedule(&bnapi->napi);
1850 return IRQ_HANDLED;
1851 }
1852
1853 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1854 {
1855 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1856 u32 raw_cons = cpr->cp_raw_cons;
1857 u32 cons;
1858 int tx_pkts = 0;
1859 int rx_pkts = 0;
1860 u8 event = 0;
1861 struct tx_cmp *txcmp;
1862
1863 while (1) {
1864 int rc;
1865
1866 cons = RING_CMP(raw_cons);
1867 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1868
1869 if (!TX_CMP_VALID(txcmp, raw_cons))
1870 break;
1871
1872 /* The valid test of the entry must be done first before
1873 * reading any further.
1874 */
1875 dma_rmb();
1876 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1877 tx_pkts++;
1878 /* return full budget so NAPI will complete. */
1879 if (unlikely(tx_pkts > bp->tx_wake_thresh))
1880 rx_pkts = budget;
1881 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1882 if (likely(budget))
1883 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1884 else
1885 rc = bnxt_force_rx_discard(bp, bnapi, &raw_cons,
1886 &event);
1887 if (likely(rc >= 0))
1888 rx_pkts += rc;
1889 /* Increment rx_pkts when rc is -ENOMEM to count towards
1890 * the NAPI budget. Otherwise, we may potentially loop
1891 * here forever if we consistently cannot allocate
1892 * buffers.
1893 */
1894 else if (rc == -ENOMEM && budget)
1895 rx_pkts++;
1896 else if (rc == -EBUSY) /* partial completion */
1897 break;
1898 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1899 CMPL_BASE_TYPE_HWRM_DONE) ||
1900 (TX_CMP_TYPE(txcmp) ==
1901 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1902 (TX_CMP_TYPE(txcmp) ==
1903 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1904 bnxt_hwrm_handler(bp, txcmp);
1905 }
1906 raw_cons = NEXT_RAW_CMP(raw_cons);
1907
1908 if (rx_pkts == budget)
1909 break;
1910 }
1911
1912 if (event & BNXT_TX_EVENT) {
1913 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1914 void __iomem *db = txr->tx_doorbell;
1915 u16 prod = txr->tx_prod;
1916
1917 /* Sync BD data before updating doorbell */
1918 wmb();
1919
1920 bnxt_db_write(bp, db, DB_KEY_TX | prod);
1921 }
1922
1923 cpr->cp_raw_cons = raw_cons;
1924 /* ACK completion ring before freeing tx ring and producing new
1925 * buffers in rx/agg rings to prevent overflowing the completion
1926 * ring.
1927 */
1928 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1929
1930 if (tx_pkts)
1931 bnapi->tx_int(bp, bnapi, tx_pkts);
1932
1933 if (event & BNXT_RX_EVENT) {
1934 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1935
1936 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
1937 if (event & BNXT_AGG_EVENT)
1938 bnxt_db_write(bp, rxr->rx_agg_doorbell,
1939 DB_KEY_RX | rxr->rx_agg_prod);
1940 }
1941 return rx_pkts;
1942 }
1943
1944 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1945 {
1946 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1947 struct bnxt *bp = bnapi->bp;
1948 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1949 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1950 struct tx_cmp *txcmp;
1951 struct rx_cmp_ext *rxcmp1;
1952 u32 cp_cons, tmp_raw_cons;
1953 u32 raw_cons = cpr->cp_raw_cons;
1954 u32 rx_pkts = 0;
1955 u8 event = 0;
1956
1957 while (1) {
1958 int rc;
1959
1960 cp_cons = RING_CMP(raw_cons);
1961 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1962
1963 if (!TX_CMP_VALID(txcmp, raw_cons))
1964 break;
1965
1966 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1967 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
1968 cp_cons = RING_CMP(tmp_raw_cons);
1969 rxcmp1 = (struct rx_cmp_ext *)
1970 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1971
1972 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1973 break;
1974
1975 /* force an error to recycle the buffer */
1976 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1977 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1978
1979 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1980 if (likely(rc == -EIO) && budget)
1981 rx_pkts++;
1982 else if (rc == -EBUSY) /* partial completion */
1983 break;
1984 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
1985 CMPL_BASE_TYPE_HWRM_DONE)) {
1986 bnxt_hwrm_handler(bp, txcmp);
1987 } else {
1988 netdev_err(bp->dev,
1989 "Invalid completion received on special ring\n");
1990 }
1991 raw_cons = NEXT_RAW_CMP(raw_cons);
1992
1993 if (rx_pkts == budget)
1994 break;
1995 }
1996
1997 cpr->cp_raw_cons = raw_cons;
1998 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1999 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
2000
2001 if (event & BNXT_AGG_EVENT)
2002 bnxt_db_write(bp, rxr->rx_agg_doorbell,
2003 DB_KEY_RX | rxr->rx_agg_prod);
2004
2005 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2006 napi_complete_done(napi, rx_pkts);
2007 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
2008 }
2009 return rx_pkts;
2010 }
2011
2012 static int bnxt_poll(struct napi_struct *napi, int budget)
2013 {
2014 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2015 struct bnxt *bp = bnapi->bp;
2016 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2017 int work_done = 0;
2018
2019 while (1) {
2020 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
2021
2022 if (work_done >= budget)
2023 break;
2024
2025 if (!bnxt_has_work(bp, cpr)) {
2026 if (napi_complete_done(napi, work_done))
2027 BNXT_CP_DB_REARM(cpr->cp_doorbell,
2028 cpr->cp_raw_cons);
2029 break;
2030 }
2031 }
2032 if (bp->flags & BNXT_FLAG_DIM) {
2033 struct net_dim_sample dim_sample;
2034
2035 net_dim_sample(cpr->event_ctr,
2036 cpr->rx_packets,
2037 cpr->rx_bytes,
2038 &dim_sample);
2039 net_dim(&cpr->dim, dim_sample);
2040 }
2041 mmiowb();
2042 return work_done;
2043 }
2044
2045 static void bnxt_free_tx_skbs(struct bnxt *bp)
2046 {
2047 int i, max_idx;
2048 struct pci_dev *pdev = bp->pdev;
2049
2050 if (!bp->tx_ring)
2051 return;
2052
2053 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2054 for (i = 0; i < bp->tx_nr_rings; i++) {
2055 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2056 int j;
2057
2058 for (j = 0; j < max_idx;) {
2059 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2060 struct sk_buff *skb = tx_buf->skb;
2061 int k, last;
2062
2063 if (!skb) {
2064 j++;
2065 continue;
2066 }
2067
2068 tx_buf->skb = NULL;
2069
2070 if (tx_buf->is_push) {
2071 dev_kfree_skb(skb);
2072 j += 2;
2073 continue;
2074 }
2075
2076 dma_unmap_single(&pdev->dev,
2077 dma_unmap_addr(tx_buf, mapping),
2078 skb_headlen(skb),
2079 PCI_DMA_TODEVICE);
2080
2081 last = tx_buf->nr_frags;
2082 j += 2;
2083 for (k = 0; k < last; k++, j++) {
2084 int ring_idx = j & bp->tx_ring_mask;
2085 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2086
2087 tx_buf = &txr->tx_buf_ring[ring_idx];
2088 dma_unmap_page(
2089 &pdev->dev,
2090 dma_unmap_addr(tx_buf, mapping),
2091 skb_frag_size(frag), PCI_DMA_TODEVICE);
2092 }
2093 dev_kfree_skb(skb);
2094 }
2095 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2096 }
2097 }
2098
2099 static void bnxt_free_rx_skbs(struct bnxt *bp)
2100 {
2101 int i, max_idx, max_agg_idx;
2102 struct pci_dev *pdev = bp->pdev;
2103
2104 if (!bp->rx_ring)
2105 return;
2106
2107 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2108 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2109 for (i = 0; i < bp->rx_nr_rings; i++) {
2110 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2111 int j;
2112
2113 if (rxr->rx_tpa) {
2114 for (j = 0; j < MAX_TPA; j++) {
2115 struct bnxt_tpa_info *tpa_info =
2116 &rxr->rx_tpa[j];
2117 u8 *data = tpa_info->data;
2118
2119 if (!data)
2120 continue;
2121
2122 dma_unmap_single_attrs(&pdev->dev,
2123 tpa_info->mapping,
2124 bp->rx_buf_use_size,
2125 bp->rx_dir,
2126 DMA_ATTR_WEAK_ORDERING);
2127
2128 tpa_info->data = NULL;
2129
2130 kfree(data);
2131 }
2132 }
2133
2134 for (j = 0; j < max_idx; j++) {
2135 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
2136 dma_addr_t mapping = rx_buf->mapping;
2137 void *data = rx_buf->data;
2138
2139 if (!data)
2140 continue;
2141
2142 rx_buf->data = NULL;
2143
2144 if (BNXT_RX_PAGE_MODE(bp)) {
2145 mapping -= bp->rx_dma_offset;
2146 dma_unmap_page_attrs(&pdev->dev, mapping,
2147 PAGE_SIZE, bp->rx_dir,
2148 DMA_ATTR_WEAK_ORDERING);
2149 __free_page(data);
2150 } else {
2151 dma_unmap_single_attrs(&pdev->dev, mapping,
2152 bp->rx_buf_use_size,
2153 bp->rx_dir,
2154 DMA_ATTR_WEAK_ORDERING);
2155 kfree(data);
2156 }
2157 }
2158
2159 for (j = 0; j < max_agg_idx; j++) {
2160 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2161 &rxr->rx_agg_ring[j];
2162 struct page *page = rx_agg_buf->page;
2163
2164 if (!page)
2165 continue;
2166
2167 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2168 BNXT_RX_PAGE_SIZE,
2169 PCI_DMA_FROMDEVICE,
2170 DMA_ATTR_WEAK_ORDERING);
2171
2172 rx_agg_buf->page = NULL;
2173 __clear_bit(j, rxr->rx_agg_bmap);
2174
2175 __free_page(page);
2176 }
2177 if (rxr->rx_page) {
2178 __free_page(rxr->rx_page);
2179 rxr->rx_page = NULL;
2180 }
2181 }
2182 }
2183
2184 static void bnxt_free_skbs(struct bnxt *bp)
2185 {
2186 bnxt_free_tx_skbs(bp);
2187 bnxt_free_rx_skbs(bp);
2188 }
2189
2190 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2191 {
2192 struct pci_dev *pdev = bp->pdev;
2193 int i;
2194
2195 for (i = 0; i < ring->nr_pages; i++) {
2196 if (!ring->pg_arr[i])
2197 continue;
2198
2199 dma_free_coherent(&pdev->dev, ring->page_size,
2200 ring->pg_arr[i], ring->dma_arr[i]);
2201
2202 ring->pg_arr[i] = NULL;
2203 }
2204 if (ring->pg_tbl) {
2205 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
2206 ring->pg_tbl, ring->pg_tbl_map);
2207 ring->pg_tbl = NULL;
2208 }
2209 if (ring->vmem_size && *ring->vmem) {
2210 vfree(*ring->vmem);
2211 *ring->vmem = NULL;
2212 }
2213 }
2214
2215 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2216 {
2217 int i;
2218 struct pci_dev *pdev = bp->pdev;
2219
2220 if (ring->nr_pages > 1) {
2221 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
2222 ring->nr_pages * 8,
2223 &ring->pg_tbl_map,
2224 GFP_KERNEL);
2225 if (!ring->pg_tbl)
2226 return -ENOMEM;
2227 }
2228
2229 for (i = 0; i < ring->nr_pages; i++) {
2230 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2231 ring->page_size,
2232 &ring->dma_arr[i],
2233 GFP_KERNEL);
2234 if (!ring->pg_arr[i])
2235 return -ENOMEM;
2236
2237 if (ring->nr_pages > 1)
2238 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
2239 }
2240
2241 if (ring->vmem_size) {
2242 *ring->vmem = vzalloc(ring->vmem_size);
2243 if (!(*ring->vmem))
2244 return -ENOMEM;
2245 }
2246 return 0;
2247 }
2248
2249 static void bnxt_free_rx_rings(struct bnxt *bp)
2250 {
2251 int i;
2252
2253 if (!bp->rx_ring)
2254 return;
2255
2256 for (i = 0; i < bp->rx_nr_rings; i++) {
2257 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2258 struct bnxt_ring_struct *ring;
2259
2260 if (rxr->xdp_prog)
2261 bpf_prog_put(rxr->xdp_prog);
2262
2263 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2264 xdp_rxq_info_unreg(&rxr->xdp_rxq);
2265
2266 kfree(rxr->rx_tpa);
2267 rxr->rx_tpa = NULL;
2268
2269 kfree(rxr->rx_agg_bmap);
2270 rxr->rx_agg_bmap = NULL;
2271
2272 ring = &rxr->rx_ring_struct;
2273 bnxt_free_ring(bp, ring);
2274
2275 ring = &rxr->rx_agg_ring_struct;
2276 bnxt_free_ring(bp, ring);
2277 }
2278 }
2279
2280 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2281 {
2282 int i, rc, agg_rings = 0, tpa_rings = 0;
2283
2284 if (!bp->rx_ring)
2285 return -ENOMEM;
2286
2287 if (bp->flags & BNXT_FLAG_AGG_RINGS)
2288 agg_rings = 1;
2289
2290 if (bp->flags & BNXT_FLAG_TPA)
2291 tpa_rings = 1;
2292
2293 for (i = 0; i < bp->rx_nr_rings; i++) {
2294 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2295 struct bnxt_ring_struct *ring;
2296
2297 ring = &rxr->rx_ring_struct;
2298
2299 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i);
2300 if (rc < 0)
2301 return rc;
2302
2303 rc = bnxt_alloc_ring(bp, ring);
2304 if (rc)
2305 return rc;
2306
2307 if (agg_rings) {
2308 u16 mem_size;
2309
2310 ring = &rxr->rx_agg_ring_struct;
2311 rc = bnxt_alloc_ring(bp, ring);
2312 if (rc)
2313 return rc;
2314
2315 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2316 mem_size = rxr->rx_agg_bmap_size / 8;
2317 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2318 if (!rxr->rx_agg_bmap)
2319 return -ENOMEM;
2320
2321 if (tpa_rings) {
2322 rxr->rx_tpa = kcalloc(MAX_TPA,
2323 sizeof(struct bnxt_tpa_info),
2324 GFP_KERNEL);
2325 if (!rxr->rx_tpa)
2326 return -ENOMEM;
2327 }
2328 }
2329 }
2330 return 0;
2331 }
2332
2333 static void bnxt_free_tx_rings(struct bnxt *bp)
2334 {
2335 int i;
2336 struct pci_dev *pdev = bp->pdev;
2337
2338 if (!bp->tx_ring)
2339 return;
2340
2341 for (i = 0; i < bp->tx_nr_rings; i++) {
2342 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2343 struct bnxt_ring_struct *ring;
2344
2345 if (txr->tx_push) {
2346 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2347 txr->tx_push, txr->tx_push_mapping);
2348 txr->tx_push = NULL;
2349 }
2350
2351 ring = &txr->tx_ring_struct;
2352
2353 bnxt_free_ring(bp, ring);
2354 }
2355 }
2356
2357 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2358 {
2359 int i, j, rc;
2360 struct pci_dev *pdev = bp->pdev;
2361
2362 bp->tx_push_size = 0;
2363 if (bp->tx_push_thresh) {
2364 int push_size;
2365
2366 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2367 bp->tx_push_thresh);
2368
2369 if (push_size > 256) {
2370 push_size = 0;
2371 bp->tx_push_thresh = 0;
2372 }
2373
2374 bp->tx_push_size = push_size;
2375 }
2376
2377 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2378 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2379 struct bnxt_ring_struct *ring;
2380
2381 ring = &txr->tx_ring_struct;
2382
2383 rc = bnxt_alloc_ring(bp, ring);
2384 if (rc)
2385 return rc;
2386
2387 if (bp->tx_push_size) {
2388 dma_addr_t mapping;
2389
2390 /* One pre-allocated DMA buffer to backup
2391 * TX push operation
2392 */
2393 txr->tx_push = dma_alloc_coherent(&pdev->dev,
2394 bp->tx_push_size,
2395 &txr->tx_push_mapping,
2396 GFP_KERNEL);
2397
2398 if (!txr->tx_push)
2399 return -ENOMEM;
2400
2401 mapping = txr->tx_push_mapping +
2402 sizeof(struct tx_push_bd);
2403 txr->data_mapping = cpu_to_le64(mapping);
2404
2405 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2406 }
2407 ring->queue_id = bp->q_info[j].queue_id;
2408 if (i < bp->tx_nr_rings_xdp)
2409 continue;
2410 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2411 j++;
2412 }
2413 return 0;
2414 }
2415
2416 static void bnxt_free_cp_rings(struct bnxt *bp)
2417 {
2418 int i;
2419
2420 if (!bp->bnapi)
2421 return;
2422
2423 for (i = 0; i < bp->cp_nr_rings; i++) {
2424 struct bnxt_napi *bnapi = bp->bnapi[i];
2425 struct bnxt_cp_ring_info *cpr;
2426 struct bnxt_ring_struct *ring;
2427
2428 if (!bnapi)
2429 continue;
2430
2431 cpr = &bnapi->cp_ring;
2432 ring = &cpr->cp_ring_struct;
2433
2434 bnxt_free_ring(bp, ring);
2435 }
2436 }
2437
2438 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2439 {
2440 int i, rc;
2441
2442 for (i = 0; i < bp->cp_nr_rings; i++) {
2443 struct bnxt_napi *bnapi = bp->bnapi[i];
2444 struct bnxt_cp_ring_info *cpr;
2445 struct bnxt_ring_struct *ring;
2446
2447 if (!bnapi)
2448 continue;
2449
2450 cpr = &bnapi->cp_ring;
2451 ring = &cpr->cp_ring_struct;
2452
2453 rc = bnxt_alloc_ring(bp, ring);
2454 if (rc)
2455 return rc;
2456 }
2457 return 0;
2458 }
2459
2460 static void bnxt_init_ring_struct(struct bnxt *bp)
2461 {
2462 int i;
2463
2464 for (i = 0; i < bp->cp_nr_rings; i++) {
2465 struct bnxt_napi *bnapi = bp->bnapi[i];
2466 struct bnxt_cp_ring_info *cpr;
2467 struct bnxt_rx_ring_info *rxr;
2468 struct bnxt_tx_ring_info *txr;
2469 struct bnxt_ring_struct *ring;
2470
2471 if (!bnapi)
2472 continue;
2473
2474 cpr = &bnapi->cp_ring;
2475 ring = &cpr->cp_ring_struct;
2476 ring->nr_pages = bp->cp_nr_pages;
2477 ring->page_size = HW_CMPD_RING_SIZE;
2478 ring->pg_arr = (void **)cpr->cp_desc_ring;
2479 ring->dma_arr = cpr->cp_desc_mapping;
2480 ring->vmem_size = 0;
2481
2482 rxr = bnapi->rx_ring;
2483 if (!rxr)
2484 goto skip_rx;
2485
2486 ring = &rxr->rx_ring_struct;
2487 ring->nr_pages = bp->rx_nr_pages;
2488 ring->page_size = HW_RXBD_RING_SIZE;
2489 ring->pg_arr = (void **)rxr->rx_desc_ring;
2490 ring->dma_arr = rxr->rx_desc_mapping;
2491 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2492 ring->vmem = (void **)&rxr->rx_buf_ring;
2493
2494 ring = &rxr->rx_agg_ring_struct;
2495 ring->nr_pages = bp->rx_agg_nr_pages;
2496 ring->page_size = HW_RXBD_RING_SIZE;
2497 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2498 ring->dma_arr = rxr->rx_agg_desc_mapping;
2499 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2500 ring->vmem = (void **)&rxr->rx_agg_ring;
2501
2502 skip_rx:
2503 txr = bnapi->tx_ring;
2504 if (!txr)
2505 continue;
2506
2507 ring = &txr->tx_ring_struct;
2508 ring->nr_pages = bp->tx_nr_pages;
2509 ring->page_size = HW_RXBD_RING_SIZE;
2510 ring->pg_arr = (void **)txr->tx_desc_ring;
2511 ring->dma_arr = txr->tx_desc_mapping;
2512 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2513 ring->vmem = (void **)&txr->tx_buf_ring;
2514 }
2515 }
2516
2517 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2518 {
2519 int i;
2520 u32 prod;
2521 struct rx_bd **rx_buf_ring;
2522
2523 rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2524 for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2525 int j;
2526 struct rx_bd *rxbd;
2527
2528 rxbd = rx_buf_ring[i];
2529 if (!rxbd)
2530 continue;
2531
2532 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2533 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2534 rxbd->rx_bd_opaque = prod;
2535 }
2536 }
2537 }
2538
2539 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2540 {
2541 struct net_device *dev = bp->dev;
2542 struct bnxt_rx_ring_info *rxr;
2543 struct bnxt_ring_struct *ring;
2544 u32 prod, type;
2545 int i;
2546
2547 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2548 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2549
2550 if (NET_IP_ALIGN == 2)
2551 type |= RX_BD_FLAGS_SOP;
2552
2553 rxr = &bp->rx_ring[ring_nr];
2554 ring = &rxr->rx_ring_struct;
2555 bnxt_init_rxbd_pages(ring, type);
2556
2557 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2558 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2559 if (IS_ERR(rxr->xdp_prog)) {
2560 int rc = PTR_ERR(rxr->xdp_prog);
2561
2562 rxr->xdp_prog = NULL;
2563 return rc;
2564 }
2565 }
2566 prod = rxr->rx_prod;
2567 for (i = 0; i < bp->rx_ring_size; i++) {
2568 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2569 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2570 ring_nr, i, bp->rx_ring_size);
2571 break;
2572 }
2573 prod = NEXT_RX(prod);
2574 }
2575 rxr->rx_prod = prod;
2576 ring->fw_ring_id = INVALID_HW_RING_ID;
2577
2578 ring = &rxr->rx_agg_ring_struct;
2579 ring->fw_ring_id = INVALID_HW_RING_ID;
2580
2581 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2582 return 0;
2583
2584 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2585 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2586
2587 bnxt_init_rxbd_pages(ring, type);
2588
2589 prod = rxr->rx_agg_prod;
2590 for (i = 0; i < bp->rx_agg_ring_size; i++) {
2591 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2592 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2593 ring_nr, i, bp->rx_ring_size);
2594 break;
2595 }
2596 prod = NEXT_RX_AGG(prod);
2597 }
2598 rxr->rx_agg_prod = prod;
2599
2600 if (bp->flags & BNXT_FLAG_TPA) {
2601 if (rxr->rx_tpa) {
2602 u8 *data;
2603 dma_addr_t mapping;
2604
2605 for (i = 0; i < MAX_TPA; i++) {
2606 data = __bnxt_alloc_rx_data(bp, &mapping,
2607 GFP_KERNEL);
2608 if (!data)
2609 return -ENOMEM;
2610
2611 rxr->rx_tpa[i].data = data;
2612 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2613 rxr->rx_tpa[i].mapping = mapping;
2614 }
2615 } else {
2616 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2617 return -ENOMEM;
2618 }
2619 }
2620
2621 return 0;
2622 }
2623
2624 static void bnxt_init_cp_rings(struct bnxt *bp)
2625 {
2626 int i;
2627
2628 for (i = 0; i < bp->cp_nr_rings; i++) {
2629 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2630 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2631
2632 ring->fw_ring_id = INVALID_HW_RING_ID;
2633 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2634 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2635 }
2636 }
2637
2638 static int bnxt_init_rx_rings(struct bnxt *bp)
2639 {
2640 int i, rc = 0;
2641
2642 if (BNXT_RX_PAGE_MODE(bp)) {
2643 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2644 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
2645 } else {
2646 bp->rx_offset = BNXT_RX_OFFSET;
2647 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2648 }
2649
2650 for (i = 0; i < bp->rx_nr_rings; i++) {
2651 rc = bnxt_init_one_rx_ring(bp, i);
2652 if (rc)
2653 break;
2654 }
2655
2656 return rc;
2657 }
2658
2659 static int bnxt_init_tx_rings(struct bnxt *bp)
2660 {
2661 u16 i;
2662
2663 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2664 MAX_SKB_FRAGS + 1);
2665
2666 for (i = 0; i < bp->tx_nr_rings; i++) {
2667 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2668 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2669
2670 ring->fw_ring_id = INVALID_HW_RING_ID;
2671 }
2672
2673 return 0;
2674 }
2675
2676 static void bnxt_free_ring_grps(struct bnxt *bp)
2677 {
2678 kfree(bp->grp_info);
2679 bp->grp_info = NULL;
2680 }
2681
2682 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2683 {
2684 int i;
2685
2686 if (irq_re_init) {
2687 bp->grp_info = kcalloc(bp->cp_nr_rings,
2688 sizeof(struct bnxt_ring_grp_info),
2689 GFP_KERNEL);
2690 if (!bp->grp_info)
2691 return -ENOMEM;
2692 }
2693 for (i = 0; i < bp->cp_nr_rings; i++) {
2694 if (irq_re_init)
2695 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2696 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2697 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2698 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2699 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2700 }
2701 return 0;
2702 }
2703
2704 static void bnxt_free_vnics(struct bnxt *bp)
2705 {
2706 kfree(bp->vnic_info);
2707 bp->vnic_info = NULL;
2708 bp->nr_vnics = 0;
2709 }
2710
2711 static int bnxt_alloc_vnics(struct bnxt *bp)
2712 {
2713 int num_vnics = 1;
2714
2715 #ifdef CONFIG_RFS_ACCEL
2716 if (bp->flags & BNXT_FLAG_RFS)
2717 num_vnics += bp->rx_nr_rings;
2718 #endif
2719
2720 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2721 num_vnics++;
2722
2723 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2724 GFP_KERNEL);
2725 if (!bp->vnic_info)
2726 return -ENOMEM;
2727
2728 bp->nr_vnics = num_vnics;
2729 return 0;
2730 }
2731
2732 static void bnxt_init_vnics(struct bnxt *bp)
2733 {
2734 int i;
2735
2736 for (i = 0; i < bp->nr_vnics; i++) {
2737 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2738
2739 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2740 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2741 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
2742 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2743
2744 if (bp->vnic_info[i].rss_hash_key) {
2745 if (i == 0)
2746 prandom_bytes(vnic->rss_hash_key,
2747 HW_HASH_KEY_SIZE);
2748 else
2749 memcpy(vnic->rss_hash_key,
2750 bp->vnic_info[0].rss_hash_key,
2751 HW_HASH_KEY_SIZE);
2752 }
2753 }
2754 }
2755
2756 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2757 {
2758 int pages;
2759
2760 pages = ring_size / desc_per_pg;
2761
2762 if (!pages)
2763 return 1;
2764
2765 pages++;
2766
2767 while (pages & (pages - 1))
2768 pages++;
2769
2770 return pages;
2771 }
2772
2773 void bnxt_set_tpa_flags(struct bnxt *bp)
2774 {
2775 bp->flags &= ~BNXT_FLAG_TPA;
2776 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
2777 return;
2778 if (bp->dev->features & NETIF_F_LRO)
2779 bp->flags |= BNXT_FLAG_LRO;
2780 else if (bp->dev->features & NETIF_F_GRO_HW)
2781 bp->flags |= BNXT_FLAG_GRO;
2782 }
2783
2784 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2785 * be set on entry.
2786 */
2787 void bnxt_set_ring_params(struct bnxt *bp)
2788 {
2789 u32 ring_size, rx_size, rx_space;
2790 u32 agg_factor = 0, agg_ring_size = 0;
2791
2792 /* 8 for CRC and VLAN */
2793 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2794
2795 rx_space = rx_size + NET_SKB_PAD +
2796 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2797
2798 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2799 ring_size = bp->rx_ring_size;
2800 bp->rx_agg_ring_size = 0;
2801 bp->rx_agg_nr_pages = 0;
2802
2803 if (bp->flags & BNXT_FLAG_TPA)
2804 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
2805
2806 bp->flags &= ~BNXT_FLAG_JUMBO;
2807 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
2808 u32 jumbo_factor;
2809
2810 bp->flags |= BNXT_FLAG_JUMBO;
2811 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2812 if (jumbo_factor > agg_factor)
2813 agg_factor = jumbo_factor;
2814 }
2815 agg_ring_size = ring_size * agg_factor;
2816
2817 if (agg_ring_size) {
2818 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2819 RX_DESC_CNT);
2820 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2821 u32 tmp = agg_ring_size;
2822
2823 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2824 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2825 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2826 tmp, agg_ring_size);
2827 }
2828 bp->rx_agg_ring_size = agg_ring_size;
2829 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2830 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2831 rx_space = rx_size + NET_SKB_PAD +
2832 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2833 }
2834
2835 bp->rx_buf_use_size = rx_size;
2836 bp->rx_buf_size = rx_space;
2837
2838 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2839 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2840
2841 ring_size = bp->tx_ring_size;
2842 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2843 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2844
2845 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2846 bp->cp_ring_size = ring_size;
2847
2848 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2849 if (bp->cp_nr_pages > MAX_CP_PAGES) {
2850 bp->cp_nr_pages = MAX_CP_PAGES;
2851 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2852 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2853 ring_size, bp->cp_ring_size);
2854 }
2855 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2856 bp->cp_ring_mask = bp->cp_bit - 1;
2857 }
2858
2859 /* Changing allocation mode of RX rings.
2860 * TODO: Update when extending xdp_rxq_info to support allocation modes.
2861 */
2862 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
2863 {
2864 if (page_mode) {
2865 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
2866 return -EOPNOTSUPP;
2867 bp->dev->max_mtu =
2868 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
2869 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
2870 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
2871 bp->rx_dir = DMA_BIDIRECTIONAL;
2872 bp->rx_skb_func = bnxt_rx_page_skb;
2873 /* Disable LRO or GRO_HW */
2874 netdev_update_features(bp->dev);
2875 } else {
2876 bp->dev->max_mtu = bp->max_mtu;
2877 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
2878 bp->rx_dir = DMA_FROM_DEVICE;
2879 bp->rx_skb_func = bnxt_rx_skb;
2880 }
2881 return 0;
2882 }
2883
2884 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2885 {
2886 int i;
2887 struct bnxt_vnic_info *vnic;
2888 struct pci_dev *pdev = bp->pdev;
2889
2890 if (!bp->vnic_info)
2891 return;
2892
2893 for (i = 0; i < bp->nr_vnics; i++) {
2894 vnic = &bp->vnic_info[i];
2895
2896 kfree(vnic->fw_grp_ids);
2897 vnic->fw_grp_ids = NULL;
2898
2899 kfree(vnic->uc_list);
2900 vnic->uc_list = NULL;
2901
2902 if (vnic->mc_list) {
2903 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2904 vnic->mc_list, vnic->mc_list_mapping);
2905 vnic->mc_list = NULL;
2906 }
2907
2908 if (vnic->rss_table) {
2909 dma_free_coherent(&pdev->dev, PAGE_SIZE,
2910 vnic->rss_table,
2911 vnic->rss_table_dma_addr);
2912 vnic->rss_table = NULL;
2913 }
2914
2915 vnic->rss_hash_key = NULL;
2916 vnic->flags = 0;
2917 }
2918 }
2919
2920 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2921 {
2922 int i, rc = 0, size;
2923 struct bnxt_vnic_info *vnic;
2924 struct pci_dev *pdev = bp->pdev;
2925 int max_rings;
2926
2927 for (i = 0; i < bp->nr_vnics; i++) {
2928 vnic = &bp->vnic_info[i];
2929
2930 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2931 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2932
2933 if (mem_size > 0) {
2934 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2935 if (!vnic->uc_list) {
2936 rc = -ENOMEM;
2937 goto out;
2938 }
2939 }
2940 }
2941
2942 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2943 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2944 vnic->mc_list =
2945 dma_alloc_coherent(&pdev->dev,
2946 vnic->mc_list_size,
2947 &vnic->mc_list_mapping,
2948 GFP_KERNEL);
2949 if (!vnic->mc_list) {
2950 rc = -ENOMEM;
2951 goto out;
2952 }
2953 }
2954
2955 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2956 max_rings = bp->rx_nr_rings;
2957 else
2958 max_rings = 1;
2959
2960 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2961 if (!vnic->fw_grp_ids) {
2962 rc = -ENOMEM;
2963 goto out;
2964 }
2965
2966 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
2967 !(vnic->flags & BNXT_VNIC_RSS_FLAG))
2968 continue;
2969
2970 /* Allocate rss table and hash key */
2971 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2972 &vnic->rss_table_dma_addr,
2973 GFP_KERNEL);
2974 if (!vnic->rss_table) {
2975 rc = -ENOMEM;
2976 goto out;
2977 }
2978
2979 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2980
2981 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2982 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2983 }
2984 return 0;
2985
2986 out:
2987 return rc;
2988 }
2989
2990 static void bnxt_free_hwrm_resources(struct bnxt *bp)
2991 {
2992 struct pci_dev *pdev = bp->pdev;
2993
2994 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2995 bp->hwrm_cmd_resp_dma_addr);
2996
2997 bp->hwrm_cmd_resp_addr = NULL;
2998 if (bp->hwrm_dbg_resp_addr) {
2999 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
3000 bp->hwrm_dbg_resp_addr,
3001 bp->hwrm_dbg_resp_dma_addr);
3002
3003 bp->hwrm_dbg_resp_addr = NULL;
3004 }
3005 }
3006
3007 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3008 {
3009 struct pci_dev *pdev = bp->pdev;
3010
3011 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3012 &bp->hwrm_cmd_resp_dma_addr,
3013 GFP_KERNEL);
3014 if (!bp->hwrm_cmd_resp_addr)
3015 return -ENOMEM;
3016 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
3017 HWRM_DBG_REG_BUF_SIZE,
3018 &bp->hwrm_dbg_resp_dma_addr,
3019 GFP_KERNEL);
3020 if (!bp->hwrm_dbg_resp_addr)
3021 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
3022
3023 return 0;
3024 }
3025
3026 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3027 {
3028 if (bp->hwrm_short_cmd_req_addr) {
3029 struct pci_dev *pdev = bp->pdev;
3030
3031 dma_free_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
3032 bp->hwrm_short_cmd_req_addr,
3033 bp->hwrm_short_cmd_req_dma_addr);
3034 bp->hwrm_short_cmd_req_addr = NULL;
3035 }
3036 }
3037
3038 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3039 {
3040 struct pci_dev *pdev = bp->pdev;
3041
3042 bp->hwrm_short_cmd_req_addr =
3043 dma_alloc_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
3044 &bp->hwrm_short_cmd_req_dma_addr,
3045 GFP_KERNEL);
3046 if (!bp->hwrm_short_cmd_req_addr)
3047 return -ENOMEM;
3048
3049 return 0;
3050 }
3051
3052 static void bnxt_free_stats(struct bnxt *bp)
3053 {
3054 u32 size, i;
3055 struct pci_dev *pdev = bp->pdev;
3056
3057 if (bp->hw_rx_port_stats) {
3058 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3059 bp->hw_rx_port_stats,
3060 bp->hw_rx_port_stats_map);
3061 bp->hw_rx_port_stats = NULL;
3062 bp->flags &= ~BNXT_FLAG_PORT_STATS;
3063 }
3064
3065 if (!bp->bnapi)
3066 return;
3067
3068 size = sizeof(struct ctx_hw_stats);
3069
3070 for (i = 0; i < bp->cp_nr_rings; i++) {
3071 struct bnxt_napi *bnapi = bp->bnapi[i];
3072 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3073
3074 if (cpr->hw_stats) {
3075 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3076 cpr->hw_stats_map);
3077 cpr->hw_stats = NULL;
3078 }
3079 }
3080 }
3081
3082 static int bnxt_alloc_stats(struct bnxt *bp)
3083 {
3084 u32 size, i;
3085 struct pci_dev *pdev = bp->pdev;
3086
3087 size = sizeof(struct ctx_hw_stats);
3088
3089 for (i = 0; i < bp->cp_nr_rings; i++) {
3090 struct bnxt_napi *bnapi = bp->bnapi[i];
3091 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3092
3093 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3094 &cpr->hw_stats_map,
3095 GFP_KERNEL);
3096 if (!cpr->hw_stats)
3097 return -ENOMEM;
3098
3099 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3100 }
3101
3102 if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
3103 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3104 sizeof(struct tx_port_stats) + 1024;
3105
3106 bp->hw_rx_port_stats =
3107 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3108 &bp->hw_rx_port_stats_map,
3109 GFP_KERNEL);
3110 if (!bp->hw_rx_port_stats)
3111 return -ENOMEM;
3112
3113 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
3114 512;
3115 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3116 sizeof(struct rx_port_stats) + 512;
3117 bp->flags |= BNXT_FLAG_PORT_STATS;
3118 }
3119 return 0;
3120 }
3121
3122 static void bnxt_clear_ring_indices(struct bnxt *bp)
3123 {
3124 int i;
3125
3126 if (!bp->bnapi)
3127 return;
3128
3129 for (i = 0; i < bp->cp_nr_rings; i++) {
3130 struct bnxt_napi *bnapi = bp->bnapi[i];
3131 struct bnxt_cp_ring_info *cpr;
3132 struct bnxt_rx_ring_info *rxr;
3133 struct bnxt_tx_ring_info *txr;
3134
3135 if (!bnapi)
3136 continue;
3137
3138 cpr = &bnapi->cp_ring;
3139 cpr->cp_raw_cons = 0;
3140
3141 txr = bnapi->tx_ring;
3142 if (txr) {
3143 txr->tx_prod = 0;
3144 txr->tx_cons = 0;
3145 }
3146
3147 rxr = bnapi->rx_ring;
3148 if (rxr) {
3149 rxr->rx_prod = 0;
3150 rxr->rx_agg_prod = 0;
3151 rxr->rx_sw_agg_prod = 0;
3152 rxr->rx_next_cons = 0;
3153 }
3154 }
3155 }
3156
3157 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3158 {
3159 #ifdef CONFIG_RFS_ACCEL
3160 int i;
3161
3162 /* Under rtnl_lock and all our NAPIs have been disabled. It's
3163 * safe to delete the hash table.
3164 */
3165 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3166 struct hlist_head *head;
3167 struct hlist_node *tmp;
3168 struct bnxt_ntuple_filter *fltr;
3169
3170 head = &bp->ntp_fltr_hash_tbl[i];
3171 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3172 hlist_del(&fltr->hash);
3173 kfree(fltr);
3174 }
3175 }
3176 if (irq_reinit) {
3177 kfree(bp->ntp_fltr_bmap);
3178 bp->ntp_fltr_bmap = NULL;
3179 }
3180 bp->ntp_fltr_count = 0;
3181 #endif
3182 }
3183
3184 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3185 {
3186 #ifdef CONFIG_RFS_ACCEL
3187 int i, rc = 0;
3188
3189 if (!(bp->flags & BNXT_FLAG_RFS))
3190 return 0;
3191
3192 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3193 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3194
3195 bp->ntp_fltr_count = 0;
3196 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3197 sizeof(long),
3198 GFP_KERNEL);
3199
3200 if (!bp->ntp_fltr_bmap)
3201 rc = -ENOMEM;
3202
3203 return rc;
3204 #else
3205 return 0;
3206 #endif
3207 }
3208
3209 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3210 {
3211 bnxt_free_vnic_attributes(bp);
3212 bnxt_free_tx_rings(bp);
3213 bnxt_free_rx_rings(bp);
3214 bnxt_free_cp_rings(bp);
3215 bnxt_free_ntp_fltrs(bp, irq_re_init);
3216 if (irq_re_init) {
3217 bnxt_free_stats(bp);
3218 bnxt_free_ring_grps(bp);
3219 bnxt_free_vnics(bp);
3220 kfree(bp->tx_ring_map);
3221 bp->tx_ring_map = NULL;
3222 kfree(bp->tx_ring);
3223 bp->tx_ring = NULL;
3224 kfree(bp->rx_ring);
3225 bp->rx_ring = NULL;
3226 kfree(bp->bnapi);
3227 bp->bnapi = NULL;
3228 } else {
3229 bnxt_clear_ring_indices(bp);
3230 }
3231 }
3232
3233 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3234 {
3235 int i, j, rc, size, arr_size;
3236 void *bnapi;
3237
3238 if (irq_re_init) {
3239 /* Allocate bnapi mem pointer array and mem block for
3240 * all queues
3241 */
3242 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3243 bp->cp_nr_rings);
3244 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3245 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3246 if (!bnapi)
3247 return -ENOMEM;
3248
3249 bp->bnapi = bnapi;
3250 bnapi += arr_size;
3251 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3252 bp->bnapi[i] = bnapi;
3253 bp->bnapi[i]->index = i;
3254 bp->bnapi[i]->bp = bp;
3255 }
3256
3257 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3258 sizeof(struct bnxt_rx_ring_info),
3259 GFP_KERNEL);
3260 if (!bp->rx_ring)
3261 return -ENOMEM;
3262
3263 for (i = 0; i < bp->rx_nr_rings; i++) {
3264 bp->rx_ring[i].bnapi = bp->bnapi[i];
3265 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3266 }
3267
3268 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3269 sizeof(struct bnxt_tx_ring_info),
3270 GFP_KERNEL);
3271 if (!bp->tx_ring)
3272 return -ENOMEM;
3273
3274 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3275 GFP_KERNEL);
3276
3277 if (!bp->tx_ring_map)
3278 return -ENOMEM;
3279
3280 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3281 j = 0;
3282 else
3283 j = bp->rx_nr_rings;
3284
3285 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3286 bp->tx_ring[i].bnapi = bp->bnapi[j];
3287 bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
3288 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3289 if (i >= bp->tx_nr_rings_xdp) {
3290 bp->tx_ring[i].txq_index = i -
3291 bp->tx_nr_rings_xdp;
3292 bp->bnapi[j]->tx_int = bnxt_tx_int;
3293 } else {
3294 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3295 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3296 }
3297 }
3298
3299 rc = bnxt_alloc_stats(bp);
3300 if (rc)
3301 goto alloc_mem_err;
3302
3303 rc = bnxt_alloc_ntp_fltrs(bp);
3304 if (rc)
3305 goto alloc_mem_err;
3306
3307 rc = bnxt_alloc_vnics(bp);
3308 if (rc)
3309 goto alloc_mem_err;
3310 }
3311
3312 bnxt_init_ring_struct(bp);
3313
3314 rc = bnxt_alloc_rx_rings(bp);
3315 if (rc)
3316 goto alloc_mem_err;
3317
3318 rc = bnxt_alloc_tx_rings(bp);
3319 if (rc)
3320 goto alloc_mem_err;
3321
3322 rc = bnxt_alloc_cp_rings(bp);
3323 if (rc)
3324 goto alloc_mem_err;
3325
3326 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3327 BNXT_VNIC_UCAST_FLAG;
3328 rc = bnxt_alloc_vnic_attributes(bp);
3329 if (rc)
3330 goto alloc_mem_err;
3331 return 0;
3332
3333 alloc_mem_err:
3334 bnxt_free_mem(bp, true);
3335 return rc;
3336 }
3337
3338 static void bnxt_disable_int(struct bnxt *bp)
3339 {
3340 int i;
3341
3342 if (!bp->bnapi)
3343 return;
3344
3345 for (i = 0; i < bp->cp_nr_rings; i++) {
3346 struct bnxt_napi *bnapi = bp->bnapi[i];
3347 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3348 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3349
3350 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3351 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3352 }
3353 }
3354
3355 static void bnxt_disable_int_sync(struct bnxt *bp)
3356 {
3357 int i;
3358
3359 atomic_inc(&bp->intr_sem);
3360
3361 bnxt_disable_int(bp);
3362 for (i = 0; i < bp->cp_nr_rings; i++)
3363 synchronize_irq(bp->irq_tbl[i].vector);
3364 }
3365
3366 static void bnxt_enable_int(struct bnxt *bp)
3367 {
3368 int i;
3369
3370 atomic_set(&bp->intr_sem, 0);
3371 for (i = 0; i < bp->cp_nr_rings; i++) {
3372 struct bnxt_napi *bnapi = bp->bnapi[i];
3373 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3374
3375 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
3376 }
3377 }
3378
3379 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3380 u16 cmpl_ring, u16 target_id)
3381 {
3382 struct input *req = request;
3383
3384 req->req_type = cpu_to_le16(req_type);
3385 req->cmpl_ring = cpu_to_le16(cmpl_ring);
3386 req->target_id = cpu_to_le16(target_id);
3387 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3388 }
3389
3390 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3391 int timeout, bool silent)
3392 {
3393 int i, intr_process, rc, tmo_count;
3394 struct input *req = msg;
3395 u32 *data = msg;
3396 __le32 *resp_len, *valid;
3397 u16 cp_ring_id, len = 0;
3398 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3399 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
3400 struct hwrm_short_input short_input = {0};
3401
3402 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
3403 memset(resp, 0, PAGE_SIZE);
3404 cp_ring_id = le16_to_cpu(req->cmpl_ring);
3405 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3406
3407 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
3408 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3409
3410 memcpy(short_cmd_req, req, msg_len);
3411 memset(short_cmd_req + msg_len, 0, BNXT_HWRM_MAX_REQ_LEN -
3412 msg_len);
3413
3414 short_input.req_type = req->req_type;
3415 short_input.signature =
3416 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3417 short_input.size = cpu_to_le16(msg_len);
3418 short_input.req_addr =
3419 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3420
3421 data = (u32 *)&short_input;
3422 msg_len = sizeof(short_input);
3423
3424 /* Sync memory write before updating doorbell */
3425 wmb();
3426
3427 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3428 }
3429
3430 /* Write request msg to hwrm channel */
3431 __iowrite32_copy(bp->bar0, data, msg_len / 4);
3432
3433 for (i = msg_len; i < max_req_len; i += 4)
3434 writel(0, bp->bar0 + i);
3435
3436 /* currently supports only one outstanding message */
3437 if (intr_process)
3438 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3439
3440 /* Ring channel doorbell */
3441 writel(1, bp->bar0 + 0x100);
3442
3443 if (!timeout)
3444 timeout = DFLT_HWRM_CMD_TIMEOUT;
3445
3446 i = 0;
3447 tmo_count = timeout * 40;
3448 if (intr_process) {
3449 /* Wait until hwrm response cmpl interrupt is processed */
3450 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
3451 i++ < tmo_count) {
3452 usleep_range(25, 40);
3453 }
3454
3455 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3456 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3457 le16_to_cpu(req->req_type));
3458 return -1;
3459 }
3460 } else {
3461 /* Check if response len is updated */
3462 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
3463 for (i = 0; i < tmo_count; i++) {
3464 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3465 HWRM_RESP_LEN_SFT;
3466 if (len)
3467 break;
3468 usleep_range(25, 40);
3469 }
3470
3471 if (i >= tmo_count) {
3472 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3473 timeout, le16_to_cpu(req->req_type),
3474 le16_to_cpu(req->seq_id), len);
3475 return -1;
3476 }
3477
3478 /* Last word of resp contains valid bit */
3479 valid = bp->hwrm_cmd_resp_addr + len - 4;
3480 for (i = 0; i < 5; i++) {
3481 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
3482 break;
3483 udelay(1);
3484 }
3485
3486 if (i >= 5) {
3487 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3488 timeout, le16_to_cpu(req->req_type),
3489 le16_to_cpu(req->seq_id), len, *valid);
3490 return -1;
3491 }
3492 }
3493
3494 rc = le16_to_cpu(resp->error_code);
3495 if (rc && !silent)
3496 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3497 le16_to_cpu(resp->req_type),
3498 le16_to_cpu(resp->seq_id), rc);
3499 return rc;
3500 }
3501
3502 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3503 {
3504 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3505 }
3506
3507 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3508 int timeout)
3509 {
3510 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3511 }
3512
3513 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3514 {
3515 int rc;
3516
3517 mutex_lock(&bp->hwrm_cmd_lock);
3518 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3519 mutex_unlock(&bp->hwrm_cmd_lock);
3520 return rc;
3521 }
3522
3523 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3524 int timeout)
3525 {
3526 int rc;
3527
3528 mutex_lock(&bp->hwrm_cmd_lock);
3529 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3530 mutex_unlock(&bp->hwrm_cmd_lock);
3531 return rc;
3532 }
3533
3534 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3535 int bmap_size)
3536 {
3537 struct hwrm_func_drv_rgtr_input req = {0};
3538 DECLARE_BITMAP(async_events_bmap, 256);
3539 u32 *events = (u32 *)async_events_bmap;
3540 int i;
3541
3542 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3543
3544 req.enables =
3545 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3546
3547 memset(async_events_bmap, 0, sizeof(async_events_bmap));
3548 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3549 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3550
3551 if (bmap && bmap_size) {
3552 for (i = 0; i < bmap_size; i++) {
3553 if (test_bit(i, bmap))
3554 __set_bit(i, async_events_bmap);
3555 }
3556 }
3557
3558 for (i = 0; i < 8; i++)
3559 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3560
3561 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3562 }
3563
3564 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3565 {
3566 struct hwrm_func_drv_rgtr_input req = {0};
3567
3568 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3569
3570 req.enables =
3571 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3572 FUNC_DRV_RGTR_REQ_ENABLES_VER);
3573
3574 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
3575 req.ver_maj = DRV_VER_MAJ;
3576 req.ver_min = DRV_VER_MIN;
3577 req.ver_upd = DRV_VER_UPD;
3578
3579 if (BNXT_PF(bp)) {
3580 u32 data[8];
3581 int i;
3582
3583 memset(data, 0, sizeof(data));
3584 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
3585 u16 cmd = bnxt_vf_req_snif[i];
3586 unsigned int bit, idx;
3587
3588 idx = cmd / 32;
3589 bit = cmd % 32;
3590 data[idx] |= 1 << bit;
3591 }
3592
3593 for (i = 0; i < 8; i++)
3594 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3595
3596 req.enables |=
3597 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3598 }
3599
3600 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3601 }
3602
3603 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3604 {
3605 struct hwrm_func_drv_unrgtr_input req = {0};
3606
3607 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3608 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3609 }
3610
3611 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3612 {
3613 u32 rc = 0;
3614 struct hwrm_tunnel_dst_port_free_input req = {0};
3615
3616 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3617 req.tunnel_type = tunnel_type;
3618
3619 switch (tunnel_type) {
3620 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3621 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3622 break;
3623 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3624 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3625 break;
3626 default:
3627 break;
3628 }
3629
3630 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3631 if (rc)
3632 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3633 rc);
3634 return rc;
3635 }
3636
3637 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3638 u8 tunnel_type)
3639 {
3640 u32 rc = 0;
3641 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3642 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3643
3644 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3645
3646 req.tunnel_type = tunnel_type;
3647 req.tunnel_dst_port_val = port;
3648
3649 mutex_lock(&bp->hwrm_cmd_lock);
3650 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3651 if (rc) {
3652 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3653 rc);
3654 goto err_out;
3655 }
3656
3657 switch (tunnel_type) {
3658 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
3659 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3660 break;
3661 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
3662 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
3663 break;
3664 default:
3665 break;
3666 }
3667
3668 err_out:
3669 mutex_unlock(&bp->hwrm_cmd_lock);
3670 return rc;
3671 }
3672
3673 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3674 {
3675 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3676 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3677
3678 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
3679 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3680
3681 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3682 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3683 req.mask = cpu_to_le32(vnic->rx_mask);
3684 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3685 }
3686
3687 #ifdef CONFIG_RFS_ACCEL
3688 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3689 struct bnxt_ntuple_filter *fltr)
3690 {
3691 struct hwrm_cfa_ntuple_filter_free_input req = {0};
3692
3693 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3694 req.ntuple_filter_id = fltr->filter_id;
3695 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3696 }
3697
3698 #define BNXT_NTP_FLTR_FLAGS \
3699 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
3700 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
3701 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
3702 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
3703 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
3704 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
3705 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
3706 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
3707 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
3708 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
3709 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
3710 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
3711 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
3712 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3713
3714 #define BNXT_NTP_TUNNEL_FLTR_FLAG \
3715 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
3716
3717 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3718 struct bnxt_ntuple_filter *fltr)
3719 {
3720 int rc = 0;
3721 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3722 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3723 bp->hwrm_cmd_resp_addr;
3724 struct flow_keys *keys = &fltr->fkeys;
3725 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3726
3727 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
3728 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
3729
3730 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3731
3732 req.ethertype = htons(ETH_P_IP);
3733 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
3734 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
3735 req.ip_protocol = keys->basic.ip_proto;
3736
3737 if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
3738 int i;
3739
3740 req.ethertype = htons(ETH_P_IPV6);
3741 req.ip_addr_type =
3742 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
3743 *(struct in6_addr *)&req.src_ipaddr[0] =
3744 keys->addrs.v6addrs.src;
3745 *(struct in6_addr *)&req.dst_ipaddr[0] =
3746 keys->addrs.v6addrs.dst;
3747 for (i = 0; i < 4; i++) {
3748 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3749 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3750 }
3751 } else {
3752 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3753 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3754 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3755 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3756 }
3757 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
3758 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
3759 req.tunnel_type =
3760 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
3761 }
3762
3763 req.src_port = keys->ports.src;
3764 req.src_port_mask = cpu_to_be16(0xffff);
3765 req.dst_port = keys->ports.dst;
3766 req.dst_port_mask = cpu_to_be16(0xffff);
3767
3768 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
3769 mutex_lock(&bp->hwrm_cmd_lock);
3770 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3771 if (!rc)
3772 fltr->filter_id = resp->ntuple_filter_id;
3773 mutex_unlock(&bp->hwrm_cmd_lock);
3774 return rc;
3775 }
3776 #endif
3777
3778 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3779 u8 *mac_addr)
3780 {
3781 u32 rc = 0;
3782 struct hwrm_cfa_l2_filter_alloc_input req = {0};
3783 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3784
3785 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
3786 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3787 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3788 req.flags |=
3789 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
3790 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
3791 req.enables =
3792 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
3793 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
3794 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3795 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3796 req.l2_addr_mask[0] = 0xff;
3797 req.l2_addr_mask[1] = 0xff;
3798 req.l2_addr_mask[2] = 0xff;
3799 req.l2_addr_mask[3] = 0xff;
3800 req.l2_addr_mask[4] = 0xff;
3801 req.l2_addr_mask[5] = 0xff;
3802
3803 mutex_lock(&bp->hwrm_cmd_lock);
3804 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3805 if (!rc)
3806 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3807 resp->l2_filter_id;
3808 mutex_unlock(&bp->hwrm_cmd_lock);
3809 return rc;
3810 }
3811
3812 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3813 {
3814 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3815 int rc = 0;
3816
3817 /* Any associated ntuple filters will also be cleared by firmware. */
3818 mutex_lock(&bp->hwrm_cmd_lock);
3819 for (i = 0; i < num_of_vnics; i++) {
3820 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3821
3822 for (j = 0; j < vnic->uc_filter_count; j++) {
3823 struct hwrm_cfa_l2_filter_free_input req = {0};
3824
3825 bnxt_hwrm_cmd_hdr_init(bp, &req,
3826 HWRM_CFA_L2_FILTER_FREE, -1, -1);
3827
3828 req.l2_filter_id = vnic->fw_l2_filter_id[j];
3829
3830 rc = _hwrm_send_message(bp, &req, sizeof(req),
3831 HWRM_CMD_TIMEOUT);
3832 }
3833 vnic->uc_filter_count = 0;
3834 }
3835 mutex_unlock(&bp->hwrm_cmd_lock);
3836
3837 return rc;
3838 }
3839
3840 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3841 {
3842 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3843 struct hwrm_vnic_tpa_cfg_input req = {0};
3844
3845 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3846
3847 if (tpa_flags) {
3848 u16 mss = bp->dev->mtu - 40;
3849 u32 nsegs, n, segs = 0, flags;
3850
3851 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3852 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3853 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3854 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3855 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3856 if (tpa_flags & BNXT_FLAG_GRO)
3857 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3858
3859 req.flags = cpu_to_le32(flags);
3860
3861 req.enables =
3862 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
3863 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3864 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
3865
3866 /* Number of segs are log2 units, and first packet is not
3867 * included as part of this units.
3868 */
3869 if (mss <= BNXT_RX_PAGE_SIZE) {
3870 n = BNXT_RX_PAGE_SIZE / mss;
3871 nsegs = (MAX_SKB_FRAGS - 1) * n;
3872 } else {
3873 n = mss / BNXT_RX_PAGE_SIZE;
3874 if (mss & (BNXT_RX_PAGE_SIZE - 1))
3875 n++;
3876 nsegs = (MAX_SKB_FRAGS - n) / n;
3877 }
3878
3879 segs = ilog2(nsegs);
3880 req.max_agg_segs = cpu_to_le16(segs);
3881 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
3882
3883 req.min_agg_len = cpu_to_le32(512);
3884 }
3885 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3886
3887 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3888 }
3889
3890 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3891 {
3892 u32 i, j, max_rings;
3893 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3894 struct hwrm_vnic_rss_cfg_input req = {0};
3895
3896 if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
3897 return 0;
3898
3899 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3900 if (set_rss) {
3901 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
3902 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
3903 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3904 max_rings = bp->rx_nr_rings - 1;
3905 else
3906 max_rings = bp->rx_nr_rings;
3907 } else {
3908 max_rings = 1;
3909 }
3910
3911 /* Fill the RSS indirection table with ring group ids */
3912 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3913 if (j == max_rings)
3914 j = 0;
3915 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3916 }
3917
3918 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3919 req.hash_key_tbl_addr =
3920 cpu_to_le64(vnic->rss_hash_key_dma_addr);
3921 }
3922 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3923 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3924 }
3925
3926 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3927 {
3928 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3929 struct hwrm_vnic_plcmodes_cfg_input req = {0};
3930
3931 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3932 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3933 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3934 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3935 req.enables =
3936 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3937 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3938 /* thresholds not implemented in firmware yet */
3939 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3940 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3941 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3942 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3943 }
3944
3945 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
3946 u16 ctx_idx)
3947 {
3948 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3949
3950 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3951 req.rss_cos_lb_ctx_id =
3952 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
3953
3954 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3955 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
3956 }
3957
3958 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3959 {
3960 int i, j;
3961
3962 for (i = 0; i < bp->nr_vnics; i++) {
3963 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3964
3965 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
3966 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
3967 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
3968 }
3969 }
3970 bp->rsscos_nr_ctxs = 0;
3971 }
3972
3973 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
3974 {
3975 int rc;
3976 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3977 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3978 bp->hwrm_cmd_resp_addr;
3979
3980 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3981 -1);
3982
3983 mutex_lock(&bp->hwrm_cmd_lock);
3984 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3985 if (!rc)
3986 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
3987 le16_to_cpu(resp->rss_cos_lb_ctx_id);
3988 mutex_unlock(&bp->hwrm_cmd_lock);
3989
3990 return rc;
3991 }
3992
3993 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3994 {
3995 unsigned int ring = 0, grp_idx;
3996 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3997 struct hwrm_vnic_cfg_input req = {0};
3998 u16 def_vlan = 0;
3999
4000 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
4001
4002 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
4003 /* Only RSS support for now TBD: COS & LB */
4004 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
4005 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4006 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4007 VNIC_CFG_REQ_ENABLES_MRU);
4008 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
4009 req.rss_rule =
4010 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
4011 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4012 VNIC_CFG_REQ_ENABLES_MRU);
4013 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
4014 } else {
4015 req.rss_rule = cpu_to_le16(0xffff);
4016 }
4017
4018 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
4019 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
4020 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
4021 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
4022 } else {
4023 req.cos_rule = cpu_to_le16(0xffff);
4024 }
4025
4026 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
4027 ring = 0;
4028 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
4029 ring = vnic_id - 1;
4030 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
4031 ring = bp->rx_nr_rings - 1;
4032
4033 grp_idx = bp->rx_ring[ring].bnapi->index;
4034 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4035 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
4036
4037 req.lb_rule = cpu_to_le16(0xffff);
4038 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4039 VLAN_HLEN);
4040
4041 #ifdef CONFIG_BNXT_SRIOV
4042 if (BNXT_VF(bp))
4043 def_vlan = bp->vf.vlan;
4044 #endif
4045 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
4046 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
4047 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
4048 req.flags |=
4049 cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE);
4050
4051 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4052 }
4053
4054 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4055 {
4056 u32 rc = 0;
4057
4058 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4059 struct hwrm_vnic_free_input req = {0};
4060
4061 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
4062 req.vnic_id =
4063 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4064
4065 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4066 if (rc)
4067 return rc;
4068 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4069 }
4070 return rc;
4071 }
4072
4073 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
4074 {
4075 u16 i;
4076
4077 for (i = 0; i < bp->nr_vnics; i++)
4078 bnxt_hwrm_vnic_free_one(bp, i);
4079 }
4080
4081 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4082 unsigned int start_rx_ring_idx,
4083 unsigned int nr_rings)
4084 {
4085 int rc = 0;
4086 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
4087 struct hwrm_vnic_alloc_input req = {0};
4088 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4089
4090 /* map ring groups to this vnic */
4091 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4092 grp_idx = bp->rx_ring[i].bnapi->index;
4093 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
4094 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
4095 j, nr_rings);
4096 break;
4097 }
4098 bp->vnic_info[vnic_id].fw_grp_ids[j] =
4099 bp->grp_info[grp_idx].fw_grp_id;
4100 }
4101
4102 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
4103 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
4104 if (vnic_id == 0)
4105 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4106
4107 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4108
4109 mutex_lock(&bp->hwrm_cmd_lock);
4110 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4111 if (!rc)
4112 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
4113 mutex_unlock(&bp->hwrm_cmd_lock);
4114 return rc;
4115 }
4116
4117 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4118 {
4119 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4120 struct hwrm_vnic_qcaps_input req = {0};
4121 int rc;
4122
4123 if (bp->hwrm_spec_code < 0x10600)
4124 return 0;
4125
4126 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4127 mutex_lock(&bp->hwrm_cmd_lock);
4128 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4129 if (!rc) {
4130 if (resp->flags &
4131 cpu_to_le32(VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
4132 bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
4133 }
4134 mutex_unlock(&bp->hwrm_cmd_lock);
4135 return rc;
4136 }
4137
4138 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4139 {
4140 u16 i;
4141 u32 rc = 0;
4142
4143 mutex_lock(&bp->hwrm_cmd_lock);
4144 for (i = 0; i < bp->rx_nr_rings; i++) {
4145 struct hwrm_ring_grp_alloc_input req = {0};
4146 struct hwrm_ring_grp_alloc_output *resp =
4147 bp->hwrm_cmd_resp_addr;
4148 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
4149
4150 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4151
4152 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4153 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4154 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4155 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
4156
4157 rc = _hwrm_send_message(bp, &req, sizeof(req),
4158 HWRM_CMD_TIMEOUT);
4159 if (rc)
4160 break;
4161
4162 bp->grp_info[grp_idx].fw_grp_id =
4163 le32_to_cpu(resp->ring_group_id);
4164 }
4165 mutex_unlock(&bp->hwrm_cmd_lock);
4166 return rc;
4167 }
4168
4169 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4170 {
4171 u16 i;
4172 u32 rc = 0;
4173 struct hwrm_ring_grp_free_input req = {0};
4174
4175 if (!bp->grp_info)
4176 return 0;
4177
4178 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4179
4180 mutex_lock(&bp->hwrm_cmd_lock);
4181 for (i = 0; i < bp->cp_nr_rings; i++) {
4182 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4183 continue;
4184 req.ring_group_id =
4185 cpu_to_le32(bp->grp_info[i].fw_grp_id);
4186
4187 rc = _hwrm_send_message(bp, &req, sizeof(req),
4188 HWRM_CMD_TIMEOUT);
4189 if (rc)
4190 break;
4191 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4192 }
4193 mutex_unlock(&bp->hwrm_cmd_lock);
4194 return rc;
4195 }
4196
4197 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4198 struct bnxt_ring_struct *ring,
4199 u32 ring_type, u32 map_index,
4200 u32 stats_ctx_id)
4201 {
4202 int rc = 0, err = 0;
4203 struct hwrm_ring_alloc_input req = {0};
4204 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4205 u16 ring_id;
4206
4207 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4208
4209 req.enables = 0;
4210 if (ring->nr_pages > 1) {
4211 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
4212 /* Page size is in log2 units */
4213 req.page_size = BNXT_PAGE_SHIFT;
4214 req.page_tbl_depth = 1;
4215 } else {
4216 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]);
4217 }
4218 req.fbo = 0;
4219 /* Association of ring index with doorbell index and MSIX number */
4220 req.logical_id = cpu_to_le16(map_index);
4221
4222 switch (ring_type) {
4223 case HWRM_RING_ALLOC_TX:
4224 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4225 /* Association of transmit ring with completion ring */
4226 req.cmpl_ring_id =
4227 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
4228 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4229 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
4230 req.queue_id = cpu_to_le16(ring->queue_id);
4231 break;
4232 case HWRM_RING_ALLOC_RX:
4233 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4234 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4235 break;
4236 case HWRM_RING_ALLOC_AGG:
4237 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4238 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4239 break;
4240 case HWRM_RING_ALLOC_CMPL:
4241 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
4242 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4243 if (bp->flags & BNXT_FLAG_USING_MSIX)
4244 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4245 break;
4246 default:
4247 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4248 ring_type);
4249 return -1;
4250 }
4251
4252 mutex_lock(&bp->hwrm_cmd_lock);
4253 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4254 err = le16_to_cpu(resp->error_code);
4255 ring_id = le16_to_cpu(resp->ring_id);
4256 mutex_unlock(&bp->hwrm_cmd_lock);
4257
4258 if (rc || err) {
4259 switch (ring_type) {
4260 case RING_FREE_REQ_RING_TYPE_L2_CMPL:
4261 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
4262 rc, err);
4263 return -1;
4264
4265 case RING_FREE_REQ_RING_TYPE_RX:
4266 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
4267 rc, err);
4268 return -1;
4269
4270 case RING_FREE_REQ_RING_TYPE_TX:
4271 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
4272 rc, err);
4273 return -1;
4274
4275 default:
4276 netdev_err(bp->dev, "Invalid ring\n");
4277 return -1;
4278 }
4279 }
4280 ring->fw_ring_id = ring_id;
4281 return rc;
4282 }
4283
4284 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4285 {
4286 int rc;
4287
4288 if (BNXT_PF(bp)) {
4289 struct hwrm_func_cfg_input req = {0};
4290
4291 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4292 req.fid = cpu_to_le16(0xffff);
4293 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4294 req.async_event_cr = cpu_to_le16(idx);
4295 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4296 } else {
4297 struct hwrm_func_vf_cfg_input req = {0};
4298
4299 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4300 req.enables =
4301 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4302 req.async_event_cr = cpu_to_le16(idx);
4303 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4304 }
4305 return rc;
4306 }
4307
4308 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4309 {
4310 int i, rc = 0;
4311
4312 for (i = 0; i < bp->cp_nr_rings; i++) {
4313 struct bnxt_napi *bnapi = bp->bnapi[i];
4314 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4315 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4316
4317 cpr->cp_doorbell = bp->bar1 + i * 0x80;
4318 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
4319 INVALID_STATS_CTX_ID);
4320 if (rc)
4321 goto err_out;
4322 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4323 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
4324
4325 if (!i) {
4326 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
4327 if (rc)
4328 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
4329 }
4330 }
4331
4332 for (i = 0; i < bp->tx_nr_rings; i++) {
4333 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4334 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4335 u32 map_idx = txr->bnapi->index;
4336 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
4337
4338 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
4339 map_idx, fw_stats_ctx);
4340 if (rc)
4341 goto err_out;
4342 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
4343 }
4344
4345 for (i = 0; i < bp->rx_nr_rings; i++) {
4346 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4347 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4348 u32 map_idx = rxr->bnapi->index;
4349
4350 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
4351 map_idx, INVALID_STATS_CTX_ID);
4352 if (rc)
4353 goto err_out;
4354 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
4355 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
4356 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
4357 }
4358
4359 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4360 for (i = 0; i < bp->rx_nr_rings; i++) {
4361 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4362 struct bnxt_ring_struct *ring =
4363 &rxr->rx_agg_ring_struct;
4364 u32 grp_idx = rxr->bnapi->index;
4365 u32 map_idx = grp_idx + bp->rx_nr_rings;
4366
4367 rc = hwrm_ring_alloc_send_msg(bp, ring,
4368 HWRM_RING_ALLOC_AGG,
4369 map_idx,
4370 INVALID_STATS_CTX_ID);
4371 if (rc)
4372 goto err_out;
4373
4374 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
4375 writel(DB_KEY_RX | rxr->rx_agg_prod,
4376 rxr->rx_agg_doorbell);
4377 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
4378 }
4379 }
4380 err_out:
4381 return rc;
4382 }
4383
4384 static int hwrm_ring_free_send_msg(struct bnxt *bp,
4385 struct bnxt_ring_struct *ring,
4386 u32 ring_type, int cmpl_ring_id)
4387 {
4388 int rc;
4389 struct hwrm_ring_free_input req = {0};
4390 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
4391 u16 error_code;
4392
4393 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
4394 req.ring_type = ring_type;
4395 req.ring_id = cpu_to_le16(ring->fw_ring_id);
4396
4397 mutex_lock(&bp->hwrm_cmd_lock);
4398 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4399 error_code = le16_to_cpu(resp->error_code);
4400 mutex_unlock(&bp->hwrm_cmd_lock);
4401
4402 if (rc || error_code) {
4403 switch (ring_type) {
4404 case RING_FREE_REQ_RING_TYPE_L2_CMPL:
4405 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
4406 rc);
4407 return rc;
4408 case RING_FREE_REQ_RING_TYPE_RX:
4409 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
4410 rc);
4411 return rc;
4412 case RING_FREE_REQ_RING_TYPE_TX:
4413 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
4414 rc);
4415 return rc;
4416 default:
4417 netdev_err(bp->dev, "Invalid ring\n");
4418 return -1;
4419 }
4420 }
4421 return 0;
4422 }
4423
4424 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
4425 {
4426 int i;
4427
4428 if (!bp->bnapi)
4429 return;
4430
4431 for (i = 0; i < bp->tx_nr_rings; i++) {
4432 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4433 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4434 u32 grp_idx = txr->bnapi->index;
4435 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4436
4437 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4438 hwrm_ring_free_send_msg(bp, ring,
4439 RING_FREE_REQ_RING_TYPE_TX,
4440 close_path ? cmpl_ring_id :
4441 INVALID_HW_RING_ID);
4442 ring->fw_ring_id = INVALID_HW_RING_ID;
4443 }
4444 }
4445
4446 for (i = 0; i < bp->rx_nr_rings; i++) {
4447 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4448 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4449 u32 grp_idx = rxr->bnapi->index;
4450 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4451
4452 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4453 hwrm_ring_free_send_msg(bp, ring,
4454 RING_FREE_REQ_RING_TYPE_RX,
4455 close_path ? cmpl_ring_id :
4456 INVALID_HW_RING_ID);
4457 ring->fw_ring_id = INVALID_HW_RING_ID;
4458 bp->grp_info[grp_idx].rx_fw_ring_id =
4459 INVALID_HW_RING_ID;
4460 }
4461 }
4462
4463 for (i = 0; i < bp->rx_nr_rings; i++) {
4464 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4465 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
4466 u32 grp_idx = rxr->bnapi->index;
4467 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4468
4469 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4470 hwrm_ring_free_send_msg(bp, ring,
4471 RING_FREE_REQ_RING_TYPE_RX,
4472 close_path ? cmpl_ring_id :
4473 INVALID_HW_RING_ID);
4474 ring->fw_ring_id = INVALID_HW_RING_ID;
4475 bp->grp_info[grp_idx].agg_fw_ring_id =
4476 INVALID_HW_RING_ID;
4477 }
4478 }
4479
4480 /* The completion rings are about to be freed. After that the
4481 * IRQ doorbell will not work anymore. So we need to disable
4482 * IRQ here.
4483 */
4484 bnxt_disable_int_sync(bp);
4485
4486 for (i = 0; i < bp->cp_nr_rings; i++) {
4487 struct bnxt_napi *bnapi = bp->bnapi[i];
4488 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4489 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4490
4491 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4492 hwrm_ring_free_send_msg(bp, ring,
4493 RING_FREE_REQ_RING_TYPE_L2_CMPL,
4494 INVALID_HW_RING_ID);
4495 ring->fw_ring_id = INVALID_HW_RING_ID;
4496 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
4497 }
4498 }
4499 }
4500
4501 /* Caller must hold bp->hwrm_cmd_lock */
4502 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
4503 {
4504 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4505 struct hwrm_func_qcfg_input req = {0};
4506 int rc;
4507
4508 if (bp->hwrm_spec_code < 0x10601)
4509 return 0;
4510
4511 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4512 req.fid = cpu_to_le16(fid);
4513 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4514 if (!rc)
4515 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4516
4517 return rc;
4518 }
4519
4520 static int bnxt_hwrm_reserve_tx_rings(struct bnxt *bp, int *tx_rings)
4521 {
4522 struct hwrm_func_cfg_input req = {0};
4523 int rc;
4524
4525 if (bp->hwrm_spec_code < 0x10601)
4526 return 0;
4527
4528 if (BNXT_VF(bp))
4529 return 0;
4530
4531 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4532 req.fid = cpu_to_le16(0xffff);
4533 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS);
4534 req.num_tx_rings = cpu_to_le16(*tx_rings);
4535 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4536 if (rc)
4537 return rc;
4538
4539 mutex_lock(&bp->hwrm_cmd_lock);
4540 rc = __bnxt_hwrm_get_tx_rings(bp, 0xffff, tx_rings);
4541 mutex_unlock(&bp->hwrm_cmd_lock);
4542 if (!rc)
4543 bp->tx_reserved_rings = *tx_rings;
4544 return rc;
4545 }
4546
4547 static int bnxt_hwrm_check_tx_rings(struct bnxt *bp, int tx_rings)
4548 {
4549 struct hwrm_func_cfg_input req = {0};
4550 int rc;
4551
4552 if (bp->hwrm_spec_code < 0x10801)
4553 return 0;
4554
4555 if (BNXT_VF(bp))
4556 return 0;
4557
4558 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4559 req.fid = cpu_to_le16(0xffff);
4560 req.flags = cpu_to_le32(FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST);
4561 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS);
4562 req.num_tx_rings = cpu_to_le16(tx_rings);
4563 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4564 if (rc)
4565 return -ENOMEM;
4566 return 0;
4567 }
4568
4569 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4570 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4571 {
4572 u16 val, tmr, max, flags;
4573
4574 max = hw_coal->bufs_per_record * 128;
4575 if (hw_coal->budget)
4576 max = hw_coal->bufs_per_record * hw_coal->budget;
4577
4578 val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
4579 req->num_cmpl_aggr_int = cpu_to_le16(val);
4580
4581 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4582 val = min_t(u16, val, 63);
4583 req->num_cmpl_dma_aggr = cpu_to_le16(val);
4584
4585 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4586 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 63);
4587 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
4588
4589 tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks);
4590 tmr = max_t(u16, tmr, 1);
4591 req->int_lat_tmr_max = cpu_to_le16(tmr);
4592
4593 /* min timer set to 1/2 of interrupt timer */
4594 val = tmr / 2;
4595 req->int_lat_tmr_min = cpu_to_le16(val);
4596
4597 /* buf timer set to 1/4 of interrupt timer */
4598 val = max_t(u16, tmr / 4, 1);
4599 req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
4600
4601 tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks_irq);
4602 tmr = max_t(u16, tmr, 1);
4603 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr);
4604
4605 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4606 if (hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
4607 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
4608 req->flags = cpu_to_le16(flags);
4609 }
4610
4611 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
4612 {
4613 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
4614 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4615 struct bnxt_coal coal;
4616 unsigned int grp_idx;
4617
4618 /* Tick values in micro seconds.
4619 * 1 coal_buf x bufs_per_record = 1 completion record.
4620 */
4621 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
4622
4623 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
4624 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
4625
4626 if (!bnapi->rx_ring)
4627 return -ENODEV;
4628
4629 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4630 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4631
4632 bnxt_hwrm_set_coal_params(&coal, &req_rx);
4633
4634 grp_idx = bnapi->index;
4635 req_rx.ring_id = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4636
4637 return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
4638 HWRM_CMD_TIMEOUT);
4639 }
4640
4641 int bnxt_hwrm_set_coal(struct bnxt *bp)
4642 {
4643 int i, rc = 0;
4644 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
4645 req_tx = {0}, *req;
4646
4647 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4648 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4649 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
4650 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4651
4652 bnxt_hwrm_set_coal_params(&bp->rx_coal, &req_rx);
4653 bnxt_hwrm_set_coal_params(&bp->tx_coal, &req_tx);
4654
4655 mutex_lock(&bp->hwrm_cmd_lock);
4656 for (i = 0; i < bp->cp_nr_rings; i++) {
4657 struct bnxt_napi *bnapi = bp->bnapi[i];
4658
4659 req = &req_rx;
4660 if (!bnapi->rx_ring)
4661 req = &req_tx;
4662 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
4663
4664 rc = _hwrm_send_message(bp, req, sizeof(*req),
4665 HWRM_CMD_TIMEOUT);
4666 if (rc)
4667 break;
4668 }
4669 mutex_unlock(&bp->hwrm_cmd_lock);
4670 return rc;
4671 }
4672
4673 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
4674 {
4675 int rc = 0, i;
4676 struct hwrm_stat_ctx_free_input req = {0};
4677
4678 if (!bp->bnapi)
4679 return 0;
4680
4681 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4682 return 0;
4683
4684 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
4685
4686 mutex_lock(&bp->hwrm_cmd_lock);
4687 for (i = 0; i < bp->cp_nr_rings; i++) {
4688 struct bnxt_napi *bnapi = bp->bnapi[i];
4689 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4690
4691 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
4692 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
4693
4694 rc = _hwrm_send_message(bp, &req, sizeof(req),
4695 HWRM_CMD_TIMEOUT);
4696 if (rc)
4697 break;
4698
4699 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4700 }
4701 }
4702 mutex_unlock(&bp->hwrm_cmd_lock);
4703 return rc;
4704 }
4705
4706 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
4707 {
4708 int rc = 0, i;
4709 struct hwrm_stat_ctx_alloc_input req = {0};
4710 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4711
4712 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4713 return 0;
4714
4715 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
4716
4717 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
4718
4719 mutex_lock(&bp->hwrm_cmd_lock);
4720 for (i = 0; i < bp->cp_nr_rings; i++) {
4721 struct bnxt_napi *bnapi = bp->bnapi[i];
4722 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4723
4724 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
4725
4726 rc = _hwrm_send_message(bp, &req, sizeof(req),
4727 HWRM_CMD_TIMEOUT);
4728 if (rc)
4729 break;
4730
4731 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
4732
4733 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
4734 }
4735 mutex_unlock(&bp->hwrm_cmd_lock);
4736 return rc;
4737 }
4738
4739 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
4740 {
4741 struct hwrm_func_qcfg_input req = {0};
4742 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4743 u16 flags;
4744 int rc;
4745
4746 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4747 req.fid = cpu_to_le16(0xffff);
4748 mutex_lock(&bp->hwrm_cmd_lock);
4749 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4750 if (rc)
4751 goto func_qcfg_exit;
4752
4753 #ifdef CONFIG_BNXT_SRIOV
4754 if (BNXT_VF(bp)) {
4755 struct bnxt_vf_info *vf = &bp->vf;
4756
4757 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
4758 }
4759 #endif
4760 flags = le16_to_cpu(resp->flags);
4761 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
4762 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
4763 bp->flags |= BNXT_FLAG_FW_LLDP_AGENT;
4764 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
4765 bp->flags |= BNXT_FLAG_FW_DCBX_AGENT;
4766 }
4767 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
4768 bp->flags |= BNXT_FLAG_MULTI_HOST;
4769
4770 switch (resp->port_partition_type) {
4771 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
4772 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
4773 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
4774 bp->port_partition_type = resp->port_partition_type;
4775 break;
4776 }
4777 if (bp->hwrm_spec_code < 0x10707 ||
4778 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
4779 bp->br_mode = BRIDGE_MODE_VEB;
4780 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
4781 bp->br_mode = BRIDGE_MODE_VEPA;
4782 else
4783 bp->br_mode = BRIDGE_MODE_UNDEF;
4784
4785 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
4786 if (!bp->max_mtu)
4787 bp->max_mtu = BNXT_MAX_MTU;
4788
4789 func_qcfg_exit:
4790 mutex_unlock(&bp->hwrm_cmd_lock);
4791 return rc;
4792 }
4793
4794 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
4795 {
4796 int rc = 0;
4797 struct hwrm_func_qcaps_input req = {0};
4798 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4799
4800 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
4801 req.fid = cpu_to_le16(0xffff);
4802
4803 mutex_lock(&bp->hwrm_cmd_lock);
4804 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4805 if (rc)
4806 goto hwrm_func_qcaps_exit;
4807
4808 if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED))
4809 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
4810 if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED))
4811 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
4812
4813 bp->tx_push_thresh = 0;
4814 if (resp->flags &
4815 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
4816 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
4817
4818 if (BNXT_PF(bp)) {
4819 struct bnxt_pf_info *pf = &bp->pf;
4820
4821 pf->fw_fid = le16_to_cpu(resp->fid);
4822 pf->port_id = le16_to_cpu(resp->port_id);
4823 bp->dev->dev_port = pf->port_id;
4824 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
4825 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4826 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4827 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4828 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4829 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4830 if (!pf->max_hw_ring_grps)
4831 pf->max_hw_ring_grps = pf->max_tx_rings;
4832 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4833 pf->max_vnics = le16_to_cpu(resp->max_vnics);
4834 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4835 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
4836 pf->max_vfs = le16_to_cpu(resp->max_vfs);
4837 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
4838 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
4839 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
4840 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
4841 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
4842 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
4843 if (resp->flags &
4844 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED))
4845 bp->flags |= BNXT_FLAG_WOL_CAP;
4846 } else {
4847 #ifdef CONFIG_BNXT_SRIOV
4848 struct bnxt_vf_info *vf = &bp->vf;
4849
4850 vf->fw_fid = le16_to_cpu(resp->fid);
4851
4852 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4853 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4854 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4855 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4856 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4857 if (!vf->max_hw_ring_grps)
4858 vf->max_hw_ring_grps = vf->max_tx_rings;
4859 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4860 vf->max_vnics = le16_to_cpu(resp->max_vnics);
4861 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4862
4863 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
4864 #endif
4865 }
4866
4867 hwrm_func_qcaps_exit:
4868 mutex_unlock(&bp->hwrm_cmd_lock);
4869 return rc;
4870 }
4871
4872 static int bnxt_hwrm_func_reset(struct bnxt *bp)
4873 {
4874 struct hwrm_func_reset_input req = {0};
4875
4876 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
4877 req.enables = 0;
4878
4879 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
4880 }
4881
4882 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
4883 {
4884 int rc = 0;
4885 struct hwrm_queue_qportcfg_input req = {0};
4886 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
4887 u8 i, *qptr;
4888
4889 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
4890
4891 mutex_lock(&bp->hwrm_cmd_lock);
4892 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4893 if (rc)
4894 goto qportcfg_exit;
4895
4896 if (!resp->max_configurable_queues) {
4897 rc = -EINVAL;
4898 goto qportcfg_exit;
4899 }
4900 bp->max_tc = resp->max_configurable_queues;
4901 bp->max_lltc = resp->max_configurable_lossless_queues;
4902 if (bp->max_tc > BNXT_MAX_QUEUE)
4903 bp->max_tc = BNXT_MAX_QUEUE;
4904
4905 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
4906 bp->max_tc = 1;
4907
4908 if (bp->max_lltc > bp->max_tc)
4909 bp->max_lltc = bp->max_tc;
4910
4911 qptr = &resp->queue_id0;
4912 for (i = 0; i < bp->max_tc; i++) {
4913 bp->q_info[i].queue_id = *qptr++;
4914 bp->q_info[i].queue_profile = *qptr++;
4915 }
4916
4917 qportcfg_exit:
4918 mutex_unlock(&bp->hwrm_cmd_lock);
4919 return rc;
4920 }
4921
4922 static int bnxt_hwrm_ver_get(struct bnxt *bp)
4923 {
4924 int rc;
4925 struct hwrm_ver_get_input req = {0};
4926 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
4927 u32 dev_caps_cfg;
4928
4929 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
4930 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
4931 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
4932 req.hwrm_intf_min = HWRM_VERSION_MINOR;
4933 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
4934 mutex_lock(&bp->hwrm_cmd_lock);
4935 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4936 if (rc)
4937 goto hwrm_ver_get_exit;
4938
4939 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
4940
4941 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
4942 resp->hwrm_intf_min_8b << 8 |
4943 resp->hwrm_intf_upd_8b;
4944 if (resp->hwrm_intf_maj_8b < 1) {
4945 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
4946 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
4947 resp->hwrm_intf_upd_8b);
4948 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
4949 }
4950 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
4951 resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
4952 resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
4953
4954 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
4955 if (!bp->hwrm_cmd_timeout)
4956 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
4957
4958 if (resp->hwrm_intf_maj_8b >= 1)
4959 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
4960
4961 bp->chip_num = le16_to_cpu(resp->chip_num);
4962 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
4963 !resp->chip_metal)
4964 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
4965
4966 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
4967 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
4968 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
4969 bp->flags |= BNXT_FLAG_SHORT_CMD;
4970
4971 hwrm_ver_get_exit:
4972 mutex_unlock(&bp->hwrm_cmd_lock);
4973 return rc;
4974 }
4975
4976 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
4977 {
4978 struct hwrm_fw_set_time_input req = {0};
4979 struct tm tm;
4980 time64_t now = ktime_get_real_seconds();
4981
4982 if (bp->hwrm_spec_code < 0x10400)
4983 return -EOPNOTSUPP;
4984
4985 time64_to_tm(now, 0, &tm);
4986 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
4987 req.year = cpu_to_le16(1900 + tm.tm_year);
4988 req.month = 1 + tm.tm_mon;
4989 req.day = tm.tm_mday;
4990 req.hour = tm.tm_hour;
4991 req.minute = tm.tm_min;
4992 req.second = tm.tm_sec;
4993 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4994 }
4995
4996 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
4997 {
4998 int rc;
4999 struct bnxt_pf_info *pf = &bp->pf;
5000 struct hwrm_port_qstats_input req = {0};
5001
5002 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
5003 return 0;
5004
5005 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
5006 req.port_id = cpu_to_le16(pf->port_id);
5007 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
5008 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
5009 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5010 return rc;
5011 }
5012
5013 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
5014 {
5015 if (bp->vxlan_port_cnt) {
5016 bnxt_hwrm_tunnel_dst_port_free(
5017 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5018 }
5019 bp->vxlan_port_cnt = 0;
5020 if (bp->nge_port_cnt) {
5021 bnxt_hwrm_tunnel_dst_port_free(
5022 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
5023 }
5024 bp->nge_port_cnt = 0;
5025 }
5026
5027 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
5028 {
5029 int rc, i;
5030 u32 tpa_flags = 0;
5031
5032 if (set_tpa)
5033 tpa_flags = bp->flags & BNXT_FLAG_TPA;
5034 for (i = 0; i < bp->nr_vnics; i++) {
5035 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
5036 if (rc) {
5037 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
5038 i, rc);
5039 return rc;
5040 }
5041 }
5042 return 0;
5043 }
5044
5045 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
5046 {
5047 int i;
5048
5049 for (i = 0; i < bp->nr_vnics; i++)
5050 bnxt_hwrm_vnic_set_rss(bp, i, false);
5051 }
5052
5053 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
5054 bool irq_re_init)
5055 {
5056 if (bp->vnic_info) {
5057 bnxt_hwrm_clear_vnic_filter(bp);
5058 /* clear all RSS setting before free vnic ctx */
5059 bnxt_hwrm_clear_vnic_rss(bp);
5060 bnxt_hwrm_vnic_ctx_free(bp);
5061 /* before free the vnic, undo the vnic tpa settings */
5062 if (bp->flags & BNXT_FLAG_TPA)
5063 bnxt_set_tpa(bp, false);
5064 bnxt_hwrm_vnic_free(bp);
5065 }
5066 bnxt_hwrm_ring_free(bp, close_path);
5067 bnxt_hwrm_ring_grp_free(bp);
5068 if (irq_re_init) {
5069 bnxt_hwrm_stat_ctx_free(bp);
5070 bnxt_hwrm_free_tunnel_ports(bp);
5071 }
5072 }
5073
5074 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
5075 {
5076 struct hwrm_func_cfg_input req = {0};
5077 int rc;
5078
5079 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5080 req.fid = cpu_to_le16(0xffff);
5081 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
5082 if (br_mode == BRIDGE_MODE_VEB)
5083 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
5084 else if (br_mode == BRIDGE_MODE_VEPA)
5085 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
5086 else
5087 return -EINVAL;
5088 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5089 if (rc)
5090 rc = -EIO;
5091 return rc;
5092 }
5093
5094 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
5095 {
5096 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5097 int rc;
5098
5099 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
5100 goto skip_rss_ctx;
5101
5102 /* allocate context for vnic */
5103 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
5104 if (rc) {
5105 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5106 vnic_id, rc);
5107 goto vnic_setup_err;
5108 }
5109 bp->rsscos_nr_ctxs++;
5110
5111 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5112 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
5113 if (rc) {
5114 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
5115 vnic_id, rc);
5116 goto vnic_setup_err;
5117 }
5118 bp->rsscos_nr_ctxs++;
5119 }
5120
5121 skip_rss_ctx:
5122 /* configure default vnic, ring grp */
5123 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
5124 if (rc) {
5125 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
5126 vnic_id, rc);
5127 goto vnic_setup_err;
5128 }
5129
5130 /* Enable RSS hashing on vnic */
5131 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
5132 if (rc) {
5133 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
5134 vnic_id, rc);
5135 goto vnic_setup_err;
5136 }
5137
5138 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5139 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
5140 if (rc) {
5141 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
5142 vnic_id, rc);
5143 }
5144 }
5145
5146 vnic_setup_err:
5147 return rc;
5148 }
5149
5150 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
5151 {
5152 #ifdef CONFIG_RFS_ACCEL
5153 int i, rc = 0;
5154
5155 for (i = 0; i < bp->rx_nr_rings; i++) {
5156 struct bnxt_vnic_info *vnic;
5157 u16 vnic_id = i + 1;
5158 u16 ring_id = i;
5159
5160 if (vnic_id >= bp->nr_vnics)
5161 break;
5162
5163 vnic = &bp->vnic_info[vnic_id];
5164 vnic->flags |= BNXT_VNIC_RFS_FLAG;
5165 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
5166 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
5167 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
5168 if (rc) {
5169 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5170 vnic_id, rc);
5171 break;
5172 }
5173 rc = bnxt_setup_vnic(bp, vnic_id);
5174 if (rc)
5175 break;
5176 }
5177 return rc;
5178 #else
5179 return 0;
5180 #endif
5181 }
5182
5183 /* Allow PF and VF with default VLAN to be in promiscuous mode */
5184 static bool bnxt_promisc_ok(struct bnxt *bp)
5185 {
5186 #ifdef CONFIG_BNXT_SRIOV
5187 if (BNXT_VF(bp) && !bp->vf.vlan)
5188 return false;
5189 #endif
5190 return true;
5191 }
5192
5193 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
5194 {
5195 unsigned int rc = 0;
5196
5197 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
5198 if (rc) {
5199 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5200 rc);
5201 return rc;
5202 }
5203
5204 rc = bnxt_hwrm_vnic_cfg(bp, 1);
5205 if (rc) {
5206 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5207 rc);
5208 return rc;
5209 }
5210 return rc;
5211 }
5212
5213 static int bnxt_cfg_rx_mode(struct bnxt *);
5214 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
5215
5216 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
5217 {
5218 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5219 int rc = 0;
5220 unsigned int rx_nr_rings = bp->rx_nr_rings;
5221
5222 if (irq_re_init) {
5223 rc = bnxt_hwrm_stat_ctx_alloc(bp);
5224 if (rc) {
5225 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
5226 rc);
5227 goto err_out;
5228 }
5229 if (bp->tx_reserved_rings != bp->tx_nr_rings) {
5230 int tx = bp->tx_nr_rings;
5231
5232 if (bnxt_hwrm_reserve_tx_rings(bp, &tx) ||
5233 tx < bp->tx_nr_rings) {
5234 rc = -ENOMEM;
5235 goto err_out;
5236 }
5237 }
5238 }
5239
5240 rc = bnxt_hwrm_ring_alloc(bp);
5241 if (rc) {
5242 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
5243 goto err_out;
5244 }
5245
5246 rc = bnxt_hwrm_ring_grp_alloc(bp);
5247 if (rc) {
5248 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
5249 goto err_out;
5250 }
5251
5252 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5253 rx_nr_rings--;
5254
5255 /* default vnic 0 */
5256 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
5257 if (rc) {
5258 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
5259 goto err_out;
5260 }
5261
5262 rc = bnxt_setup_vnic(bp, 0);
5263 if (rc)
5264 goto err_out;
5265
5266 if (bp->flags & BNXT_FLAG_RFS) {
5267 rc = bnxt_alloc_rfs_vnics(bp);
5268 if (rc)
5269 goto err_out;
5270 }
5271
5272 if (bp->flags & BNXT_FLAG_TPA) {
5273 rc = bnxt_set_tpa(bp, true);
5274 if (rc)
5275 goto err_out;
5276 }
5277
5278 if (BNXT_VF(bp))
5279 bnxt_update_vf_mac(bp);
5280
5281 /* Filter for default vnic 0 */
5282 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
5283 if (rc) {
5284 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
5285 goto err_out;
5286 }
5287 vnic->uc_filter_count = 1;
5288
5289 vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
5290
5291 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
5292 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5293
5294 if (bp->dev->flags & IFF_ALLMULTI) {
5295 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5296 vnic->mc_list_count = 0;
5297 } else {
5298 u32 mask = 0;
5299
5300 bnxt_mc_list_updated(bp, &mask);
5301 vnic->rx_mask |= mask;
5302 }
5303
5304 rc = bnxt_cfg_rx_mode(bp);
5305 if (rc)
5306 goto err_out;
5307
5308 rc = bnxt_hwrm_set_coal(bp);
5309 if (rc)
5310 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
5311 rc);
5312
5313 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5314 rc = bnxt_setup_nitroa0_vnic(bp);
5315 if (rc)
5316 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
5317 rc);
5318 }
5319
5320 if (BNXT_VF(bp)) {
5321 bnxt_hwrm_func_qcfg(bp);
5322 netdev_update_features(bp->dev);
5323 }
5324
5325 return 0;
5326
5327 err_out:
5328 bnxt_hwrm_resource_free(bp, 0, true);
5329
5330 return rc;
5331 }
5332
5333 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
5334 {
5335 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
5336 return 0;
5337 }
5338
5339 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
5340 {
5341 bnxt_init_cp_rings(bp);
5342 bnxt_init_rx_rings(bp);
5343 bnxt_init_tx_rings(bp);
5344 bnxt_init_ring_grps(bp, irq_re_init);
5345 bnxt_init_vnics(bp);
5346
5347 return bnxt_init_chip(bp, irq_re_init);
5348 }
5349
5350 static int bnxt_set_real_num_queues(struct bnxt *bp)
5351 {
5352 int rc;
5353 struct net_device *dev = bp->dev;
5354
5355 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
5356 bp->tx_nr_rings_xdp);
5357 if (rc)
5358 return rc;
5359
5360 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
5361 if (rc)
5362 return rc;
5363
5364 #ifdef CONFIG_RFS_ACCEL
5365 if (bp->flags & BNXT_FLAG_RFS)
5366 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
5367 #endif
5368
5369 return rc;
5370 }
5371
5372 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5373 bool shared)
5374 {
5375 int _rx = *rx, _tx = *tx;
5376
5377 if (shared) {
5378 *rx = min_t(int, _rx, max);
5379 *tx = min_t(int, _tx, max);
5380 } else {
5381 if (max < 2)
5382 return -ENOMEM;
5383
5384 while (_rx + _tx > max) {
5385 if (_rx > _tx && _rx > 1)
5386 _rx--;
5387 else if (_tx > 1)
5388 _tx--;
5389 }
5390 *rx = _rx;
5391 *tx = _tx;
5392 }
5393 return 0;
5394 }
5395
5396 static void bnxt_setup_msix(struct bnxt *bp)
5397 {
5398 const int len = sizeof(bp->irq_tbl[0].name);
5399 struct net_device *dev = bp->dev;
5400 int tcs, i;
5401
5402 tcs = netdev_get_num_tc(dev);
5403 if (tcs > 1) {
5404 int i, off, count;
5405
5406 for (i = 0; i < tcs; i++) {
5407 count = bp->tx_nr_rings_per_tc;
5408 off = i * count;
5409 netdev_set_tc_queue(dev, i, count, off);
5410 }
5411 }
5412
5413 for (i = 0; i < bp->cp_nr_rings; i++) {
5414 char *attr;
5415
5416 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5417 attr = "TxRx";
5418 else if (i < bp->rx_nr_rings)
5419 attr = "rx";
5420 else
5421 attr = "tx";
5422
5423 snprintf(bp->irq_tbl[i].name, len, "%s-%s-%d", dev->name, attr,
5424 i);
5425 bp->irq_tbl[i].handler = bnxt_msix;
5426 }
5427 }
5428
5429 static void bnxt_setup_inta(struct bnxt *bp)
5430 {
5431 const int len = sizeof(bp->irq_tbl[0].name);
5432
5433 if (netdev_get_num_tc(bp->dev))
5434 netdev_reset_tc(bp->dev);
5435
5436 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
5437 0);
5438 bp->irq_tbl[0].handler = bnxt_inta;
5439 }
5440
5441 static int bnxt_setup_int_mode(struct bnxt *bp)
5442 {
5443 int rc;
5444
5445 if (bp->flags & BNXT_FLAG_USING_MSIX)
5446 bnxt_setup_msix(bp);
5447 else
5448 bnxt_setup_inta(bp);
5449
5450 rc = bnxt_set_real_num_queues(bp);
5451 return rc;
5452 }
5453
5454 #ifdef CONFIG_RFS_ACCEL
5455 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
5456 {
5457 #if defined(CONFIG_BNXT_SRIOV)
5458 if (BNXT_VF(bp))
5459 return bp->vf.max_rsscos_ctxs;
5460 #endif
5461 return bp->pf.max_rsscos_ctxs;
5462 }
5463
5464 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
5465 {
5466 #if defined(CONFIG_BNXT_SRIOV)
5467 if (BNXT_VF(bp))
5468 return bp->vf.max_vnics;
5469 #endif
5470 return bp->pf.max_vnics;
5471 }
5472 #endif
5473
5474 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
5475 {
5476 #if defined(CONFIG_BNXT_SRIOV)
5477 if (BNXT_VF(bp))
5478 return bp->vf.max_stat_ctxs;
5479 #endif
5480 return bp->pf.max_stat_ctxs;
5481 }
5482
5483 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max)
5484 {
5485 #if defined(CONFIG_BNXT_SRIOV)
5486 if (BNXT_VF(bp))
5487 bp->vf.max_stat_ctxs = max;
5488 else
5489 #endif
5490 bp->pf.max_stat_ctxs = max;
5491 }
5492
5493 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
5494 {
5495 #if defined(CONFIG_BNXT_SRIOV)
5496 if (BNXT_VF(bp))
5497 return bp->vf.max_cp_rings;
5498 #endif
5499 return bp->pf.max_cp_rings;
5500 }
5501
5502 void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max)
5503 {
5504 #if defined(CONFIG_BNXT_SRIOV)
5505 if (BNXT_VF(bp))
5506 bp->vf.max_cp_rings = max;
5507 else
5508 #endif
5509 bp->pf.max_cp_rings = max;
5510 }
5511
5512 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
5513 {
5514 #if defined(CONFIG_BNXT_SRIOV)
5515 if (BNXT_VF(bp))
5516 return min_t(unsigned int, bp->vf.max_irqs,
5517 bp->vf.max_cp_rings);
5518 #endif
5519 return min_t(unsigned int, bp->pf.max_irqs, bp->pf.max_cp_rings);
5520 }
5521
5522 void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
5523 {
5524 #if defined(CONFIG_BNXT_SRIOV)
5525 if (BNXT_VF(bp))
5526 bp->vf.max_irqs = max_irqs;
5527 else
5528 #endif
5529 bp->pf.max_irqs = max_irqs;
5530 }
5531
5532 static int bnxt_init_msix(struct bnxt *bp)
5533 {
5534 int i, total_vecs, rc = 0, min = 1;
5535 struct msix_entry *msix_ent;
5536
5537 total_vecs = bnxt_get_max_func_irqs(bp);
5538 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
5539 if (!msix_ent)
5540 return -ENOMEM;
5541
5542 for (i = 0; i < total_vecs; i++) {
5543 msix_ent[i].entry = i;
5544 msix_ent[i].vector = 0;
5545 }
5546
5547 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
5548 min = 2;
5549
5550 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
5551 if (total_vecs < 0) {
5552 rc = -ENODEV;
5553 goto msix_setup_exit;
5554 }
5555
5556 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
5557 if (bp->irq_tbl) {
5558 for (i = 0; i < total_vecs; i++)
5559 bp->irq_tbl[i].vector = msix_ent[i].vector;
5560
5561 bp->total_irqs = total_vecs;
5562 /* Trim rings based upon num of vectors allocated */
5563 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
5564 total_vecs, min == 1);
5565 if (rc)
5566 goto msix_setup_exit;
5567
5568 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
5569 bp->cp_nr_rings = (min == 1) ?
5570 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5571 bp->tx_nr_rings + bp->rx_nr_rings;
5572
5573 } else {
5574 rc = -ENOMEM;
5575 goto msix_setup_exit;
5576 }
5577 bp->flags |= BNXT_FLAG_USING_MSIX;
5578 kfree(msix_ent);
5579 return 0;
5580
5581 msix_setup_exit:
5582 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
5583 kfree(bp->irq_tbl);
5584 bp->irq_tbl = NULL;
5585 pci_disable_msix(bp->pdev);
5586 kfree(msix_ent);
5587 return rc;
5588 }
5589
5590 static int bnxt_init_inta(struct bnxt *bp)
5591 {
5592 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
5593 if (!bp->irq_tbl)
5594 return -ENOMEM;
5595
5596 bp->total_irqs = 1;
5597 bp->rx_nr_rings = 1;
5598 bp->tx_nr_rings = 1;
5599 bp->cp_nr_rings = 1;
5600 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
5601 bp->flags |= BNXT_FLAG_SHARED_RINGS;
5602 bp->irq_tbl[0].vector = bp->pdev->irq;
5603 return 0;
5604 }
5605
5606 static int bnxt_init_int_mode(struct bnxt *bp)
5607 {
5608 int rc = 0;
5609
5610 if (bp->flags & BNXT_FLAG_MSIX_CAP)
5611 rc = bnxt_init_msix(bp);
5612
5613 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
5614 /* fallback to INTA */
5615 rc = bnxt_init_inta(bp);
5616 }
5617 return rc;
5618 }
5619
5620 static void bnxt_clear_int_mode(struct bnxt *bp)
5621 {
5622 if (bp->flags & BNXT_FLAG_USING_MSIX)
5623 pci_disable_msix(bp->pdev);
5624
5625 kfree(bp->irq_tbl);
5626 bp->irq_tbl = NULL;
5627 bp->flags &= ~BNXT_FLAG_USING_MSIX;
5628 }
5629
5630 static void bnxt_free_irq(struct bnxt *bp)
5631 {
5632 struct bnxt_irq *irq;
5633 int i;
5634
5635 #ifdef CONFIG_RFS_ACCEL
5636 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
5637 bp->dev->rx_cpu_rmap = NULL;
5638 #endif
5639 if (!bp->irq_tbl)
5640 return;
5641
5642 for (i = 0; i < bp->cp_nr_rings; i++) {
5643 irq = &bp->irq_tbl[i];
5644 if (irq->requested) {
5645 if (irq->have_cpumask) {
5646 irq_set_affinity_hint(irq->vector, NULL);
5647 free_cpumask_var(irq->cpu_mask);
5648 irq->have_cpumask = 0;
5649 }
5650 free_irq(irq->vector, bp->bnapi[i]);
5651 }
5652
5653 irq->requested = 0;
5654 }
5655 }
5656
5657 static int bnxt_request_irq(struct bnxt *bp)
5658 {
5659 int i, j, rc = 0;
5660 unsigned long flags = 0;
5661 #ifdef CONFIG_RFS_ACCEL
5662 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
5663 #endif
5664
5665 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
5666 flags = IRQF_SHARED;
5667
5668 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
5669 struct bnxt_irq *irq = &bp->irq_tbl[i];
5670 #ifdef CONFIG_RFS_ACCEL
5671 if (rmap && bp->bnapi[i]->rx_ring) {
5672 rc = irq_cpu_rmap_add(rmap, irq->vector);
5673 if (rc)
5674 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
5675 j);
5676 j++;
5677 }
5678 #endif
5679 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5680 bp->bnapi[i]);
5681 if (rc)
5682 break;
5683
5684 irq->requested = 1;
5685
5686 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
5687 int numa_node = dev_to_node(&bp->pdev->dev);
5688
5689 irq->have_cpumask = 1;
5690 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
5691 irq->cpu_mask);
5692 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
5693 if (rc) {
5694 netdev_warn(bp->dev,
5695 "Set affinity failed, IRQ = %d\n",
5696 irq->vector);
5697 break;
5698 }
5699 }
5700 }
5701 return rc;
5702 }
5703
5704 static void bnxt_del_napi(struct bnxt *bp)
5705 {
5706 int i;
5707
5708 if (!bp->bnapi)
5709 return;
5710
5711 for (i = 0; i < bp->cp_nr_rings; i++) {
5712 struct bnxt_napi *bnapi = bp->bnapi[i];
5713
5714 napi_hash_del(&bnapi->napi);
5715 netif_napi_del(&bnapi->napi);
5716 }
5717 /* We called napi_hash_del() before netif_napi_del(), we need
5718 * to respect an RCU grace period before freeing napi structures.
5719 */
5720 synchronize_net();
5721 }
5722
5723 static void bnxt_init_napi(struct bnxt *bp)
5724 {
5725 int i;
5726 unsigned int cp_nr_rings = bp->cp_nr_rings;
5727 struct bnxt_napi *bnapi;
5728
5729 if (bp->flags & BNXT_FLAG_USING_MSIX) {
5730 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5731 cp_nr_rings--;
5732 for (i = 0; i < cp_nr_rings; i++) {
5733 bnapi = bp->bnapi[i];
5734 netif_napi_add(bp->dev, &bnapi->napi,
5735 bnxt_poll, 64);
5736 }
5737 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5738 bnapi = bp->bnapi[cp_nr_rings];
5739 netif_napi_add(bp->dev, &bnapi->napi,
5740 bnxt_poll_nitroa0, 64);
5741 }
5742 } else {
5743 bnapi = bp->bnapi[0];
5744 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
5745 }
5746 }
5747
5748 static void bnxt_disable_napi(struct bnxt *bp)
5749 {
5750 int i;
5751
5752 if (!bp->bnapi)
5753 return;
5754
5755 for (i = 0; i < bp->cp_nr_rings; i++)
5756 napi_disable(&bp->bnapi[i]->napi);
5757 }
5758
5759 static void bnxt_enable_napi(struct bnxt *bp)
5760 {
5761 int i;
5762
5763 for (i = 0; i < bp->cp_nr_rings; i++) {
5764 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
5765 bp->bnapi[i]->in_reset = false;
5766
5767 if (bp->bnapi[i]->rx_ring) {
5768 INIT_WORK(&cpr->dim.work, bnxt_dim_work);
5769 cpr->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
5770 }
5771 napi_enable(&bp->bnapi[i]->napi);
5772 }
5773 }
5774
5775 void bnxt_tx_disable(struct bnxt *bp)
5776 {
5777 int i;
5778 struct bnxt_tx_ring_info *txr;
5779
5780 if (bp->tx_ring) {
5781 for (i = 0; i < bp->tx_nr_rings; i++) {
5782 txr = &bp->tx_ring[i];
5783 txr->dev_state = BNXT_DEV_STATE_CLOSING;
5784 }
5785 }
5786 /* Stop all TX queues */
5787 netif_tx_disable(bp->dev);
5788 netif_carrier_off(bp->dev);
5789 }
5790
5791 void bnxt_tx_enable(struct bnxt *bp)
5792 {
5793 int i;
5794 struct bnxt_tx_ring_info *txr;
5795
5796 for (i = 0; i < bp->tx_nr_rings; i++) {
5797 txr = &bp->tx_ring[i];
5798 txr->dev_state = 0;
5799 }
5800 netif_tx_wake_all_queues(bp->dev);
5801 if (bp->link_info.link_up)
5802 netif_carrier_on(bp->dev);
5803 }
5804
5805 static void bnxt_report_link(struct bnxt *bp)
5806 {
5807 if (bp->link_info.link_up) {
5808 const char *duplex;
5809 const char *flow_ctrl;
5810 u32 speed;
5811 u16 fec;
5812
5813 netif_carrier_on(bp->dev);
5814 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
5815 duplex = "full";
5816 else
5817 duplex = "half";
5818 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
5819 flow_ctrl = "ON - receive & transmit";
5820 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
5821 flow_ctrl = "ON - transmit";
5822 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
5823 flow_ctrl = "ON - receive";
5824 else
5825 flow_ctrl = "none";
5826 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
5827 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
5828 speed, duplex, flow_ctrl);
5829 if (bp->flags & BNXT_FLAG_EEE_CAP)
5830 netdev_info(bp->dev, "EEE is %s\n",
5831 bp->eee.eee_active ? "active" :
5832 "not active");
5833 fec = bp->link_info.fec_cfg;
5834 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
5835 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
5836 (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
5837 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
5838 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
5839 } else {
5840 netif_carrier_off(bp->dev);
5841 netdev_err(bp->dev, "NIC Link is Down\n");
5842 }
5843 }
5844
5845 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
5846 {
5847 int rc = 0;
5848 struct hwrm_port_phy_qcaps_input req = {0};
5849 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5850 struct bnxt_link_info *link_info = &bp->link_info;
5851
5852 if (bp->hwrm_spec_code < 0x10201)
5853 return 0;
5854
5855 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
5856
5857 mutex_lock(&bp->hwrm_cmd_lock);
5858 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5859 if (rc)
5860 goto hwrm_phy_qcaps_exit;
5861
5862 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
5863 struct ethtool_eee *eee = &bp->eee;
5864 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
5865
5866 bp->flags |= BNXT_FLAG_EEE_CAP;
5867 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5868 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
5869 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
5870 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
5871 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
5872 }
5873 if (resp->supported_speeds_auto_mode)
5874 link_info->support_auto_speeds =
5875 le16_to_cpu(resp->supported_speeds_auto_mode);
5876
5877 bp->port_count = resp->port_cnt;
5878
5879 hwrm_phy_qcaps_exit:
5880 mutex_unlock(&bp->hwrm_cmd_lock);
5881 return rc;
5882 }
5883
5884 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
5885 {
5886 int rc = 0;
5887 struct bnxt_link_info *link_info = &bp->link_info;
5888 struct hwrm_port_phy_qcfg_input req = {0};
5889 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5890 u8 link_up = link_info->link_up;
5891 u16 diff;
5892
5893 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
5894
5895 mutex_lock(&bp->hwrm_cmd_lock);
5896 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5897 if (rc) {
5898 mutex_unlock(&bp->hwrm_cmd_lock);
5899 return rc;
5900 }
5901
5902 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
5903 link_info->phy_link_status = resp->link;
5904 link_info->duplex = resp->duplex_cfg;
5905 if (bp->hwrm_spec_code >= 0x10800)
5906 link_info->duplex = resp->duplex_state;
5907 link_info->pause = resp->pause;
5908 link_info->auto_mode = resp->auto_mode;
5909 link_info->auto_pause_setting = resp->auto_pause;
5910 link_info->lp_pause = resp->link_partner_adv_pause;
5911 link_info->force_pause_setting = resp->force_pause;
5912 link_info->duplex_setting = resp->duplex_cfg;
5913 if (link_info->phy_link_status == BNXT_LINK_LINK)
5914 link_info->link_speed = le16_to_cpu(resp->link_speed);
5915 else
5916 link_info->link_speed = 0;
5917 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
5918 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
5919 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
5920 link_info->lp_auto_link_speeds =
5921 le16_to_cpu(resp->link_partner_adv_speeds);
5922 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
5923 link_info->phy_ver[0] = resp->phy_maj;
5924 link_info->phy_ver[1] = resp->phy_min;
5925 link_info->phy_ver[2] = resp->phy_bld;
5926 link_info->media_type = resp->media_type;
5927 link_info->phy_type = resp->phy_type;
5928 link_info->transceiver = resp->xcvr_pkg_type;
5929 link_info->phy_addr = resp->eee_config_phy_addr &
5930 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
5931 link_info->module_status = resp->module_status;
5932
5933 if (bp->flags & BNXT_FLAG_EEE_CAP) {
5934 struct ethtool_eee *eee = &bp->eee;
5935 u16 fw_speeds;
5936
5937 eee->eee_active = 0;
5938 if (resp->eee_config_phy_addr &
5939 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
5940 eee->eee_active = 1;
5941 fw_speeds = le16_to_cpu(
5942 resp->link_partner_adv_eee_link_speed_mask);
5943 eee->lp_advertised =
5944 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5945 }
5946
5947 /* Pull initial EEE config */
5948 if (!chng_link_state) {
5949 if (resp->eee_config_phy_addr &
5950 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
5951 eee->eee_enabled = 1;
5952
5953 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
5954 eee->advertised =
5955 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5956
5957 if (resp->eee_config_phy_addr &
5958 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
5959 __le32 tmr;
5960
5961 eee->tx_lpi_enabled = 1;
5962 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
5963 eee->tx_lpi_timer = le32_to_cpu(tmr) &
5964 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
5965 }
5966 }
5967 }
5968
5969 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
5970 if (bp->hwrm_spec_code >= 0x10504)
5971 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
5972
5973 /* TODO: need to add more logic to report VF link */
5974 if (chng_link_state) {
5975 if (link_info->phy_link_status == BNXT_LINK_LINK)
5976 link_info->link_up = 1;
5977 else
5978 link_info->link_up = 0;
5979 if (link_up != link_info->link_up)
5980 bnxt_report_link(bp);
5981 } else {
5982 /* alwasy link down if not require to update link state */
5983 link_info->link_up = 0;
5984 }
5985 mutex_unlock(&bp->hwrm_cmd_lock);
5986
5987 diff = link_info->support_auto_speeds ^ link_info->advertising;
5988 if ((link_info->support_auto_speeds | diff) !=
5989 link_info->support_auto_speeds) {
5990 /* An advertised speed is no longer supported, so we need to
5991 * update the advertisement settings. Caller holds RTNL
5992 * so we can modify link settings.
5993 */
5994 link_info->advertising = link_info->support_auto_speeds;
5995 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
5996 bnxt_hwrm_set_link_setting(bp, true, false);
5997 }
5998 return 0;
5999 }
6000
6001 static void bnxt_get_port_module_status(struct bnxt *bp)
6002 {
6003 struct bnxt_link_info *link_info = &bp->link_info;
6004 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
6005 u8 module_status;
6006
6007 if (bnxt_update_link(bp, true))
6008 return;
6009
6010 module_status = link_info->module_status;
6011 switch (module_status) {
6012 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
6013 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
6014 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
6015 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
6016 bp->pf.port_id);
6017 if (bp->hwrm_spec_code >= 0x10201) {
6018 netdev_warn(bp->dev, "Module part number %s\n",
6019 resp->phy_vendor_partnumber);
6020 }
6021 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
6022 netdev_warn(bp->dev, "TX is disabled\n");
6023 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
6024 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
6025 }
6026 }
6027
6028 static void
6029 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
6030 {
6031 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
6032 if (bp->hwrm_spec_code >= 0x10201)
6033 req->auto_pause =
6034 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
6035 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
6036 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
6037 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
6038 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
6039 req->enables |=
6040 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
6041 } else {
6042 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
6043 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
6044 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
6045 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
6046 req->enables |=
6047 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
6048 if (bp->hwrm_spec_code >= 0x10201) {
6049 req->auto_pause = req->force_pause;
6050 req->enables |= cpu_to_le32(
6051 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
6052 }
6053 }
6054 }
6055
6056 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
6057 struct hwrm_port_phy_cfg_input *req)
6058 {
6059 u8 autoneg = bp->link_info.autoneg;
6060 u16 fw_link_speed = bp->link_info.req_link_speed;
6061 u16 advertising = bp->link_info.advertising;
6062
6063 if (autoneg & BNXT_AUTONEG_SPEED) {
6064 req->auto_mode |=
6065 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
6066
6067 req->enables |= cpu_to_le32(
6068 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
6069 req->auto_link_speed_mask = cpu_to_le16(advertising);
6070
6071 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
6072 req->flags |=
6073 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
6074 } else {
6075 req->force_link_speed = cpu_to_le16(fw_link_speed);
6076 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
6077 }
6078
6079 /* tell chimp that the setting takes effect immediately */
6080 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
6081 }
6082
6083 int bnxt_hwrm_set_pause(struct bnxt *bp)
6084 {
6085 struct hwrm_port_phy_cfg_input req = {0};
6086 int rc;
6087
6088 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6089 bnxt_hwrm_set_pause_common(bp, &req);
6090
6091 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
6092 bp->link_info.force_link_chng)
6093 bnxt_hwrm_set_link_common(bp, &req);
6094
6095 mutex_lock(&bp->hwrm_cmd_lock);
6096 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6097 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
6098 /* since changing of pause setting doesn't trigger any link
6099 * change event, the driver needs to update the current pause
6100 * result upon successfully return of the phy_cfg command
6101 */
6102 bp->link_info.pause =
6103 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
6104 bp->link_info.auto_pause_setting = 0;
6105 if (!bp->link_info.force_link_chng)
6106 bnxt_report_link(bp);
6107 }
6108 bp->link_info.force_link_chng = false;
6109 mutex_unlock(&bp->hwrm_cmd_lock);
6110 return rc;
6111 }
6112
6113 static void bnxt_hwrm_set_eee(struct bnxt *bp,
6114 struct hwrm_port_phy_cfg_input *req)
6115 {
6116 struct ethtool_eee *eee = &bp->eee;
6117
6118 if (eee->eee_enabled) {
6119 u16 eee_speeds;
6120 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
6121
6122 if (eee->tx_lpi_enabled)
6123 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
6124 else
6125 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
6126
6127 req->flags |= cpu_to_le32(flags);
6128 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
6129 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
6130 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
6131 } else {
6132 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
6133 }
6134 }
6135
6136 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
6137 {
6138 struct hwrm_port_phy_cfg_input req = {0};
6139
6140 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6141 if (set_pause)
6142 bnxt_hwrm_set_pause_common(bp, &req);
6143
6144 bnxt_hwrm_set_link_common(bp, &req);
6145
6146 if (set_eee)
6147 bnxt_hwrm_set_eee(bp, &req);
6148 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6149 }
6150
6151 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
6152 {
6153 struct hwrm_port_phy_cfg_input req = {0};
6154
6155 if (!BNXT_SINGLE_PF(bp))
6156 return 0;
6157
6158 if (pci_num_vf(bp->pdev))
6159 return 0;
6160
6161 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6162 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
6163 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6164 }
6165
6166 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
6167 {
6168 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6169 struct hwrm_port_led_qcaps_input req = {0};
6170 struct bnxt_pf_info *pf = &bp->pf;
6171 int rc;
6172
6173 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
6174 return 0;
6175
6176 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
6177 req.port_id = cpu_to_le16(pf->port_id);
6178 mutex_lock(&bp->hwrm_cmd_lock);
6179 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6180 if (rc) {
6181 mutex_unlock(&bp->hwrm_cmd_lock);
6182 return rc;
6183 }
6184 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
6185 int i;
6186
6187 bp->num_leds = resp->num_leds;
6188 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
6189 bp->num_leds);
6190 for (i = 0; i < bp->num_leds; i++) {
6191 struct bnxt_led_info *led = &bp->leds[i];
6192 __le16 caps = led->led_state_caps;
6193
6194 if (!led->led_group_id ||
6195 !BNXT_LED_ALT_BLINK_CAP(caps)) {
6196 bp->num_leds = 0;
6197 break;
6198 }
6199 }
6200 }
6201 mutex_unlock(&bp->hwrm_cmd_lock);
6202 return 0;
6203 }
6204
6205 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
6206 {
6207 struct hwrm_wol_filter_alloc_input req = {0};
6208 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6209 int rc;
6210
6211 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
6212 req.port_id = cpu_to_le16(bp->pf.port_id);
6213 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
6214 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
6215 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
6216 mutex_lock(&bp->hwrm_cmd_lock);
6217 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6218 if (!rc)
6219 bp->wol_filter_id = resp->wol_filter_id;
6220 mutex_unlock(&bp->hwrm_cmd_lock);
6221 return rc;
6222 }
6223
6224 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
6225 {
6226 struct hwrm_wol_filter_free_input req = {0};
6227 int rc;
6228
6229 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
6230 req.port_id = cpu_to_le16(bp->pf.port_id);
6231 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
6232 req.wol_filter_id = bp->wol_filter_id;
6233 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6234 return rc;
6235 }
6236
6237 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
6238 {
6239 struct hwrm_wol_filter_qcfg_input req = {0};
6240 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6241 u16 next_handle = 0;
6242 int rc;
6243
6244 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
6245 req.port_id = cpu_to_le16(bp->pf.port_id);
6246 req.handle = cpu_to_le16(handle);
6247 mutex_lock(&bp->hwrm_cmd_lock);
6248 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6249 if (!rc) {
6250 next_handle = le16_to_cpu(resp->next_handle);
6251 if (next_handle != 0) {
6252 if (resp->wol_type ==
6253 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
6254 bp->wol = 1;
6255 bp->wol_filter_id = resp->wol_filter_id;
6256 }
6257 }
6258 }
6259 mutex_unlock(&bp->hwrm_cmd_lock);
6260 return next_handle;
6261 }
6262
6263 static void bnxt_get_wol_settings(struct bnxt *bp)
6264 {
6265 u16 handle = 0;
6266
6267 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
6268 return;
6269
6270 do {
6271 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
6272 } while (handle && handle != 0xffff);
6273 }
6274
6275 static bool bnxt_eee_config_ok(struct bnxt *bp)
6276 {
6277 struct ethtool_eee *eee = &bp->eee;
6278 struct bnxt_link_info *link_info = &bp->link_info;
6279
6280 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
6281 return true;
6282
6283 if (eee->eee_enabled) {
6284 u32 advertising =
6285 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
6286
6287 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6288 eee->eee_enabled = 0;
6289 return false;
6290 }
6291 if (eee->advertised & ~advertising) {
6292 eee->advertised = advertising & eee->supported;
6293 return false;
6294 }
6295 }
6296 return true;
6297 }
6298
6299 static int bnxt_update_phy_setting(struct bnxt *bp)
6300 {
6301 int rc;
6302 bool update_link = false;
6303 bool update_pause = false;
6304 bool update_eee = false;
6305 struct bnxt_link_info *link_info = &bp->link_info;
6306
6307 rc = bnxt_update_link(bp, true);
6308 if (rc) {
6309 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
6310 rc);
6311 return rc;
6312 }
6313 if (!BNXT_SINGLE_PF(bp))
6314 return 0;
6315
6316 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
6317 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
6318 link_info->req_flow_ctrl)
6319 update_pause = true;
6320 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
6321 link_info->force_pause_setting != link_info->req_flow_ctrl)
6322 update_pause = true;
6323 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6324 if (BNXT_AUTO_MODE(link_info->auto_mode))
6325 update_link = true;
6326 if (link_info->req_link_speed != link_info->force_link_speed)
6327 update_link = true;
6328 if (link_info->req_duplex != link_info->duplex_setting)
6329 update_link = true;
6330 } else {
6331 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
6332 update_link = true;
6333 if (link_info->advertising != link_info->auto_link_speeds)
6334 update_link = true;
6335 }
6336
6337 /* The last close may have shutdown the link, so need to call
6338 * PHY_CFG to bring it back up.
6339 */
6340 if (!netif_carrier_ok(bp->dev))
6341 update_link = true;
6342
6343 if (!bnxt_eee_config_ok(bp))
6344 update_eee = true;
6345
6346 if (update_link)
6347 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
6348 else if (update_pause)
6349 rc = bnxt_hwrm_set_pause(bp);
6350 if (rc) {
6351 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
6352 rc);
6353 return rc;
6354 }
6355
6356 return rc;
6357 }
6358
6359 /* Common routine to pre-map certain register block to different GRC window.
6360 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
6361 * in PF and 3 windows in VF that can be customized to map in different
6362 * register blocks.
6363 */
6364 static void bnxt_preset_reg_win(struct bnxt *bp)
6365 {
6366 if (BNXT_PF(bp)) {
6367 /* CAG registers map to GRC window #4 */
6368 writel(BNXT_CAG_REG_BASE,
6369 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
6370 }
6371 }
6372
6373 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6374 {
6375 int rc = 0;
6376
6377 bnxt_preset_reg_win(bp);
6378 netif_carrier_off(bp->dev);
6379 if (irq_re_init) {
6380 rc = bnxt_setup_int_mode(bp);
6381 if (rc) {
6382 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
6383 rc);
6384 return rc;
6385 }
6386 }
6387 if ((bp->flags & BNXT_FLAG_RFS) &&
6388 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
6389 /* disable RFS if falling back to INTA */
6390 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
6391 bp->flags &= ~BNXT_FLAG_RFS;
6392 }
6393
6394 rc = bnxt_alloc_mem(bp, irq_re_init);
6395 if (rc) {
6396 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6397 goto open_err_free_mem;
6398 }
6399
6400 if (irq_re_init) {
6401 bnxt_init_napi(bp);
6402 rc = bnxt_request_irq(bp);
6403 if (rc) {
6404 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
6405 goto open_err;
6406 }
6407 }
6408
6409 bnxt_enable_napi(bp);
6410
6411 rc = bnxt_init_nic(bp, irq_re_init);
6412 if (rc) {
6413 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6414 goto open_err;
6415 }
6416
6417 if (link_re_init) {
6418 mutex_lock(&bp->link_lock);
6419 rc = bnxt_update_phy_setting(bp);
6420 mutex_unlock(&bp->link_lock);
6421 if (rc)
6422 netdev_warn(bp->dev, "failed to update phy settings\n");
6423 }
6424
6425 if (irq_re_init)
6426 udp_tunnel_get_rx_info(bp->dev);
6427
6428 set_bit(BNXT_STATE_OPEN, &bp->state);
6429 bnxt_enable_int(bp);
6430 /* Enable TX queues */
6431 bnxt_tx_enable(bp);
6432 mod_timer(&bp->timer, jiffies + bp->current_interval);
6433 /* Poll link status and check for SFP+ module status */
6434 bnxt_get_port_module_status(bp);
6435
6436 /* VF-reps may need to be re-opened after the PF is re-opened */
6437 if (BNXT_PF(bp))
6438 bnxt_vf_reps_open(bp);
6439 return 0;
6440
6441 open_err:
6442 bnxt_disable_napi(bp);
6443 bnxt_del_napi(bp);
6444
6445 open_err_free_mem:
6446 bnxt_free_skbs(bp);
6447 bnxt_free_irq(bp);
6448 bnxt_free_mem(bp, true);
6449 return rc;
6450 }
6451
6452 /* rtnl_lock held */
6453 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6454 {
6455 int rc = 0;
6456
6457 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
6458 if (rc) {
6459 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
6460 dev_close(bp->dev);
6461 }
6462 return rc;
6463 }
6464
6465 /* rtnl_lock held, open the NIC half way by allocating all resources, but
6466 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline
6467 * self tests.
6468 */
6469 int bnxt_half_open_nic(struct bnxt *bp)
6470 {
6471 int rc = 0;
6472
6473 rc = bnxt_alloc_mem(bp, false);
6474 if (rc) {
6475 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6476 goto half_open_err;
6477 }
6478 rc = bnxt_init_nic(bp, false);
6479 if (rc) {
6480 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6481 goto half_open_err;
6482 }
6483 return 0;
6484
6485 half_open_err:
6486 bnxt_free_skbs(bp);
6487 bnxt_free_mem(bp, false);
6488 dev_close(bp->dev);
6489 return rc;
6490 }
6491
6492 /* rtnl_lock held, this call can only be made after a previous successful
6493 * call to bnxt_half_open_nic().
6494 */
6495 void bnxt_half_close_nic(struct bnxt *bp)
6496 {
6497 bnxt_hwrm_resource_free(bp, false, false);
6498 bnxt_free_skbs(bp);
6499 bnxt_free_mem(bp, false);
6500 }
6501
6502 static int bnxt_open(struct net_device *dev)
6503 {
6504 struct bnxt *bp = netdev_priv(dev);
6505
6506 return __bnxt_open_nic(bp, true, true);
6507 }
6508
6509 static bool bnxt_drv_busy(struct bnxt *bp)
6510 {
6511 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
6512 test_bit(BNXT_STATE_READ_STATS, &bp->state));
6513 }
6514
6515 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6516 {
6517 int rc = 0;
6518
6519 #ifdef CONFIG_BNXT_SRIOV
6520 if (bp->sriov_cfg) {
6521 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
6522 !bp->sriov_cfg,
6523 BNXT_SRIOV_CFG_WAIT_TMO);
6524 if (rc)
6525 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
6526 }
6527
6528 /* Close the VF-reps before closing PF */
6529 if (BNXT_PF(bp))
6530 bnxt_vf_reps_close(bp);
6531 #endif
6532 /* Change device state to avoid TX queue wake up's */
6533 bnxt_tx_disable(bp);
6534
6535 clear_bit(BNXT_STATE_OPEN, &bp->state);
6536 smp_mb__after_atomic();
6537 while (bnxt_drv_busy(bp))
6538 msleep(20);
6539
6540 /* Flush rings and and disable interrupts */
6541 bnxt_shutdown_nic(bp, irq_re_init);
6542
6543 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
6544
6545 bnxt_disable_napi(bp);
6546 del_timer_sync(&bp->timer);
6547 bnxt_free_skbs(bp);
6548
6549 if (irq_re_init) {
6550 bnxt_free_irq(bp);
6551 bnxt_del_napi(bp);
6552 }
6553 bnxt_free_mem(bp, irq_re_init);
6554 return rc;
6555 }
6556
6557 static int bnxt_close(struct net_device *dev)
6558 {
6559 struct bnxt *bp = netdev_priv(dev);
6560
6561 bnxt_close_nic(bp, true, true);
6562 bnxt_hwrm_shutdown_link(bp);
6563 return 0;
6564 }
6565
6566 /* rtnl_lock held */
6567 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6568 {
6569 switch (cmd) {
6570 case SIOCGMIIPHY:
6571 /* fallthru */
6572 case SIOCGMIIREG: {
6573 if (!netif_running(dev))
6574 return -EAGAIN;
6575
6576 return 0;
6577 }
6578
6579 case SIOCSMIIREG:
6580 if (!netif_running(dev))
6581 return -EAGAIN;
6582
6583 return 0;
6584
6585 default:
6586 /* do nothing */
6587 break;
6588 }
6589 return -EOPNOTSUPP;
6590 }
6591
6592 static void
6593 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6594 {
6595 u32 i;
6596 struct bnxt *bp = netdev_priv(dev);
6597
6598 set_bit(BNXT_STATE_READ_STATS, &bp->state);
6599 /* Make sure bnxt_close_nic() sees that we are reading stats before
6600 * we check the BNXT_STATE_OPEN flag.
6601 */
6602 smp_mb__after_atomic();
6603 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6604 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
6605 return;
6606 }
6607
6608 /* TODO check if we need to synchronize with bnxt_close path */
6609 for (i = 0; i < bp->cp_nr_rings; i++) {
6610 struct bnxt_napi *bnapi = bp->bnapi[i];
6611 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6612 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
6613
6614 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
6615 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
6616 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
6617
6618 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
6619 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
6620 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
6621
6622 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
6623 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
6624 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
6625
6626 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
6627 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
6628 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
6629
6630 stats->rx_missed_errors +=
6631 le64_to_cpu(hw_stats->rx_discard_pkts);
6632
6633 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
6634
6635 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
6636 }
6637
6638 if (bp->flags & BNXT_FLAG_PORT_STATS) {
6639 struct rx_port_stats *rx = bp->hw_rx_port_stats;
6640 struct tx_port_stats *tx = bp->hw_tx_port_stats;
6641
6642 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
6643 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
6644 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
6645 le64_to_cpu(rx->rx_ovrsz_frames) +
6646 le64_to_cpu(rx->rx_runt_frames);
6647 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
6648 le64_to_cpu(rx->rx_jbr_frames);
6649 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
6650 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
6651 stats->tx_errors = le64_to_cpu(tx->tx_err);
6652 }
6653 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
6654 }
6655
6656 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
6657 {
6658 struct net_device *dev = bp->dev;
6659 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6660 struct netdev_hw_addr *ha;
6661 u8 *haddr;
6662 int mc_count = 0;
6663 bool update = false;
6664 int off = 0;
6665
6666 netdev_for_each_mc_addr(ha, dev) {
6667 if (mc_count >= BNXT_MAX_MC_ADDRS) {
6668 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6669 vnic->mc_list_count = 0;
6670 return false;
6671 }
6672 haddr = ha->addr;
6673 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
6674 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
6675 update = true;
6676 }
6677 off += ETH_ALEN;
6678 mc_count++;
6679 }
6680 if (mc_count)
6681 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
6682
6683 if (mc_count != vnic->mc_list_count) {
6684 vnic->mc_list_count = mc_count;
6685 update = true;
6686 }
6687 return update;
6688 }
6689
6690 static bool bnxt_uc_list_updated(struct bnxt *bp)
6691 {
6692 struct net_device *dev = bp->dev;
6693 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6694 struct netdev_hw_addr *ha;
6695 int off = 0;
6696
6697 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
6698 return true;
6699
6700 netdev_for_each_uc_addr(ha, dev) {
6701 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
6702 return true;
6703
6704 off += ETH_ALEN;
6705 }
6706 return false;
6707 }
6708
6709 static void bnxt_set_rx_mode(struct net_device *dev)
6710 {
6711 struct bnxt *bp = netdev_priv(dev);
6712 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6713 u32 mask = vnic->rx_mask;
6714 bool mc_update = false;
6715 bool uc_update;
6716
6717 if (!netif_running(dev))
6718 return;
6719
6720 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
6721 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
6722 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
6723
6724 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
6725 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6726
6727 uc_update = bnxt_uc_list_updated(bp);
6728
6729 if (dev->flags & IFF_ALLMULTI) {
6730 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6731 vnic->mc_list_count = 0;
6732 } else {
6733 mc_update = bnxt_mc_list_updated(bp, &mask);
6734 }
6735
6736 if (mask != vnic->rx_mask || uc_update || mc_update) {
6737 vnic->rx_mask = mask;
6738
6739 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
6740 bnxt_queue_sp_work(bp);
6741 }
6742 }
6743
6744 static int bnxt_cfg_rx_mode(struct bnxt *bp)
6745 {
6746 struct net_device *dev = bp->dev;
6747 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6748 struct netdev_hw_addr *ha;
6749 int i, off = 0, rc;
6750 bool uc_update;
6751
6752 netif_addr_lock_bh(dev);
6753 uc_update = bnxt_uc_list_updated(bp);
6754 netif_addr_unlock_bh(dev);
6755
6756 if (!uc_update)
6757 goto skip_uc;
6758
6759 mutex_lock(&bp->hwrm_cmd_lock);
6760 for (i = 1; i < vnic->uc_filter_count; i++) {
6761 struct hwrm_cfa_l2_filter_free_input req = {0};
6762
6763 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
6764 -1);
6765
6766 req.l2_filter_id = vnic->fw_l2_filter_id[i];
6767
6768 rc = _hwrm_send_message(bp, &req, sizeof(req),
6769 HWRM_CMD_TIMEOUT);
6770 }
6771 mutex_unlock(&bp->hwrm_cmd_lock);
6772
6773 vnic->uc_filter_count = 1;
6774
6775 netif_addr_lock_bh(dev);
6776 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
6777 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6778 } else {
6779 netdev_for_each_uc_addr(ha, dev) {
6780 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
6781 off += ETH_ALEN;
6782 vnic->uc_filter_count++;
6783 }
6784 }
6785 netif_addr_unlock_bh(dev);
6786
6787 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
6788 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
6789 if (rc) {
6790 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
6791 rc);
6792 vnic->uc_filter_count = i;
6793 return rc;
6794 }
6795 }
6796
6797 skip_uc:
6798 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
6799 if (rc)
6800 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
6801 rc);
6802
6803 return rc;
6804 }
6805
6806 /* If the chip and firmware supports RFS */
6807 static bool bnxt_rfs_supported(struct bnxt *bp)
6808 {
6809 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
6810 return true;
6811 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6812 return true;
6813 return false;
6814 }
6815
6816 /* If runtime conditions support RFS */
6817 static bool bnxt_rfs_capable(struct bnxt *bp)
6818 {
6819 #ifdef CONFIG_RFS_ACCEL
6820 int vnics, max_vnics, max_rss_ctxs;
6821
6822 if (!(bp->flags & BNXT_FLAG_MSIX_CAP))
6823 return false;
6824
6825 vnics = 1 + bp->rx_nr_rings;
6826 max_vnics = bnxt_get_max_func_vnics(bp);
6827 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
6828
6829 /* RSS contexts not a limiting factor */
6830 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6831 max_rss_ctxs = max_vnics;
6832 if (vnics > max_vnics || vnics > max_rss_ctxs) {
6833 netdev_warn(bp->dev,
6834 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
6835 min(max_rss_ctxs - 1, max_vnics - 1));
6836 return false;
6837 }
6838
6839 return true;
6840 #else
6841 return false;
6842 #endif
6843 }
6844
6845 static netdev_features_t bnxt_fix_features(struct net_device *dev,
6846 netdev_features_t features)
6847 {
6848 struct bnxt *bp = netdev_priv(dev);
6849
6850 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
6851 features &= ~NETIF_F_NTUPLE;
6852
6853 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
6854 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
6855
6856 if (!(features & NETIF_F_GRO))
6857 features &= ~NETIF_F_GRO_HW;
6858
6859 if (features & NETIF_F_GRO_HW)
6860 features &= ~NETIF_F_LRO;
6861
6862 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
6863 * turned on or off together.
6864 */
6865 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
6866 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
6867 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
6868 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6869 NETIF_F_HW_VLAN_STAG_RX);
6870 else
6871 features |= NETIF_F_HW_VLAN_CTAG_RX |
6872 NETIF_F_HW_VLAN_STAG_RX;
6873 }
6874 #ifdef CONFIG_BNXT_SRIOV
6875 if (BNXT_VF(bp)) {
6876 if (bp->vf.vlan) {
6877 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6878 NETIF_F_HW_VLAN_STAG_RX);
6879 }
6880 }
6881 #endif
6882 return features;
6883 }
6884
6885 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
6886 {
6887 struct bnxt *bp = netdev_priv(dev);
6888 u32 flags = bp->flags;
6889 u32 changes;
6890 int rc = 0;
6891 bool re_init = false;
6892 bool update_tpa = false;
6893
6894 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
6895 if (features & NETIF_F_GRO_HW)
6896 flags |= BNXT_FLAG_GRO;
6897 else if (features & NETIF_F_LRO)
6898 flags |= BNXT_FLAG_LRO;
6899
6900 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
6901 flags &= ~BNXT_FLAG_TPA;
6902
6903 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6904 flags |= BNXT_FLAG_STRIP_VLAN;
6905
6906 if (features & NETIF_F_NTUPLE)
6907 flags |= BNXT_FLAG_RFS;
6908
6909 changes = flags ^ bp->flags;
6910 if (changes & BNXT_FLAG_TPA) {
6911 update_tpa = true;
6912 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
6913 (flags & BNXT_FLAG_TPA) == 0)
6914 re_init = true;
6915 }
6916
6917 if (changes & ~BNXT_FLAG_TPA)
6918 re_init = true;
6919
6920 if (flags != bp->flags) {
6921 u32 old_flags = bp->flags;
6922
6923 bp->flags = flags;
6924
6925 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6926 if (update_tpa)
6927 bnxt_set_ring_params(bp);
6928 return rc;
6929 }
6930
6931 if (re_init) {
6932 bnxt_close_nic(bp, false, false);
6933 if (update_tpa)
6934 bnxt_set_ring_params(bp);
6935
6936 return bnxt_open_nic(bp, false, false);
6937 }
6938 if (update_tpa) {
6939 rc = bnxt_set_tpa(bp,
6940 (flags & BNXT_FLAG_TPA) ?
6941 true : false);
6942 if (rc)
6943 bp->flags = old_flags;
6944 }
6945 }
6946 return rc;
6947 }
6948
6949 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
6950 {
6951 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
6952 int i = bnapi->index;
6953
6954 if (!txr)
6955 return;
6956
6957 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
6958 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
6959 txr->tx_cons);
6960 }
6961
6962 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
6963 {
6964 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
6965 int i = bnapi->index;
6966
6967 if (!rxr)
6968 return;
6969
6970 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
6971 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
6972 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
6973 rxr->rx_sw_agg_prod);
6974 }
6975
6976 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
6977 {
6978 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6979 int i = bnapi->index;
6980
6981 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
6982 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
6983 }
6984
6985 static void bnxt_dbg_dump_states(struct bnxt *bp)
6986 {
6987 int i;
6988 struct bnxt_napi *bnapi;
6989
6990 for (i = 0; i < bp->cp_nr_rings; i++) {
6991 bnapi = bp->bnapi[i];
6992 if (netif_msg_drv(bp)) {
6993 bnxt_dump_tx_sw_state(bnapi);
6994 bnxt_dump_rx_sw_state(bnapi);
6995 bnxt_dump_cp_sw_state(bnapi);
6996 }
6997 }
6998 }
6999
7000 static void bnxt_reset_task(struct bnxt *bp, bool silent)
7001 {
7002 if (!silent)
7003 bnxt_dbg_dump_states(bp);
7004 if (netif_running(bp->dev)) {
7005 int rc;
7006
7007 if (!silent)
7008 bnxt_ulp_stop(bp);
7009 bnxt_close_nic(bp, false, false);
7010 rc = bnxt_open_nic(bp, false, false);
7011 if (!silent && !rc)
7012 bnxt_ulp_start(bp);
7013 }
7014 }
7015
7016 static void bnxt_tx_timeout(struct net_device *dev)
7017 {
7018 struct bnxt *bp = netdev_priv(dev);
7019
7020 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
7021 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
7022 bnxt_queue_sp_work(bp);
7023 }
7024
7025 #ifdef CONFIG_NET_POLL_CONTROLLER
7026 static void bnxt_poll_controller(struct net_device *dev)
7027 {
7028 struct bnxt *bp = netdev_priv(dev);
7029 int i;
7030
7031 /* Only process tx rings/combined rings in netpoll mode. */
7032 for (i = 0; i < bp->tx_nr_rings; i++) {
7033 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
7034
7035 napi_schedule(&txr->bnapi->napi);
7036 }
7037 }
7038 #endif
7039
7040 static void bnxt_timer(struct timer_list *t)
7041 {
7042 struct bnxt *bp = from_timer(bp, t, timer);
7043 struct net_device *dev = bp->dev;
7044
7045 if (!netif_running(dev))
7046 return;
7047
7048 if (atomic_read(&bp->intr_sem) != 0)
7049 goto bnxt_restart_timer;
7050
7051 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
7052 bp->stats_coal_ticks) {
7053 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
7054 bnxt_queue_sp_work(bp);
7055 }
7056
7057 if (bnxt_tc_flower_enabled(bp)) {
7058 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
7059 bnxt_queue_sp_work(bp);
7060 }
7061 bnxt_restart_timer:
7062 mod_timer(&bp->timer, jiffies + bp->current_interval);
7063 }
7064
7065 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
7066 {
7067 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
7068 * set. If the device is being closed, bnxt_close() may be holding
7069 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
7070 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
7071 */
7072 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7073 rtnl_lock();
7074 }
7075
7076 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
7077 {
7078 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7079 rtnl_unlock();
7080 }
7081
7082 /* Only called from bnxt_sp_task() */
7083 static void bnxt_reset(struct bnxt *bp, bool silent)
7084 {
7085 bnxt_rtnl_lock_sp(bp);
7086 if (test_bit(BNXT_STATE_OPEN, &bp->state))
7087 bnxt_reset_task(bp, silent);
7088 bnxt_rtnl_unlock_sp(bp);
7089 }
7090
7091 static void bnxt_cfg_ntp_filters(struct bnxt *);
7092
7093 static void bnxt_sp_task(struct work_struct *work)
7094 {
7095 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
7096
7097 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7098 smp_mb__after_atomic();
7099 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7100 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7101 return;
7102 }
7103
7104 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
7105 bnxt_cfg_rx_mode(bp);
7106
7107 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
7108 bnxt_cfg_ntp_filters(bp);
7109 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
7110 bnxt_hwrm_exec_fwd_req(bp);
7111 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7112 bnxt_hwrm_tunnel_dst_port_alloc(
7113 bp, bp->vxlan_port,
7114 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7115 }
7116 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7117 bnxt_hwrm_tunnel_dst_port_free(
7118 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7119 }
7120 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7121 bnxt_hwrm_tunnel_dst_port_alloc(
7122 bp, bp->nge_port,
7123 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7124 }
7125 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7126 bnxt_hwrm_tunnel_dst_port_free(
7127 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7128 }
7129 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
7130 bnxt_hwrm_port_qstats(bp);
7131
7132 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
7133 int rc;
7134
7135 mutex_lock(&bp->link_lock);
7136 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
7137 &bp->sp_event))
7138 bnxt_hwrm_phy_qcaps(bp);
7139
7140 rc = bnxt_update_link(bp, true);
7141 mutex_unlock(&bp->link_lock);
7142 if (rc)
7143 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
7144 rc);
7145 }
7146 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
7147 mutex_lock(&bp->link_lock);
7148 bnxt_get_port_module_status(bp);
7149 mutex_unlock(&bp->link_lock);
7150 }
7151
7152 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
7153 bnxt_tc_flow_stats_work(bp);
7154
7155 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
7156 * must be the last functions to be called before exiting.
7157 */
7158 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
7159 bnxt_reset(bp, false);
7160
7161 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
7162 bnxt_reset(bp, true);
7163
7164 smp_mb__before_atomic();
7165 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7166 }
7167
7168 /* Under rtnl_lock */
7169 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
7170 int tx_xdp)
7171 {
7172 int max_rx, max_tx, tx_sets = 1;
7173 int tx_rings_needed;
7174 int rc;
7175
7176 if (tcs)
7177 tx_sets = tcs;
7178
7179 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
7180 if (rc)
7181 return rc;
7182
7183 if (max_rx < rx)
7184 return -ENOMEM;
7185
7186 tx_rings_needed = tx * tx_sets + tx_xdp;
7187 if (max_tx < tx_rings_needed)
7188 return -ENOMEM;
7189
7190 return bnxt_hwrm_check_tx_rings(bp, tx_rings_needed);
7191 }
7192
7193 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
7194 {
7195 if (bp->bar2) {
7196 pci_iounmap(pdev, bp->bar2);
7197 bp->bar2 = NULL;
7198 }
7199
7200 if (bp->bar1) {
7201 pci_iounmap(pdev, bp->bar1);
7202 bp->bar1 = NULL;
7203 }
7204
7205 if (bp->bar0) {
7206 pci_iounmap(pdev, bp->bar0);
7207 bp->bar0 = NULL;
7208 }
7209 }
7210
7211 static void bnxt_cleanup_pci(struct bnxt *bp)
7212 {
7213 bnxt_unmap_bars(bp, bp->pdev);
7214 pci_release_regions(bp->pdev);
7215 pci_disable_device(bp->pdev);
7216 }
7217
7218 static void bnxt_init_dflt_coal(struct bnxt *bp)
7219 {
7220 struct bnxt_coal *coal;
7221
7222 /* Tick values in micro seconds.
7223 * 1 coal_buf x bufs_per_record = 1 completion record.
7224 */
7225 coal = &bp->rx_coal;
7226 coal->coal_ticks = 14;
7227 coal->coal_bufs = 30;
7228 coal->coal_ticks_irq = 1;
7229 coal->coal_bufs_irq = 2;
7230 coal->idle_thresh = 25;
7231 coal->bufs_per_record = 2;
7232 coal->budget = 64; /* NAPI budget */
7233
7234 coal = &bp->tx_coal;
7235 coal->coal_ticks = 28;
7236 coal->coal_bufs = 30;
7237 coal->coal_ticks_irq = 2;
7238 coal->coal_bufs_irq = 2;
7239 coal->bufs_per_record = 1;
7240
7241 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
7242 }
7243
7244 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
7245 {
7246 int rc;
7247 struct bnxt *bp = netdev_priv(dev);
7248
7249 SET_NETDEV_DEV(dev, &pdev->dev);
7250
7251 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7252 rc = pci_enable_device(pdev);
7253 if (rc) {
7254 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
7255 goto init_err;
7256 }
7257
7258 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7259 dev_err(&pdev->dev,
7260 "Cannot find PCI device base address, aborting\n");
7261 rc = -ENODEV;
7262 goto init_err_disable;
7263 }
7264
7265 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7266 if (rc) {
7267 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
7268 goto init_err_disable;
7269 }
7270
7271 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
7272 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
7273 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
7274 goto init_err_disable;
7275 }
7276
7277 pci_set_master(pdev);
7278
7279 bp->dev = dev;
7280 bp->pdev = pdev;
7281
7282 bp->bar0 = pci_ioremap_bar(pdev, 0);
7283 if (!bp->bar0) {
7284 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
7285 rc = -ENOMEM;
7286 goto init_err_release;
7287 }
7288
7289 bp->bar1 = pci_ioremap_bar(pdev, 2);
7290 if (!bp->bar1) {
7291 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
7292 rc = -ENOMEM;
7293 goto init_err_release;
7294 }
7295
7296 bp->bar2 = pci_ioremap_bar(pdev, 4);
7297 if (!bp->bar2) {
7298 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
7299 rc = -ENOMEM;
7300 goto init_err_release;
7301 }
7302
7303 pci_enable_pcie_error_reporting(pdev);
7304
7305 INIT_WORK(&bp->sp_task, bnxt_sp_task);
7306
7307 spin_lock_init(&bp->ntp_fltr_lock);
7308
7309 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
7310 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
7311
7312 bnxt_init_dflt_coal(bp);
7313
7314 timer_setup(&bp->timer, bnxt_timer, 0);
7315 bp->current_interval = BNXT_TIMER_INTERVAL;
7316
7317 clear_bit(BNXT_STATE_OPEN, &bp->state);
7318 return 0;
7319
7320 init_err_release:
7321 bnxt_unmap_bars(bp, pdev);
7322 pci_release_regions(pdev);
7323
7324 init_err_disable:
7325 pci_disable_device(pdev);
7326
7327 init_err:
7328 return rc;
7329 }
7330
7331 /* rtnl_lock held */
7332 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
7333 {
7334 struct sockaddr *addr = p;
7335 struct bnxt *bp = netdev_priv(dev);
7336 int rc = 0;
7337
7338 if (!is_valid_ether_addr(addr->sa_data))
7339 return -EADDRNOTAVAIL;
7340
7341 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
7342 return 0;
7343
7344 rc = bnxt_approve_mac(bp, addr->sa_data);
7345 if (rc)
7346 return rc;
7347
7348 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7349 if (netif_running(dev)) {
7350 bnxt_close_nic(bp, false, false);
7351 rc = bnxt_open_nic(bp, false, false);
7352 }
7353
7354 return rc;
7355 }
7356
7357 /* rtnl_lock held */
7358 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
7359 {
7360 struct bnxt *bp = netdev_priv(dev);
7361
7362 if (netif_running(dev))
7363 bnxt_close_nic(bp, false, false);
7364
7365 dev->mtu = new_mtu;
7366 bnxt_set_ring_params(bp);
7367
7368 if (netif_running(dev))
7369 return bnxt_open_nic(bp, false, false);
7370
7371 return 0;
7372 }
7373
7374 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
7375 {
7376 struct bnxt *bp = netdev_priv(dev);
7377 bool sh = false;
7378 int rc;
7379
7380 if (tc > bp->max_tc) {
7381 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
7382 tc, bp->max_tc);
7383 return -EINVAL;
7384 }
7385
7386 if (netdev_get_num_tc(dev) == tc)
7387 return 0;
7388
7389 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7390 sh = true;
7391
7392 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
7393 sh, tc, bp->tx_nr_rings_xdp);
7394 if (rc)
7395 return rc;
7396
7397 /* Needs to close the device and do hw resource re-allocations */
7398 if (netif_running(bp->dev))
7399 bnxt_close_nic(bp, true, false);
7400
7401 if (tc) {
7402 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
7403 netdev_set_num_tc(dev, tc);
7404 } else {
7405 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
7406 netdev_reset_tc(dev);
7407 }
7408 bp->tx_nr_rings += bp->tx_nr_rings_xdp;
7409 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7410 bp->tx_nr_rings + bp->rx_nr_rings;
7411 bp->num_stat_ctxs = bp->cp_nr_rings;
7412
7413 if (netif_running(bp->dev))
7414 return bnxt_open_nic(bp, true, false);
7415
7416 return 0;
7417 }
7418
7419 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
7420 void *cb_priv)
7421 {
7422 struct bnxt *bp = cb_priv;
7423
7424 if (!bnxt_tc_flower_enabled(bp) || !tc_can_offload(bp->dev))
7425 return -EOPNOTSUPP;
7426
7427 switch (type) {
7428 case TC_SETUP_CLSFLOWER:
7429 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
7430 default:
7431 return -EOPNOTSUPP;
7432 }
7433 }
7434
7435 static int bnxt_setup_tc_block(struct net_device *dev,
7436 struct tc_block_offload *f)
7437 {
7438 struct bnxt *bp = netdev_priv(dev);
7439
7440 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
7441 return -EOPNOTSUPP;
7442
7443 switch (f->command) {
7444 case TC_BLOCK_BIND:
7445 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb,
7446 bp, bp);
7447 case TC_BLOCK_UNBIND:
7448 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp);
7449 return 0;
7450 default:
7451 return -EOPNOTSUPP;
7452 }
7453 }
7454
7455 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
7456 void *type_data)
7457 {
7458 switch (type) {
7459 case TC_SETUP_BLOCK:
7460 return bnxt_setup_tc_block(dev, type_data);
7461 case TC_SETUP_QDISC_MQPRIO: {
7462 struct tc_mqprio_qopt *mqprio = type_data;
7463
7464 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
7465
7466 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
7467 }
7468 default:
7469 return -EOPNOTSUPP;
7470 }
7471 }
7472
7473 #ifdef CONFIG_RFS_ACCEL
7474 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
7475 struct bnxt_ntuple_filter *f2)
7476 {
7477 struct flow_keys *keys1 = &f1->fkeys;
7478 struct flow_keys *keys2 = &f2->fkeys;
7479
7480 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
7481 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
7482 keys1->ports.ports == keys2->ports.ports &&
7483 keys1->basic.ip_proto == keys2->basic.ip_proto &&
7484 keys1->basic.n_proto == keys2->basic.n_proto &&
7485 keys1->control.flags == keys2->control.flags &&
7486 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
7487 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
7488 return true;
7489
7490 return false;
7491 }
7492
7493 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
7494 u16 rxq_index, u32 flow_id)
7495 {
7496 struct bnxt *bp = netdev_priv(dev);
7497 struct bnxt_ntuple_filter *fltr, *new_fltr;
7498 struct flow_keys *fkeys;
7499 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
7500 int rc = 0, idx, bit_id, l2_idx = 0;
7501 struct hlist_head *head;
7502
7503 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
7504 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7505 int off = 0, j;
7506
7507 netif_addr_lock_bh(dev);
7508 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
7509 if (ether_addr_equal(eth->h_dest,
7510 vnic->uc_list + off)) {
7511 l2_idx = j + 1;
7512 break;
7513 }
7514 }
7515 netif_addr_unlock_bh(dev);
7516 if (!l2_idx)
7517 return -EINVAL;
7518 }
7519 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
7520 if (!new_fltr)
7521 return -ENOMEM;
7522
7523 fkeys = &new_fltr->fkeys;
7524 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
7525 rc = -EPROTONOSUPPORT;
7526 goto err_free;
7527 }
7528
7529 if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
7530 fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
7531 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
7532 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
7533 rc = -EPROTONOSUPPORT;
7534 goto err_free;
7535 }
7536 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
7537 bp->hwrm_spec_code < 0x10601) {
7538 rc = -EPROTONOSUPPORT;
7539 goto err_free;
7540 }
7541 if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
7542 bp->hwrm_spec_code < 0x10601) {
7543 rc = -EPROTONOSUPPORT;
7544 goto err_free;
7545 }
7546
7547 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
7548 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
7549
7550 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
7551 head = &bp->ntp_fltr_hash_tbl[idx];
7552 rcu_read_lock();
7553 hlist_for_each_entry_rcu(fltr, head, hash) {
7554 if (bnxt_fltr_match(fltr, new_fltr)) {
7555 rcu_read_unlock();
7556 rc = 0;
7557 goto err_free;
7558 }
7559 }
7560 rcu_read_unlock();
7561
7562 spin_lock_bh(&bp->ntp_fltr_lock);
7563 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
7564 BNXT_NTP_FLTR_MAX_FLTR, 0);
7565 if (bit_id < 0) {
7566 spin_unlock_bh(&bp->ntp_fltr_lock);
7567 rc = -ENOMEM;
7568 goto err_free;
7569 }
7570
7571 new_fltr->sw_id = (u16)bit_id;
7572 new_fltr->flow_id = flow_id;
7573 new_fltr->l2_fltr_idx = l2_idx;
7574 new_fltr->rxq = rxq_index;
7575 hlist_add_head_rcu(&new_fltr->hash, head);
7576 bp->ntp_fltr_count++;
7577 spin_unlock_bh(&bp->ntp_fltr_lock);
7578
7579 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
7580 bnxt_queue_sp_work(bp);
7581
7582 return new_fltr->sw_id;
7583
7584 err_free:
7585 kfree(new_fltr);
7586 return rc;
7587 }
7588
7589 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
7590 {
7591 int i;
7592
7593 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
7594 struct hlist_head *head;
7595 struct hlist_node *tmp;
7596 struct bnxt_ntuple_filter *fltr;
7597 int rc;
7598
7599 head = &bp->ntp_fltr_hash_tbl[i];
7600 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
7601 bool del = false;
7602
7603 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
7604 if (rps_may_expire_flow(bp->dev, fltr->rxq,
7605 fltr->flow_id,
7606 fltr->sw_id)) {
7607 bnxt_hwrm_cfa_ntuple_filter_free(bp,
7608 fltr);
7609 del = true;
7610 }
7611 } else {
7612 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
7613 fltr);
7614 if (rc)
7615 del = true;
7616 else
7617 set_bit(BNXT_FLTR_VALID, &fltr->state);
7618 }
7619
7620 if (del) {
7621 spin_lock_bh(&bp->ntp_fltr_lock);
7622 hlist_del_rcu(&fltr->hash);
7623 bp->ntp_fltr_count--;
7624 spin_unlock_bh(&bp->ntp_fltr_lock);
7625 synchronize_rcu();
7626 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
7627 kfree(fltr);
7628 }
7629 }
7630 }
7631 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
7632 netdev_info(bp->dev, "Receive PF driver unload event!");
7633 }
7634
7635 #else
7636
7637 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
7638 {
7639 }
7640
7641 #endif /* CONFIG_RFS_ACCEL */
7642
7643 static void bnxt_udp_tunnel_add(struct net_device *dev,
7644 struct udp_tunnel_info *ti)
7645 {
7646 struct bnxt *bp = netdev_priv(dev);
7647
7648 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
7649 return;
7650
7651 if (!netif_running(dev))
7652 return;
7653
7654 switch (ti->type) {
7655 case UDP_TUNNEL_TYPE_VXLAN:
7656 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
7657 return;
7658
7659 bp->vxlan_port_cnt++;
7660 if (bp->vxlan_port_cnt == 1) {
7661 bp->vxlan_port = ti->port;
7662 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
7663 bnxt_queue_sp_work(bp);
7664 }
7665 break;
7666 case UDP_TUNNEL_TYPE_GENEVE:
7667 if (bp->nge_port_cnt && bp->nge_port != ti->port)
7668 return;
7669
7670 bp->nge_port_cnt++;
7671 if (bp->nge_port_cnt == 1) {
7672 bp->nge_port = ti->port;
7673 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
7674 }
7675 break;
7676 default:
7677 return;
7678 }
7679
7680 bnxt_queue_sp_work(bp);
7681 }
7682
7683 static void bnxt_udp_tunnel_del(struct net_device *dev,
7684 struct udp_tunnel_info *ti)
7685 {
7686 struct bnxt *bp = netdev_priv(dev);
7687
7688 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
7689 return;
7690
7691 if (!netif_running(dev))
7692 return;
7693
7694 switch (ti->type) {
7695 case UDP_TUNNEL_TYPE_VXLAN:
7696 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
7697 return;
7698 bp->vxlan_port_cnt--;
7699
7700 if (bp->vxlan_port_cnt != 0)
7701 return;
7702
7703 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
7704 break;
7705 case UDP_TUNNEL_TYPE_GENEVE:
7706 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
7707 return;
7708 bp->nge_port_cnt--;
7709
7710 if (bp->nge_port_cnt != 0)
7711 return;
7712
7713 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
7714 break;
7715 default:
7716 return;
7717 }
7718
7719 bnxt_queue_sp_work(bp);
7720 }
7721
7722 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7723 struct net_device *dev, u32 filter_mask,
7724 int nlflags)
7725 {
7726 struct bnxt *bp = netdev_priv(dev);
7727
7728 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
7729 nlflags, filter_mask, NULL);
7730 }
7731
7732 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
7733 u16 flags)
7734 {
7735 struct bnxt *bp = netdev_priv(dev);
7736 struct nlattr *attr, *br_spec;
7737 int rem, rc = 0;
7738
7739 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
7740 return -EOPNOTSUPP;
7741
7742 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7743 if (!br_spec)
7744 return -EINVAL;
7745
7746 nla_for_each_nested(attr, br_spec, rem) {
7747 u16 mode;
7748
7749 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7750 continue;
7751
7752 if (nla_len(attr) < sizeof(mode))
7753 return -EINVAL;
7754
7755 mode = nla_get_u16(attr);
7756 if (mode == bp->br_mode)
7757 break;
7758
7759 rc = bnxt_hwrm_set_br_mode(bp, mode);
7760 if (!rc)
7761 bp->br_mode = mode;
7762 break;
7763 }
7764 return rc;
7765 }
7766
7767 static int bnxt_get_phys_port_name(struct net_device *dev, char *buf,
7768 size_t len)
7769 {
7770 struct bnxt *bp = netdev_priv(dev);
7771 int rc;
7772
7773 /* The PF and it's VF-reps only support the switchdev framework */
7774 if (!BNXT_PF(bp))
7775 return -EOPNOTSUPP;
7776
7777 rc = snprintf(buf, len, "p%d", bp->pf.port_id);
7778
7779 if (rc >= len)
7780 return -EOPNOTSUPP;
7781 return 0;
7782 }
7783
7784 int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr)
7785 {
7786 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
7787 return -EOPNOTSUPP;
7788
7789 /* The PF and it's VF-reps only support the switchdev framework */
7790 if (!BNXT_PF(bp))
7791 return -EOPNOTSUPP;
7792
7793 switch (attr->id) {
7794 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
7795 /* In SRIOV each PF-pool (PF + child VFs) serves as a
7796 * switching domain, the PF's perm mac-addr can be used
7797 * as the unique parent-id
7798 */
7799 attr->u.ppid.id_len = ETH_ALEN;
7800 ether_addr_copy(attr->u.ppid.id, bp->pf.mac_addr);
7801 break;
7802 default:
7803 return -EOPNOTSUPP;
7804 }
7805 return 0;
7806 }
7807
7808 static int bnxt_swdev_port_attr_get(struct net_device *dev,
7809 struct switchdev_attr *attr)
7810 {
7811 return bnxt_port_attr_get(netdev_priv(dev), attr);
7812 }
7813
7814 static const struct switchdev_ops bnxt_switchdev_ops = {
7815 .switchdev_port_attr_get = bnxt_swdev_port_attr_get
7816 };
7817
7818 static const struct net_device_ops bnxt_netdev_ops = {
7819 .ndo_open = bnxt_open,
7820 .ndo_start_xmit = bnxt_start_xmit,
7821 .ndo_stop = bnxt_close,
7822 .ndo_get_stats64 = bnxt_get_stats64,
7823 .ndo_set_rx_mode = bnxt_set_rx_mode,
7824 .ndo_do_ioctl = bnxt_ioctl,
7825 .ndo_validate_addr = eth_validate_addr,
7826 .ndo_set_mac_address = bnxt_change_mac_addr,
7827 .ndo_change_mtu = bnxt_change_mtu,
7828 .ndo_fix_features = bnxt_fix_features,
7829 .ndo_set_features = bnxt_set_features,
7830 .ndo_tx_timeout = bnxt_tx_timeout,
7831 #ifdef CONFIG_BNXT_SRIOV
7832 .ndo_get_vf_config = bnxt_get_vf_config,
7833 .ndo_set_vf_mac = bnxt_set_vf_mac,
7834 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
7835 .ndo_set_vf_rate = bnxt_set_vf_bw,
7836 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
7837 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
7838 #endif
7839 #ifdef CONFIG_NET_POLL_CONTROLLER
7840 .ndo_poll_controller = bnxt_poll_controller,
7841 #endif
7842 .ndo_setup_tc = bnxt_setup_tc,
7843 #ifdef CONFIG_RFS_ACCEL
7844 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
7845 #endif
7846 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add,
7847 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del,
7848 .ndo_bpf = bnxt_xdp,
7849 .ndo_bridge_getlink = bnxt_bridge_getlink,
7850 .ndo_bridge_setlink = bnxt_bridge_setlink,
7851 .ndo_get_phys_port_name = bnxt_get_phys_port_name
7852 };
7853
7854 static void bnxt_remove_one(struct pci_dev *pdev)
7855 {
7856 struct net_device *dev = pci_get_drvdata(pdev);
7857 struct bnxt *bp = netdev_priv(dev);
7858
7859 if (BNXT_PF(bp)) {
7860 bnxt_sriov_disable(bp);
7861 bnxt_dl_unregister(bp);
7862 }
7863
7864 pci_disable_pcie_error_reporting(pdev);
7865 unregister_netdev(dev);
7866 bnxt_shutdown_tc(bp);
7867 bnxt_cancel_sp_work(bp);
7868 bp->sp_event = 0;
7869
7870 bnxt_clear_int_mode(bp);
7871 bnxt_hwrm_func_drv_unrgtr(bp);
7872 bnxt_free_hwrm_resources(bp);
7873 bnxt_free_hwrm_short_cmd_req(bp);
7874 bnxt_ethtool_free(bp);
7875 bnxt_dcb_free(bp);
7876 kfree(bp->edev);
7877 bp->edev = NULL;
7878 bnxt_cleanup_pci(bp);
7879 free_netdev(dev);
7880 }
7881
7882 static int bnxt_probe_phy(struct bnxt *bp)
7883 {
7884 int rc = 0;
7885 struct bnxt_link_info *link_info = &bp->link_info;
7886
7887 rc = bnxt_hwrm_phy_qcaps(bp);
7888 if (rc) {
7889 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
7890 rc);
7891 return rc;
7892 }
7893 mutex_init(&bp->link_lock);
7894
7895 rc = bnxt_update_link(bp, false);
7896 if (rc) {
7897 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
7898 rc);
7899 return rc;
7900 }
7901
7902 /* Older firmware does not have supported_auto_speeds, so assume
7903 * that all supported speeds can be autonegotiated.
7904 */
7905 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
7906 link_info->support_auto_speeds = link_info->support_speeds;
7907
7908 /*initialize the ethool setting copy with NVM settings */
7909 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
7910 link_info->autoneg = BNXT_AUTONEG_SPEED;
7911 if (bp->hwrm_spec_code >= 0x10201) {
7912 if (link_info->auto_pause_setting &
7913 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
7914 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7915 } else {
7916 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7917 }
7918 link_info->advertising = link_info->auto_link_speeds;
7919 } else {
7920 link_info->req_link_speed = link_info->force_link_speed;
7921 link_info->req_duplex = link_info->duplex_setting;
7922 }
7923 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
7924 link_info->req_flow_ctrl =
7925 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
7926 else
7927 link_info->req_flow_ctrl = link_info->force_pause_setting;
7928 return rc;
7929 }
7930
7931 static int bnxt_get_max_irq(struct pci_dev *pdev)
7932 {
7933 u16 ctrl;
7934
7935 if (!pdev->msix_cap)
7936 return 1;
7937
7938 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
7939 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
7940 }
7941
7942 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7943 int *max_cp)
7944 {
7945 int max_ring_grps = 0;
7946
7947 #ifdef CONFIG_BNXT_SRIOV
7948 if (!BNXT_PF(bp)) {
7949 *max_tx = bp->vf.max_tx_rings;
7950 *max_rx = bp->vf.max_rx_rings;
7951 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
7952 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
7953 max_ring_grps = bp->vf.max_hw_ring_grps;
7954 } else
7955 #endif
7956 {
7957 *max_tx = bp->pf.max_tx_rings;
7958 *max_rx = bp->pf.max_rx_rings;
7959 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
7960 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
7961 max_ring_grps = bp->pf.max_hw_ring_grps;
7962 }
7963 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
7964 *max_cp -= 1;
7965 *max_rx -= 2;
7966 }
7967 if (bp->flags & BNXT_FLAG_AGG_RINGS)
7968 *max_rx >>= 1;
7969 *max_rx = min_t(int, *max_rx, max_ring_grps);
7970 }
7971
7972 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
7973 {
7974 int rx, tx, cp;
7975
7976 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
7977 if (!rx || !tx || !cp)
7978 return -ENOMEM;
7979
7980 *max_rx = rx;
7981 *max_tx = tx;
7982 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
7983 }
7984
7985 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7986 bool shared)
7987 {
7988 int rc;
7989
7990 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
7991 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
7992 /* Not enough rings, try disabling agg rings. */
7993 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
7994 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
7995 if (rc)
7996 return rc;
7997 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
7998 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
7999 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
8000 bnxt_set_ring_params(bp);
8001 }
8002
8003 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
8004 int max_cp, max_stat, max_irq;
8005
8006 /* Reserve minimum resources for RoCE */
8007 max_cp = bnxt_get_max_func_cp_rings(bp);
8008 max_stat = bnxt_get_max_func_stat_ctxs(bp);
8009 max_irq = bnxt_get_max_func_irqs(bp);
8010 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
8011 max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
8012 max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
8013 return 0;
8014
8015 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
8016 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
8017 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
8018 max_cp = min_t(int, max_cp, max_irq);
8019 max_cp = min_t(int, max_cp, max_stat);
8020 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
8021 if (rc)
8022 rc = 0;
8023 }
8024 return rc;
8025 }
8026
8027 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
8028 {
8029 int dflt_rings, max_rx_rings, max_tx_rings, rc;
8030
8031 if (sh)
8032 bp->flags |= BNXT_FLAG_SHARED_RINGS;
8033 dflt_rings = netif_get_num_default_rss_queues();
8034 /* Reduce default rings to reduce memory usage on multi-port cards */
8035 if (bp->port_count > 1)
8036 dflt_rings = min_t(int, dflt_rings, 4);
8037 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
8038 if (rc)
8039 return rc;
8040 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
8041 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
8042
8043 rc = bnxt_hwrm_reserve_tx_rings(bp, &bp->tx_nr_rings_per_tc);
8044 if (rc)
8045 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
8046
8047 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
8048 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
8049 bp->tx_nr_rings + bp->rx_nr_rings;
8050 bp->num_stat_ctxs = bp->cp_nr_rings;
8051 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8052 bp->rx_nr_rings++;
8053 bp->cp_nr_rings++;
8054 }
8055 return rc;
8056 }
8057
8058 void bnxt_restore_pf_fw_resources(struct bnxt *bp)
8059 {
8060 ASSERT_RTNL();
8061 bnxt_hwrm_func_qcaps(bp);
8062 bnxt_subtract_ulp_resources(bp, BNXT_ROCE_ULP);
8063 }
8064
8065 static int bnxt_init_mac_addr(struct bnxt *bp)
8066 {
8067 int rc = 0;
8068
8069 if (BNXT_PF(bp)) {
8070 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
8071 } else {
8072 #ifdef CONFIG_BNXT_SRIOV
8073 struct bnxt_vf_info *vf = &bp->vf;
8074
8075 if (is_valid_ether_addr(vf->mac_addr)) {
8076 /* overwrite netdev dev_adr with admin VF MAC */
8077 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
8078 } else {
8079 eth_hw_addr_random(bp->dev);
8080 rc = bnxt_approve_mac(bp, bp->dev->dev_addr);
8081 }
8082 #endif
8083 }
8084 return rc;
8085 }
8086
8087 static void bnxt_parse_log_pcie_link(struct bnxt *bp)
8088 {
8089 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
8090 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
8091
8092 if (pcie_get_minimum_link(pci_physfn(bp->pdev), &speed, &width) ||
8093 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
8094 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
8095 else
8096 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
8097 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
8098 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
8099 speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
8100 "Unknown", width);
8101 }
8102
8103 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8104 {
8105 static int version_printed;
8106 struct net_device *dev;
8107 struct bnxt *bp;
8108 int rc, max_irqs;
8109
8110 if (pci_is_bridge(pdev))
8111 return -ENODEV;
8112
8113 if (version_printed++ == 0)
8114 pr_info("%s", version);
8115
8116 max_irqs = bnxt_get_max_irq(pdev);
8117 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
8118 if (!dev)
8119 return -ENOMEM;
8120
8121 bp = netdev_priv(dev);
8122
8123 if (bnxt_vf_pciid(ent->driver_data))
8124 bp->flags |= BNXT_FLAG_VF;
8125
8126 if (pdev->msix_cap)
8127 bp->flags |= BNXT_FLAG_MSIX_CAP;
8128
8129 rc = bnxt_init_board(pdev, dev);
8130 if (rc < 0)
8131 goto init_err_free;
8132
8133 dev->netdev_ops = &bnxt_netdev_ops;
8134 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
8135 dev->ethtool_ops = &bnxt_ethtool_ops;
8136 SWITCHDEV_SET_OPS(dev, &bnxt_switchdev_ops);
8137 pci_set_drvdata(pdev, dev);
8138
8139 rc = bnxt_alloc_hwrm_resources(bp);
8140 if (rc)
8141 goto init_err_pci_clean;
8142
8143 mutex_init(&bp->hwrm_cmd_lock);
8144 rc = bnxt_hwrm_ver_get(bp);
8145 if (rc)
8146 goto init_err_pci_clean;
8147
8148 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
8149 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
8150 if (rc)
8151 goto init_err_pci_clean;
8152 }
8153
8154 rc = bnxt_hwrm_func_reset(bp);
8155 if (rc)
8156 goto init_err_pci_clean;
8157
8158 bnxt_hwrm_fw_set_time(bp);
8159
8160 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
8161 NETIF_F_TSO | NETIF_F_TSO6 |
8162 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
8163 NETIF_F_GSO_IPXIP4 |
8164 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
8165 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
8166 NETIF_F_RXCSUM | NETIF_F_GRO;
8167
8168 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
8169 dev->hw_features |= NETIF_F_LRO;
8170
8171 dev->hw_enc_features =
8172 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
8173 NETIF_F_TSO | NETIF_F_TSO6 |
8174 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
8175 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
8176 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
8177 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
8178 NETIF_F_GSO_GRE_CSUM;
8179 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
8180 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
8181 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
8182 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
8183 dev->hw_features |= NETIF_F_GRO_HW;
8184 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
8185 if (dev->features & NETIF_F_GRO_HW)
8186 dev->features &= ~NETIF_F_LRO;
8187 dev->priv_flags |= IFF_UNICAST_FLT;
8188
8189 #ifdef CONFIG_BNXT_SRIOV
8190 init_waitqueue_head(&bp->sriov_cfg_wait);
8191 mutex_init(&bp->sriov_lock);
8192 #endif
8193 bp->gro_func = bnxt_gro_func_5730x;
8194 if (BNXT_CHIP_P4_PLUS(bp))
8195 bp->gro_func = bnxt_gro_func_5731x;
8196 else
8197 bp->flags |= BNXT_FLAG_DOUBLE_DB;
8198
8199 rc = bnxt_hwrm_func_drv_rgtr(bp);
8200 if (rc)
8201 goto init_err_pci_clean;
8202
8203 rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
8204 if (rc)
8205 goto init_err_pci_clean;
8206
8207 bp->ulp_probe = bnxt_ulp_probe;
8208
8209 /* Get the MAX capabilities for this function */
8210 rc = bnxt_hwrm_func_qcaps(bp);
8211 if (rc) {
8212 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
8213 rc);
8214 rc = -1;
8215 goto init_err_pci_clean;
8216 }
8217 rc = bnxt_init_mac_addr(bp);
8218 if (rc) {
8219 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
8220 rc = -EADDRNOTAVAIL;
8221 goto init_err_pci_clean;
8222 }
8223 rc = bnxt_hwrm_queue_qportcfg(bp);
8224 if (rc) {
8225 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
8226 rc);
8227 rc = -1;
8228 goto init_err_pci_clean;
8229 }
8230
8231 bnxt_hwrm_func_qcfg(bp);
8232 bnxt_hwrm_port_led_qcaps(bp);
8233 bnxt_ethtool_init(bp);
8234 bnxt_dcb_init(bp);
8235
8236 /* MTU range: 60 - FW defined max */
8237 dev->min_mtu = ETH_ZLEN;
8238 dev->max_mtu = bp->max_mtu;
8239
8240 rc = bnxt_probe_phy(bp);
8241 if (rc)
8242 goto init_err_pci_clean;
8243
8244 bnxt_set_rx_skb_mode(bp, false);
8245 bnxt_set_tpa_flags(bp);
8246 bnxt_set_ring_params(bp);
8247 bnxt_set_max_func_irqs(bp, max_irqs);
8248 rc = bnxt_set_dflt_rings(bp, true);
8249 if (rc) {
8250 netdev_err(bp->dev, "Not enough rings available.\n");
8251 rc = -ENOMEM;
8252 goto init_err_pci_clean;
8253 }
8254
8255 /* Default RSS hash cfg. */
8256 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
8257 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
8258 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
8259 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
8260 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
8261 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
8262 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
8263 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
8264 }
8265
8266 bnxt_hwrm_vnic_qcaps(bp);
8267 if (bnxt_rfs_supported(bp)) {
8268 dev->hw_features |= NETIF_F_NTUPLE;
8269 if (bnxt_rfs_capable(bp)) {
8270 bp->flags |= BNXT_FLAG_RFS;
8271 dev->features |= NETIF_F_NTUPLE;
8272 }
8273 }
8274
8275 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
8276 bp->flags |= BNXT_FLAG_STRIP_VLAN;
8277
8278 rc = bnxt_init_int_mode(bp);
8279 if (rc)
8280 goto init_err_pci_clean;
8281
8282 bnxt_get_wol_settings(bp);
8283 if (bp->flags & BNXT_FLAG_WOL_CAP)
8284 device_set_wakeup_enable(&pdev->dev, bp->wol);
8285 else
8286 device_set_wakeup_capable(&pdev->dev, false);
8287
8288 if (BNXT_PF(bp)) {
8289 if (!bnxt_pf_wq) {
8290 bnxt_pf_wq =
8291 create_singlethread_workqueue("bnxt_pf_wq");
8292 if (!bnxt_pf_wq) {
8293 dev_err(&pdev->dev, "Unable to create workqueue.\n");
8294 goto init_err_pci_clean;
8295 }
8296 }
8297 bnxt_init_tc(bp);
8298 }
8299
8300 rc = register_netdev(dev);
8301 if (rc)
8302 goto init_err_cleanup_tc;
8303
8304 if (BNXT_PF(bp))
8305 bnxt_dl_register(bp);
8306
8307 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
8308 board_info[ent->driver_data].name,
8309 (long)pci_resource_start(pdev, 0), dev->dev_addr);
8310
8311 bnxt_parse_log_pcie_link(bp);
8312
8313 return 0;
8314
8315 init_err_cleanup_tc:
8316 bnxt_shutdown_tc(bp);
8317 bnxt_clear_int_mode(bp);
8318
8319 init_err_pci_clean:
8320 bnxt_cleanup_pci(bp);
8321
8322 init_err_free:
8323 free_netdev(dev);
8324 return rc;
8325 }
8326
8327 static void bnxt_shutdown(struct pci_dev *pdev)
8328 {
8329 struct net_device *dev = pci_get_drvdata(pdev);
8330 struct bnxt *bp;
8331
8332 if (!dev)
8333 return;
8334
8335 rtnl_lock();
8336 bp = netdev_priv(dev);
8337 if (!bp)
8338 goto shutdown_exit;
8339
8340 if (netif_running(dev))
8341 dev_close(dev);
8342
8343 bnxt_ulp_shutdown(bp);
8344
8345 if (system_state == SYSTEM_POWER_OFF) {
8346 bnxt_clear_int_mode(bp);
8347 pci_wake_from_d3(pdev, bp->wol);
8348 pci_set_power_state(pdev, PCI_D3hot);
8349 }
8350
8351 shutdown_exit:
8352 rtnl_unlock();
8353 }
8354
8355 #ifdef CONFIG_PM_SLEEP
8356 static int bnxt_suspend(struct device *device)
8357 {
8358 struct pci_dev *pdev = to_pci_dev(device);
8359 struct net_device *dev = pci_get_drvdata(pdev);
8360 struct bnxt *bp = netdev_priv(dev);
8361 int rc = 0;
8362
8363 rtnl_lock();
8364 if (netif_running(dev)) {
8365 netif_device_detach(dev);
8366 rc = bnxt_close(dev);
8367 }
8368 bnxt_hwrm_func_drv_unrgtr(bp);
8369 rtnl_unlock();
8370 return rc;
8371 }
8372
8373 static int bnxt_resume(struct device *device)
8374 {
8375 struct pci_dev *pdev = to_pci_dev(device);
8376 struct net_device *dev = pci_get_drvdata(pdev);
8377 struct bnxt *bp = netdev_priv(dev);
8378 int rc = 0;
8379
8380 rtnl_lock();
8381 if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
8382 rc = -ENODEV;
8383 goto resume_exit;
8384 }
8385 rc = bnxt_hwrm_func_reset(bp);
8386 if (rc) {
8387 rc = -EBUSY;
8388 goto resume_exit;
8389 }
8390 bnxt_get_wol_settings(bp);
8391 if (netif_running(dev)) {
8392 rc = bnxt_open(dev);
8393 if (!rc)
8394 netif_device_attach(dev);
8395 }
8396
8397 resume_exit:
8398 rtnl_unlock();
8399 return rc;
8400 }
8401
8402 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
8403 #define BNXT_PM_OPS (&bnxt_pm_ops)
8404
8405 #else
8406
8407 #define BNXT_PM_OPS NULL
8408
8409 #endif /* CONFIG_PM_SLEEP */
8410
8411 /**
8412 * bnxt_io_error_detected - called when PCI error is detected
8413 * @pdev: Pointer to PCI device
8414 * @state: The current pci connection state
8415 *
8416 * This function is called after a PCI bus error affecting
8417 * this device has been detected.
8418 */
8419 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
8420 pci_channel_state_t state)
8421 {
8422 struct net_device *netdev = pci_get_drvdata(pdev);
8423 struct bnxt *bp = netdev_priv(netdev);
8424
8425 netdev_info(netdev, "PCI I/O error detected\n");
8426
8427 rtnl_lock();
8428 netif_device_detach(netdev);
8429
8430 bnxt_ulp_stop(bp);
8431
8432 if (state == pci_channel_io_perm_failure) {
8433 rtnl_unlock();
8434 return PCI_ERS_RESULT_DISCONNECT;
8435 }
8436
8437 if (netif_running(netdev))
8438 bnxt_close(netdev);
8439
8440 pci_disable_device(pdev);
8441 rtnl_unlock();
8442
8443 /* Request a slot slot reset. */
8444 return PCI_ERS_RESULT_NEED_RESET;
8445 }
8446
8447 /**
8448 * bnxt_io_slot_reset - called after the pci bus has been reset.
8449 * @pdev: Pointer to PCI device
8450 *
8451 * Restart the card from scratch, as if from a cold-boot.
8452 * At this point, the card has exprienced a hard reset,
8453 * followed by fixups by BIOS, and has its config space
8454 * set up identically to what it was at cold boot.
8455 */
8456 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
8457 {
8458 struct net_device *netdev = pci_get_drvdata(pdev);
8459 struct bnxt *bp = netdev_priv(netdev);
8460 int err = 0;
8461 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
8462
8463 netdev_info(bp->dev, "PCI Slot Reset\n");
8464
8465 rtnl_lock();
8466
8467 if (pci_enable_device(pdev)) {
8468 dev_err(&pdev->dev,
8469 "Cannot re-enable PCI device after reset.\n");
8470 } else {
8471 pci_set_master(pdev);
8472
8473 err = bnxt_hwrm_func_reset(bp);
8474 if (!err && netif_running(netdev))
8475 err = bnxt_open(netdev);
8476
8477 if (!err) {
8478 result = PCI_ERS_RESULT_RECOVERED;
8479 bnxt_ulp_start(bp);
8480 }
8481 }
8482
8483 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
8484 dev_close(netdev);
8485
8486 rtnl_unlock();
8487
8488 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8489 if (err) {
8490 dev_err(&pdev->dev,
8491 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8492 err); /* non-fatal, continue */
8493 }
8494
8495 return PCI_ERS_RESULT_RECOVERED;
8496 }
8497
8498 /**
8499 * bnxt_io_resume - called when traffic can start flowing again.
8500 * @pdev: Pointer to PCI device
8501 *
8502 * This callback is called when the error recovery driver tells
8503 * us that its OK to resume normal operation.
8504 */
8505 static void bnxt_io_resume(struct pci_dev *pdev)
8506 {
8507 struct net_device *netdev = pci_get_drvdata(pdev);
8508
8509 rtnl_lock();
8510
8511 netif_device_attach(netdev);
8512
8513 rtnl_unlock();
8514 }
8515
8516 static const struct pci_error_handlers bnxt_err_handler = {
8517 .error_detected = bnxt_io_error_detected,
8518 .slot_reset = bnxt_io_slot_reset,
8519 .resume = bnxt_io_resume
8520 };
8521
8522 static struct pci_driver bnxt_pci_driver = {
8523 .name = DRV_MODULE_NAME,
8524 .id_table = bnxt_pci_tbl,
8525 .probe = bnxt_init_one,
8526 .remove = bnxt_remove_one,
8527 .shutdown = bnxt_shutdown,
8528 .driver.pm = BNXT_PM_OPS,
8529 .err_handler = &bnxt_err_handler,
8530 #if defined(CONFIG_BNXT_SRIOV)
8531 .sriov_configure = bnxt_sriov_configure,
8532 #endif
8533 };
8534
8535 static int __init bnxt_init(void)
8536 {
8537 return pci_register_driver(&bnxt_pci_driver);
8538 }
8539
8540 static void __exit bnxt_exit(void)
8541 {
8542 pci_unregister_driver(&bnxt_pci_driver);
8543 if (bnxt_pf_wq)
8544 destroy_workqueue(bnxt_pf_wq);
8545 }
8546
8547 module_init(bnxt_init);
8548 module_exit(bnxt_exit);
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