arch/arm/common/vic.c

   1 /*
   2  *  linux/arch/arm/common/vic.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #include <linux/export.h>
  23 #include <linux/init.h>
  24 #include <linux/list.h>
  25 #include <linux/io.h>
  26 #include <linux/irqdomain.h>
  27 #include <linux/of.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_irq.h>
  30 #include <linux/syscore_ops.h>
  31 #include <linux/device.h>
  32 #include <linux/amba/bus.h>
  33
  34 #include <asm/exception.h>
  35 #include <asm/mach/irq.h>
  36 #include <asm/hardware/vic.h>
  37
  38 /**
  39  * struct vic_device - VIC PM device
  40  * @irq: The IRQ number for the base of the VIC.
  41  * @base: The register base for the VIC.
  42  * @resume_sources: A bitmask of interrupts for resume.
  43  * @resume_irqs: The IRQs enabled for resume.
  44  * @int_select: Save for VIC_INT_SELECT.
  45  * @int_enable: Save for VIC_INT_ENABLE.
  46  * @soft_int: Save for VIC_INT_SOFT.
  47  * @protect: Save for VIC_PROTECT.
  48  * @domain: The IRQ domain for the VIC.
  49  */
  50 struct vic_device {
  51         void __iomem    *base;
  52         int             irq;
  53         u32             resume_sources;
  54         u32             resume_irqs;
  55         u32             int_select;
  56         u32             int_enable;
  57         u32             soft_int;
  58         u32             protect;
  59         struct irq_domain domain;
  60 };
  61
  62 /* we cannot allocate memory when VICs are initially registered */
  63 static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
  64
  65 static int vic_id;
  66
  67 /**
  68  * vic_init2 - common initialisation code
  69  * @base: Base of the VIC.
  70  *
  71  * Common initialisation code for registration
  72  * and resume.
  73 */
  74 static void vic_init2(void __iomem *base)
  75 {
  76         int i;
  77
  78         for (i = 0; i < 16; i++) {
  79                 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
  80                 writel(VIC_VECT_CNTL_ENABLE | i, reg);
  81         }
  82
  83         writel(32, base + VIC_PL190_DEF_VECT_ADDR);
  84 }
  85
  86 #ifdef CONFIG_PM
  87 static void resume_one_vic(struct vic_device *vic)
  88 {
  89         void __iomem *base = vic->base;
  90
  91         printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
  92
  93         /* re-initialise static settings */
  94         vic_init2(base);
  95
  96         writel(vic->int_select, base + VIC_INT_SELECT);
  97         writel(vic->protect, base + VIC_PROTECT);
  98
  99         /* set the enabled ints and then clear the non-enabled */
 100         writel(vic->int_enable, base + VIC_INT_ENABLE);
 101         writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
 102
 103         /* and the same for the soft-int register */
 104
 105         writel(vic->soft_int, base + VIC_INT_SOFT);
 106         writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
 107 }
 108
 109 static void vic_resume(void)
 110 {
 111         int id;
 112
 113         for (id = vic_id - 1; id >= 0; id--)
 114                 resume_one_vic(vic_devices + id);
 115 }
 116
 117 static void suspend_one_vic(struct vic_device *vic)
 118 {
 119         void __iomem *base = vic->base;
 120
 121         printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
 122
 123         vic->int_select = readl(base + VIC_INT_SELECT);
 124         vic->int_enable = readl(base + VIC_INT_ENABLE);
 125         vic->soft_int = readl(base + VIC_INT_SOFT);
 126         vic->protect = readl(base + VIC_PROTECT);
 127
 128         /* set the interrupts (if any) that are used for
 129          * resuming the system */
 130
 131         writel(vic->resume_irqs, base + VIC_INT_ENABLE);
 132         writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
 133 }
 134
 135 static int vic_suspend(void)
 136 {
 137         int id;
 138
 139         for (id = 0; id < vic_id; id++)
 140                 suspend_one_vic(vic_devices + id);
 141
 142         return 0;
 143 }
 144
 145 struct syscore_ops vic_syscore_ops = {
 146         .suspend        = vic_suspend,
 147         .resume         = vic_resume,
 148 };
 149
 150 /**
 151  * vic_pm_init - initicall to register VIC pm
 152  *
 153  * This is called via late_initcall() to register
 154  * the resources for the VICs due to the early
 155  * nature of the VIC's registration.
 156 */
 157 static int __init vic_pm_init(void)
 158 {
 159         if (vic_id > 0)
 160                 register_syscore_ops(&vic_syscore_ops);
 161
 162         return 0;
 163 }
 164 late_initcall(vic_pm_init);
 165 #endif /* CONFIG_PM */
 166
 167 /**
 168  * vic_register() - Register a VIC.
 169  * @base: The base address of the VIC.
 170  * @irq: The base IRQ for the VIC.
 171  * @resume_sources: bitmask of interrupts allowed for resume sources.
 172  * @node: The device tree node associated with the VIC.
 173  *
 174  * Register the VIC with the system device tree so that it can be notified
 175  * of suspend and resume requests and ensure that the correct actions are
 176  * taken to re-instate the settings on resume.
 177  *
 178  * This also configures the IRQ domain for the VIC.
 179  */
 180 static void __init vic_register(void __iomem *base, unsigned int irq,
 181                                 u32 resume_sources, struct device_node *node)
 182 {
 183         struct vic_device *v;
 184
 185         if (vic_id >= ARRAY_SIZE(vic_devices)) {
 186                 printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
 187                 return;
 188         }
 189
 190         v = &vic_devices[vic_id];
 191         v->base = base;
 192         v->resume_sources = resume_sources;
 193         v->irq = irq;
 194         vic_id++;
 195
 196         v->domain.irq_base = irq;
 197         v->domain.nr_irq = 32;
 198 #ifdef CONFIG_OF_IRQ
 199         v->domain.of_node = of_node_get(node);
 200 #endif /* CONFIG_OF */
 201         v->domain.ops = &irq_domain_simple_ops;
 202         irq_domain_add(&v->domain);
 203 }
 204
 205 static void vic_ack_irq(struct irq_data *d)
 206 {
 207         void __iomem *base = irq_data_get_irq_chip_data(d);
 208         unsigned int irq = d->hwirq;
 209         writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
 210         /* moreover, clear the soft-triggered, in case it was the reason */
 211         writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
 212 }
 213
 214 static void vic_mask_irq(struct irq_data *d)
 215 {
 216         void __iomem *base = irq_data_get_irq_chip_data(d);
 217         unsigned int irq = d->hwirq;
 218         writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
 219 }
 220
 221 static void vic_unmask_irq(struct irq_data *d)
 222 {
 223         void __iomem *base = irq_data_get_irq_chip_data(d);
 224         unsigned int irq = d->hwirq;
 225         writel(1 << irq, base + VIC_INT_ENABLE);
 226 }
 227
 228 #if defined(CONFIG_PM)
 229 static struct vic_device *vic_from_irq(unsigned int irq)
 230 {
 231         struct vic_device *v = vic_devices;
 232         unsigned int base_irq = irq & ~31;
 233         int id;
 234
 235         for (id = 0; id < vic_id; id++, v++) {
 236                 if (v->irq == base_irq)
 237                         return v;
 238         }
 239
 240         return NULL;
 241 }
 242
 243 static int vic_set_wake(struct irq_data *d, unsigned int on)
 244 {
 245         struct vic_device *v = vic_from_irq(d->irq);
 246         unsigned int off = d->hwirq;
 247         u32 bit = 1 << off;
 248
 249         if (!v)
 250                 return -EINVAL;
 251
 252         if (!(bit & v->resume_sources))
 253                 return -EINVAL;
 254
 255         if (on)
 256                 v->resume_irqs |= bit;
 257         else
 258                 v->resume_irqs &= ~bit;
 259
 260         return 0;
 261 }
 262 #else
 263 #define vic_set_wake NULL
 264 #endif /* CONFIG_PM */
 265
 266 static struct irq_chip vic_chip = {
 267         .name           = "VIC",
 268         .irq_ack        = vic_ack_irq,
 269         .irq_mask       = vic_mask_irq,
 270         .irq_unmask     = vic_unmask_irq,
 271         .irq_set_wake   = vic_set_wake,
 272 };
 273
 274 static void __init vic_disable(void __iomem *base)
 275 {
 276         writel(0, base + VIC_INT_SELECT);
 277         writel(0, base + VIC_INT_ENABLE);
 278         writel(~0, base + VIC_INT_ENABLE_CLEAR);
 279         writel(0, base + VIC_ITCR);
 280         writel(~0, base + VIC_INT_SOFT_CLEAR);
 281 }
 282
 283 static void __init vic_clear_interrupts(void __iomem *base)
 284 {
 285         unsigned int i;
 286
 287         writel(0, base + VIC_PL190_VECT_ADDR);
 288         for (i = 0; i < 19; i++) {
 289                 unsigned int value;
 290
 291                 value = readl(base + VIC_PL190_VECT_ADDR);
 292                 writel(value, base + VIC_PL190_VECT_ADDR);
 293         }
 294 }
 295
 296 static void __init vic_set_irq_sources(void __iomem *base,
 297                                 unsigned int irq_start, u32 vic_sources)
 298 {
 299         unsigned int i;
 300
 301         for (i = 0; i < 32; i++) {
 302                 if (vic_sources & (1 << i)) {
 303                         unsigned int irq = irq_start + i;
 304
 305                         irq_set_chip_and_handler(irq, &vic_chip,
 306                                                  handle_level_irq);
 307                         irq_set_chip_data(irq, base);
 308                         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 309                 }
 310         }
 311 }
 312
 313 /*
 314  * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
 315  * The original cell has 32 interrupts, while the modified one has 64,
 316  * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
 317  * the probe function is called twice, with base set to offset 000
 318  *  and 020 within the page. We call this "second block".
 319  */
 320 static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
 321                                u32 vic_sources, struct device_node *node)
 322 {
 323         unsigned int i;
 324         int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
 325
 326         /* Disable all interrupts initially. */
 327         vic_disable(base);
 328
 329         /*
 330          * Make sure we clear all existing interrupts. The vector registers
 331          * in this cell are after the second block of general registers,
 332          * so we can address them using standard offsets, but only from
 333          * the second base address, which is 0x20 in the page
 334          */
 335         if (vic_2nd_block) {
 336                 vic_clear_interrupts(base);
 337
 338                 /* ST has 16 vectors as well, but we don't enable them by now */
 339                 for (i = 0; i < 16; i++) {
 340                         void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
 341                         writel(0, reg);
 342                 }
 343
 344                 writel(32, base + VIC_PL190_DEF_VECT_ADDR);
 345         }
 346
 347         vic_set_irq_sources(base, irq_start, vic_sources);
 348         vic_register(base, irq_start, 0, node);
 349 }
 350
 351 static void __init __vic_init(void __iomem *base, unsigned int irq_start,
 352                               u32 vic_sources, u32 resume_sources,
 353                               struct device_node *node)
 354 {
 355         unsigned int i;
 356         u32 cellid = 0;
 357         enum amba_vendor vendor;
 358
 359         /* Identify which VIC cell this one is, by reading the ID */
 360         for (i = 0; i < 4; i++) {
 361                 void __iomem *addr;
 362                 addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
 363                 cellid |= (readl(addr) & 0xff) << (8 * i);
 364         }
 365         vendor = (cellid >> 12) & 0xff;
 366         printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
 367                base, cellid, vendor);
 368
 369         switch(vendor) {
 370         case AMBA_VENDOR_ST:
 371                 vic_init_st(base, irq_start, vic_sources, node);
 372                 return;
 373         default:
 374                 printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
 375                 /* fall through */
 376         case AMBA_VENDOR_ARM:
 377                 break;
 378         }
 379
 380         /* Disable all interrupts initially. */
 381         vic_disable(base);
 382
 383         /* Make sure we clear all existing interrupts */
 384         vic_clear_interrupts(base);
 385
 386         vic_init2(base);
 387
 388         vic_set_irq_sources(base, irq_start, vic_sources);
 389
 390         vic_register(base, irq_start, resume_sources, node);
 391 }
 392
 393 /**
 394  * vic_init() - initialise a vectored interrupt controller
 395  * @base: iomem base address
 396  * @irq_start: starting interrupt number, must be muliple of 32
 397  * @vic_sources: bitmask of interrupt sources to allow
 398  * @resume_sources: bitmask of interrupt sources to allow for resume
 399  */
 400 void __init vic_init(void __iomem *base, unsigned int irq_start,
 401                      u32 vic_sources, u32 resume_sources)
 402 {
 403         __vic_init(base, irq_start, vic_sources, resume_sources, NULL);
 404 }
 405
 406 #ifdef CONFIG_OF
 407 int __init vic_of_init(struct device_node *node, struct device_node *parent)
 408 {
 409         void __iomem *regs;
 410         int irq_base;
 411
 412         if (WARN(parent, "non-root VICs are not supported"))
 413                 return -EINVAL;
 414
 415         regs = of_iomap(node, 0);
 416         if (WARN_ON(!regs))
 417                 return -EIO;
 418
 419         irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
 420         if (WARN_ON(irq_base < 0))
 421                 goto out_unmap;
 422
 423         __vic_init(regs, irq_base, ~0, ~0, node);
 424
 425         return 0;
 426
 427  out_unmap:
 428         iounmap(regs);
 429
 430         return -EIO;
 431 }
 432 #endif /* CONFIG OF */
 433
 434 /*
 435  * Handle each interrupt in a single VIC.  Returns non-zero if we've
 436  * handled at least one interrupt.  This does a single read of the
 437  * status register and handles all interrupts in order from LSB first.
 438  */
 439 static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
 440 {
 441         u32 stat, irq;
 442         int handled = 0;
 443
 444         stat = readl_relaxed(vic->base + VIC_IRQ_STATUS);
 445         while (stat) {
 446                 irq = ffs(stat) - 1;
 447                 handle_IRQ(irq_domain_to_irq(&vic->domain, irq), regs);
 448                 stat &= ~(1 << irq);
 449                 handled = 1;
 450         }
 451
 452         return handled;
 453 }
 454
 455 /*
 456  * Keep iterating over all registered VIC's until there are no pending
 457  * interrupts.
 458  */
 459 asmlinkage void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
 460 {
 461         int i, handled;
 462
 463         do {
 464                 for (i = 0, handled = 0; i < vic_id; ++i)
 465                         handled |= handle_one_vic(&vic_devices[i], regs);
 466         } while (handled);
 467 }