drivers/regulator/anatop-regulator.c

   1 /*
   2  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
   3  */
   4
   5 /*
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21 #include <linux/slab.h>
  22 #include <linux/device.h>
  23 #include <linux/module.h>
  24 #include <linux/mfd/syscon.h>
  25 #include <linux/err.h>
  26 #include <linux/io.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/regmap.h>
  31 #include <linux/regulator/driver.h>
  32 #include <linux/regulator/of_regulator.h>
  33 #include <linux/regulator/machine.h>
  34
  35 #define LDO_RAMP_UP_UNIT_IN_CYCLES      64 /* 64 cycles per step */
  36 #define LDO_RAMP_UP_FREQ_IN_MHZ         24 /* cycle based on 24M OSC */
  37
  38 #define LDO_POWER_GATE                  0x00
  39 #define LDO_FET_FULL_ON                 0x1f
  40
  41 struct anatop_regulator {
  42         const char *name;
  43         u32 control_reg;
  44         struct regmap *anatop;
  45         int vol_bit_shift;
  46         int vol_bit_width;
  47         u32 delay_reg;
  48         int delay_bit_shift;
  49         int delay_bit_width;
  50         int min_bit_val;
  51         int min_voltage;
  52         int max_voltage;
  53         struct regulator_desc rdesc;
  54         struct regulator_init_data *initdata;
  55         bool bypass;
  56         int sel;
  57 };
  58
  59 static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg,
  60         unsigned int old_sel,
  61         unsigned int new_sel)
  62 {
  63         struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
  64         u32 val;
  65         int ret = 0;
  66
  67         /* check whether need to care about LDO ramp up speed */
  68         if (anatop_reg->delay_bit_width && new_sel > old_sel) {
  69                 /*
  70                  * the delay for LDO ramp up time is
  71                  * based on the register setting, we need
  72                  * to calculate how many steps LDO need to
  73                  * ramp up, and how much delay needed. (us)
  74                  */
  75                 regmap_read(anatop_reg->anatop, anatop_reg->delay_reg, &val);
  76                 val = (val >> anatop_reg->delay_bit_shift) &
  77                         ((1 << anatop_reg->delay_bit_width) - 1);
  78                 ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES <<
  79                         val) / LDO_RAMP_UP_FREQ_IN_MHZ + 1;
  80         }
  81
  82         return ret;
  83 }
  84
  85 static int anatop_regmap_enable(struct regulator_dev *reg)
  86 {
  87         struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
  88         int sel;
  89
  90         sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel;
  91         return regulator_set_voltage_sel_regmap(reg, sel);
  92 }
  93
  94 static int anatop_regmap_disable(struct regulator_dev *reg)
  95 {
  96         return regulator_set_voltage_sel_regmap(reg, LDO_POWER_GATE);
  97 }
  98
  99 static int anatop_regmap_is_enabled(struct regulator_dev *reg)
 100 {
 101         return regulator_get_voltage_sel_regmap(reg) != LDO_POWER_GATE;
 102 }
 103
 104 static int anatop_regmap_core_set_voltage_sel(struct regulator_dev *reg,
 105                                               unsigned selector)
 106 {
 107         struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
 108         int ret;
 109
 110         if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) {
 111                 anatop_reg->sel = selector;
 112                 return 0;
 113         }
 114
 115         ret = regulator_set_voltage_sel_regmap(reg, selector);
 116         if (!ret)
 117                 anatop_reg->sel = selector;
 118         return ret;
 119 }
 120
 121 static int anatop_regmap_core_get_voltage_sel(struct regulator_dev *reg)
 122 {
 123         struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
 124
 125         if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg))
 126                 return anatop_reg->sel;
 127
 128         return regulator_get_voltage_sel_regmap(reg);
 129 }
 130
 131 static int anatop_regmap_get_bypass(struct regulator_dev *reg, bool *enable)
 132 {
 133         struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
 134         int sel;
 135
 136         sel = regulator_get_voltage_sel_regmap(reg);
 137         if (sel == LDO_FET_FULL_ON)
 138                 WARN_ON(!anatop_reg->bypass);
 139         else if (sel != LDO_POWER_GATE)
 140                 WARN_ON(anatop_reg->bypass);
 141
 142         *enable = anatop_reg->bypass;
 143         return 0;
 144 }
 145
 146 static int anatop_regmap_set_bypass(struct regulator_dev *reg, bool enable)
 147 {
 148         struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
 149         int sel;
 150
 151         if (enable == anatop_reg->bypass)
 152                 return 0;
 153
 154         sel = enable ? LDO_FET_FULL_ON : anatop_reg->sel;
 155         anatop_reg->bypass = enable;
 156
 157         return regulator_set_voltage_sel_regmap(reg, sel);
 158 }
 159
 160 static struct regulator_ops anatop_rops = {
 161         .set_voltage_sel = regulator_set_voltage_sel_regmap,
 162         .get_voltage_sel = regulator_get_voltage_sel_regmap,
 163         .list_voltage = regulator_list_voltage_linear,
 164         .map_voltage = regulator_map_voltage_linear,
 165 };
 166
 167 static struct regulator_ops anatop_core_rops = {
 168         .enable = anatop_regmap_enable,
 169         .disable = anatop_regmap_disable,
 170         .is_enabled = anatop_regmap_is_enabled,
 171         .set_voltage_sel = anatop_regmap_core_set_voltage_sel,
 172         .set_voltage_time_sel = anatop_regmap_set_voltage_time_sel,
 173         .get_voltage_sel = anatop_regmap_core_get_voltage_sel,
 174         .list_voltage = regulator_list_voltage_linear,
 175         .map_voltage = regulator_map_voltage_linear,
 176         .get_bypass = anatop_regmap_get_bypass,
 177         .set_bypass = anatop_regmap_set_bypass,
 178 };
 179
 180 static int anatop_regulator_probe(struct platform_device *pdev)
 181 {
 182         struct device *dev = &pdev->dev;
 183         struct device_node *np = dev->of_node;
 184         struct device_node *anatop_np;
 185         struct regulator_desc *rdesc;
 186         struct regulator_dev *rdev;
 187         struct anatop_regulator *sreg;
 188         struct regulator_init_data *initdata;
 189         struct regulator_config config = { };
 190         int ret = 0;
 191         u32 val;
 192
 193         sreg = devm_kzalloc(dev, sizeof(*sreg), GFP_KERNEL);
 194         if (!sreg)
 195                 return -ENOMEM;
 196         sreg->name = of_get_property(np, "regulator-name", NULL);
 197         rdesc = &sreg->rdesc;
 198         rdesc->name = sreg->name;
 199         rdesc->type = REGULATOR_VOLTAGE;
 200         rdesc->owner = THIS_MODULE;
 201
 202         initdata = of_get_regulator_init_data(dev, np, rdesc);
 203         initdata->supply_regulator = "vin";
 204         sreg->initdata = initdata;
 205
 206         anatop_np = of_get_parent(np);
 207         if (!anatop_np)
 208                 return -ENODEV;
 209         sreg->anatop = syscon_node_to_regmap(anatop_np);
 210         of_node_put(anatop_np);
 211         if (IS_ERR(sreg->anatop))
 212                 return PTR_ERR(sreg->anatop);
 213
 214         ret = of_property_read_u32(np, "anatop-reg-offset",
 215                                    &sreg->control_reg);
 216         if (ret) {
 217                 dev_err(dev, "no anatop-reg-offset property set\n");
 218                 return ret;
 219         }
 220         ret = of_property_read_u32(np, "anatop-vol-bit-width",
 221                                    &sreg->vol_bit_width);
 222         if (ret) {
 223                 dev_err(dev, "no anatop-vol-bit-width property set\n");
 224                 return ret;
 225         }
 226         ret = of_property_read_u32(np, "anatop-vol-bit-shift",
 227                                    &sreg->vol_bit_shift);
 228         if (ret) {
 229                 dev_err(dev, "no anatop-vol-bit-shift property set\n");
 230                 return ret;
 231         }
 232         ret = of_property_read_u32(np, "anatop-min-bit-val",
 233                                    &sreg->min_bit_val);
 234         if (ret) {
 235                 dev_err(dev, "no anatop-min-bit-val property set\n");
 236                 return ret;
 237         }
 238         ret = of_property_read_u32(np, "anatop-min-voltage",
 239                                    &sreg->min_voltage);
 240         if (ret) {
 241                 dev_err(dev, "no anatop-min-voltage property set\n");
 242                 return ret;
 243         }
 244         ret = of_property_read_u32(np, "anatop-max-voltage",
 245                                    &sreg->max_voltage);
 246         if (ret) {
 247                 dev_err(dev, "no anatop-max-voltage property set\n");
 248                 return ret;
 249         }
 250
 251         /* read LDO ramp up setting, only for core reg */
 252         of_property_read_u32(np, "anatop-delay-reg-offset",
 253                              &sreg->delay_reg);
 254         of_property_read_u32(np, "anatop-delay-bit-width",
 255                              &sreg->delay_bit_width);
 256         of_property_read_u32(np, "anatop-delay-bit-shift",
 257                              &sreg->delay_bit_shift);
 258
 259         rdesc->n_voltages = (sreg->max_voltage - sreg->min_voltage) / 25000 + 1
 260                             + sreg->min_bit_val;
 261         rdesc->min_uV = sreg->min_voltage;
 262         rdesc->uV_step = 25000;
 263         rdesc->linear_min_sel = sreg->min_bit_val;
 264         rdesc->vsel_reg = sreg->control_reg;
 265         rdesc->vsel_mask = ((1 << sreg->vol_bit_width) - 1) <<
 266                            sreg->vol_bit_shift;
 267         rdesc->min_dropout_uV = 125000;
 268
 269         config.dev = &pdev->dev;
 270         config.init_data = initdata;
 271         config.driver_data = sreg;
 272         config.of_node = pdev->dev.of_node;
 273         config.regmap = sreg->anatop;
 274
 275         /* Only core regulators have the ramp up delay configuration. */
 276         if (sreg->control_reg && sreg->delay_bit_width) {
 277                 rdesc->ops = &anatop_core_rops;
 278
 279                 ret = regmap_read(config.regmap, rdesc->vsel_reg, &val);
 280                 if (ret) {
 281                         dev_err(dev, "failed to read initial state\n");
 282                         return ret;
 283                 }
 284
 285                 sreg->sel = (val & rdesc->vsel_mask) >> sreg->vol_bit_shift;
 286                 if (sreg->sel == LDO_FET_FULL_ON) {
 287                         sreg->sel = 0;
 288                         sreg->bypass = true;
 289                 }
 290
 291                 /*
 292                  * In case vddpu was disabled by the bootloader, we need to set
 293                  * a sane default until imx6-cpufreq was probed and changes the
 294                  * voltage to the correct value. In this case we set 1.25V.
 295                  */
 296                 if (!sreg->sel && !strcmp(sreg->name, "vddpu"))
 297                         sreg->sel = 22;
 298
 299                 if (!sreg->bypass && !sreg->sel) {
 300                         dev_err(&pdev->dev, "Failed to read a valid default voltage selector.\n");
 301                         return -EINVAL;
 302                 }
 303         } else {
 304                 u32 enable_bit;
 305
 306                 rdesc->ops = &anatop_rops;
 307
 308                 if (!of_property_read_u32(np, "anatop-enable-bit",
 309                                           &enable_bit)) {
 310                         anatop_rops.enable  = regulator_enable_regmap;
 311                         anatop_rops.disable = regulator_disable_regmap;
 312                         anatop_rops.is_enabled = regulator_is_enabled_regmap;
 313
 314                         rdesc->enable_reg = sreg->control_reg;
 315                         rdesc->enable_mask = BIT(enable_bit);
 316                 }
 317         }
 318
 319         /* register regulator */
 320         rdev = devm_regulator_register(dev, rdesc, &config);
 321         if (IS_ERR(rdev)) {
 322                 dev_err(dev, "failed to register %s\n",
 323                         rdesc->name);
 324                 return PTR_ERR(rdev);
 325         }
 326
 327         platform_set_drvdata(pdev, rdev);
 328
 329         return 0;
 330 }
 331
 332 static const struct of_device_id of_anatop_regulator_match_tbl[] = {
 333         { .compatible = "fsl,anatop-regulator", },
 334         { /* end */ }
 335 };
 336 MODULE_DEVICE_TABLE(of, of_anatop_regulator_match_tbl);
 337
 338 static struct platform_driver anatop_regulator_driver = {
 339         .driver = {
 340                 .name   = "anatop_regulator",
 341                 .of_match_table = of_anatop_regulator_match_tbl,
 342         },
 343         .probe  = anatop_regulator_probe,
 344 };
 345
 346 static int __init anatop_regulator_init(void)
 347 {
 348         return platform_driver_register(&anatop_regulator_driver);
 349 }
 350 postcore_initcall(anatop_regulator_init);
 351
 352 static void __exit anatop_regulator_exit(void)
 353 {
 354         platform_driver_unregister(&anatop_regulator_driver);
 355 }
 356 module_exit(anatop_regulator_exit);
 357
 358 MODULE_AUTHOR("Nancy Chen <Nancy.Chen@freescale.com>");
 359 MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>");
 360 MODULE_DESCRIPTION("ANATOP Regulator driver");
 361 MODULE_LICENSE("GPL v2");
 362 MODULE_ALIAS("platform:anatop_regulator");