drivers/media/video/ov9640.c

   1 /*
   2  * OmniVision OV96xx Camera Driver
   3  *
   4  * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * Based on ov772x camera driver:
   7  *
   8  * Copyright (C) 2008 Renesas Solutions Corp.
   9  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  10  *
  11  * Based on ov7670 and soc_camera_platform driver,
  12  *
  13  * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
  14  * Copyright (C) 2008 Magnus Damm
  15  * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24 #include <linux/i2c.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/videodev2.h>
  28
  29 #include <media/soc_camera.h>
  30 #include <media/soc_mediabus.h>
  31 #include <media/v4l2-chip-ident.h>
  32 #include <media/v4l2-common.h>
  33
  34 #include "ov9640.h"
  35
  36 #define to_ov9640_sensor(sd)    container_of(sd, struct ov9640_priv, subdev)
  37
  38 /* default register setup */
  39 static const struct ov9640_reg ov9640_regs_dflt[] = {
  40         { OV9640_COM5,  OV9640_COM5_SYSCLK | OV9640_COM5_LONGEXP },
  41         { OV9640_COM6,  OV9640_COM6_OPT_BLC | OV9640_COM6_ADBLC_BIAS |
  42                         OV9640_COM6_FMT_RST | OV9640_COM6_ADBLC_OPTEN },
  43         { OV9640_PSHFT, OV9640_PSHFT_VAL(0x01) },
  44         { OV9640_ACOM,  OV9640_ACOM_2X_ANALOG | OV9640_ACOM_RSVD },
  45         { OV9640_TSLB,  OV9640_TSLB_YUYV_UYVY },
  46         { OV9640_COM16, OV9640_COM16_RB_AVG },
  47
  48         /* Gamma curve P */
  49         { 0x6c, 0x40 }, { 0x6d, 0x30 }, { 0x6e, 0x4b }, { 0x6f, 0x60 },
  50         { 0x70, 0x70 }, { 0x71, 0x70 }, { 0x72, 0x70 }, { 0x73, 0x70 },
  51         { 0x74, 0x60 }, { 0x75, 0x60 }, { 0x76, 0x50 }, { 0x77, 0x48 },
  52         { 0x78, 0x3a }, { 0x79, 0x2e }, { 0x7a, 0x28 }, { 0x7b, 0x22 },
  53
  54         /* Gamma curve T */
  55         { 0x7c, 0x04 }, { 0x7d, 0x07 }, { 0x7e, 0x10 }, { 0x7f, 0x28 },
  56         { 0x80, 0x36 }, { 0x81, 0x44 }, { 0x82, 0x52 }, { 0x83, 0x60 },
  57         { 0x84, 0x6c }, { 0x85, 0x78 }, { 0x86, 0x8c }, { 0x87, 0x9e },
  58         { 0x88, 0xbb }, { 0x89, 0xd2 }, { 0x8a, 0xe6 },
  59 };
  60
  61 /* Configurations
  62  * NOTE: for YUV, alter the following registers:
  63  *              COM12 |= OV9640_COM12_YUV_AVG
  64  *
  65  *       for RGB, alter the following registers:
  66  *              COM7  |= OV9640_COM7_RGB
  67  *              COM13 |= OV9640_COM13_RGB_AVG
  68  *              COM15 |= proper RGB color encoding mode
  69  */
  70 static const struct ov9640_reg ov9640_regs_qqcif[] = {
  71         { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x0f) },
  72         { OV9640_COM1,  OV9640_COM1_QQFMT | OV9640_COM1_HREF_2SKIP },
  73         { OV9640_COM4,  OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
  74         { OV9640_COM7,  OV9640_COM7_QCIF },
  75         { OV9640_COM12, OV9640_COM12_RSVD },
  76         { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
  77         { OV9640_COM15, OV9640_COM15_OR_10F0 },
  78 };
  79
  80 static const struct ov9640_reg ov9640_regs_qqvga[] = {
  81         { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x07) },
  82         { OV9640_COM1,  OV9640_COM1_QQFMT | OV9640_COM1_HREF_2SKIP },
  83         { OV9640_COM4,  OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
  84         { OV9640_COM7,  OV9640_COM7_QVGA },
  85         { OV9640_COM12, OV9640_COM12_RSVD },
  86         { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
  87         { OV9640_COM15, OV9640_COM15_OR_10F0 },
  88 };
  89
  90 static const struct ov9640_reg ov9640_regs_qcif[] = {
  91         { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x07) },
  92         { OV9640_COM4,  OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
  93         { OV9640_COM7,  OV9640_COM7_QCIF },
  94         { OV9640_COM12, OV9640_COM12_RSVD },
  95         { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
  96         { OV9640_COM15, OV9640_COM15_OR_10F0 },
  97 };
  98
  99 static const struct ov9640_reg ov9640_regs_qvga[] = {
 100         { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x03) },
 101         { OV9640_COM4,  OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
 102         { OV9640_COM7,  OV9640_COM7_QVGA },
 103         { OV9640_COM12, OV9640_COM12_RSVD },
 104         { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
 105         { OV9640_COM15, OV9640_COM15_OR_10F0 },
 106 };
 107
 108 static const struct ov9640_reg ov9640_regs_cif[] = {
 109         { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x03) },
 110         { OV9640_COM3,  OV9640_COM3_VP },
 111         { OV9640_COM7,  OV9640_COM7_CIF },
 112         { OV9640_COM12, OV9640_COM12_RSVD },
 113         { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
 114         { OV9640_COM15, OV9640_COM15_OR_10F0 },
 115 };
 116
 117 static const struct ov9640_reg ov9640_regs_vga[] = {
 118         { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x01) },
 119         { OV9640_COM3,  OV9640_COM3_VP },
 120         { OV9640_COM7,  OV9640_COM7_VGA },
 121         { OV9640_COM12, OV9640_COM12_RSVD },
 122         { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
 123         { OV9640_COM15, OV9640_COM15_OR_10F0 },
 124 };
 125
 126 static const struct ov9640_reg ov9640_regs_sxga[] = {
 127         { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x01) },
 128         { OV9640_COM3,  OV9640_COM3_VP },
 129         { OV9640_COM7,  0 },
 130         { OV9640_COM12, OV9640_COM12_RSVD },
 131         { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
 132         { OV9640_COM15, OV9640_COM15_OR_10F0 },
 133 };
 134
 135 static const struct ov9640_reg ov9640_regs_yuv[] = {
 136         { OV9640_MTX1,  0x58 },
 137         { OV9640_MTX2,  0x48 },
 138         { OV9640_MTX3,  0x10 },
 139         { OV9640_MTX4,  0x28 },
 140         { OV9640_MTX5,  0x48 },
 141         { OV9640_MTX6,  0x70 },
 142         { OV9640_MTX7,  0x40 },
 143         { OV9640_MTX8,  0x40 },
 144         { OV9640_MTX9,  0x40 },
 145         { OV9640_MTXS,  0x0f },
 146 };
 147
 148 static const struct ov9640_reg ov9640_regs_rgb[] = {
 149         { OV9640_MTX1,  0x71 },
 150         { OV9640_MTX2,  0x3e },
 151         { OV9640_MTX3,  0x0c },
 152         { OV9640_MTX4,  0x33 },
 153         { OV9640_MTX5,  0x72 },
 154         { OV9640_MTX6,  0x00 },
 155         { OV9640_MTX7,  0x2b },
 156         { OV9640_MTX8,  0x66 },
 157         { OV9640_MTX9,  0xd2 },
 158         { OV9640_MTXS,  0x65 },
 159 };
 160
 161 static enum v4l2_mbus_pixelcode ov9640_codes[] = {
 162         V4L2_MBUS_FMT_UYVY8_2X8,
 163         V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE,
 164         V4L2_MBUS_FMT_RGB565_2X8_LE,
 165 };
 166
 167 static const struct v4l2_queryctrl ov9640_controls[] = {
 168         {
 169                 .id             = V4L2_CID_VFLIP,
 170                 .type           = V4L2_CTRL_TYPE_BOOLEAN,
 171                 .name           = "Flip Vertically",
 172                 .minimum        = 0,
 173                 .maximum        = 1,
 174                 .step           = 1,
 175                 .default_value  = 0,
 176         },
 177         {
 178                 .id             = V4L2_CID_HFLIP,
 179                 .type           = V4L2_CTRL_TYPE_BOOLEAN,
 180                 .name           = "Flip Horizontally",
 181                 .minimum        = 0,
 182                 .maximum        = 1,
 183                 .step           = 1,
 184                 .default_value  = 0,
 185         },
 186 };
 187
 188 /* read a register */
 189 static int ov9640_reg_read(struct i2c_client *client, u8 reg, u8 *val)
 190 {
 191         int ret;
 192         u8 data = reg;
 193         struct i2c_msg msg = {
 194                 .addr   = client->addr,
 195                 .flags  = 0,
 196                 .len    = 1,
 197                 .buf    = &data,
 198         };
 199
 200         ret = i2c_transfer(client->adapter, &msg, 1);
 201         if (ret < 0)
 202                 goto err;
 203
 204         msg.flags = I2C_M_RD;
 205         ret = i2c_transfer(client->adapter, &msg, 1);
 206         if (ret < 0)
 207                 goto err;
 208
 209         *val = data;
 210         return 0;
 211
 212 err:
 213         dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
 214         return ret;
 215 }
 216
 217 /* write a register */
 218 static int ov9640_reg_write(struct i2c_client *client, u8 reg, u8 val)
 219 {
 220         int ret;
 221         u8 _val;
 222         unsigned char data[2] = { reg, val };
 223         struct i2c_msg msg = {
 224                 .addr   = client->addr,
 225                 .flags  = 0,
 226                 .len    = 2,
 227                 .buf    = data,
 228         };
 229
 230         ret = i2c_transfer(client->adapter, &msg, 1);
 231         if (ret < 0) {
 232                 dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
 233                 return ret;
 234         }
 235
 236         /* we have to read the register back ... no idea why, maybe HW bug */
 237         ret = ov9640_reg_read(client, reg, &_val);
 238         if (ret)
 239                 dev_err(&client->dev,
 240                         "Failed reading back register 0x%02x!\n", reg);
 241
 242         return 0;
 243 }
 244
 245
 246 /* Read a register, alter its bits, write it back */
 247 static int ov9640_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 unset)
 248 {
 249         u8 val;
 250         int ret;
 251
 252         ret = ov9640_reg_read(client, reg, &val);
 253         if (ret) {
 254                 dev_err(&client->dev,
 255                         "[Read]-Modify-Write of register %02x failed!\n", reg);
 256                 return val;
 257         }
 258
 259         val |= set;
 260         val &= ~unset;
 261
 262         ret = ov9640_reg_write(client, reg, val);
 263         if (ret)
 264                 dev_err(&client->dev,
 265                         "Read-Modify-[Write] of register %02x failed!\n", reg);
 266
 267         return ret;
 268 }
 269
 270 /* Soft reset the camera. This has nothing to do with the RESET pin! */
 271 static int ov9640_reset(struct i2c_client *client)
 272 {
 273         int ret;
 274
 275         ret = ov9640_reg_write(client, OV9640_COM7, OV9640_COM7_SCCB_RESET);
 276         if (ret)
 277                 dev_err(&client->dev,
 278                         "An error occurred while entering soft reset!\n");
 279
 280         return ret;
 281 }
 282
 283 /* Start/Stop streaming from the device */
 284 static int ov9640_s_stream(struct v4l2_subdev *sd, int enable)
 285 {
 286         return 0;
 287 }
 288
 289 /* Get status of additional camera capabilities */
 290 static int ov9640_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
 291 {
 292         struct ov9640_priv *priv = to_ov9640_sensor(sd);
 293
 294         switch (ctrl->id) {
 295         case V4L2_CID_VFLIP:
 296                 ctrl->value = priv->flag_vflip;
 297                 break;
 298         case V4L2_CID_HFLIP:
 299                 ctrl->value = priv->flag_hflip;
 300                 break;
 301         }
 302         return 0;
 303 }
 304
 305 /* Set status of additional camera capabilities */
 306 static int ov9640_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
 307 {
 308         struct i2c_client *client = v4l2_get_subdevdata(sd);
 309         struct ov9640_priv *priv = to_ov9640_sensor(sd);
 310
 311         int ret = 0;
 312
 313         switch (ctrl->id) {
 314         case V4L2_CID_VFLIP:
 315                 priv->flag_vflip = ctrl->value;
 316                 if (ctrl->value)
 317                         ret = ov9640_reg_rmw(client, OV9640_MVFP,
 318                                                         OV9640_MVFP_V, 0);
 319                 else
 320                         ret = ov9640_reg_rmw(client, OV9640_MVFP,
 321                                                         0, OV9640_MVFP_V);
 322                 break;
 323         case V4L2_CID_HFLIP:
 324                 priv->flag_hflip = ctrl->value;
 325                 if (ctrl->value)
 326                         ret = ov9640_reg_rmw(client, OV9640_MVFP,
 327                                                         OV9640_MVFP_H, 0);
 328                 else
 329                         ret = ov9640_reg_rmw(client, OV9640_MVFP,
 330                                                         0, OV9640_MVFP_H);
 331                 break;
 332         }
 333
 334         return ret;
 335 }
 336
 337 /* Get chip identification */
 338 static int ov9640_g_chip_ident(struct v4l2_subdev *sd,
 339                                 struct v4l2_dbg_chip_ident *id)
 340 {
 341         struct ov9640_priv *priv = to_ov9640_sensor(sd);
 342
 343         id->ident       = priv->model;
 344         id->revision    = priv->revision;
 345
 346         return 0;
 347 }
 348
 349 #ifdef CONFIG_VIDEO_ADV_DEBUG
 350 static int ov9640_get_register(struct v4l2_subdev *sd,
 351                                 struct v4l2_dbg_register *reg)
 352 {
 353         struct i2c_client *client = v4l2_get_subdevdata(sd);
 354         int ret;
 355         u8 val;
 356
 357         if (reg->reg & ~0xff)
 358                 return -EINVAL;
 359
 360         reg->size = 1;
 361
 362         ret = ov9640_reg_read(client, reg->reg, &val);
 363         if (ret)
 364                 return ret;
 365
 366         reg->val = (__u64)val;
 367
 368         return 0;
 369 }
 370
 371 static int ov9640_set_register(struct v4l2_subdev *sd,
 372                                 struct v4l2_dbg_register *reg)
 373 {
 374         struct i2c_client *client = v4l2_get_subdevdata(sd);
 375
 376         if (reg->reg & ~0xff || reg->val & ~0xff)
 377                 return -EINVAL;
 378
 379         return ov9640_reg_write(client, reg->reg, reg->val);
 380 }
 381 #endif
 382
 383 /* select nearest higher resolution for capture */
 384 static void ov9640_res_roundup(u32 *width, u32 *height)
 385 {
 386         int i;
 387         enum { QQCIF, QQVGA, QCIF, QVGA, CIF, VGA, SXGA };
 388         int res_x[] = { 88, 160, 176, 320, 352, 640, 1280 };
 389         int res_y[] = { 72, 120, 144, 240, 288, 480, 960 };
 390
 391         for (i = 0; i < ARRAY_SIZE(res_x); i++) {
 392                 if (res_x[i] >= *width && res_y[i] >= *height) {
 393                         *width = res_x[i];
 394                         *height = res_y[i];
 395                         return;
 396                 }
 397         }
 398
 399         *width = res_x[SXGA];
 400         *height = res_y[SXGA];
 401 }
 402
 403 /* Prepare necessary register changes depending on color encoding */
 404 static void ov9640_alter_regs(enum v4l2_mbus_pixelcode code,
 405                               struct ov9640_reg_alt *alt)
 406 {
 407         switch (code) {
 408         default:
 409         case V4L2_MBUS_FMT_UYVY8_2X8:
 410                 alt->com12      = OV9640_COM12_YUV_AVG;
 411                 alt->com13      = OV9640_COM13_Y_DELAY_EN |
 412                                         OV9640_COM13_YUV_DLY(0x01);
 413                 break;
 414         case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
 415                 alt->com7       = OV9640_COM7_RGB;
 416                 alt->com13      = OV9640_COM13_RGB_AVG;
 417                 alt->com15      = OV9640_COM15_RGB_555;
 418                 break;
 419         case V4L2_MBUS_FMT_RGB565_2X8_LE:
 420                 alt->com7       = OV9640_COM7_RGB;
 421                 alt->com13      = OV9640_COM13_RGB_AVG;
 422                 alt->com15      = OV9640_COM15_RGB_565;
 423                 break;
 424         };
 425 }
 426
 427 /* Setup registers according to resolution and color encoding */
 428 static int ov9640_write_regs(struct i2c_client *client, u32 width,
 429                 enum v4l2_mbus_pixelcode code, struct ov9640_reg_alt *alts)
 430 {
 431         const struct ov9640_reg *ov9640_regs, *matrix_regs;
 432         int                     ov9640_regs_len, matrix_regs_len;
 433         int                     i, ret;
 434         u8                      val;
 435
 436         /* select register configuration for given resolution */
 437         switch (width) {
 438         case W_QQCIF:
 439                 ov9640_regs     = ov9640_regs_qqcif;
 440                 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qqcif);
 441                 break;
 442         case W_QQVGA:
 443                 ov9640_regs     = ov9640_regs_qqvga;
 444                 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qqvga);
 445                 break;
 446         case W_QCIF:
 447                 ov9640_regs     = ov9640_regs_qcif;
 448                 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qcif);
 449                 break;
 450         case W_QVGA:
 451                 ov9640_regs     = ov9640_regs_qvga;
 452                 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qvga);
 453                 break;
 454         case W_CIF:
 455                 ov9640_regs     = ov9640_regs_cif;
 456                 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_cif);
 457                 break;
 458         case W_VGA:
 459                 ov9640_regs     = ov9640_regs_vga;
 460                 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_vga);
 461                 break;
 462         case W_SXGA:
 463                 ov9640_regs     = ov9640_regs_sxga;
 464                 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_sxga);
 465                 break;
 466         default:
 467                 dev_err(&client->dev, "Failed to select resolution!\n");
 468                 return -EINVAL;
 469         }
 470
 471         /* select color matrix configuration for given color encoding */
 472         if (code == V4L2_MBUS_FMT_UYVY8_2X8) {
 473                 matrix_regs     = ov9640_regs_yuv;
 474                 matrix_regs_len = ARRAY_SIZE(ov9640_regs_yuv);
 475         } else {
 476                 matrix_regs     = ov9640_regs_rgb;
 477                 matrix_regs_len = ARRAY_SIZE(ov9640_regs_rgb);
 478         }
 479
 480         /* write register settings into the module */
 481         for (i = 0; i < ov9640_regs_len; i++) {
 482                 val = ov9640_regs[i].val;
 483
 484                 switch (ov9640_regs[i].reg) {
 485                 case OV9640_COM7:
 486                         val |= alts->com7;
 487                         break;
 488                 case OV9640_COM12:
 489                         val |= alts->com12;
 490                         break;
 491                 case OV9640_COM13:
 492                         val |= alts->com13;
 493                         break;
 494                 case OV9640_COM15:
 495                         val |= alts->com15;
 496                         break;
 497                 }
 498
 499                 ret = ov9640_reg_write(client, ov9640_regs[i].reg, val);
 500                 if (ret)
 501                         return ret;
 502         }
 503
 504         /* write color matrix configuration into the module */
 505         for (i = 0; i < matrix_regs_len; i++) {
 506                 ret = ov9640_reg_write(client, matrix_regs[i].reg,
 507                                                 matrix_regs[i].val);
 508                 if (ret)
 509                         return ret;
 510         }
 511
 512         return 0;
 513 }
 514
 515 /* program default register values */
 516 static int ov9640_prog_dflt(struct i2c_client *client)
 517 {
 518         int i, ret;
 519
 520         for (i = 0; i < ARRAY_SIZE(ov9640_regs_dflt); i++) {
 521                 ret = ov9640_reg_write(client, ov9640_regs_dflt[i].reg,
 522                                                 ov9640_regs_dflt[i].val);
 523                 if (ret)
 524                         return ret;
 525         }
 526
 527         /* wait for the changes to actually happen, 140ms are not enough yet */
 528         mdelay(150);
 529
 530         return 0;
 531 }
 532
 533 /* set the format we will capture in */
 534 static int ov9640_s_fmt(struct v4l2_subdev *sd,
 535                         struct v4l2_mbus_framefmt *mf)
 536 {
 537         struct i2c_client *client = v4l2_get_subdevdata(sd);
 538         struct ov9640_reg_alt alts = {0};
 539         enum v4l2_colorspace cspace;
 540         enum v4l2_mbus_pixelcode code = mf->code;
 541         int ret;
 542
 543         ov9640_res_roundup(&mf->width, &mf->height);
 544         ov9640_alter_regs(mf->code, &alts);
 545
 546         ov9640_reset(client);
 547
 548         ret = ov9640_prog_dflt(client);
 549         if (ret)
 550                 return ret;
 551
 552         switch (code) {
 553         case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
 554         case V4L2_MBUS_FMT_RGB565_2X8_LE:
 555                 cspace = V4L2_COLORSPACE_SRGB;
 556                 break;
 557         default:
 558                 code = V4L2_MBUS_FMT_UYVY8_2X8;
 559         case V4L2_MBUS_FMT_UYVY8_2X8:
 560                 cspace = V4L2_COLORSPACE_JPEG;
 561         }
 562
 563         ret = ov9640_write_regs(client, mf->width, code, &alts);
 564         if (!ret) {
 565                 mf->code        = code;
 566                 mf->colorspace  = cspace;
 567         }
 568
 569         return ret;
 570 }
 571
 572 static int ov9640_try_fmt(struct v4l2_subdev *sd,
 573                           struct v4l2_mbus_framefmt *mf)
 574 {
 575         ov9640_res_roundup(&mf->width, &mf->height);
 576
 577         mf->field = V4L2_FIELD_NONE;
 578
 579         switch (mf->code) {
 580         case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
 581         case V4L2_MBUS_FMT_RGB565_2X8_LE:
 582                 mf->colorspace = V4L2_COLORSPACE_SRGB;
 583                 break;
 584         default:
 585                 mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
 586         case V4L2_MBUS_FMT_UYVY8_2X8:
 587                 mf->colorspace = V4L2_COLORSPACE_JPEG;
 588         }
 589
 590         return 0;
 591 }
 592
 593 static int ov9640_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
 594                            enum v4l2_mbus_pixelcode *code)
 595 {
 596         if (index >= ARRAY_SIZE(ov9640_codes))
 597                 return -EINVAL;
 598
 599         *code = ov9640_codes[index];
 600         return 0;
 601 }
 602
 603 static int ov9640_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
 604 {
 605         a->c.left       = 0;
 606         a->c.top        = 0;
 607         a->c.width      = W_SXGA;
 608         a->c.height     = H_SXGA;
 609         a->type         = V4L2_BUF_TYPE_VIDEO_CAPTURE;
 610
 611         return 0;
 612 }
 613
 614 static int ov9640_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
 615 {
 616         a->bounds.left                  = 0;
 617         a->bounds.top                   = 0;
 618         a->bounds.width                 = W_SXGA;
 619         a->bounds.height                = H_SXGA;
 620         a->defrect                      = a->bounds;
 621         a->type                         = V4L2_BUF_TYPE_VIDEO_CAPTURE;
 622         a->pixelaspect.numerator        = 1;
 623         a->pixelaspect.denominator      = 1;
 624
 625         return 0;
 626 }
 627
 628 static int ov9640_video_probe(struct soc_camera_device *icd,
 629                                 struct i2c_client *client)
 630 {
 631         struct v4l2_subdev *sd = i2c_get_clientdata(client);
 632         struct ov9640_priv *priv = to_ov9640_sensor(sd);
 633         u8              pid, ver, midh, midl;
 634         const char      *devname;
 635         int             ret = 0;
 636
 637         /* We must have a parent by now. And it cannot be a wrong one. */
 638         BUG_ON(!icd->parent ||
 639                to_soc_camera_host(icd->parent)->nr != icd->iface);
 640
 641         /*
 642          * check and show product ID and manufacturer ID
 643          */
 644
 645         ret = ov9640_reg_read(client, OV9640_PID, &pid);
 646         if (ret)
 647                 goto err;
 648
 649         ret = ov9640_reg_read(client, OV9640_VER, &ver);
 650         if (ret)
 651                 goto err;
 652
 653         ret = ov9640_reg_read(client, OV9640_MIDH, &midh);
 654         if (ret)
 655                 goto err;
 656
 657         ret = ov9640_reg_read(client, OV9640_MIDL, &midl);
 658         if (ret)
 659                 goto err;
 660
 661         switch (VERSION(pid, ver)) {
 662         case OV9640_V2:
 663                 devname         = "ov9640";
 664                 priv->model     = V4L2_IDENT_OV9640;
 665                 priv->revision  = 2;
 666         case OV9640_V3:
 667                 devname         = "ov9640";
 668                 priv->model     = V4L2_IDENT_OV9640;
 669                 priv->revision  = 3;
 670                 break;
 671         default:
 672                 dev_err(&client->dev, "Product ID error %x:%x\n", pid, ver);
 673                 ret = -ENODEV;
 674                 goto err;
 675         }
 676
 677         dev_info(&client->dev, "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
 678                  devname, pid, ver, midh, midl);
 679
 680 err:
 681         return ret;
 682 }
 683
 684 static struct soc_camera_ops ov9640_ops = {
 685         .controls               = ov9640_controls,
 686         .num_controls           = ARRAY_SIZE(ov9640_controls),
 687 };
 688
 689 static struct v4l2_subdev_core_ops ov9640_core_ops = {
 690         .g_ctrl                 = ov9640_g_ctrl,
 691         .s_ctrl                 = ov9640_s_ctrl,
 692         .g_chip_ident           = ov9640_g_chip_ident,
 693 #ifdef CONFIG_VIDEO_ADV_DEBUG
 694         .g_register             = ov9640_get_register,
 695         .s_register             = ov9640_set_register,
 696 #endif
 697
 698 };
 699
 700 /* Request bus settings on camera side */
 701 static int ov9640_g_mbus_config(struct v4l2_subdev *sd,
 702                                 struct v4l2_mbus_config *cfg)
 703 {
 704         struct i2c_client *client = v4l2_get_subdevdata(sd);
 705         struct soc_camera_device *icd = client->dev.platform_data;
 706         struct soc_camera_link *icl = to_soc_camera_link(icd);
 707
 708         cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
 709                 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
 710                 V4L2_MBUS_DATA_ACTIVE_HIGH;
 711         cfg->type = V4L2_MBUS_PARALLEL;
 712         cfg->flags = soc_camera_apply_board_flags(icl, cfg);
 713
 714         return 0;
 715 }
 716
 717 static struct v4l2_subdev_video_ops ov9640_video_ops = {
 718         .s_stream       = ov9640_s_stream,
 719         .s_mbus_fmt     = ov9640_s_fmt,
 720         .try_mbus_fmt   = ov9640_try_fmt,
 721         .enum_mbus_fmt  = ov9640_enum_fmt,
 722         .cropcap        = ov9640_cropcap,
 723         .g_crop         = ov9640_g_crop,
 724         .g_mbus_config  = ov9640_g_mbus_config,
 725 };
 726
 727 static struct v4l2_subdev_ops ov9640_subdev_ops = {
 728         .core   = &ov9640_core_ops,
 729         .video  = &ov9640_video_ops,
 730 };
 731
 732 /*
 733  * i2c_driver function
 734  */
 735 static int ov9640_probe(struct i2c_client *client,
 736                         const struct i2c_device_id *did)
 737 {
 738         struct ov9640_priv *priv;
 739         struct soc_camera_device *icd   = client->dev.platform_data;
 740         struct soc_camera_link *icl;
 741         int ret;
 742
 743         if (!icd) {
 744                 dev_err(&client->dev, "Missing soc-camera data!\n");
 745                 return -EINVAL;
 746         }
 747
 748         icl = to_soc_camera_link(icd);
 749         if (!icl) {
 750                 dev_err(&client->dev, "Missing platform_data for driver\n");
 751                 return -EINVAL;
 752         }
 753
 754         priv = kzalloc(sizeof(struct ov9640_priv), GFP_KERNEL);
 755         if (!priv) {
 756                 dev_err(&client->dev,
 757                         "Failed to allocate memory for private data!\n");
 758                 return -ENOMEM;
 759         }
 760
 761         v4l2_i2c_subdev_init(&priv->subdev, client, &ov9640_subdev_ops);
 762
 763         icd->ops        = &ov9640_ops;
 764
 765         ret = ov9640_video_probe(icd, client);
 766
 767         if (ret) {
 768                 icd->ops = NULL;
 769                 kfree(priv);
 770         }
 771
 772         return ret;
 773 }
 774
 775 static int ov9640_remove(struct i2c_client *client)
 776 {
 777         struct v4l2_subdev *sd = i2c_get_clientdata(client);
 778         struct ov9640_priv *priv = to_ov9640_sensor(sd);
 779
 780         kfree(priv);
 781         return 0;
 782 }
 783
 784 static const struct i2c_device_id ov9640_id[] = {
 785         { "ov9640", 0 },
 786         { }
 787 };
 788 MODULE_DEVICE_TABLE(i2c, ov9640_id);
 789
 790 static struct i2c_driver ov9640_i2c_driver = {
 791         .driver = {
 792                 .name = "ov9640",
 793         },
 794         .probe    = ov9640_probe,
 795         .remove   = ov9640_remove,
 796         .id_table = ov9640_id,
 797 };
 798
 799 static int __init ov9640_module_init(void)
 800 {
 801         return i2c_add_driver(&ov9640_i2c_driver);
 802 }
 803
 804 static void __exit ov9640_module_exit(void)
 805 {
 806         i2c_del_driver(&ov9640_i2c_driver);
 807 }
 808
 809 module_init(ov9640_module_init);
 810 module_exit(ov9640_module_exit);
 811
 812 MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV96xx");
 813 MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
 814 MODULE_LICENSE("GPL v2");