arch/powerpc/sysdev/fsl_pci.c

   1 /*
   2  * MPC85xx/86xx PCI/PCIE support routing.
   3  *
   4  * Copyright 2007 Freescale Semiconductor, Inc
   5  *
   6  * Initial author: Xianghua Xiao <x.xiao@freescale.com>
   7  * Recode: ZHANG WEI <wei.zhang@freescale.com>
   8  * Rewrite the routing for Frescale PCI and PCI Express
   9  *      Roy Zang <tie-fei.zang@freescale.com>
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  */
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/delay.h>
  19 #include <linux/string.h>
  20 #include <linux/init.h>
  21 #include <linux/bootmem.h>
  22
  23 #include <asm/io.h>
  24 #include <asm/prom.h>
  25 #include <asm/pci-bridge.h>
  26 #include <asm/machdep.h>
  27 #include <sysdev/fsl_soc.h>
  28 #include <sysdev/fsl_pci.h>
  29
  30 /* atmu setup for fsl pci/pcie controller */
  31 void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
  32 {
  33         struct ccsr_pci __iomem *pci;
  34         int i;
  35
  36         pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
  37                     (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1);
  38         pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
  39
  40         /* Disable all windows (except powar0 since its ignored) */
  41         for(i = 1; i < 5; i++)
  42                 out_be32(&pci->pow[i].powar, 0);
  43         for(i = 0; i < 3; i++)
  44                 out_be32(&pci->piw[i].piwar, 0);
  45
  46         /* Setup outbound MEM window */
  47         for(i = 0; i < 3; i++)
  48                 if (hose->mem_resources[i].flags & IORESOURCE_MEM){
  49                         resource_size_t pci_addr_start =
  50                                  hose->mem_resources[i].start -
  51                                  hose->pci_mem_offset;
  52                         pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
  53                                 (u64)hose->mem_resources[i].start,
  54                                 (u64)hose->mem_resources[i].end
  55                                   - (u64)hose->mem_resources[i].start + 1);
  56                         out_be32(&pci->pow[i+1].potar, (pci_addr_start >> 12));
  57                         out_be32(&pci->pow[i+1].potear, 0);
  58                         out_be32(&pci->pow[i+1].powbar,
  59                                 (hose->mem_resources[i].start >> 12));
  60                         /* Enable, Mem R/W */
  61                         out_be32(&pci->pow[i+1].powar, 0x80044000
  62                                 | (__ilog2(hose->mem_resources[i].end
  63                                 - hose->mem_resources[i].start + 1) - 1));
  64                 }
  65
  66         /* Setup outbound IO window */
  67         if (hose->io_resource.flags & IORESOURCE_IO){
  68                 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
  69                          "phy base 0x%016llx.\n",
  70                         (u64)hose->io_resource.start,
  71                         (u64)hose->io_resource.end - (u64)hose->io_resource.start + 1,
  72                         (u64)hose->io_base_phys);
  73                 out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12));
  74                 out_be32(&pci->pow[i+1].potear, 0);
  75                 out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12));
  76                 /* Enable, IO R/W */
  77                 out_be32(&pci->pow[i+1].powar, 0x80088000
  78                         | (__ilog2(hose->io_resource.end
  79                         - hose->io_resource.start + 1) - 1));
  80         }
  81
  82         /* Setup 2G inbound Memory Window @ 1 */
  83         out_be32(&pci->piw[2].pitar, 0x00000000);
  84         out_be32(&pci->piw[2].piwbar,0x00000000);
  85         out_be32(&pci->piw[2].piwar, PIWAR_2G);
  86 }
  87
  88 void __init setup_pci_cmd(struct pci_controller *hose)
  89 {
  90         u16 cmd;
  91         int cap_x;
  92
  93         early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
  94         cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
  95                 | PCI_COMMAND_IO;
  96         early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
  97
  98         cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
  99         if (cap_x) {
 100                 int pci_x_cmd = cap_x + PCI_X_CMD;
 101                 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
 102                         | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
 103                 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
 104         } else {
 105                 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
 106         }
 107 }
 108
 109 static int fsl_pcie_bus_fixup;
 110
 111 static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
 112 {
 113         /* if we aren't a PCIe don't bother */
 114         if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
 115                 return ;
 116
 117         dev->class = PCI_CLASS_BRIDGE_PCI << 8;
 118         fsl_pcie_bus_fixup = 1;
 119         return ;
 120 }
 121
 122 int __init fsl_pcie_check_link(struct pci_controller *hose)
 123 {
 124         u32 val;
 125         early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
 126         if (val < PCIE_LTSSM_L0)
 127                 return 1;
 128         return 0;
 129 }
 130
 131 void fsl_pcibios_fixup_bus(struct pci_bus *bus)
 132 {
 133         struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
 134         int i;
 135
 136         if ((bus->parent == hose->bus) &&
 137             ((fsl_pcie_bus_fixup &&
 138               early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) ||
 139              (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)))
 140         {
 141                 for (i = 0; i < 4; ++i) {
 142                         struct resource *res = bus->resource[i];
 143                         struct resource *par = bus->parent->resource[i];
 144                         if (res) {
 145                                 res->start = 0;
 146                                 res->end   = 0;
 147                                 res->flags = 0;
 148                         }
 149                         if (res && par) {
 150                                 res->start = par->start;
 151                                 res->end   = par->end;
 152                                 res->flags = par->flags;
 153                         }
 154                 }
 155         }
 156 }
 157
 158 int __init fsl_add_bridge(struct device_node *dev, int is_primary)
 159 {
 160         int len;
 161         struct pci_controller *hose;
 162         struct resource rsrc;
 163         const int *bus_range;
 164
 165         pr_debug("Adding PCI host bridge %s\n", dev->full_name);
 166
 167         /* Fetch host bridge registers address */
 168         if (of_address_to_resource(dev, 0, &rsrc)) {
 169                 printk(KERN_WARNING "Can't get pci register base!");
 170                 return -ENOMEM;
 171         }
 172
 173         /* Get bus range if any */
 174         bus_range = of_get_property(dev, "bus-range", &len);
 175         if (bus_range == NULL || len < 2 * sizeof(int))
 176                 printk(KERN_WARNING "Can't get bus-range for %s, assume"
 177                         " bus 0\n", dev->full_name);
 178
 179         ppc_pci_flags |= PPC_PCI_REASSIGN_ALL_BUS;
 180         hose = pcibios_alloc_controller(dev);
 181         if (!hose)
 182                 return -ENOMEM;
 183
 184         hose->first_busno = bus_range ? bus_range[0] : 0x0;
 185         hose->last_busno = bus_range ? bus_range[1] : 0xff;
 186
 187         setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
 188                 PPC_INDIRECT_TYPE_BIG_ENDIAN);
 189         setup_pci_cmd(hose);
 190
 191         /* check PCI express link status */
 192         if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
 193                 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
 194                         PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
 195                 if (fsl_pcie_check_link(hose))
 196                         hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
 197         }
 198
 199         printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
 200                 "Firmware bus number: %d->%d\n",
 201                 (unsigned long long)rsrc.start, hose->first_busno,
 202                 hose->last_busno);
 203
 204         pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
 205                 hose, hose->cfg_addr, hose->cfg_data);
 206
 207         /* Interpret the "ranges" property */
 208         /* This also maps the I/O region and sets isa_io/mem_base */
 209         pci_process_bridge_OF_ranges(hose, dev, is_primary);
 210
 211         /* Setup PEX window registers */
 212         setup_pci_atmu(hose, &rsrc);
 213
 214         return 0;
 215 }
 216
 217 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_header);
 218 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_header);
 219 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_header);
 220 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header);
 221 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header);
 222 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header);
 223 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header);
 224 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header);
 225 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header);
 226 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header);
 227 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_header);
 228 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_header);
 229 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_header);
 230 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header);
 231 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header);
 232 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header);
 233 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header);
 234 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header);
 235 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header);
 236 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header);