arch/powerpc/platforms/pasemi/iommu.c

   1 /*
   2  * Copyright (C) 2005-2008, PA Semi, Inc
   3  *
   4  * Maintained by: Olof Johansson <olof@lixom.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18  */
  19
  20 #undef DEBUG
  21
  22 #include <linux/types.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/pci.h>
  25 #include <asm/iommu.h>
  26 #include <asm/machdep.h>
  27 #include <asm/abs_addr.h>
  28 #include <asm/firmware.h>
  29
  30 #define IOBMAP_PAGE_SHIFT       12
  31 #define IOBMAP_PAGE_SIZE        (1 << IOBMAP_PAGE_SHIFT)
  32 #define IOBMAP_PAGE_MASK        (IOBMAP_PAGE_SIZE - 1)
  33
  34 #define IOB_BASE                0xe0000000
  35 #define IOB_SIZE                0x3000
  36 /* Configuration registers */
  37 #define IOBCAP_REG              0x40
  38 #define IOBCOM_REG              0x100
  39 /* Enable IOB address translation */
  40 #define IOBCOM_ATEN             0x00000100
  41
  42 /* Address decode configuration register */
  43 #define IOB_AD_REG              0x14c
  44 /* IOBCOM_AD_REG fields */
  45 #define IOB_AD_VGPRT            0x00000e00
  46 #define IOB_AD_VGAEN            0x00000100
  47 /* Direct mapping settings */
  48 #define IOB_AD_MPSEL_MASK       0x00000030
  49 #define IOB_AD_MPSEL_B38        0x00000000
  50 #define IOB_AD_MPSEL_B40        0x00000010
  51 #define IOB_AD_MPSEL_B42        0x00000020
  52 /* Translation window size / enable */
  53 #define IOB_AD_TRNG_MASK        0x00000003
  54 #define IOB_AD_TRNG_256M        0x00000000
  55 #define IOB_AD_TRNG_2G          0x00000001
  56 #define IOB_AD_TRNG_128G        0x00000003
  57
  58 #define IOB_TABLEBASE_REG       0x154
  59
  60 /* Base of the 64 4-byte L1 registers */
  61 #define IOB_XLT_L1_REGBASE      0x2b00
  62
  63 /* Register to invalidate TLB entries */
  64 #define IOB_AT_INVAL_TLB_REG    0x2d00
  65
  66 /* The top two bits of the level 1 entry contains valid and type flags */
  67 #define IOBMAP_L1E_V            0x40000000
  68 #define IOBMAP_L1E_V_B          0x80000000
  69
  70 /* For big page entries, the bottom two bits contains flags */
  71 #define IOBMAP_L1E_BIG_CACHED   0x00000002
  72 #define IOBMAP_L1E_BIG_PRIORITY 0x00000001
  73
  74 /* For regular level 2 entries, top 2 bits contain valid and cache flags */
  75 #define IOBMAP_L2E_V            0x80000000
  76 #define IOBMAP_L2E_V_CACHED     0xc0000000
  77
  78 static void __iomem *iob;
  79 static u32 iob_l1_emptyval;
  80 static u32 iob_l2_emptyval;
  81 static u32 *iob_l2_base;
  82
  83 static struct iommu_table iommu_table_iobmap;
  84 static int iommu_table_iobmap_inited;
  85
  86 static void iobmap_build(struct iommu_table *tbl, long index,
  87                          long npages, unsigned long uaddr,
  88                          enum dma_data_direction direction)
  89 {
  90         u32 *ip;
  91         u32 rpn;
  92         unsigned long bus_addr;
  93
  94         pr_debug("iobmap: build at: %lx, %lx, addr: %lx\n", index, npages, uaddr);
  95
  96         bus_addr = (tbl->it_offset + index) << IOBMAP_PAGE_SHIFT;
  97
  98         ip = ((u32 *)tbl->it_base) + index;
  99
 100         while (npages--) {
 101                 rpn = virt_to_abs(uaddr) >> IOBMAP_PAGE_SHIFT;
 102
 103                 *(ip++) = IOBMAP_L2E_V | rpn;
 104                 /* invalidate tlb, can be optimized more */
 105                 out_le32(iob+IOB_AT_INVAL_TLB_REG, bus_addr >> 14);
 106
 107                 uaddr += IOBMAP_PAGE_SIZE;
 108                 bus_addr += IOBMAP_PAGE_SIZE;
 109         }
 110 }
 111
 112
 113 static void iobmap_free(struct iommu_table *tbl, long index,
 114                         long npages)
 115 {
 116         u32 *ip;
 117         unsigned long bus_addr;
 118
 119         pr_debug("iobmap: free at: %lx, %lx\n", index, npages);
 120
 121         bus_addr = (tbl->it_offset + index) << IOBMAP_PAGE_SHIFT;
 122
 123         ip = ((u32 *)tbl->it_base) + index;
 124
 125         while (npages--) {
 126                 *(ip++) = iob_l2_emptyval;
 127                 /* invalidate tlb, can be optimized more */
 128                 out_le32(iob+IOB_AT_INVAL_TLB_REG, bus_addr >> 14);
 129                 bus_addr += IOBMAP_PAGE_SIZE;
 130         }
 131 }
 132
 133
 134 static void iommu_table_iobmap_setup(void)
 135 {
 136         pr_debug(" -> %s\n", __func__);
 137         iommu_table_iobmap.it_busno = 0;
 138         iommu_table_iobmap.it_offset = 0;
 139         /* it_size is in number of entries */
 140         iommu_table_iobmap.it_size = 0x80000000 >> IOBMAP_PAGE_SHIFT;
 141
 142         /* Initialize the common IOMMU code */
 143         iommu_table_iobmap.it_base = (unsigned long)iob_l2_base;
 144         iommu_table_iobmap.it_index = 0;
 145         /* XXXOJN tune this to avoid IOB cache invals.
 146          * Should probably be 8 (64 bytes)
 147          */
 148         iommu_table_iobmap.it_blocksize = 4;
 149         iommu_init_table(&iommu_table_iobmap, 0);
 150         pr_debug(" <- %s\n", __func__);
 151 }
 152
 153
 154
 155 static void pci_dma_bus_setup_pasemi(struct pci_bus *bus)
 156 {
 157         struct device_node *dn;
 158
 159         pr_debug("pci_dma_bus_setup, bus %p, bus->self %p\n", bus, bus->self);
 160
 161         if (!iommu_table_iobmap_inited) {
 162                 iommu_table_iobmap_inited = 1;
 163                 iommu_table_iobmap_setup();
 164         }
 165
 166         dn = pci_bus_to_OF_node(bus);
 167
 168         if (dn)
 169                 PCI_DN(dn)->iommu_table = &iommu_table_iobmap;
 170
 171 }
 172
 173
 174 static void pci_dma_dev_setup_pasemi(struct pci_dev *dev)
 175 {
 176         pr_debug("pci_dma_dev_setup, dev %p (%s)\n", dev, pci_name(dev));
 177
 178 #if !defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE)
 179         /* For non-LPAR environment, don't translate anything for the DMA
 180          * engine. The exception to this is if the user has enabled
 181          * CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE at build time.
 182          */
 183         if (dev->vendor == 0x1959 && dev->device == 0xa007 &&
 184             !firmware_has_feature(FW_FEATURE_LPAR)) {
 185                 dev->dev.archdata.dma_ops = &dma_direct_ops;
 186                 return;
 187         }
 188 #endif
 189
 190         dev->dev.archdata.dma_data = &iommu_table_iobmap;
 191 }
 192
 193 static void pci_dma_bus_setup_null(struct pci_bus *b) { }
 194 static void pci_dma_dev_setup_null(struct pci_dev *d) { }
 195
 196 int __init iob_init(struct device_node *dn)
 197 {
 198         unsigned long tmp;
 199         u32 regword;
 200         int i;
 201
 202         pr_debug(" -> %s\n", __func__);
 203
 204         /* Allocate a spare page to map all invalid IOTLB pages. */
 205         tmp = lmb_alloc(IOBMAP_PAGE_SIZE, IOBMAP_PAGE_SIZE);
 206         if (!tmp)
 207                 panic("IOBMAP: Cannot allocate spare page!");
 208         /* Empty l1 is marked invalid */
 209         iob_l1_emptyval = 0;
 210         /* Empty l2 is mapped to dummy page */
 211         iob_l2_emptyval = IOBMAP_L2E_V | (tmp >> IOBMAP_PAGE_SHIFT);
 212
 213         iob = ioremap(IOB_BASE, IOB_SIZE);
 214         if (!iob)
 215                 panic("IOBMAP: Cannot map registers!");
 216
 217         /* setup direct mapping of the L1 entries */
 218         for (i = 0; i < 64; i++) {
 219                 /* Each L1 covers 32MB, i.e. 8K entries = 32K of ram */
 220                 regword = IOBMAP_L1E_V | (__pa(iob_l2_base + i*0x2000) >> 12);
 221                 out_le32(iob+IOB_XLT_L1_REGBASE+i*4, regword);
 222         }
 223
 224         /* set 2GB translation window, based at 0 */
 225         regword = in_le32(iob+IOB_AD_REG);
 226         regword &= ~IOB_AD_TRNG_MASK;
 227         regword |= IOB_AD_TRNG_2G;
 228         out_le32(iob+IOB_AD_REG, regword);
 229
 230         /* Enable translation */
 231         regword = in_le32(iob+IOBCOM_REG);
 232         regword |= IOBCOM_ATEN;
 233         out_le32(iob+IOBCOM_REG, regword);
 234
 235         pr_debug(" <- %s\n", __func__);
 236
 237         return 0;
 238 }
 239
 240
 241 /* These are called very early. */
 242 void __init iommu_init_early_pasemi(void)
 243 {
 244         int iommu_off;
 245
 246 #ifndef CONFIG_PPC_PASEMI_IOMMU
 247         iommu_off = 1;
 248 #else
 249         iommu_off = of_chosen &&
 250                         of_get_property(of_chosen, "linux,iommu-off", NULL);
 251 #endif
 252         if (iommu_off) {
 253                 /* Direct I/O, IOMMU off */
 254                 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_null;
 255                 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_null;
 256                 set_pci_dma_ops(&dma_direct_ops);
 257
 258                 return;
 259         }
 260
 261         iob_init(NULL);
 262
 263         ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pasemi;
 264         ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pasemi;
 265         ppc_md.tce_build = iobmap_build;
 266         ppc_md.tce_free  = iobmap_free;
 267         set_pci_dma_ops(&dma_iommu_ops);
 268 }
 269
 270 void __init alloc_iobmap_l2(void)
 271 {
 272 #ifndef CONFIG_PPC_PASEMI_IOMMU
 273         return;
 274 #endif
 275         /* For 2G space, 8x64 pages (2^21 bytes) is max total l2 size */
 276         iob_l2_base = (u32 *)abs_to_virt(lmb_alloc_base(1UL<<21, 1UL<<21, 0x80000000));
 277
 278         printk(KERN_INFO "IOBMAP L2 allocated at: %p\n", iob_l2_base);
 279 }