ibm_emac: Remove the ibm_emac driver
[linux-2.6/btrfs-unstable.git] / arch / powerpc / kernel / setup_32.c
blob5112a4aa801d7d6843c2202c7815147831a74d2e
1 /*
2 * Common prep/pmac/chrp boot and setup code.
3 */
5 #include <linux/module.h>
6 #include <linux/string.h>
7 #include <linux/sched.h>
8 #include <linux/init.h>
9 #include <linux/kernel.h>
10 #include <linux/reboot.h>
11 #include <linux/delay.h>
12 #include <linux/initrd.h>
13 #include <linux/tty.h>
14 #include <linux/bootmem.h>
15 #include <linux/seq_file.h>
16 #include <linux/root_dev.h>
17 #include <linux/cpu.h>
18 #include <linux/console.h>
19 #include <linux/lmb.h>
21 #include <asm/io.h>
22 #include <asm/prom.h>
23 #include <asm/processor.h>
24 #include <asm/pgtable.h>
25 #include <asm/setup.h>
26 #include <asm/smp.h>
27 #include <asm/elf.h>
28 #include <asm/cputable.h>
29 #include <asm/bootx.h>
30 #include <asm/btext.h>
31 #include <asm/machdep.h>
32 #include <asm/uaccess.h>
33 #include <asm/system.h>
34 #include <asm/pmac_feature.h>
35 #include <asm/sections.h>
36 #include <asm/nvram.h>
37 #include <asm/xmon.h>
38 #include <asm/time.h>
39 #include <asm/serial.h>
40 #include <asm/udbg.h>
42 #include "setup.h"
44 #define DBG(fmt...)
46 #if defined CONFIG_KGDB
47 #include <asm/kgdb.h>
48 #endif
50 extern void bootx_init(unsigned long r4, unsigned long phys);
52 int boot_cpuid;
53 EXPORT_SYMBOL_GPL(boot_cpuid);
54 int boot_cpuid_phys;
56 unsigned long ISA_DMA_THRESHOLD;
57 unsigned int DMA_MODE_READ;
58 unsigned int DMA_MODE_WRITE;
60 int have_of = 1;
62 #ifdef CONFIG_VGA_CONSOLE
63 unsigned long vgacon_remap_base;
64 EXPORT_SYMBOL(vgacon_remap_base);
65 #endif
68 * These are used in binfmt_elf.c to put aux entries on the stack
69 * for each elf executable being started.
71 int dcache_bsize;
72 int icache_bsize;
73 int ucache_bsize;
76 * We're called here very early in the boot. We determine the machine
77 * type and call the appropriate low-level setup functions.
78 * -- Cort <cort@fsmlabs.com>
80 * Note that the kernel may be running at an address which is different
81 * from the address that it was linked at, so we must use RELOC/PTRRELOC
82 * to access static data (including strings). -- paulus
84 unsigned long __init early_init(unsigned long dt_ptr)
86 unsigned long offset = reloc_offset();
87 struct cpu_spec *spec;
89 /* First zero the BSS -- use memset_io, some platforms don't have
90 * caches on yet */
91 memset_io((void __iomem *)PTRRELOC(&__bss_start), 0,
92 __bss_stop - __bss_start);
95 * Identify the CPU type and fix up code sections
96 * that depend on which cpu we have.
98 spec = identify_cpu(offset, mfspr(SPRN_PVR));
100 do_feature_fixups(spec->cpu_features,
101 PTRRELOC(&__start___ftr_fixup),
102 PTRRELOC(&__stop___ftr_fixup));
104 return KERNELBASE + offset;
109 * Find out what kind of machine we're on and save any data we need
110 * from the early boot process (devtree is copied on pmac by prom_init()).
111 * This is called very early on the boot process, after a minimal
112 * MMU environment has been set up but before MMU_init is called.
114 void __init machine_init(unsigned long dt_ptr, unsigned long phys)
116 /* Enable early debugging if any specified (see udbg.h) */
117 udbg_early_init();
119 /* Do some early initialization based on the flat device tree */
120 early_init_devtree(__va(dt_ptr));
122 probe_machine();
124 #ifdef CONFIG_6xx
125 if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
126 cpu_has_feature(CPU_FTR_CAN_NAP))
127 ppc_md.power_save = ppc6xx_idle;
128 #endif
130 if (ppc_md.progress)
131 ppc_md.progress("id mach(): done", 0x200);
134 #ifdef CONFIG_BOOKE_WDT
135 /* Checks wdt=x and wdt_period=xx command-line option */
136 int __init early_parse_wdt(char *p)
138 if (p && strncmp(p, "0", 1) != 0)
139 booke_wdt_enabled = 1;
141 return 0;
143 early_param("wdt", early_parse_wdt);
145 int __init early_parse_wdt_period (char *p)
147 if (p)
148 booke_wdt_period = simple_strtoul(p, NULL, 0);
150 return 0;
152 early_param("wdt_period", early_parse_wdt_period);
153 #endif /* CONFIG_BOOKE_WDT */
155 /* Checks "l2cr=xxxx" command-line option */
156 int __init ppc_setup_l2cr(char *str)
158 if (cpu_has_feature(CPU_FTR_L2CR)) {
159 unsigned long val = simple_strtoul(str, NULL, 0);
160 printk(KERN_INFO "l2cr set to %lx\n", val);
161 _set_L2CR(0); /* force invalidate by disable cache */
162 _set_L2CR(val); /* and enable it */
164 return 1;
166 __setup("l2cr=", ppc_setup_l2cr);
168 /* Checks "l3cr=xxxx" command-line option */
169 int __init ppc_setup_l3cr(char *str)
171 if (cpu_has_feature(CPU_FTR_L3CR)) {
172 unsigned long val = simple_strtoul(str, NULL, 0);
173 printk(KERN_INFO "l3cr set to %lx\n", val);
174 _set_L3CR(val); /* and enable it */
176 return 1;
178 __setup("l3cr=", ppc_setup_l3cr);
180 #ifdef CONFIG_GENERIC_NVRAM
182 /* Generic nvram hooks used by drivers/char/gen_nvram.c */
183 unsigned char nvram_read_byte(int addr)
185 if (ppc_md.nvram_read_val)
186 return ppc_md.nvram_read_val(addr);
187 return 0xff;
189 EXPORT_SYMBOL(nvram_read_byte);
191 void nvram_write_byte(unsigned char val, int addr)
193 if (ppc_md.nvram_write_val)
194 ppc_md.nvram_write_val(addr, val);
196 EXPORT_SYMBOL(nvram_write_byte);
198 void nvram_sync(void)
200 if (ppc_md.nvram_sync)
201 ppc_md.nvram_sync();
203 EXPORT_SYMBOL(nvram_sync);
205 #endif /* CONFIG_NVRAM */
207 static DEFINE_PER_CPU(struct cpu, cpu_devices);
209 int __init ppc_init(void)
211 int cpu;
213 /* clear the progress line */
214 if (ppc_md.progress)
215 ppc_md.progress(" ", 0xffff);
217 /* register CPU devices */
218 for_each_possible_cpu(cpu) {
219 struct cpu *c = &per_cpu(cpu_devices, cpu);
220 c->hotpluggable = 1;
221 register_cpu(c, cpu);
224 /* call platform init */
225 if (ppc_md.init != NULL) {
226 ppc_md.init();
228 return 0;
231 arch_initcall(ppc_init);
233 #ifdef CONFIG_IRQSTACKS
234 static void __init irqstack_early_init(void)
236 unsigned int i;
238 /* interrupt stacks must be in lowmem, we get that for free on ppc32
239 * as the lmb is limited to lowmem by LMB_REAL_LIMIT */
240 for_each_possible_cpu(i) {
241 softirq_ctx[i] = (struct thread_info *)
242 __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
243 hardirq_ctx[i] = (struct thread_info *)
244 __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
247 #else
248 #define irqstack_early_init()
249 #endif
251 /* Warning, IO base is not yet inited */
252 void __init setup_arch(char **cmdline_p)
254 *cmdline_p = cmd_line;
256 /* so udelay does something sensible, assume <= 1000 bogomips */
257 loops_per_jiffy = 500000000 / HZ;
259 unflatten_device_tree();
260 check_for_initrd();
262 if (ppc_md.init_early)
263 ppc_md.init_early();
265 find_legacy_serial_ports();
267 smp_setup_cpu_maps();
269 /* Register early console */
270 register_early_udbg_console();
272 xmon_setup();
274 #if defined(CONFIG_KGDB)
275 if (ppc_md.kgdb_map_scc)
276 ppc_md.kgdb_map_scc();
277 set_debug_traps();
278 if (strstr(cmd_line, "gdb")) {
279 if (ppc_md.progress)
280 ppc_md.progress("setup_arch: kgdb breakpoint", 0x4000);
281 printk("kgdb breakpoint activated\n");
282 breakpoint();
284 #endif
287 * Set cache line size based on type of cpu as a default.
288 * Systems with OF can look in the properties on the cpu node(s)
289 * for a possibly more accurate value.
291 dcache_bsize = cur_cpu_spec->dcache_bsize;
292 icache_bsize = cur_cpu_spec->icache_bsize;
293 ucache_bsize = 0;
294 if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))
295 ucache_bsize = icache_bsize = dcache_bsize;
297 /* reboot on panic */
298 panic_timeout = 180;
300 if (ppc_md.panic)
301 setup_panic();
303 init_mm.start_code = (unsigned long)_stext;
304 init_mm.end_code = (unsigned long) _etext;
305 init_mm.end_data = (unsigned long) _edata;
306 init_mm.brk = klimit;
308 irqstack_early_init();
310 /* set up the bootmem stuff with available memory */
311 do_init_bootmem();
312 if ( ppc_md.progress ) ppc_md.progress("setup_arch: bootmem", 0x3eab);
314 #ifdef CONFIG_DUMMY_CONSOLE
315 conswitchp = &dummy_con;
316 #endif
318 if (ppc_md.setup_arch)
319 ppc_md.setup_arch();
320 if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab);
322 paging_init();