?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
net: macb: Add ethtool get_ringparam and set_ringparam functionality
[linux-2.6/btrfs-unstable.git] / drivers / net / ethernet / cadence / macb.c
blobe1847ce6308deba39998fcdd81e9d3d272a23873
1 /*
2 * Cadence MACB/GEM Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/circ_buf.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
20 #include <linux/io.h>
21 #include <linux/gpio.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/interrupt.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_data/macb.h>
28 #include <linux/platform_device.h>
29 #include <linux/phy.h>
30 #include <linux/of.h>
31 #include <linux/of_device.h>
32 #include <linux/of_gpio.h>
33 #include <linux/of_mdio.h>
34 #include <linux/of_net.h>
35
36 #include "macb.h"
37
38 #define MACB_RX_BUFFER_SIZE 128
39 #define RX_BUFFER_MULTIPLE 64 /* bytes */
40
41 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
42 #define MIN_RX_RING_SIZE 64
43 #define MAX_RX_RING_SIZE 8192
44 #define RX_RING_BYTES(bp) (sizeof(struct macb_dma_desc) \
45 * (bp)->rx_ring_size)
46
47 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
48 #define MIN_TX_RING_SIZE 64
49 #define MAX_TX_RING_SIZE 4096
50 #define TX_RING_BYTES(bp) (sizeof(struct macb_dma_desc) \
51 * (bp)->tx_ring_size)
52
53 /* level of occupied TX descriptors under which we wake up TX process */
54 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
55
56 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
57 | MACB_BIT(ISR_ROVR))
58 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
59 | MACB_BIT(ISR_RLE) \
60 | MACB_BIT(TXERR))
61 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
62
63 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1))
64 #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1))
65
66 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
67
68 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
69 #define MACB_WOL_ENABLED (0x1 << 1)
70
71 /* Graceful stop timeouts in us. We should allow up to
72 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
73 */
74 #define MACB_HALT_TIMEOUT 1230
75
76 /* Ring buffer accessors */
77 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
78 {
79 return index & (bp->tx_ring_size - 1);
80 }
81
82 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
83 unsigned int index)
84 {
85 return &queue->tx_ring[macb_tx_ring_wrap(queue->bp, index)];
86 }
87
88 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
89 unsigned int index)
90 {
91 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
92 }
93
94 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
95 {
96 dma_addr_t offset;
97
98 offset = macb_tx_ring_wrap(queue->bp, index) *
99 sizeof(struct macb_dma_desc);
100
101 return queue->tx_ring_dma + offset;
102 }
103
104 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
105 {
106 return index & (bp->rx_ring_size - 1);
107 }
108
109 static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
110 {
111 return &bp->rx_ring[macb_rx_ring_wrap(bp, index)];
112 }
113
114 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
115 {
116 return bp->rx_buffers + bp->rx_buffer_size *
117 macb_rx_ring_wrap(bp, index);
118 }
119
120 /* I/O accessors */
121 static u32 hw_readl_native(struct macb *bp, int offset)
122 {
123 return __raw_readl(bp->regs + offset);
124 }
125
126 static void hw_writel_native(struct macb *bp, int offset, u32 value)
127 {
128 __raw_writel(value, bp->regs + offset);
129 }
130
131 static u32 hw_readl(struct macb *bp, int offset)
132 {
133 return readl_relaxed(bp->regs + offset);
134 }
135
136 static void hw_writel(struct macb *bp, int offset, u32 value)
137 {
138 writel_relaxed(value, bp->regs + offset);
139 }
140
141 /* Find the CPU endianness by using the loopback bit of NCR register. When the
142 * CPU is in big endian we need to program swapped mode for management
143 * descriptor access.
144 */
145 static bool hw_is_native_io(void __iomem *addr)
146 {
147 u32 value = MACB_BIT(LLB);
148
149 __raw_writel(value, addr + MACB_NCR);
150 value = __raw_readl(addr + MACB_NCR);
151
152 /* Write 0 back to disable everything */
153 __raw_writel(0, addr + MACB_NCR);
154
155 return value == MACB_BIT(LLB);
156 }
157
158 static bool hw_is_gem(void __iomem *addr, bool native_io)
159 {
160 u32 id;
161
162 if (native_io)
163 id = __raw_readl(addr + MACB_MID);
164 else
165 id = readl_relaxed(addr + MACB_MID);
166
167 return MACB_BFEXT(IDNUM, id) >= 0x2;
168 }
169
170 static void macb_set_hwaddr(struct macb *bp)
171 {
172 u32 bottom;
173 u16 top;
174
175 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
176 macb_or_gem_writel(bp, SA1B, bottom);
177 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
178 macb_or_gem_writel(bp, SA1T, top);
179
180 /* Clear unused address register sets */
181 macb_or_gem_writel(bp, SA2B, 0);
182 macb_or_gem_writel(bp, SA2T, 0);
183 macb_or_gem_writel(bp, SA3B, 0);
184 macb_or_gem_writel(bp, SA3T, 0);
185 macb_or_gem_writel(bp, SA4B, 0);
186 macb_or_gem_writel(bp, SA4T, 0);
187 }
188
189 static void macb_get_hwaddr(struct macb *bp)
190 {
191 struct macb_platform_data *pdata;
192 u32 bottom;
193 u16 top;
194 u8 addr[6];
195 int i;
196
197 pdata = dev_get_platdata(&bp->pdev->dev);
198
199 /* Check all 4 address register for valid address */
200 for (i = 0; i < 4; i++) {
201 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
202 top = macb_or_gem_readl(bp, SA1T + i * 8);
203
204 if (pdata && pdata->rev_eth_addr) {
205 addr[5] = bottom & 0xff;
206 addr[4] = (bottom >> 8) & 0xff;
207 addr[3] = (bottom >> 16) & 0xff;
208 addr[2] = (bottom >> 24) & 0xff;
209 addr[1] = top & 0xff;
210 addr[0] = (top & 0xff00) >> 8;
211 } else {
212 addr[0] = bottom & 0xff;
213 addr[1] = (bottom >> 8) & 0xff;
214 addr[2] = (bottom >> 16) & 0xff;
215 addr[3] = (bottom >> 24) & 0xff;
216 addr[4] = top & 0xff;
217 addr[5] = (top >> 8) & 0xff;
218 }
219
220 if (is_valid_ether_addr(addr)) {
221 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
222 return;
223 }
224 }
225
226 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
227 eth_hw_addr_random(bp->dev);
228 }
229
230 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
231 {
232 struct macb *bp = bus->priv;
233 int value;
234
235 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
236 | MACB_BF(RW, MACB_MAN_READ)
237 | MACB_BF(PHYA, mii_id)
238 | MACB_BF(REGA, regnum)
239 | MACB_BF(CODE, MACB_MAN_CODE)));
240
241 /* wait for end of transfer */
242 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
243 cpu_relax();
244
245 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
246
247 return value;
248 }
249
250 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
251 u16 value)
252 {
253 struct macb *bp = bus->priv;
254
255 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
256 | MACB_BF(RW, MACB_MAN_WRITE)
257 | MACB_BF(PHYA, mii_id)
258 | MACB_BF(REGA, regnum)
259 | MACB_BF(CODE, MACB_MAN_CODE)
260 | MACB_BF(DATA, value)));
261
262 /* wait for end of transfer */
263 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
264 cpu_relax();
265
266 return 0;
267 }
268
269 /**
270 * macb_set_tx_clk() - Set a clock to a new frequency
271 * @clk Pointer to the clock to change
272 * @rate New frequency in Hz
273 * @dev Pointer to the struct net_device
274 */
275 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
276 {
277 long ferr, rate, rate_rounded;
278
279 if (!clk)
280 return;
281
282 switch (speed) {
283 case SPEED_10:
284 rate = 2500000;
285 break;
286 case SPEED_100:
287 rate = 25000000;
288 break;
289 case SPEED_1000:
290 rate = 125000000;
291 break;
292 default:
293 return;
294 }
295
296 rate_rounded = clk_round_rate(clk, rate);
297 if (rate_rounded < 0)
298 return;
299
300 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
301 * is not satisfied.
302 */
303 ferr = abs(rate_rounded - rate);
304 ferr = DIV_ROUND_UP(ferr, rate / 100000);
305 if (ferr > 5)
306 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
307 rate);
308
309 if (clk_set_rate(clk, rate_rounded))
310 netdev_err(dev, "adjusting tx_clk failed.\n");
311 }
312
313 static void macb_handle_link_change(struct net_device *dev)
314 {
315 struct macb *bp = netdev_priv(dev);
316 struct phy_device *phydev = dev->phydev;
317 unsigned long flags;
318 int status_change = 0;
319
320 spin_lock_irqsave(&bp->lock, flags);
321
322 if (phydev->link) {
323 if ((bp->speed != phydev->speed) ||
324 (bp->duplex != phydev->duplex)) {
325 u32 reg;
326
327 reg = macb_readl(bp, NCFGR);
328 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
329 if (macb_is_gem(bp))
330 reg &= ~GEM_BIT(GBE);
331
332 if (phydev->duplex)
333 reg |= MACB_BIT(FD);
334 if (phydev->speed == SPEED_100)
335 reg |= MACB_BIT(SPD);
336 if (phydev->speed == SPEED_1000 &&
337 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
338 reg |= GEM_BIT(GBE);
339
340 macb_or_gem_writel(bp, NCFGR, reg);
341
342 bp->speed = phydev->speed;
343 bp->duplex = phydev->duplex;
344 status_change = 1;
345 }
346 }
347
348 if (phydev->link != bp->link) {
349 if (!phydev->link) {
350 bp->speed = 0;
351 bp->duplex = -1;
352 }
353 bp->link = phydev->link;
354
355 status_change = 1;
356 }
357
358 spin_unlock_irqrestore(&bp->lock, flags);
359
360 if (status_change) {
361 if (phydev->link) {
362 /* Update the TX clock rate if and only if the link is
363 * up and there has been a link change.
364 */
365 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
366
367 netif_carrier_on(dev);
368 netdev_info(dev, "link up (%d/%s)\n",
369 phydev->speed,
370 phydev->duplex == DUPLEX_FULL ?
371 "Full" : "Half");
372 } else {
373 netif_carrier_off(dev);
374 netdev_info(dev, "link down\n");
375 }
376 }
377 }
378
379 /* based on au1000_eth. c*/
380 static int macb_mii_probe(struct net_device *dev)
381 {
382 struct macb *bp = netdev_priv(dev);
383 struct macb_platform_data *pdata;
384 struct phy_device *phydev;
385 int phy_irq;
386 int ret;
387
388 phydev = phy_find_first(bp->mii_bus);
389 if (!phydev) {
390 netdev_err(dev, "no PHY found\n");
391 return -ENXIO;
392 }
393
394 pdata = dev_get_platdata(&bp->pdev->dev);
395 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
396 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin,
397 "phy int");
398 if (!ret) {
399 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
400 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
401 }
402 }
403
404 /* attach the mac to the phy */
405 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
406 bp->phy_interface);
407 if (ret) {
408 netdev_err(dev, "Could not attach to PHY\n");
409 return ret;
410 }
411
412 /* mask with MAC supported features */
413 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
414 phydev->supported &= PHY_GBIT_FEATURES;
415 else
416 phydev->supported &= PHY_BASIC_FEATURES;
417
418 if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF)
419 phydev->supported &= ~SUPPORTED_1000baseT_Half;
420
421 phydev->advertising = phydev->supported;
422
423 bp->link = 0;
424 bp->speed = 0;
425 bp->duplex = -1;
426
427 return 0;
428 }
429
430 static int macb_mii_init(struct macb *bp)
431 {
432 struct macb_platform_data *pdata;
433 struct device_node *np;
434 int err = -ENXIO, i;
435
436 /* Enable management port */
437 macb_writel(bp, NCR, MACB_BIT(MPE));
438
439 bp->mii_bus = mdiobus_alloc();
440 if (!bp->mii_bus) {
441 err = -ENOMEM;
442 goto err_out;
443 }
444
445 bp->mii_bus->name = "MACB_mii_bus";
446 bp->mii_bus->read = &macb_mdio_read;
447 bp->mii_bus->write = &macb_mdio_write;
448 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
449 bp->pdev->name, bp->pdev->id);
450 bp->mii_bus->priv = bp;
451 bp->mii_bus->parent = &bp->pdev->dev;
452 pdata = dev_get_platdata(&bp->pdev->dev);
453
454 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
455
456 np = bp->pdev->dev.of_node;
457 if (np) {
458 /* try dt phy registration */
459 err = of_mdiobus_register(bp->mii_bus, np);
460
461 /* fallback to standard phy registration if no phy were
462 * found during dt phy registration
463 */
464 if (!err && !phy_find_first(bp->mii_bus)) {
465 for (i = 0; i < PHY_MAX_ADDR; i++) {
466 struct phy_device *phydev;
467
468 phydev = mdiobus_scan(bp->mii_bus, i);
469 if (IS_ERR(phydev) &&
470 PTR_ERR(phydev) != -ENODEV) {
471 err = PTR_ERR(phydev);
472 break;
473 }
474 }
475
476 if (err)
477 goto err_out_unregister_bus;
478 }
479 } else {
480 if (pdata)
481 bp->mii_bus->phy_mask = pdata->phy_mask;
482
483 err = mdiobus_register(bp->mii_bus);
484 }
485
486 if (err)
487 goto err_out_free_mdiobus;
488
489 err = macb_mii_probe(bp->dev);
490 if (err)
491 goto err_out_unregister_bus;
492
493 return 0;
494
495 err_out_unregister_bus:
496 mdiobus_unregister(bp->mii_bus);
497 err_out_free_mdiobus:
498 mdiobus_free(bp->mii_bus);
499 err_out:
500 return err;
501 }
502
503 static void macb_update_stats(struct macb *bp)
504 {
505 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
506 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
507 int offset = MACB_PFR;
508
509 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
510
511 for (; p < end; p++, offset += 4)
512 *p += bp->macb_reg_readl(bp, offset);
513 }
514
515 static int macb_halt_tx(struct macb *bp)
516 {
517 unsigned long halt_time, timeout;
518 u32 status;
519
520 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
521
522 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
523 do {
524 halt_time = jiffies;
525 status = macb_readl(bp, TSR);
526 if (!(status & MACB_BIT(TGO)))
527 return 0;
528
529 usleep_range(10, 250);
530 } while (time_before(halt_time, timeout));
531
532 return -ETIMEDOUT;
533 }
534
535 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
536 {
537 if (tx_skb->mapping) {
538 if (tx_skb->mapped_as_page)
539 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
540 tx_skb->size, DMA_TO_DEVICE);
541 else
542 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
543 tx_skb->size, DMA_TO_DEVICE);
544 tx_skb->mapping = 0;
545 }
546
547 if (tx_skb->skb) {
548 dev_kfree_skb_any(tx_skb->skb);
549 tx_skb->skb = NULL;
550 }
551 }
552
553 static inline void macb_set_addr(struct macb_dma_desc *desc, dma_addr_t addr)
554 {
555 desc->addr = (u32)addr;
556 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
557 desc->addrh = (u32)(addr >> 32);
558 #endif
559 }
560
561 static void macb_tx_error_task(struct work_struct *work)
562 {
563 struct macb_queue *queue = container_of(work, struct macb_queue,
564 tx_error_task);
565 struct macb *bp = queue->bp;
566 struct macb_tx_skb *tx_skb;
567 struct macb_dma_desc *desc;
568 struct sk_buff *skb;
569 unsigned int tail;
570 unsigned long flags;
571
572 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
573 (unsigned int)(queue - bp->queues),
574 queue->tx_tail, queue->tx_head);
575
576 /* Prevent the queue IRQ handlers from running: each of them may call
577 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
578 * As explained below, we have to halt the transmission before updating
579 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
580 * network engine about the macb/gem being halted.
581 */
582 spin_lock_irqsave(&bp->lock, flags);
583
584 /* Make sure nobody is trying to queue up new packets */
585 netif_tx_stop_all_queues(bp->dev);
586
587 /* Stop transmission now
588 * (in case we have just queued new packets)
589 * macb/gem must be halted to write TBQP register
590 */
591 if (macb_halt_tx(bp))
592 /* Just complain for now, reinitializing TX path can be good */
593 netdev_err(bp->dev, "BUG: halt tx timed out\n");
594
595 /* Treat frames in TX queue including the ones that caused the error.
596 * Free transmit buffers in upper layer.
597 */
598 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
599 u32 ctrl;
600
601 desc = macb_tx_desc(queue, tail);
602 ctrl = desc->ctrl;
603 tx_skb = macb_tx_skb(queue, tail);
604 skb = tx_skb->skb;
605
606 if (ctrl & MACB_BIT(TX_USED)) {
607 /* skb is set for the last buffer of the frame */
608 while (!skb) {
609 macb_tx_unmap(bp, tx_skb);
610 tail++;
611 tx_skb = macb_tx_skb(queue, tail);
612 skb = tx_skb->skb;
613 }
614
615 /* ctrl still refers to the first buffer descriptor
616 * since it's the only one written back by the hardware
617 */
618 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
619 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
620 macb_tx_ring_wrap(bp, tail),
621 skb->data);
622 bp->stats.tx_packets++;
623 bp->stats.tx_bytes += skb->len;
624 }
625 } else {
626 /* "Buffers exhausted mid-frame" errors may only happen
627 * if the driver is buggy, so complain loudly about
628 * those. Statistics are updated by hardware.
629 */
630 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
631 netdev_err(bp->dev,
632 "BUG: TX buffers exhausted mid-frame\n");
633
634 desc->ctrl = ctrl | MACB_BIT(TX_USED);
635 }
636
637 macb_tx_unmap(bp, tx_skb);
638 }
639
640 /* Set end of TX queue */
641 desc = macb_tx_desc(queue, 0);
642 macb_set_addr(desc, 0);
643 desc->ctrl = MACB_BIT(TX_USED);
644
645 /* Make descriptor updates visible to hardware */
646 wmb();
647
648 /* Reinitialize the TX desc queue */
649 queue_writel(queue, TBQP, (u32)(queue->tx_ring_dma));
650 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
651 queue_writel(queue, TBQPH, (u32)(queue->tx_ring_dma >> 32));
652 #endif
653 /* Make TX ring reflect state of hardware */
654 queue->tx_head = 0;
655 queue->tx_tail = 0;
656
657 /* Housework before enabling TX IRQ */
658 macb_writel(bp, TSR, macb_readl(bp, TSR));
659 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
660
661 /* Now we are ready to start transmission again */
662 netif_tx_start_all_queues(bp->dev);
663 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
664
665 spin_unlock_irqrestore(&bp->lock, flags);
666 }
667
668 static void macb_tx_interrupt(struct macb_queue *queue)
669 {
670 unsigned int tail;
671 unsigned int head;
672 u32 status;
673 struct macb *bp = queue->bp;
674 u16 queue_index = queue - bp->queues;
675
676 status = macb_readl(bp, TSR);
677 macb_writel(bp, TSR, status);
678
679 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
680 queue_writel(queue, ISR, MACB_BIT(TCOMP));
681
682 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
683 (unsigned long)status);
684
685 head = queue->tx_head;
686 for (tail = queue->tx_tail; tail != head; tail++) {
687 struct macb_tx_skb *tx_skb;
688 struct sk_buff *skb;
689 struct macb_dma_desc *desc;
690 u32 ctrl;
691
692 desc = macb_tx_desc(queue, tail);
693
694 /* Make hw descriptor updates visible to CPU */
695 rmb();
696
697 ctrl = desc->ctrl;
698
699 /* TX_USED bit is only set by hardware on the very first buffer
700 * descriptor of the transmitted frame.
701 */
702 if (!(ctrl & MACB_BIT(TX_USED)))
703 break;
704
705 /* Process all buffers of the current transmitted frame */
706 for (;; tail++) {
707 tx_skb = macb_tx_skb(queue, tail);
708 skb = tx_skb->skb;
709
710 /* First, update TX stats if needed */
711 if (skb) {
712 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
713 macb_tx_ring_wrap(bp, tail),
714 skb->data);
715 bp->stats.tx_packets++;
716 bp->stats.tx_bytes += skb->len;
717 }
718
719 /* Now we can safely release resources */
720 macb_tx_unmap(bp, tx_skb);
721
722 /* skb is set only for the last buffer of the frame.
723 * WARNING: at this point skb has been freed by
724 * macb_tx_unmap().
725 */
726 if (skb)
727 break;
728 }
729 }
730
731 queue->tx_tail = tail;
732 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
733 CIRC_CNT(queue->tx_head, queue->tx_tail,
734 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
735 netif_wake_subqueue(bp->dev, queue_index);
736 }
737
738 static void gem_rx_refill(struct macb *bp)
739 {
740 unsigned int entry;
741 struct sk_buff *skb;
742 dma_addr_t paddr;
743
744 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail,
745 bp->rx_ring_size) > 0) {
746 entry = macb_rx_ring_wrap(bp, bp->rx_prepared_head);
747
748 /* Make hw descriptor updates visible to CPU */
749 rmb();
750
751 bp->rx_prepared_head++;
752
753 if (!bp->rx_skbuff[entry]) {
754 /* allocate sk_buff for this free entry in ring */
755 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
756 if (unlikely(!skb)) {
757 netdev_err(bp->dev,
758 "Unable to allocate sk_buff\n");
759 break;
760 }
761
762 /* now fill corresponding descriptor entry */
763 paddr = dma_map_single(&bp->pdev->dev, skb->data,
764 bp->rx_buffer_size,
765 DMA_FROM_DEVICE);
766 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
767 dev_kfree_skb(skb);
768 break;
769 }
770
771 bp->rx_skbuff[entry] = skb;
772
773 if (entry == bp->rx_ring_size - 1)
774 paddr |= MACB_BIT(RX_WRAP);
775 macb_set_addr(&(bp->rx_ring[entry]), paddr);
776 bp->rx_ring[entry].ctrl = 0;
777
778 /* properly align Ethernet header */
779 skb_reserve(skb, NET_IP_ALIGN);
780 } else {
781 bp->rx_ring[entry].addr &= ~MACB_BIT(RX_USED);
782 bp->rx_ring[entry].ctrl = 0;
783 }
784 }
785
786 /* Make descriptor updates visible to hardware */
787 wmb();
788
789 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
790 bp->rx_prepared_head, bp->rx_tail);
791 }
792
793 /* Mark DMA descriptors from begin up to and not including end as unused */
794 static void discard_partial_frame(struct macb *bp, unsigned int begin,
795 unsigned int end)
796 {
797 unsigned int frag;
798
799 for (frag = begin; frag != end; frag++) {
800 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
801
802 desc->addr &= ~MACB_BIT(RX_USED);
803 }
804
805 /* Make descriptor updates visible to hardware */
806 wmb();
807
808 /* When this happens, the hardware stats registers for
809 * whatever caused this is updated, so we don't have to record
810 * anything.
811 */
812 }
813
814 static int gem_rx(struct macb *bp, int budget)
815 {
816 unsigned int len;
817 unsigned int entry;
818 struct sk_buff *skb;
819 struct macb_dma_desc *desc;
820 int count = 0;
821
822 while (count < budget) {
823 u32 ctrl;
824 dma_addr_t addr;
825 bool rxused;
826
827 entry = macb_rx_ring_wrap(bp, bp->rx_tail);
828 desc = &bp->rx_ring[entry];
829
830 /* Make hw descriptor updates visible to CPU */
831 rmb();
832
833 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
834 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
835 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
836 addr |= ((u64)(desc->addrh) << 32);
837 #endif
838 ctrl = desc->ctrl;
839
840 if (!rxused)
841 break;
842
843 bp->rx_tail++;
844 count++;
845
846 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
847 netdev_err(bp->dev,
848 "not whole frame pointed by descriptor\n");
849 bp->stats.rx_dropped++;
850 break;
851 }
852 skb = bp->rx_skbuff[entry];
853 if (unlikely(!skb)) {
854 netdev_err(bp->dev,
855 "inconsistent Rx descriptor chain\n");
856 bp->stats.rx_dropped++;
857 break;
858 }
859 /* now everything is ready for receiving packet */
860 bp->rx_skbuff[entry] = NULL;
861 len = ctrl & bp->rx_frm_len_mask;
862
863 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
864
865 skb_put(skb, len);
866 dma_unmap_single(&bp->pdev->dev, addr,
867 bp->rx_buffer_size, DMA_FROM_DEVICE);
868
869 skb->protocol = eth_type_trans(skb, bp->dev);
870 skb_checksum_none_assert(skb);
871 if (bp->dev->features & NETIF_F_RXCSUM &&
872 !(bp->dev->flags & IFF_PROMISC) &&
873 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
874 skb->ip_summed = CHECKSUM_UNNECESSARY;
875
876 bp->stats.rx_packets++;
877 bp->stats.rx_bytes += skb->len;
878
879 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
880 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
881 skb->len, skb->csum);
882 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
883 skb_mac_header(skb), 16, true);
884 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
885 skb->data, 32, true);
886 #endif
887
888 netif_receive_skb(skb);
889 }
890
891 gem_rx_refill(bp);
892
893 return count;
894 }
895
896 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
897 unsigned int last_frag)
898 {
899 unsigned int len;
900 unsigned int frag;
901 unsigned int offset;
902 struct sk_buff *skb;
903 struct macb_dma_desc *desc;
904
905 desc = macb_rx_desc(bp, last_frag);
906 len = desc->ctrl & bp->rx_frm_len_mask;
907
908 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
909 macb_rx_ring_wrap(bp, first_frag),
910 macb_rx_ring_wrap(bp, last_frag), len);
911
912 /* The ethernet header starts NET_IP_ALIGN bytes into the
913 * first buffer. Since the header is 14 bytes, this makes the
914 * payload word-aligned.
915 *
916 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
917 * the two padding bytes into the skb so that we avoid hitting
918 * the slowpath in memcpy(), and pull them off afterwards.
919 */
920 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
921 if (!skb) {
922 bp->stats.rx_dropped++;
923 for (frag = first_frag; ; frag++) {
924 desc = macb_rx_desc(bp, frag);
925 desc->addr &= ~MACB_BIT(RX_USED);
926 if (frag == last_frag)
927 break;
928 }
929
930 /* Make descriptor updates visible to hardware */
931 wmb();
932
933 return 1;
934 }
935
936 offset = 0;
937 len += NET_IP_ALIGN;
938 skb_checksum_none_assert(skb);
939 skb_put(skb, len);
940
941 for (frag = first_frag; ; frag++) {
942 unsigned int frag_len = bp->rx_buffer_size;
943
944 if (offset + frag_len > len) {
945 if (unlikely(frag != last_frag)) {
946 dev_kfree_skb_any(skb);
947 return -1;
948 }
949 frag_len = len - offset;
950 }
951 skb_copy_to_linear_data_offset(skb, offset,
952 macb_rx_buffer(bp, frag),
953 frag_len);
954 offset += bp->rx_buffer_size;
955 desc = macb_rx_desc(bp, frag);
956 desc->addr &= ~MACB_BIT(RX_USED);
957
958 if (frag == last_frag)
959 break;
960 }
961
962 /* Make descriptor updates visible to hardware */
963 wmb();
964
965 __skb_pull(skb, NET_IP_ALIGN);
966 skb->protocol = eth_type_trans(skb, bp->dev);
967
968 bp->stats.rx_packets++;
969 bp->stats.rx_bytes += skb->len;
970 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
971 skb->len, skb->csum);
972 netif_receive_skb(skb);
973
974 return 0;
975 }
976
977 static inline void macb_init_rx_ring(struct macb *bp)
978 {
979 dma_addr_t addr;
980 int i;
981
982 addr = bp->rx_buffers_dma;
983 for (i = 0; i < bp->rx_ring_size; i++) {
984 bp->rx_ring[i].addr = addr;
985 bp->rx_ring[i].ctrl = 0;
986 addr += bp->rx_buffer_size;
987 }
988 bp->rx_ring[bp->rx_ring_size - 1].addr |= MACB_BIT(RX_WRAP);
989 }
990
991 static int macb_rx(struct macb *bp, int budget)
992 {
993 bool reset_rx_queue = false;
994 int received = 0;
995 unsigned int tail;
996 int first_frag = -1;
997
998 for (tail = bp->rx_tail; budget > 0; tail++) {
999 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
1000 u32 addr, ctrl;
1001
1002 /* Make hw descriptor updates visible to CPU */
1003 rmb();
1004
1005 addr = desc->addr;
1006 ctrl = desc->ctrl;
1007
1008 if (!(addr & MACB_BIT(RX_USED)))
1009 break;
1010
1011 if (ctrl & MACB_BIT(RX_SOF)) {
1012 if (first_frag != -1)
1013 discard_partial_frame(bp, first_frag, tail);
1014 first_frag = tail;
1015 }
1016
1017 if (ctrl & MACB_BIT(RX_EOF)) {
1018 int dropped;
1019
1020 if (unlikely(first_frag == -1)) {
1021 reset_rx_queue = true;
1022 continue;
1023 }
1024
1025 dropped = macb_rx_frame(bp, first_frag, tail);
1026 first_frag = -1;
1027 if (unlikely(dropped < 0)) {
1028 reset_rx_queue = true;
1029 continue;
1030 }
1031 if (!dropped) {
1032 received++;
1033 budget--;
1034 }
1035 }
1036 }
1037
1038 if (unlikely(reset_rx_queue)) {
1039 unsigned long flags;
1040 u32 ctrl;
1041
1042 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1043
1044 spin_lock_irqsave(&bp->lock, flags);
1045
1046 ctrl = macb_readl(bp, NCR);
1047 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1048
1049 macb_init_rx_ring(bp);
1050 macb_writel(bp, RBQP, bp->rx_ring_dma);
1051
1052 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1053
1054 spin_unlock_irqrestore(&bp->lock, flags);
1055 return received;
1056 }
1057
1058 if (first_frag != -1)
1059 bp->rx_tail = first_frag;
1060 else
1061 bp->rx_tail = tail;
1062
1063 return received;
1064 }
1065
1066 static int macb_poll(struct napi_struct *napi, int budget)
1067 {
1068 struct macb *bp = container_of(napi, struct macb, napi);
1069 int work_done;
1070 u32 status;
1071
1072 status = macb_readl(bp, RSR);
1073 macb_writel(bp, RSR, status);
1074
1075 work_done = 0;
1076
1077 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1078 (unsigned long)status, budget);
1079
1080 work_done = bp->macbgem_ops.mog_rx(bp, budget);
1081 if (work_done < budget) {
1082 napi_complete(napi);
1083
1084 /* Packets received while interrupts were disabled */
1085 status = macb_readl(bp, RSR);
1086 if (status) {
1087 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1088 macb_writel(bp, ISR, MACB_BIT(RCOMP));
1089 napi_reschedule(napi);
1090 } else {
1091 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
1092 }
1093 }
1094
1095 /* TODO: Handle errors */
1096
1097 return work_done;
1098 }
1099
1100 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1101 {
1102 struct macb_queue *queue = dev_id;
1103 struct macb *bp = queue->bp;
1104 struct net_device *dev = bp->dev;
1105 u32 status, ctrl;
1106
1107 status = queue_readl(queue, ISR);
1108
1109 if (unlikely(!status))
1110 return IRQ_NONE;
1111
1112 spin_lock(&bp->lock);
1113
1114 while (status) {
1115 /* close possible race with dev_close */
1116 if (unlikely(!netif_running(dev))) {
1117 queue_writel(queue, IDR, -1);
1118 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1119 queue_writel(queue, ISR, -1);
1120 break;
1121 }
1122
1123 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1124 (unsigned int)(queue - bp->queues),
1125 (unsigned long)status);
1126
1127 if (status & MACB_RX_INT_FLAGS) {
1128 /* There's no point taking any more interrupts
1129 * until we have processed the buffers. The
1130 * scheduling call may fail if the poll routine
1131 * is already scheduled, so disable interrupts
1132 * now.
1133 */
1134 queue_writel(queue, IDR, MACB_RX_INT_FLAGS);
1135 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1136 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1137
1138 if (napi_schedule_prep(&bp->napi)) {
1139 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1140 __napi_schedule(&bp->napi);
1141 }
1142 }
1143
1144 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1145 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1146 schedule_work(&queue->tx_error_task);
1147
1148 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1149 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1150
1151 break;
1152 }
1153
1154 if (status & MACB_BIT(TCOMP))
1155 macb_tx_interrupt(queue);
1156
1157 /* Link change detection isn't possible with RMII, so we'll
1158 * add that if/when we get our hands on a full-blown MII PHY.
1159 */
1160
1161 /* There is a hardware issue under heavy load where DMA can
1162 * stop, this causes endless "used buffer descriptor read"
1163 * interrupts but it can be cleared by re-enabling RX. See
1164 * the at91 manual, section 41.3.1 or the Zynq manual
1165 * section 16.7.4 for details.
1166 */
1167 if (status & MACB_BIT(RXUBR)) {
1168 ctrl = macb_readl(bp, NCR);
1169 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1170 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1171
1172 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1173 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1174 }
1175
1176 if (status & MACB_BIT(ISR_ROVR)) {
1177 /* We missed at least one packet */
1178 if (macb_is_gem(bp))
1179 bp->hw_stats.gem.rx_overruns++;
1180 else
1181 bp->hw_stats.macb.rx_overruns++;
1182
1183 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1184 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1185 }
1186
1187 if (status & MACB_BIT(HRESP)) {
1188 /* TODO: Reset the hardware, and maybe move the
1189 * netdev_err to a lower-priority context as well
1190 * (work queue?)
1191 */
1192 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1193
1194 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1195 queue_writel(queue, ISR, MACB_BIT(HRESP));
1196 }
1197
1198 status = queue_readl(queue, ISR);
1199 }
1200
1201 spin_unlock(&bp->lock);
1202
1203 return IRQ_HANDLED;
1204 }
1205
1206 #ifdef CONFIG_NET_POLL_CONTROLLER
1207 /* Polling receive - used by netconsole and other diagnostic tools
1208 * to allow network i/o with interrupts disabled.
1209 */
1210 static void macb_poll_controller(struct net_device *dev)
1211 {
1212 struct macb *bp = netdev_priv(dev);
1213 struct macb_queue *queue;
1214 unsigned long flags;
1215 unsigned int q;
1216
1217 local_irq_save(flags);
1218 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1219 macb_interrupt(dev->irq, queue);
1220 local_irq_restore(flags);
1221 }
1222 #endif
1223
1224 static unsigned int macb_tx_map(struct macb *bp,
1225 struct macb_queue *queue,
1226 struct sk_buff *skb)
1227 {
1228 dma_addr_t mapping;
1229 unsigned int len, entry, i, tx_head = queue->tx_head;
1230 struct macb_tx_skb *tx_skb = NULL;
1231 struct macb_dma_desc *desc;
1232 unsigned int offset, size, count = 0;
1233 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1234 unsigned int eof = 1;
1235 u32 ctrl;
1236
1237 /* First, map non-paged data */
1238 len = skb_headlen(skb);
1239 offset = 0;
1240 while (len) {
1241 size = min(len, bp->max_tx_length);
1242 entry = macb_tx_ring_wrap(bp, tx_head);
1243 tx_skb = &queue->tx_skb[entry];
1244
1245 mapping = dma_map_single(&bp->pdev->dev,
1246 skb->data + offset,
1247 size, DMA_TO_DEVICE);
1248 if (dma_mapping_error(&bp->pdev->dev, mapping))
1249 goto dma_error;
1250
1251 /* Save info to properly release resources */
1252 tx_skb->skb = NULL;
1253 tx_skb->mapping = mapping;
1254 tx_skb->size = size;
1255 tx_skb->mapped_as_page = false;
1256
1257 len -= size;
1258 offset += size;
1259 count++;
1260 tx_head++;
1261 }
1262
1263 /* Then, map paged data from fragments */
1264 for (f = 0; f < nr_frags; f++) {
1265 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1266
1267 len = skb_frag_size(frag);
1268 offset = 0;
1269 while (len) {
1270 size = min(len, bp->max_tx_length);
1271 entry = macb_tx_ring_wrap(bp, tx_head);
1272 tx_skb = &queue->tx_skb[entry];
1273
1274 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1275 offset, size, DMA_TO_DEVICE);
1276 if (dma_mapping_error(&bp->pdev->dev, mapping))
1277 goto dma_error;
1278
1279 /* Save info to properly release resources */
1280 tx_skb->skb = NULL;
1281 tx_skb->mapping = mapping;
1282 tx_skb->size = size;
1283 tx_skb->mapped_as_page = true;
1284
1285 len -= size;
1286 offset += size;
1287 count++;
1288 tx_head++;
1289 }
1290 }
1291
1292 /* Should never happen */
1293 if (unlikely(!tx_skb)) {
1294 netdev_err(bp->dev, "BUG! empty skb!\n");
1295 return 0;
1296 }
1297
1298 /* This is the last buffer of the frame: save socket buffer */
1299 tx_skb->skb = skb;
1300
1301 /* Update TX ring: update buffer descriptors in reverse order
1302 * to avoid race condition
1303 */
1304
1305 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1306 * to set the end of TX queue
1307 */
1308 i = tx_head;
1309 entry = macb_tx_ring_wrap(bp, i);
1310 ctrl = MACB_BIT(TX_USED);
1311 desc = &queue->tx_ring[entry];
1312 desc->ctrl = ctrl;
1313
1314 do {
1315 i--;
1316 entry = macb_tx_ring_wrap(bp, i);
1317 tx_skb = &queue->tx_skb[entry];
1318 desc = &queue->tx_ring[entry];
1319
1320 ctrl = (u32)tx_skb->size;
1321 if (eof) {
1322 ctrl |= MACB_BIT(TX_LAST);
1323 eof = 0;
1324 }
1325 if (unlikely(entry == (bp->tx_ring_size - 1)))
1326 ctrl |= MACB_BIT(TX_WRAP);
1327
1328 /* Set TX buffer descriptor */
1329 macb_set_addr(desc, tx_skb->mapping);
1330 /* desc->addr must be visible to hardware before clearing
1331 * 'TX_USED' bit in desc->ctrl.
1332 */
1333 wmb();
1334 desc->ctrl = ctrl;
1335 } while (i != queue->tx_head);
1336
1337 queue->tx_head = tx_head;
1338
1339 return count;
1340
1341 dma_error:
1342 netdev_err(bp->dev, "TX DMA map failed\n");
1343
1344 for (i = queue->tx_head; i != tx_head; i++) {
1345 tx_skb = macb_tx_skb(queue, i);
1346
1347 macb_tx_unmap(bp, tx_skb);
1348 }
1349
1350 return 0;
1351 }
1352
1353 static inline int macb_clear_csum(struct sk_buff *skb)
1354 {
1355 /* no change for packets without checksum offloading */
1356 if (skb->ip_summed != CHECKSUM_PARTIAL)
1357 return 0;
1358
1359 /* make sure we can modify the header */
1360 if (unlikely(skb_cow_head(skb, 0)))
1361 return -1;
1362
1363 /* initialize checksum field
1364 * This is required - at least for Zynq, which otherwise calculates
1365 * wrong UDP header checksums for UDP packets with UDP data len <=2
1366 */
1367 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
1368 return 0;
1369 }
1370
1371 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1372 {
1373 u16 queue_index = skb_get_queue_mapping(skb);
1374 struct macb *bp = netdev_priv(dev);
1375 struct macb_queue *queue = &bp->queues[queue_index];
1376 unsigned long flags;
1377 unsigned int count, nr_frags, frag_size, f;
1378
1379 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1380 netdev_vdbg(bp->dev,
1381 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1382 queue_index, skb->len, skb->head, skb->data,
1383 skb_tail_pointer(skb), skb_end_pointer(skb));
1384 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1385 skb->data, 16, true);
1386 #endif
1387
1388 /* Count how many TX buffer descriptors are needed to send this
1389 * socket buffer: skb fragments of jumbo frames may need to be
1390 * split into many buffer descriptors.
1391 */
1392 count = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
1393 nr_frags = skb_shinfo(skb)->nr_frags;
1394 for (f = 0; f < nr_frags; f++) {
1395 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1396 count += DIV_ROUND_UP(frag_size, bp->max_tx_length);
1397 }
1398
1399 spin_lock_irqsave(&bp->lock, flags);
1400
1401 /* This is a hard error, log it. */
1402 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
1403 bp->tx_ring_size) < count) {
1404 netif_stop_subqueue(dev, queue_index);
1405 spin_unlock_irqrestore(&bp->lock, flags);
1406 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1407 queue->tx_head, queue->tx_tail);
1408 return NETDEV_TX_BUSY;
1409 }
1410
1411 if (macb_clear_csum(skb)) {
1412 dev_kfree_skb_any(skb);
1413 goto unlock;
1414 }
1415
1416 /* Map socket buffer for DMA transfer */
1417 if (!macb_tx_map(bp, queue, skb)) {
1418 dev_kfree_skb_any(skb);
1419 goto unlock;
1420 }
1421
1422 /* Make newly initialized descriptor visible to hardware */
1423 wmb();
1424
1425 skb_tx_timestamp(skb);
1426
1427 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1428
1429 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
1430 netif_stop_subqueue(dev, queue_index);
1431
1432 unlock:
1433 spin_unlock_irqrestore(&bp->lock, flags);
1434
1435 return NETDEV_TX_OK;
1436 }
1437
1438 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1439 {
1440 if (!macb_is_gem(bp)) {
1441 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1442 } else {
1443 bp->rx_buffer_size = size;
1444
1445 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1446 netdev_dbg(bp->dev,
1447 "RX buffer must be multiple of %d bytes, expanding\n",
1448 RX_BUFFER_MULTIPLE);
1449 bp->rx_buffer_size =
1450 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1451 }
1452 }
1453
1454 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
1455 bp->dev->mtu, bp->rx_buffer_size);
1456 }
1457
1458 static void gem_free_rx_buffers(struct macb *bp)
1459 {
1460 struct sk_buff *skb;
1461 struct macb_dma_desc *desc;
1462 dma_addr_t addr;
1463 int i;
1464
1465 if (!bp->rx_skbuff)
1466 return;
1467
1468 for (i = 0; i < bp->rx_ring_size; i++) {
1469 skb = bp->rx_skbuff[i];
1470
1471 if (!skb)
1472 continue;
1473
1474 desc = &bp->rx_ring[i];
1475 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1476 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1477 addr |= ((u64)(desc->addrh) << 32);
1478 #endif
1479 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
1480 DMA_FROM_DEVICE);
1481 dev_kfree_skb_any(skb);
1482 skb = NULL;
1483 }
1484
1485 kfree(bp->rx_skbuff);
1486 bp->rx_skbuff = NULL;
1487 }
1488
1489 static void macb_free_rx_buffers(struct macb *bp)
1490 {
1491 if (bp->rx_buffers) {
1492 dma_free_coherent(&bp->pdev->dev,
1493 bp->rx_ring_size * bp->rx_buffer_size,
1494 bp->rx_buffers, bp->rx_buffers_dma);
1495 bp->rx_buffers = NULL;
1496 }
1497 }
1498
1499 static void macb_free_consistent(struct macb *bp)
1500 {
1501 struct macb_queue *queue;
1502 unsigned int q;
1503
1504 bp->macbgem_ops.mog_free_rx_buffers(bp);
1505 if (bp->rx_ring) {
1506 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES(bp),
1507 bp->rx_ring, bp->rx_ring_dma);
1508 bp->rx_ring = NULL;
1509 }
1510
1511 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1512 kfree(queue->tx_skb);
1513 queue->tx_skb = NULL;
1514 if (queue->tx_ring) {
1515 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES(bp),
1516 queue->tx_ring, queue->tx_ring_dma);
1517 queue->tx_ring = NULL;
1518 }
1519 }
1520 }
1521
1522 static int gem_alloc_rx_buffers(struct macb *bp)
1523 {
1524 int size;
1525
1526 size = bp->rx_ring_size * sizeof(struct sk_buff *);
1527 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1528 if (!bp->rx_skbuff)
1529 return -ENOMEM;
1530 else
1531 netdev_dbg(bp->dev,
1532 "Allocated %d RX struct sk_buff entries at %p\n",
1533 bp->rx_ring_size, bp->rx_skbuff);
1534 return 0;
1535 }
1536
1537 static int macb_alloc_rx_buffers(struct macb *bp)
1538 {
1539 int size;
1540
1541 size = bp->rx_ring_size * bp->rx_buffer_size;
1542 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1543 &bp->rx_buffers_dma, GFP_KERNEL);
1544 if (!bp->rx_buffers)
1545 return -ENOMEM;
1546
1547 netdev_dbg(bp->dev,
1548 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1549 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1550 return 0;
1551 }
1552
1553 static int macb_alloc_consistent(struct macb *bp)
1554 {
1555 struct macb_queue *queue;
1556 unsigned int q;
1557 int size;
1558
1559 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1560 size = TX_RING_BYTES(bp);
1561 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1562 &queue->tx_ring_dma,
1563 GFP_KERNEL);
1564 if (!queue->tx_ring)
1565 goto out_err;
1566 netdev_dbg(bp->dev,
1567 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
1568 q, size, (unsigned long)queue->tx_ring_dma,
1569 queue->tx_ring);
1570
1571 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
1572 queue->tx_skb = kmalloc(size, GFP_KERNEL);
1573 if (!queue->tx_skb)
1574 goto out_err;
1575 }
1576
1577 size = RX_RING_BYTES(bp);
1578 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1579 &bp->rx_ring_dma, GFP_KERNEL);
1580 if (!bp->rx_ring)
1581 goto out_err;
1582 netdev_dbg(bp->dev,
1583 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1584 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
1585
1586 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
1587 goto out_err;
1588
1589 return 0;
1590
1591 out_err:
1592 macb_free_consistent(bp);
1593 return -ENOMEM;
1594 }
1595
1596 static void gem_init_rings(struct macb *bp)
1597 {
1598 struct macb_queue *queue;
1599 unsigned int q;
1600 int i;
1601
1602 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1603 for (i = 0; i < bp->tx_ring_size; i++) {
1604 queue->tx_ring[i].addr = 0;
1605 queue->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1606 }
1607 queue->tx_ring[bp->tx_ring_size - 1].ctrl |= MACB_BIT(TX_WRAP);
1608 queue->tx_head = 0;
1609 queue->tx_tail = 0;
1610 }
1611
1612 bp->rx_tail = 0;
1613 bp->rx_prepared_head = 0;
1614
1615 gem_rx_refill(bp);
1616 }
1617
1618 static void macb_init_rings(struct macb *bp)
1619 {
1620 int i;
1621
1622 macb_init_rx_ring(bp);
1623
1624 for (i = 0; i < bp->tx_ring_size; i++) {
1625 bp->queues[0].tx_ring[i].addr = 0;
1626 bp->queues[0].tx_ring[i].ctrl = MACB_BIT(TX_USED);
1627 }
1628 bp->queues[0].tx_head = 0;
1629 bp->queues[0].tx_tail = 0;
1630 bp->queues[0].tx_ring[bp->tx_ring_size - 1].ctrl |= MACB_BIT(TX_WRAP);
1631
1632 bp->rx_tail = 0;
1633 }
1634
1635 static void macb_reset_hw(struct macb *bp)
1636 {
1637 struct macb_queue *queue;
1638 unsigned int q;
1639
1640 /* Disable RX and TX (XXX: Should we halt the transmission
1641 * more gracefully?)
1642 */
1643 macb_writel(bp, NCR, 0);
1644
1645 /* Clear the stats registers (XXX: Update stats first?) */
1646 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1647
1648 /* Clear all status flags */
1649 macb_writel(bp, TSR, -1);
1650 macb_writel(bp, RSR, -1);
1651
1652 /* Disable all interrupts */
1653 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1654 queue_writel(queue, IDR, -1);
1655 queue_readl(queue, ISR);
1656 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1657 queue_writel(queue, ISR, -1);
1658 }
1659 }
1660
1661 static u32 gem_mdc_clk_div(struct macb *bp)
1662 {
1663 u32 config;
1664 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1665
1666 if (pclk_hz <= 20000000)
1667 config = GEM_BF(CLK, GEM_CLK_DIV8);
1668 else if (pclk_hz <= 40000000)
1669 config = GEM_BF(CLK, GEM_CLK_DIV16);
1670 else if (pclk_hz <= 80000000)
1671 config = GEM_BF(CLK, GEM_CLK_DIV32);
1672 else if (pclk_hz <= 120000000)
1673 config = GEM_BF(CLK, GEM_CLK_DIV48);
1674 else if (pclk_hz <= 160000000)
1675 config = GEM_BF(CLK, GEM_CLK_DIV64);
1676 else
1677 config = GEM_BF(CLK, GEM_CLK_DIV96);
1678
1679 return config;
1680 }
1681
1682 static u32 macb_mdc_clk_div(struct macb *bp)
1683 {
1684 u32 config;
1685 unsigned long pclk_hz;
1686
1687 if (macb_is_gem(bp))
1688 return gem_mdc_clk_div(bp);
1689
1690 pclk_hz = clk_get_rate(bp->pclk);
1691 if (pclk_hz <= 20000000)
1692 config = MACB_BF(CLK, MACB_CLK_DIV8);
1693 else if (pclk_hz <= 40000000)
1694 config = MACB_BF(CLK, MACB_CLK_DIV16);
1695 else if (pclk_hz <= 80000000)
1696 config = MACB_BF(CLK, MACB_CLK_DIV32);
1697 else
1698 config = MACB_BF(CLK, MACB_CLK_DIV64);
1699
1700 return config;
1701 }
1702
1703 /* Get the DMA bus width field of the network configuration register that we
1704 * should program. We find the width from decoding the design configuration
1705 * register to find the maximum supported data bus width.
1706 */
1707 static u32 macb_dbw(struct macb *bp)
1708 {
1709 if (!macb_is_gem(bp))
1710 return 0;
1711
1712 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1713 case 4:
1714 return GEM_BF(DBW, GEM_DBW128);
1715 case 2:
1716 return GEM_BF(DBW, GEM_DBW64);
1717 case 1:
1718 default:
1719 return GEM_BF(DBW, GEM_DBW32);
1720 }
1721 }
1722
1723 /* Configure the receive DMA engine
1724 * - use the correct receive buffer size
1725 * - set best burst length for DMA operations
1726 * (if not supported by FIFO, it will fallback to default)
1727 * - set both rx/tx packet buffers to full memory size
1728 * These are configurable parameters for GEM.
1729 */
1730 static void macb_configure_dma(struct macb *bp)
1731 {
1732 u32 dmacfg;
1733
1734 if (macb_is_gem(bp)) {
1735 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1736 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
1737 if (bp->dma_burst_length)
1738 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
1739 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
1740 dmacfg &= ~GEM_BIT(ENDIA_PKT);
1741
1742 if (bp->native_io)
1743 dmacfg &= ~GEM_BIT(ENDIA_DESC);
1744 else
1745 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
1746
1747 if (bp->dev->features & NETIF_F_HW_CSUM)
1748 dmacfg |= GEM_BIT(TXCOEN);
1749 else
1750 dmacfg &= ~GEM_BIT(TXCOEN);
1751
1752 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1753 dmacfg |= GEM_BIT(ADDR64);
1754 #endif
1755 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
1756 dmacfg);
1757 gem_writel(bp, DMACFG, dmacfg);
1758 }
1759 }
1760
1761 static void macb_init_hw(struct macb *bp)
1762 {
1763 struct macb_queue *queue;
1764 unsigned int q;
1765
1766 u32 config;
1767
1768 macb_reset_hw(bp);
1769 macb_set_hwaddr(bp);
1770
1771 config = macb_mdc_clk_div(bp);
1772 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
1773 config |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
1774 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
1775 config |= MACB_BIT(PAE); /* PAuse Enable */
1776 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
1777 if (bp->caps & MACB_CAPS_JUMBO)
1778 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
1779 else
1780 config |= MACB_BIT(BIG); /* Receive oversized frames */
1781 if (bp->dev->flags & IFF_PROMISC)
1782 config |= MACB_BIT(CAF); /* Copy All Frames */
1783 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
1784 config |= GEM_BIT(RXCOEN);
1785 if (!(bp->dev->flags & IFF_BROADCAST))
1786 config |= MACB_BIT(NBC); /* No BroadCast */
1787 config |= macb_dbw(bp);
1788 macb_writel(bp, NCFGR, config);
1789 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
1790 gem_writel(bp, JML, bp->jumbo_max_len);
1791 bp->speed = SPEED_10;
1792 bp->duplex = DUPLEX_HALF;
1793 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
1794 if (bp->caps & MACB_CAPS_JUMBO)
1795 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
1796
1797 macb_configure_dma(bp);
1798
1799 /* Initialize TX and RX buffers */
1800 macb_writel(bp, RBQP, (u32)(bp->rx_ring_dma));
1801 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1802 macb_writel(bp, RBQPH, (u32)(bp->rx_ring_dma >> 32));
1803 #endif
1804 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1805 queue_writel(queue, TBQP, (u32)(queue->tx_ring_dma));
1806 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1807 queue_writel(queue, TBQPH, (u32)(queue->tx_ring_dma >> 32));
1808 #endif
1809
1810 /* Enable interrupts */
1811 queue_writel(queue, IER,
1812 MACB_RX_INT_FLAGS |
1813 MACB_TX_INT_FLAGS |
1814 MACB_BIT(HRESP));
1815 }
1816
1817 /* Enable TX and RX */
1818 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
1819 }
1820
1821 /* The hash address register is 64 bits long and takes up two
1822 * locations in the memory map. The least significant bits are stored
1823 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1824 *
1825 * The unicast hash enable and the multicast hash enable bits in the
1826 * network configuration register enable the reception of hash matched
1827 * frames. The destination address is reduced to a 6 bit index into
1828 * the 64 bit hash register using the following hash function. The
1829 * hash function is an exclusive or of every sixth bit of the
1830 * destination address.
1831 *
1832 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1833 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1834 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1835 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1836 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1837 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1838 *
1839 * da[0] represents the least significant bit of the first byte
1840 * received, that is, the multicast/unicast indicator, and da[47]
1841 * represents the most significant bit of the last byte received. If
1842 * the hash index, hi[n], points to a bit that is set in the hash
1843 * register then the frame will be matched according to whether the
1844 * frame is multicast or unicast. A multicast match will be signalled
1845 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1846 * index points to a bit set in the hash register. A unicast match
1847 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1848 * and the hash index points to a bit set in the hash register. To
1849 * receive all multicast frames, the hash register should be set with
1850 * all ones and the multicast hash enable bit should be set in the
1851 * network configuration register.
1852 */
1853
1854 static inline int hash_bit_value(int bitnr, __u8 *addr)
1855 {
1856 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1857 return 1;
1858 return 0;
1859 }
1860
1861 /* Return the hash index value for the specified address. */
1862 static int hash_get_index(__u8 *addr)
1863 {
1864 int i, j, bitval;
1865 int hash_index = 0;
1866
1867 for (j = 0; j < 6; j++) {
1868 for (i = 0, bitval = 0; i < 8; i++)
1869 bitval ^= hash_bit_value(i * 6 + j, addr);
1870
1871 hash_index |= (bitval << j);
1872 }
1873
1874 return hash_index;
1875 }
1876
1877 /* Add multicast addresses to the internal multicast-hash table. */
1878 static void macb_sethashtable(struct net_device *dev)
1879 {
1880 struct netdev_hw_addr *ha;
1881 unsigned long mc_filter[2];
1882 unsigned int bitnr;
1883 struct macb *bp = netdev_priv(dev);
1884
1885 mc_filter[0] = 0;
1886 mc_filter[1] = 0;
1887
1888 netdev_for_each_mc_addr(ha, dev) {
1889 bitnr = hash_get_index(ha->addr);
1890 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1891 }
1892
1893 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1894 macb_or_gem_writel(bp, HRT, mc_filter[1]);
1895 }
1896
1897 /* Enable/Disable promiscuous and multicast modes. */
1898 static void macb_set_rx_mode(struct net_device *dev)
1899 {
1900 unsigned long cfg;
1901 struct macb *bp = netdev_priv(dev);
1902
1903 cfg = macb_readl(bp, NCFGR);
1904
1905 if (dev->flags & IFF_PROMISC) {
1906 /* Enable promiscuous mode */
1907 cfg |= MACB_BIT(CAF);
1908
1909 /* Disable RX checksum offload */
1910 if (macb_is_gem(bp))
1911 cfg &= ~GEM_BIT(RXCOEN);
1912 } else {
1913 /* Disable promiscuous mode */
1914 cfg &= ~MACB_BIT(CAF);
1915
1916 /* Enable RX checksum offload only if requested */
1917 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
1918 cfg |= GEM_BIT(RXCOEN);
1919 }
1920
1921 if (dev->flags & IFF_ALLMULTI) {
1922 /* Enable all multicast mode */
1923 macb_or_gem_writel(bp, HRB, -1);
1924 macb_or_gem_writel(bp, HRT, -1);
1925 cfg |= MACB_BIT(NCFGR_MTI);
1926 } else if (!netdev_mc_empty(dev)) {
1927 /* Enable specific multicasts */
1928 macb_sethashtable(dev);
1929 cfg |= MACB_BIT(NCFGR_MTI);
1930 } else if (dev->flags & (~IFF_ALLMULTI)) {
1931 /* Disable all multicast mode */
1932 macb_or_gem_writel(bp, HRB, 0);
1933 macb_or_gem_writel(bp, HRT, 0);
1934 cfg &= ~MACB_BIT(NCFGR_MTI);
1935 }
1936
1937 macb_writel(bp, NCFGR, cfg);
1938 }
1939
1940 static int macb_open(struct net_device *dev)
1941 {
1942 struct macb *bp = netdev_priv(dev);
1943 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
1944 int err;
1945
1946 netdev_dbg(bp->dev, "open\n");
1947
1948 /* carrier starts down */
1949 netif_carrier_off(dev);
1950
1951 /* if the phy is not yet register, retry later*/
1952 if (!dev->phydev)
1953 return -EAGAIN;
1954
1955 /* RX buffers initialization */
1956 macb_init_rx_buffer_size(bp, bufsz);
1957
1958 err = macb_alloc_consistent(bp);
1959 if (err) {
1960 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1961 err);
1962 return err;
1963 }
1964
1965 napi_enable(&bp->napi);
1966
1967 bp->macbgem_ops.mog_init_rings(bp);
1968 macb_init_hw(bp);
1969
1970 /* schedule a link state check */
1971 phy_start(dev->phydev);
1972
1973 netif_tx_start_all_queues(dev);
1974
1975 return 0;
1976 }
1977
1978 static int macb_close(struct net_device *dev)
1979 {
1980 struct macb *bp = netdev_priv(dev);
1981 unsigned long flags;
1982
1983 netif_tx_stop_all_queues(dev);
1984 napi_disable(&bp->napi);
1985
1986 if (dev->phydev)
1987 phy_stop(dev->phydev);
1988
1989 spin_lock_irqsave(&bp->lock, flags);
1990 macb_reset_hw(bp);
1991 netif_carrier_off(dev);
1992 spin_unlock_irqrestore(&bp->lock, flags);
1993
1994 macb_free_consistent(bp);
1995
1996 return 0;
1997 }
1998
1999 static int macb_change_mtu(struct net_device *dev, int new_mtu)
2000 {
2001 if (netif_running(dev))
2002 return -EBUSY;
2003
2004 dev->mtu = new_mtu;
2005
2006 return 0;
2007 }
2008
2009 static void gem_update_stats(struct macb *bp)
2010 {
2011 unsigned int i;
2012 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2013
2014 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2015 u32 offset = gem_statistics[i].offset;
2016 u64 val = bp->macb_reg_readl(bp, offset);
2017
2018 bp->ethtool_stats[i] += val;
2019 *p += val;
2020
2021 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2022 /* Add GEM_OCTTXH, GEM_OCTRXH */
2023 val = bp->macb_reg_readl(bp, offset + 4);
2024 bp->ethtool_stats[i] += ((u64)val) << 32;
2025 *(++p) += val;
2026 }
2027 }
2028 }
2029
2030 static struct net_device_stats *gem_get_stats(struct macb *bp)
2031 {
2032 struct gem_stats *hwstat = &bp->hw_stats.gem;
2033 struct net_device_stats *nstat = &bp->stats;
2034
2035 gem_update_stats(bp);
2036
2037 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2038 hwstat->rx_alignment_errors +
2039 hwstat->rx_resource_errors +
2040 hwstat->rx_overruns +
2041 hwstat->rx_oversize_frames +
2042 hwstat->rx_jabbers +
2043 hwstat->rx_undersized_frames +
2044 hwstat->rx_length_field_frame_errors);
2045 nstat->tx_errors = (hwstat->tx_late_collisions +
2046 hwstat->tx_excessive_collisions +
2047 hwstat->tx_underrun +
2048 hwstat->tx_carrier_sense_errors);
2049 nstat->multicast = hwstat->rx_multicast_frames;
2050 nstat->collisions = (hwstat->tx_single_collision_frames +
2051 hwstat->tx_multiple_collision_frames +
2052 hwstat->tx_excessive_collisions);
2053 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2054 hwstat->rx_jabbers +
2055 hwstat->rx_undersized_frames +
2056 hwstat->rx_length_field_frame_errors);
2057 nstat->rx_over_errors = hwstat->rx_resource_errors;
2058 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2059 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2060 nstat->rx_fifo_errors = hwstat->rx_overruns;
2061 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2062 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2063 nstat->tx_fifo_errors = hwstat->tx_underrun;
2064
2065 return nstat;
2066 }
2067
2068 static void gem_get_ethtool_stats(struct net_device *dev,
2069 struct ethtool_stats *stats, u64 *data)
2070 {
2071 struct macb *bp;
2072
2073 bp = netdev_priv(dev);
2074 gem_update_stats(bp);
2075 memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN);
2076 }
2077
2078 static int gem_get_sset_count(struct net_device *dev, int sset)
2079 {
2080 switch (sset) {
2081 case ETH_SS_STATS:
2082 return GEM_STATS_LEN;
2083 default:
2084 return -EOPNOTSUPP;
2085 }
2086 }
2087
2088 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2089 {
2090 unsigned int i;
2091
2092 switch (sset) {
2093 case ETH_SS_STATS:
2094 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2095 memcpy(p, gem_statistics[i].stat_string,
2096 ETH_GSTRING_LEN);
2097 break;
2098 }
2099 }
2100
2101 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2102 {
2103 struct macb *bp = netdev_priv(dev);
2104 struct net_device_stats *nstat = &bp->stats;
2105 struct macb_stats *hwstat = &bp->hw_stats.macb;
2106
2107 if (macb_is_gem(bp))
2108 return gem_get_stats(bp);
2109
2110 /* read stats from hardware */
2111 macb_update_stats(bp);
2112
2113 /* Convert HW stats into netdevice stats */
2114 nstat->rx_errors = (hwstat->rx_fcs_errors +
2115 hwstat->rx_align_errors +
2116 hwstat->rx_resource_errors +
2117 hwstat->rx_overruns +
2118 hwstat->rx_oversize_pkts +
2119 hwstat->rx_jabbers +
2120 hwstat->rx_undersize_pkts +
2121 hwstat->rx_length_mismatch);
2122 nstat->tx_errors = (hwstat->tx_late_cols +
2123 hwstat->tx_excessive_cols +
2124 hwstat->tx_underruns +
2125 hwstat->tx_carrier_errors +
2126 hwstat->sqe_test_errors);
2127 nstat->collisions = (hwstat->tx_single_cols +
2128 hwstat->tx_multiple_cols +
2129 hwstat->tx_excessive_cols);
2130 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2131 hwstat->rx_jabbers +
2132 hwstat->rx_undersize_pkts +
2133 hwstat->rx_length_mismatch);
2134 nstat->rx_over_errors = hwstat->rx_resource_errors +
2135 hwstat->rx_overruns;
2136 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2137 nstat->rx_frame_errors = hwstat->rx_align_errors;
2138 nstat->rx_fifo_errors = hwstat->rx_overruns;
2139 /* XXX: What does "missed" mean? */
2140 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2141 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2142 nstat->tx_fifo_errors = hwstat->tx_underruns;
2143 /* Don't know about heartbeat or window errors... */
2144
2145 return nstat;
2146 }
2147
2148 static int macb_get_regs_len(struct net_device *netdev)
2149 {
2150 return MACB_GREGS_NBR * sizeof(u32);
2151 }
2152
2153 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2154 void *p)
2155 {
2156 struct macb *bp = netdev_priv(dev);
2157 unsigned int tail, head;
2158 u32 *regs_buff = p;
2159
2160 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2161 | MACB_GREGS_VERSION;
2162
2163 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
2164 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
2165
2166 regs_buff[0] = macb_readl(bp, NCR);
2167 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2168 regs_buff[2] = macb_readl(bp, NSR);
2169 regs_buff[3] = macb_readl(bp, TSR);
2170 regs_buff[4] = macb_readl(bp, RBQP);
2171 regs_buff[5] = macb_readl(bp, TBQP);
2172 regs_buff[6] = macb_readl(bp, RSR);
2173 regs_buff[7] = macb_readl(bp, IMR);
2174
2175 regs_buff[8] = tail;
2176 regs_buff[9] = head;
2177 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2178 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2179
2180 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
2181 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2182 if (macb_is_gem(bp))
2183 regs_buff[13] = gem_readl(bp, DMACFG);
2184 }
2185
2186 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2187 {
2188 struct macb *bp = netdev_priv(netdev);
2189
2190 wol->supported = 0;
2191 wol->wolopts = 0;
2192
2193 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
2194 wol->supported = WAKE_MAGIC;
2195
2196 if (bp->wol & MACB_WOL_ENABLED)
2197 wol->wolopts |= WAKE_MAGIC;
2198 }
2199 }
2200
2201 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2202 {
2203 struct macb *bp = netdev_priv(netdev);
2204
2205 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
2206 (wol->wolopts & ~WAKE_MAGIC))
2207 return -EOPNOTSUPP;
2208
2209 if (wol->wolopts & WAKE_MAGIC)
2210 bp->wol |= MACB_WOL_ENABLED;
2211 else
2212 bp->wol &= ~MACB_WOL_ENABLED;
2213
2214 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
2215
2216 return 0;
2217 }
2218
2219 static void macb_get_ringparam(struct net_device *netdev,
2220 struct ethtool_ringparam *ring)
2221 {
2222 struct macb *bp = netdev_priv(netdev);
2223
2224 ring->rx_max_pending = MAX_RX_RING_SIZE;
2225 ring->tx_max_pending = MAX_TX_RING_SIZE;
2226
2227 ring->rx_pending = bp->rx_ring_size;
2228 ring->tx_pending = bp->tx_ring_size;
2229 }
2230
2231 static int macb_set_ringparam(struct net_device *netdev,
2232 struct ethtool_ringparam *ring)
2233 {
2234 struct macb *bp = netdev_priv(netdev);
2235 u32 new_rx_size, new_tx_size;
2236 unsigned int reset = 0;
2237
2238 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2239 return -EINVAL;
2240
2241 new_rx_size = clamp_t(u32, ring->rx_pending,
2242 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
2243 new_rx_size = roundup_pow_of_two(new_rx_size);
2244
2245 new_tx_size = clamp_t(u32, ring->tx_pending,
2246 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
2247 new_tx_size = roundup_pow_of_two(new_tx_size);
2248
2249 if ((new_tx_size == bp->tx_ring_size) &&
2250 (new_rx_size == bp->rx_ring_size)) {
2251 /* nothing to do */
2252 return 0;
2253 }
2254
2255 if (netif_running(bp->dev)) {
2256 reset = 1;
2257 macb_close(bp->dev);
2258 }
2259
2260 bp->rx_ring_size = new_rx_size;
2261 bp->tx_ring_size = new_tx_size;
2262
2263 if (reset)
2264 macb_open(bp->dev);
2265
2266 return 0;
2267 }
2268
2269 static const struct ethtool_ops macb_ethtool_ops = {
2270 .get_regs_len = macb_get_regs_len,
2271 .get_regs = macb_get_regs,
2272 .get_link = ethtool_op_get_link,
2273 .get_ts_info = ethtool_op_get_ts_info,
2274 .get_wol = macb_get_wol,
2275 .set_wol = macb_set_wol,
2276 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2277 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2278 .get_ringparam = macb_get_ringparam,
2279 .set_ringparam = macb_set_ringparam,
2280 };
2281
2282 static const struct ethtool_ops gem_ethtool_ops = {
2283 .get_regs_len = macb_get_regs_len,
2284 .get_regs = macb_get_regs,
2285 .get_link = ethtool_op_get_link,
2286 .get_ts_info = ethtool_op_get_ts_info,
2287 .get_ethtool_stats = gem_get_ethtool_stats,
2288 .get_strings = gem_get_ethtool_strings,
2289 .get_sset_count = gem_get_sset_count,
2290 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2291 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2292 .get_ringparam = macb_get_ringparam,
2293 .set_ringparam = macb_set_ringparam,
2294 };
2295
2296 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2297 {
2298 struct phy_device *phydev = dev->phydev;
2299
2300 if (!netif_running(dev))
2301 return -EINVAL;
2302
2303 if (!phydev)
2304 return -ENODEV;
2305
2306 return phy_mii_ioctl(phydev, rq, cmd);
2307 }
2308
2309 static int macb_set_features(struct net_device *netdev,
2310 netdev_features_t features)
2311 {
2312 struct macb *bp = netdev_priv(netdev);
2313 netdev_features_t changed = features ^ netdev->features;
2314
2315 /* TX checksum offload */
2316 if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
2317 u32 dmacfg;
2318
2319 dmacfg = gem_readl(bp, DMACFG);
2320 if (features & NETIF_F_HW_CSUM)
2321 dmacfg |= GEM_BIT(TXCOEN);
2322 else
2323 dmacfg &= ~GEM_BIT(TXCOEN);
2324 gem_writel(bp, DMACFG, dmacfg);
2325 }
2326
2327 /* RX checksum offload */
2328 if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
2329 u32 netcfg;
2330
2331 netcfg = gem_readl(bp, NCFGR);
2332 if (features & NETIF_F_RXCSUM &&
2333 !(netdev->flags & IFF_PROMISC))
2334 netcfg |= GEM_BIT(RXCOEN);
2335 else
2336 netcfg &= ~GEM_BIT(RXCOEN);
2337 gem_writel(bp, NCFGR, netcfg);
2338 }
2339
2340 return 0;
2341 }
2342
2343 static const struct net_device_ops macb_netdev_ops = {
2344 .ndo_open = macb_open,
2345 .ndo_stop = macb_close,
2346 .ndo_start_xmit = macb_start_xmit,
2347 .ndo_set_rx_mode = macb_set_rx_mode,
2348 .ndo_get_stats = macb_get_stats,
2349 .ndo_do_ioctl = macb_ioctl,
2350 .ndo_validate_addr = eth_validate_addr,
2351 .ndo_change_mtu = macb_change_mtu,
2352 .ndo_set_mac_address = eth_mac_addr,
2353 #ifdef CONFIG_NET_POLL_CONTROLLER
2354 .ndo_poll_controller = macb_poll_controller,
2355 #endif
2356 .ndo_set_features = macb_set_features,
2357 };
2358
2359 /* Configure peripheral capabilities according to device tree
2360 * and integration options used
2361 */
2362 static void macb_configure_caps(struct macb *bp,
2363 const struct macb_config *dt_conf)
2364 {
2365 u32 dcfg;
2366
2367 if (dt_conf)
2368 bp->caps = dt_conf->caps;
2369
2370 if (hw_is_gem(bp->regs, bp->native_io)) {
2371 bp->caps |= MACB_CAPS_MACB_IS_GEM;
2372
2373 dcfg = gem_readl(bp, DCFG1);
2374 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
2375 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
2376 dcfg = gem_readl(bp, DCFG2);
2377 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
2378 bp->caps |= MACB_CAPS_FIFO_MODE;
2379 }
2380
2381 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
2382 }
2383
2384 static void macb_probe_queues(void __iomem *mem,
2385 bool native_io,
2386 unsigned int *queue_mask,
2387 unsigned int *num_queues)
2388 {
2389 unsigned int hw_q;
2390
2391 *queue_mask = 0x1;
2392 *num_queues = 1;
2393
2394 /* is it macb or gem ?
2395 *
2396 * We need to read directly from the hardware here because
2397 * we are early in the probe process and don't have the
2398 * MACB_CAPS_MACB_IS_GEM flag positioned
2399 */
2400 if (!hw_is_gem(mem, native_io))
2401 return;
2402
2403 /* bit 0 is never set but queue 0 always exists */
2404 *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
2405
2406 *queue_mask |= 0x1;
2407
2408 for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
2409 if (*queue_mask & (1 << hw_q))
2410 (*num_queues)++;
2411 }
2412
2413 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
2414 struct clk **hclk, struct clk **tx_clk,
2415 struct clk **rx_clk)
2416 {
2417 int err;
2418
2419 *pclk = devm_clk_get(&pdev->dev, "pclk");
2420 if (IS_ERR(*pclk)) {
2421 err = PTR_ERR(*pclk);
2422 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
2423 return err;
2424 }
2425
2426 *hclk = devm_clk_get(&pdev->dev, "hclk");
2427 if (IS_ERR(*hclk)) {
2428 err = PTR_ERR(*hclk);
2429 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
2430 return err;
2431 }
2432
2433 *tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
2434 if (IS_ERR(*tx_clk))
2435 *tx_clk = NULL;
2436
2437 *rx_clk = devm_clk_get(&pdev->dev, "rx_clk");
2438 if (IS_ERR(*rx_clk))
2439 *rx_clk = NULL;
2440
2441 err = clk_prepare_enable(*pclk);
2442 if (err) {
2443 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2444 return err;
2445 }
2446
2447 err = clk_prepare_enable(*hclk);
2448 if (err) {
2449 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
2450 goto err_disable_pclk;
2451 }
2452
2453 err = clk_prepare_enable(*tx_clk);
2454 if (err) {
2455 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
2456 goto err_disable_hclk;
2457 }
2458
2459 err = clk_prepare_enable(*rx_clk);
2460 if (err) {
2461 dev_err(&pdev->dev, "failed to enable rx_clk (%u)\n", err);
2462 goto err_disable_txclk;
2463 }
2464
2465 return 0;
2466
2467 err_disable_txclk:
2468 clk_disable_unprepare(*tx_clk);
2469
2470 err_disable_hclk:
2471 clk_disable_unprepare(*hclk);
2472
2473 err_disable_pclk:
2474 clk_disable_unprepare(*pclk);
2475
2476 return err;
2477 }
2478
2479 static int macb_init(struct platform_device *pdev)
2480 {
2481 struct net_device *dev = platform_get_drvdata(pdev);
2482 unsigned int hw_q, q;
2483 struct macb *bp = netdev_priv(dev);
2484 struct macb_queue *queue;
2485 int err;
2486 u32 val;
2487
2488 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
2489 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
2490
2491 /* set the queue register mapping once for all: queue0 has a special
2492 * register mapping but we don't want to test the queue index then
2493 * compute the corresponding register offset at run time.
2494 */
2495 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
2496 if (!(bp->queue_mask & (1 << hw_q)))
2497 continue;
2498
2499 queue = &bp->queues[q];
2500 queue->bp = bp;
2501 if (hw_q) {
2502 queue->ISR = GEM_ISR(hw_q - 1);
2503 queue->IER = GEM_IER(hw_q - 1);
2504 queue->IDR = GEM_IDR(hw_q - 1);
2505 queue->IMR = GEM_IMR(hw_q - 1);
2506 queue->TBQP = GEM_TBQP(hw_q - 1);
2507 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2508 queue->TBQPH = GEM_TBQPH(hw_q -1);
2509 #endif
2510 } else {
2511 /* queue0 uses legacy registers */
2512 queue->ISR = MACB_ISR;
2513 queue->IER = MACB_IER;
2514 queue->IDR = MACB_IDR;
2515 queue->IMR = MACB_IMR;
2516 queue->TBQP = MACB_TBQP;
2517 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2518 queue->TBQPH = MACB_TBQPH;
2519 #endif
2520 }
2521
2522 /* get irq: here we use the linux queue index, not the hardware
2523 * queue index. the queue irq definitions in the device tree
2524 * must remove the optional gaps that could exist in the
2525 * hardware queue mask.
2526 */
2527 queue->irq = platform_get_irq(pdev, q);
2528 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
2529 IRQF_SHARED, dev->name, queue);
2530 if (err) {
2531 dev_err(&pdev->dev,
2532 "Unable to request IRQ %d (error %d)\n",
2533 queue->irq, err);
2534 return err;
2535 }
2536
2537 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
2538 q++;
2539 }
2540
2541 dev->netdev_ops = &macb_netdev_ops;
2542 netif_napi_add(dev, &bp->napi, macb_poll, 64);
2543
2544 /* setup appropriated routines according to adapter type */
2545 if (macb_is_gem(bp)) {
2546 bp->max_tx_length = GEM_MAX_TX_LEN;
2547 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
2548 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
2549 bp->macbgem_ops.mog_init_rings = gem_init_rings;
2550 bp->macbgem_ops.mog_rx = gem_rx;
2551 dev->ethtool_ops = &gem_ethtool_ops;
2552 } else {
2553 bp->max_tx_length = MACB_MAX_TX_LEN;
2554 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
2555 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
2556 bp->macbgem_ops.mog_init_rings = macb_init_rings;
2557 bp->macbgem_ops.mog_rx = macb_rx;
2558 dev->ethtool_ops = &macb_ethtool_ops;
2559 }
2560
2561 /* Set features */
2562 dev->hw_features = NETIF_F_SG;
2563 /* Checksum offload is only available on gem with packet buffer */
2564 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
2565 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
2566 if (bp->caps & MACB_CAPS_SG_DISABLED)
2567 dev->hw_features &= ~NETIF_F_SG;
2568 dev->features = dev->hw_features;
2569
2570 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
2571 val = 0;
2572 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
2573 val = GEM_BIT(RGMII);
2574 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
2575 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
2576 val = MACB_BIT(RMII);
2577 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
2578 val = MACB_BIT(MII);
2579
2580 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
2581 val |= MACB_BIT(CLKEN);
2582
2583 macb_or_gem_writel(bp, USRIO, val);
2584 }
2585
2586 /* Set MII management clock divider */
2587 val = macb_mdc_clk_div(bp);
2588 val |= macb_dbw(bp);
2589 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
2590 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
2591 macb_writel(bp, NCFGR, val);
2592
2593 return 0;
2594 }
2595
2596 #if defined(CONFIG_OF)
2597 /* 1518 rounded up */
2598 #define AT91ETHER_MAX_RBUFF_SZ 0x600
2599 /* max number of receive buffers */
2600 #define AT91ETHER_MAX_RX_DESCR 9
2601
2602 /* Initialize and start the Receiver and Transmit subsystems */
2603 static int at91ether_start(struct net_device *dev)
2604 {
2605 struct macb *lp = netdev_priv(dev);
2606 dma_addr_t addr;
2607 u32 ctl;
2608 int i;
2609
2610 lp->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
2611 (AT91ETHER_MAX_RX_DESCR *
2612 sizeof(struct macb_dma_desc)),
2613 &lp->rx_ring_dma, GFP_KERNEL);
2614 if (!lp->rx_ring)
2615 return -ENOMEM;
2616
2617 lp->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
2618 AT91ETHER_MAX_RX_DESCR *
2619 AT91ETHER_MAX_RBUFF_SZ,
2620 &lp->rx_buffers_dma, GFP_KERNEL);
2621 if (!lp->rx_buffers) {
2622 dma_free_coherent(&lp->pdev->dev,
2623 AT91ETHER_MAX_RX_DESCR *
2624 sizeof(struct macb_dma_desc),
2625 lp->rx_ring, lp->rx_ring_dma);
2626 lp->rx_ring = NULL;
2627 return -ENOMEM;
2628 }
2629
2630 addr = lp->rx_buffers_dma;
2631 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
2632 lp->rx_ring[i].addr = addr;
2633 lp->rx_ring[i].ctrl = 0;
2634 addr += AT91ETHER_MAX_RBUFF_SZ;
2635 }
2636
2637 /* Set the Wrap bit on the last descriptor */
2638 lp->rx_ring[AT91ETHER_MAX_RX_DESCR - 1].addr |= MACB_BIT(RX_WRAP);
2639
2640 /* Reset buffer index */
2641 lp->rx_tail = 0;
2642
2643 /* Program address of descriptor list in Rx Buffer Queue register */
2644 macb_writel(lp, RBQP, lp->rx_ring_dma);
2645
2646 /* Enable Receive and Transmit */
2647 ctl = macb_readl(lp, NCR);
2648 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
2649
2650 return 0;
2651 }
2652
2653 /* Open the ethernet interface */
2654 static int at91ether_open(struct net_device *dev)
2655 {
2656 struct macb *lp = netdev_priv(dev);
2657 u32 ctl;
2658 int ret;
2659
2660 /* Clear internal statistics */
2661 ctl = macb_readl(lp, NCR);
2662 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
2663
2664 macb_set_hwaddr(lp);
2665
2666 ret = at91ether_start(dev);
2667 if (ret)
2668 return ret;
2669
2670 /* Enable MAC interrupts */
2671 macb_writel(lp, IER, MACB_BIT(RCOMP) |
2672 MACB_BIT(RXUBR) |
2673 MACB_BIT(ISR_TUND) |
2674 MACB_BIT(ISR_RLE) |
2675 MACB_BIT(TCOMP) |
2676 MACB_BIT(ISR_ROVR) |
2677 MACB_BIT(HRESP));
2678
2679 /* schedule a link state check */
2680 phy_start(dev->phydev);
2681
2682 netif_start_queue(dev);
2683
2684 return 0;
2685 }
2686
2687 /* Close the interface */
2688 static int at91ether_close(struct net_device *dev)
2689 {
2690 struct macb *lp = netdev_priv(dev);
2691 u32 ctl;
2692
2693 /* Disable Receiver and Transmitter */
2694 ctl = macb_readl(lp, NCR);
2695 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
2696
2697 /* Disable MAC interrupts */
2698 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
2699 MACB_BIT(RXUBR) |
2700 MACB_BIT(ISR_TUND) |
2701 MACB_BIT(ISR_RLE) |
2702 MACB_BIT(TCOMP) |
2703 MACB_BIT(ISR_ROVR) |
2704 MACB_BIT(HRESP));
2705
2706 netif_stop_queue(dev);
2707
2708 dma_free_coherent(&lp->pdev->dev,
2709 AT91ETHER_MAX_RX_DESCR *
2710 sizeof(struct macb_dma_desc),
2711 lp->rx_ring, lp->rx_ring_dma);
2712 lp->rx_ring = NULL;
2713
2714 dma_free_coherent(&lp->pdev->dev,
2715 AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
2716 lp->rx_buffers, lp->rx_buffers_dma);
2717 lp->rx_buffers = NULL;
2718
2719 return 0;
2720 }
2721
2722 /* Transmit packet */
2723 static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
2724 {
2725 struct macb *lp = netdev_priv(dev);
2726
2727 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
2728 netif_stop_queue(dev);
2729
2730 /* Store packet information (to free when Tx completed) */
2731 lp->skb = skb;
2732 lp->skb_length = skb->len;
2733 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
2734 DMA_TO_DEVICE);
2735
2736 /* Set address of the data in the Transmit Address register */
2737 macb_writel(lp, TAR, lp->skb_physaddr);
2738 /* Set length of the packet in the Transmit Control register */
2739 macb_writel(lp, TCR, skb->len);
2740
2741 } else {
2742 netdev_err(dev, "%s called, but device is busy!\n", __func__);
2743 return NETDEV_TX_BUSY;
2744 }
2745
2746 return NETDEV_TX_OK;
2747 }
2748
2749 /* Extract received frame from buffer descriptors and sent to upper layers.
2750 * (Called from interrupt context)
2751 */
2752 static void at91ether_rx(struct net_device *dev)
2753 {
2754 struct macb *lp = netdev_priv(dev);
2755 unsigned char *p_recv;
2756 struct sk_buff *skb;
2757 unsigned int pktlen;
2758
2759 while (lp->rx_ring[lp->rx_tail].addr & MACB_BIT(RX_USED)) {
2760 p_recv = lp->rx_buffers + lp->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
2761 pktlen = MACB_BF(RX_FRMLEN, lp->rx_ring[lp->rx_tail].ctrl);
2762 skb = netdev_alloc_skb(dev, pktlen + 2);
2763 if (skb) {
2764 skb_reserve(skb, 2);
2765 memcpy(skb_put(skb, pktlen), p_recv, pktlen);
2766
2767 skb->protocol = eth_type_trans(skb, dev);
2768 lp->stats.rx_packets++;
2769 lp->stats.rx_bytes += pktlen;
2770 netif_rx(skb);
2771 } else {
2772 lp->stats.rx_dropped++;
2773 }
2774
2775 if (lp->rx_ring[lp->rx_tail].ctrl & MACB_BIT(RX_MHASH_MATCH))
2776 lp->stats.multicast++;
2777
2778 /* reset ownership bit */
2779 lp->rx_ring[lp->rx_tail].addr &= ~MACB_BIT(RX_USED);
2780
2781 /* wrap after last buffer */
2782 if (lp->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
2783 lp->rx_tail = 0;
2784 else
2785 lp->rx_tail++;
2786 }
2787 }
2788
2789 /* MAC interrupt handler */
2790 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
2791 {
2792 struct net_device *dev = dev_id;
2793 struct macb *lp = netdev_priv(dev);
2794 u32 intstatus, ctl;
2795
2796 /* MAC Interrupt Status register indicates what interrupts are pending.
2797 * It is automatically cleared once read.
2798 */
2799 intstatus = macb_readl(lp, ISR);
2800
2801 /* Receive complete */
2802 if (intstatus & MACB_BIT(RCOMP))
2803 at91ether_rx(dev);
2804
2805 /* Transmit complete */
2806 if (intstatus & MACB_BIT(TCOMP)) {
2807 /* The TCOM bit is set even if the transmission failed */
2808 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
2809 lp->stats.tx_errors++;
2810
2811 if (lp->skb) {
2812 dev_kfree_skb_irq(lp->skb);
2813 lp->skb = NULL;
2814 dma_unmap_single(NULL, lp->skb_physaddr,
2815 lp->skb_length, DMA_TO_DEVICE);
2816 lp->stats.tx_packets++;
2817 lp->stats.tx_bytes += lp->skb_length;
2818 }
2819 netif_wake_queue(dev);
2820 }
2821
2822 /* Work-around for EMAC Errata section 41.3.1 */
2823 if (intstatus & MACB_BIT(RXUBR)) {
2824 ctl = macb_readl(lp, NCR);
2825 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
2826 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
2827 }
2828
2829 if (intstatus & MACB_BIT(ISR_ROVR))
2830 netdev_err(dev, "ROVR error\n");
2831
2832 return IRQ_HANDLED;
2833 }
2834
2835 #ifdef CONFIG_NET_POLL_CONTROLLER
2836 static void at91ether_poll_controller(struct net_device *dev)
2837 {
2838 unsigned long flags;
2839
2840 local_irq_save(flags);
2841 at91ether_interrupt(dev->irq, dev);
2842 local_irq_restore(flags);
2843 }
2844 #endif
2845
2846 static const struct net_device_ops at91ether_netdev_ops = {
2847 .ndo_open = at91ether_open,
2848 .ndo_stop = at91ether_close,
2849 .ndo_start_xmit = at91ether_start_xmit,
2850 .ndo_get_stats = macb_get_stats,
2851 .ndo_set_rx_mode = macb_set_rx_mode,
2852 .ndo_set_mac_address = eth_mac_addr,
2853 .ndo_do_ioctl = macb_ioctl,
2854 .ndo_validate_addr = eth_validate_addr,
2855 #ifdef CONFIG_NET_POLL_CONTROLLER
2856 .ndo_poll_controller = at91ether_poll_controller,
2857 #endif
2858 };
2859
2860 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
2861 struct clk **hclk, struct clk **tx_clk,
2862 struct clk **rx_clk)
2863 {
2864 int err;
2865
2866 *hclk = NULL;
2867 *tx_clk = NULL;
2868 *rx_clk = NULL;
2869
2870 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
2871 if (IS_ERR(*pclk))
2872 return PTR_ERR(*pclk);
2873
2874 err = clk_prepare_enable(*pclk);
2875 if (err) {
2876 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2877 return err;
2878 }
2879
2880 return 0;
2881 }
2882
2883 static int at91ether_init(struct platform_device *pdev)
2884 {
2885 struct net_device *dev = platform_get_drvdata(pdev);
2886 struct macb *bp = netdev_priv(dev);
2887 int err;
2888 u32 reg;
2889
2890 dev->netdev_ops = &at91ether_netdev_ops;
2891 dev->ethtool_ops = &macb_ethtool_ops;
2892
2893 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
2894 0, dev->name, dev);
2895 if (err)
2896 return err;
2897
2898 macb_writel(bp, NCR, 0);
2899
2900 reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
2901 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
2902 reg |= MACB_BIT(RM9200_RMII);
2903
2904 macb_writel(bp, NCFGR, reg);
2905
2906 return 0;
2907 }
2908
2909 static const struct macb_config at91sam9260_config = {
2910 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
2911 .clk_init = macb_clk_init,
2912 .init = macb_init,
2913 };
2914
2915 static const struct macb_config pc302gem_config = {
2916 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
2917 .dma_burst_length = 16,
2918 .clk_init = macb_clk_init,
2919 .init = macb_init,
2920 };
2921
2922 static const struct macb_config sama5d2_config = {
2923 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
2924 .dma_burst_length = 16,
2925 .clk_init = macb_clk_init,
2926 .init = macb_init,
2927 };
2928
2929 static const struct macb_config sama5d3_config = {
2930 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
2931 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
2932 .dma_burst_length = 16,
2933 .clk_init = macb_clk_init,
2934 .init = macb_init,
2935 };
2936
2937 static const struct macb_config sama5d4_config = {
2938 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
2939 .dma_burst_length = 4,
2940 .clk_init = macb_clk_init,
2941 .init = macb_init,
2942 };
2943
2944 static const struct macb_config emac_config = {
2945 .clk_init = at91ether_clk_init,
2946 .init = at91ether_init,
2947 };
2948
2949 static const struct macb_config np4_config = {
2950 .caps = MACB_CAPS_USRIO_DISABLED,
2951 .clk_init = macb_clk_init,
2952 .init = macb_init,
2953 };
2954
2955 static const struct macb_config zynqmp_config = {
2956 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO,
2957 .dma_burst_length = 16,
2958 .clk_init = macb_clk_init,
2959 .init = macb_init,
2960 .jumbo_max_len = 10240,
2961 };
2962
2963 static const struct macb_config zynq_config = {
2964 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF,
2965 .dma_burst_length = 16,
2966 .clk_init = macb_clk_init,
2967 .init = macb_init,
2968 };
2969
2970 static const struct of_device_id macb_dt_ids[] = {
2971 { .compatible = "cdns,at32ap7000-macb" },
2972 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
2973 { .compatible = "cdns,macb" },
2974 { .compatible = "cdns,np4-macb", .data = &np4_config },
2975 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
2976 { .compatible = "cdns,gem", .data = &pc302gem_config },
2977 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
2978 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
2979 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
2980 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
2981 { .compatible = "cdns,emac", .data = &emac_config },
2982 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
2983 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
2984 { /* sentinel */ }
2985 };
2986 MODULE_DEVICE_TABLE(of, macb_dt_ids);
2987 #endif /* CONFIG_OF */
2988
2989 static int macb_probe(struct platform_device *pdev)
2990 {
2991 int (*clk_init)(struct platform_device *, struct clk **,
2992 struct clk **, struct clk **, struct clk **)
2993 = macb_clk_init;
2994 int (*init)(struct platform_device *) = macb_init;
2995 struct device_node *np = pdev->dev.of_node;
2996 struct device_node *phy_node;
2997 const struct macb_config *macb_config = NULL;
2998 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
2999 unsigned int queue_mask, num_queues;
3000 struct macb_platform_data *pdata;
3001 bool native_io;
3002 struct phy_device *phydev;
3003 struct net_device *dev;
3004 struct resource *regs;
3005 void __iomem *mem;
3006 const char *mac;
3007 struct macb *bp;
3008 int err;
3009
3010 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3011 mem = devm_ioremap_resource(&pdev->dev, regs);
3012 if (IS_ERR(mem))
3013 return PTR_ERR(mem);
3014
3015 if (np) {
3016 const struct of_device_id *match;
3017
3018 match = of_match_node(macb_dt_ids, np);
3019 if (match && match->data) {
3020 macb_config = match->data;
3021 clk_init = macb_config->clk_init;
3022 init = macb_config->init;
3023 }
3024 }
3025
3026 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk);
3027 if (err)
3028 return err;
3029
3030 native_io = hw_is_native_io(mem);
3031
3032 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
3033 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
3034 if (!dev) {
3035 err = -ENOMEM;
3036 goto err_disable_clocks;
3037 }
3038
3039 dev->base_addr = regs->start;
3040
3041 SET_NETDEV_DEV(dev, &pdev->dev);
3042
3043 bp = netdev_priv(dev);
3044 bp->pdev = pdev;
3045 bp->dev = dev;
3046 bp->regs = mem;
3047 bp->native_io = native_io;
3048 if (native_io) {
3049 bp->macb_reg_readl = hw_readl_native;
3050 bp->macb_reg_writel = hw_writel_native;
3051 } else {
3052 bp->macb_reg_readl = hw_readl;
3053 bp->macb_reg_writel = hw_writel;
3054 }
3055 bp->num_queues = num_queues;
3056 bp->queue_mask = queue_mask;
3057 if (macb_config)
3058 bp->dma_burst_length = macb_config->dma_burst_length;
3059 bp->pclk = pclk;
3060 bp->hclk = hclk;
3061 bp->tx_clk = tx_clk;
3062 bp->rx_clk = rx_clk;
3063 if (macb_config)
3064 bp->jumbo_max_len = macb_config->jumbo_max_len;
3065
3066 bp->wol = 0;
3067 if (of_get_property(np, "magic-packet", NULL))
3068 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
3069 device_init_wakeup(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
3070
3071 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3072 if (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1)) > GEM_DBW32)
3073 dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
3074 #endif
3075
3076 spin_lock_init(&bp->lock);
3077
3078 /* setup capabilities */
3079 macb_configure_caps(bp, macb_config);
3080
3081 platform_set_drvdata(pdev, dev);
3082
3083 dev->irq = platform_get_irq(pdev, 0);
3084 if (dev->irq < 0) {
3085 err = dev->irq;
3086 goto err_out_free_netdev;
3087 }
3088
3089 /* MTU range: 68 - 1500 or 10240 */
3090 dev->min_mtu = GEM_MTU_MIN_SIZE;
3091 if (bp->caps & MACB_CAPS_JUMBO)
3092 dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
3093 else
3094 dev->max_mtu = ETH_DATA_LEN;
3095
3096 mac = of_get_mac_address(np);
3097 if (mac)
3098 ether_addr_copy(bp->dev->dev_addr, mac);
3099 else
3100 macb_get_hwaddr(bp);
3101
3102 /* Power up the PHY if there is a GPIO reset */
3103 phy_node = of_get_next_available_child(np, NULL);
3104 if (phy_node) {
3105 int gpio = of_get_named_gpio(phy_node, "reset-gpios", 0);
3106
3107 if (gpio_is_valid(gpio)) {
3108 bp->reset_gpio = gpio_to_desc(gpio);
3109 gpiod_direction_output(bp->reset_gpio, 1);
3110 }
3111 }
3112 of_node_put(phy_node);
3113
3114 err = of_get_phy_mode(np);
3115 if (err < 0) {
3116 pdata = dev_get_platdata(&pdev->dev);
3117 if (pdata && pdata->is_rmii)
3118 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
3119 else
3120 bp->phy_interface = PHY_INTERFACE_MODE_MII;
3121 } else {
3122 bp->phy_interface = err;
3123 }
3124
3125 /* IP specific init */
3126 err = init(pdev);
3127 if (err)
3128 goto err_out_free_netdev;
3129
3130 err = macb_mii_init(bp);
3131 if (err)
3132 goto err_out_free_netdev;
3133
3134 phydev = dev->phydev;
3135
3136 netif_carrier_off(dev);
3137
3138 err = register_netdev(dev);
3139 if (err) {
3140 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
3141 goto err_out_unregister_mdio;
3142 }
3143
3144 phy_attached_info(phydev);
3145
3146 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
3147 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
3148 dev->base_addr, dev->irq, dev->dev_addr);
3149
3150 return 0;
3151
3152 err_out_unregister_mdio:
3153 phy_disconnect(dev->phydev);
3154 mdiobus_unregister(bp->mii_bus);
3155 mdiobus_free(bp->mii_bus);
3156
3157 /* Shutdown the PHY if there is a GPIO reset */
3158 if (bp->reset_gpio)
3159 gpiod_set_value(bp->reset_gpio, 0);
3160
3161 err_out_free_netdev:
3162 free_netdev(dev);
3163
3164 err_disable_clocks:
3165 clk_disable_unprepare(tx_clk);
3166 clk_disable_unprepare(hclk);
3167 clk_disable_unprepare(pclk);
3168 clk_disable_unprepare(rx_clk);
3169
3170 return err;
3171 }
3172
3173 static int macb_remove(struct platform_device *pdev)
3174 {
3175 struct net_device *dev;
3176 struct macb *bp;
3177
3178 dev = platform_get_drvdata(pdev);
3179
3180 if (dev) {
3181 bp = netdev_priv(dev);
3182 if (dev->phydev)
3183 phy_disconnect(dev->phydev);
3184 mdiobus_unregister(bp->mii_bus);
3185 dev->phydev = NULL;
3186 mdiobus_free(bp->mii_bus);
3187
3188 /* Shutdown the PHY if there is a GPIO reset */
3189 if (bp->reset_gpio)
3190 gpiod_set_value(bp->reset_gpio, 0);
3191
3192 unregister_netdev(dev);
3193 clk_disable_unprepare(bp->tx_clk);
3194 clk_disable_unprepare(bp->hclk);
3195 clk_disable_unprepare(bp->pclk);
3196 clk_disable_unprepare(bp->rx_clk);
3197 free_netdev(dev);
3198 }
3199
3200 return 0;
3201 }
3202
3203 static int __maybe_unused macb_suspend(struct device *dev)
3204 {
3205 struct platform_device *pdev = to_platform_device(dev);
3206 struct net_device *netdev = platform_get_drvdata(pdev);
3207 struct macb *bp = netdev_priv(netdev);
3208
3209 netif_carrier_off(netdev);
3210 netif_device_detach(netdev);
3211
3212 if (bp->wol & MACB_WOL_ENABLED) {
3213 macb_writel(bp, IER, MACB_BIT(WOL));
3214 macb_writel(bp, WOL, MACB_BIT(MAG));
3215 enable_irq_wake(bp->queues[0].irq);
3216 } else {
3217 clk_disable_unprepare(bp->tx_clk);
3218 clk_disable_unprepare(bp->hclk);
3219 clk_disable_unprepare(bp->pclk);
3220 clk_disable_unprepare(bp->rx_clk);
3221 }
3222
3223 return 0;
3224 }
3225
3226 static int __maybe_unused macb_resume(struct device *dev)
3227 {
3228 struct platform_device *pdev = to_platform_device(dev);
3229 struct net_device *netdev = platform_get_drvdata(pdev);
3230 struct macb *bp = netdev_priv(netdev);
3231
3232 if (bp->wol & MACB_WOL_ENABLED) {
3233 macb_writel(bp, IDR, MACB_BIT(WOL));
3234 macb_writel(bp, WOL, 0);
3235 disable_irq_wake(bp->queues[0].irq);
3236 } else {
3237 clk_prepare_enable(bp->pclk);
3238 clk_prepare_enable(bp->hclk);
3239 clk_prepare_enable(bp->tx_clk);
3240 clk_prepare_enable(bp->rx_clk);
3241 }
3242
3243 netif_device_attach(netdev);
3244
3245 return 0;
3246 }
3247
3248 static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
3249
3250 static struct platform_driver macb_driver = {
3251 .probe = macb_probe,
3252 .remove = macb_remove,
3253 .driver = {
3254 .name = "macb",
3255 .of_match_table = of_match_ptr(macb_dt_ids),
3256 .pm = &macb_pm_ops,
3257 },
3258 };
3259
3260 module_platform_driver(macb_driver);
3261
3262 MODULE_LICENSE("GPL");
3263 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
3264 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
3265 MODULE_ALIAS("platform:macb");
(deprecated) Btrfs devel tree