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ath9k_hw: remove pCap->tx_triglevel_max
[linux-2.6/btrfs-unstable.git] / drivers / net / wireless / ath / ath9k / xmit.c
blob5943bdc4c8f9b9bd95c0e453b3d829936ee3aa81
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "ath9k.h"
18 #include "ar9003_mac.h"
19
20 #define BITS_PER_BYTE 8
21 #define OFDM_PLCP_BITS 22
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
23 #define L_STF 8
24 #define L_LTF 8
25 #define L_SIG 4
26 #define HT_SIG 8
27 #define HT_STF 4
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
33
34
35 static u16 bits_per_symbol[][2] = {
36 /* 20MHz 40MHz */
37 { 26, 54 }, /* 0: BPSK */
38 { 52, 108 }, /* 1: QPSK 1/2 */
39 { 78, 162 }, /* 2: QPSK 3/4 */
40 { 104, 216 }, /* 3: 16-QAM 1/2 */
41 { 156, 324 }, /* 4: 16-QAM 3/4 */
42 { 208, 432 }, /* 5: 64-QAM 2/3 */
43 { 234, 486 }, /* 6: 64-QAM 3/4 */
44 { 260, 540 }, /* 7: 64-QAM 5/6 */
45 };
46
47 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
48
49 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
50 struct ath_atx_tid *tid,
51 struct list_head *bf_head);
52 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
53 struct ath_txq *txq, struct list_head *bf_q,
54 struct ath_tx_status *ts, int txok, int sendbar);
55 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
56 struct list_head *head);
57 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len);
58 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
59 struct ath_tx_status *ts, int nframes, int nbad,
60 int txok, bool update_rc);
61 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
62 int seqno);
63
64 enum {
65 MCS_HT20,
66 MCS_HT20_SGI,
67 MCS_HT40,
68 MCS_HT40_SGI,
69 };
70
71 static int ath_max_4ms_framelen[4][32] = {
72 [MCS_HT20] = {
73 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
74 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
75 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
76 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
77 },
78 [MCS_HT20_SGI] = {
79 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
80 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
81 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
82 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
83 },
84 [MCS_HT40] = {
85 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
86 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
87 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
88 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
89 },
90 [MCS_HT40_SGI] = {
91 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
92 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
93 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
94 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
95 }
96 };
97
98 /*********************/
99 /* Aggregation logic */
100 /*********************/
101
102 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
103 {
104 struct ath_atx_ac *ac = tid->ac;
105
106 if (tid->paused)
107 return;
108
109 if (tid->sched)
110 return;
111
112 tid->sched = true;
113 list_add_tail(&tid->list, &ac->tid_q);
114
115 if (ac->sched)
116 return;
117
118 ac->sched = true;
119 list_add_tail(&ac->list, &txq->axq_acq);
120 }
121
122 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
123 {
124 struct ath_txq *txq = tid->ac->txq;
125
126 WARN_ON(!tid->paused);
127
128 spin_lock_bh(&txq->axq_lock);
129 tid->paused = false;
130
131 if (list_empty(&tid->buf_q))
132 goto unlock;
133
134 ath_tx_queue_tid(txq, tid);
135 ath_txq_schedule(sc, txq);
136 unlock:
137 spin_unlock_bh(&txq->axq_lock);
138 }
139
140 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
141 {
142 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
143 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
144 sizeof(tx_info->rate_driver_data));
145 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
146 }
147
148 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
149 {
150 struct ath_txq *txq = tid->ac->txq;
151 struct ath_buf *bf;
152 struct list_head bf_head;
153 struct ath_tx_status ts;
154 struct ath_frame_info *fi;
155
156 INIT_LIST_HEAD(&bf_head);
157
158 memset(&ts, 0, sizeof(ts));
159 spin_lock_bh(&txq->axq_lock);
160
161 while (!list_empty(&tid->buf_q)) {
162 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
163 list_move_tail(&bf->list, &bf_head);
164
165 spin_unlock_bh(&txq->axq_lock);
166 fi = get_frame_info(bf->bf_mpdu);
167 if (fi->retries) {
168 ath_tx_update_baw(sc, tid, fi->seqno);
169 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 1);
170 } else {
171 ath_tx_send_normal(sc, txq, NULL, &bf_head);
172 }
173 spin_lock_bh(&txq->axq_lock);
174 }
175
176 spin_unlock_bh(&txq->axq_lock);
177 }
178
179 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
180 int seqno)
181 {
182 int index, cindex;
183
184 index = ATH_BA_INDEX(tid->seq_start, seqno);
185 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
186
187 __clear_bit(cindex, tid->tx_buf);
188
189 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
190 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
191 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
192 }
193 }
194
195 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
196 u16 seqno)
197 {
198 int index, cindex;
199
200 index = ATH_BA_INDEX(tid->seq_start, seqno);
201 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
202 __set_bit(cindex, tid->tx_buf);
203
204 if (index >= ((tid->baw_tail - tid->baw_head) &
205 (ATH_TID_MAX_BUFS - 1))) {
206 tid->baw_tail = cindex;
207 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
208 }
209 }
210
211 /*
212 * TODO: For frame(s) that are in the retry state, we will reuse the
213 * sequence number(s) without setting the retry bit. The
214 * alternative is to give up on these and BAR the receiver's window
215 * forward.
216 */
217 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
218 struct ath_atx_tid *tid)
219
220 {
221 struct ath_buf *bf;
222 struct list_head bf_head;
223 struct ath_tx_status ts;
224 struct ath_frame_info *fi;
225
226 memset(&ts, 0, sizeof(ts));
227 INIT_LIST_HEAD(&bf_head);
228
229 for (;;) {
230 if (list_empty(&tid->buf_q))
231 break;
232
233 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
234 list_move_tail(&bf->list, &bf_head);
235
236 fi = get_frame_info(bf->bf_mpdu);
237 if (fi->retries)
238 ath_tx_update_baw(sc, tid, fi->seqno);
239
240 spin_unlock(&txq->axq_lock);
241 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
242 spin_lock(&txq->axq_lock);
243 }
244
245 tid->seq_next = tid->seq_start;
246 tid->baw_tail = tid->baw_head;
247 }
248
249 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
250 struct sk_buff *skb)
251 {
252 struct ath_frame_info *fi = get_frame_info(skb);
253 struct ieee80211_hdr *hdr;
254
255 TX_STAT_INC(txq->axq_qnum, a_retries);
256 if (fi->retries++ > 0)
257 return;
258
259 hdr = (struct ieee80211_hdr *)skb->data;
260 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
261 }
262
263 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
264 {
265 struct ath_buf *bf = NULL;
266
267 spin_lock_bh(&sc->tx.txbuflock);
268
269 if (unlikely(list_empty(&sc->tx.txbuf))) {
270 spin_unlock_bh(&sc->tx.txbuflock);
271 return NULL;
272 }
273
274 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
275 list_del(&bf->list);
276
277 spin_unlock_bh(&sc->tx.txbuflock);
278
279 return bf;
280 }
281
282 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
283 {
284 spin_lock_bh(&sc->tx.txbuflock);
285 list_add_tail(&bf->list, &sc->tx.txbuf);
286 spin_unlock_bh(&sc->tx.txbuflock);
287 }
288
289 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
290 {
291 struct ath_buf *tbf;
292
293 tbf = ath_tx_get_buffer(sc);
294 if (WARN_ON(!tbf))
295 return NULL;
296
297 ATH_TXBUF_RESET(tbf);
298
299 tbf->bf_mpdu = bf->bf_mpdu;
300 tbf->bf_buf_addr = bf->bf_buf_addr;
301 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
302 tbf->bf_state = bf->bf_state;
303
304 return tbf;
305 }
306
307 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
308 struct ath_tx_status *ts, int txok,
309 int *nframes, int *nbad)
310 {
311 struct ath_frame_info *fi;
312 u16 seq_st = 0;
313 u32 ba[WME_BA_BMP_SIZE >> 5];
314 int ba_index;
315 int isaggr = 0;
316
317 *nbad = 0;
318 *nframes = 0;
319
320 isaggr = bf_isaggr(bf);
321 if (isaggr) {
322 seq_st = ts->ts_seqnum;
323 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
324 }
325
326 while (bf) {
327 fi = get_frame_info(bf->bf_mpdu);
328 ba_index = ATH_BA_INDEX(seq_st, fi->seqno);
329
330 (*nframes)++;
331 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
332 (*nbad)++;
333
334 bf = bf->bf_next;
335 }
336 }
337
338
339 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
340 struct ath_buf *bf, struct list_head *bf_q,
341 struct ath_tx_status *ts, int txok, bool retry)
342 {
343 struct ath_node *an = NULL;
344 struct sk_buff *skb;
345 struct ieee80211_sta *sta;
346 struct ieee80211_hw *hw = sc->hw;
347 struct ieee80211_hdr *hdr;
348 struct ieee80211_tx_info *tx_info;
349 struct ath_atx_tid *tid = NULL;
350 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
351 struct list_head bf_head, bf_pending;
352 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
353 u32 ba[WME_BA_BMP_SIZE >> 5];
354 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
355 bool rc_update = true;
356 struct ieee80211_tx_rate rates[4];
357 struct ath_frame_info *fi;
358 int nframes;
359 u8 tidno;
360
361 skb = bf->bf_mpdu;
362 hdr = (struct ieee80211_hdr *)skb->data;
363
364 tx_info = IEEE80211_SKB_CB(skb);
365
366 memcpy(rates, tx_info->control.rates, sizeof(rates));
367
368 rcu_read_lock();
369
370 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
371 if (!sta) {
372 rcu_read_unlock();
373
374 INIT_LIST_HEAD(&bf_head);
375 while (bf) {
376 bf_next = bf->bf_next;
377
378 bf->bf_state.bf_type |= BUF_XRETRY;
379 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
380 !bf->bf_stale || bf_next != NULL)
381 list_move_tail(&bf->list, &bf_head);
382
383 ath_tx_rc_status(sc, bf, ts, 1, 1, 0, false);
384 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
385 0, 0);
386
387 bf = bf_next;
388 }
389 return;
390 }
391
392 an = (struct ath_node *)sta->drv_priv;
393 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
394 tid = ATH_AN_2_TID(an, tidno);
395
396 /*
397 * The hardware occasionally sends a tx status for the wrong TID.
398 * In this case, the BA status cannot be considered valid and all
399 * subframes need to be retransmitted
400 */
401 if (tidno != ts->tid)
402 txok = false;
403
404 isaggr = bf_isaggr(bf);
405 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
406
407 if (isaggr && txok) {
408 if (ts->ts_flags & ATH9K_TX_BA) {
409 seq_st = ts->ts_seqnum;
410 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
411 } else {
412 /*
413 * AR5416 can become deaf/mute when BA
414 * issue happens. Chip needs to be reset.
415 * But AP code may have sychronization issues
416 * when perform internal reset in this routine.
417 * Only enable reset in STA mode for now.
418 */
419 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
420 needreset = 1;
421 }
422 }
423
424 INIT_LIST_HEAD(&bf_pending);
425 INIT_LIST_HEAD(&bf_head);
426
427 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
428 while (bf) {
429 txfail = txpending = sendbar = 0;
430 bf_next = bf->bf_next;
431
432 skb = bf->bf_mpdu;
433 tx_info = IEEE80211_SKB_CB(skb);
434 fi = get_frame_info(skb);
435
436 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, fi->seqno))) {
437 /* transmit completion, subframe is
438 * acked by block ack */
439 acked_cnt++;
440 } else if (!isaggr && txok) {
441 /* transmit completion */
442 acked_cnt++;
443 } else {
444 if (!(tid->state & AGGR_CLEANUP) && retry) {
445 if (fi->retries < ATH_MAX_SW_RETRIES) {
446 ath_tx_set_retry(sc, txq, bf->bf_mpdu);
447 txpending = 1;
448 } else {
449 bf->bf_state.bf_type |= BUF_XRETRY;
450 txfail = 1;
451 sendbar = 1;
452 txfail_cnt++;
453 }
454 } else {
455 /*
456 * cleanup in progress, just fail
457 * the un-acked sub-frames
458 */
459 txfail = 1;
460 }
461 }
462
463 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
464 bf_next == NULL) {
465 /*
466 * Make sure the last desc is reclaimed if it
467 * not a holding desc.
468 */
469 if (!bf_last->bf_stale)
470 list_move_tail(&bf->list, &bf_head);
471 else
472 INIT_LIST_HEAD(&bf_head);
473 } else {
474 BUG_ON(list_empty(bf_q));
475 list_move_tail(&bf->list, &bf_head);
476 }
477
478 if (!txpending || (tid->state & AGGR_CLEANUP)) {
479 /*
480 * complete the acked-ones/xretried ones; update
481 * block-ack window
482 */
483 spin_lock_bh(&txq->axq_lock);
484 ath_tx_update_baw(sc, tid, fi->seqno);
485 spin_unlock_bh(&txq->axq_lock);
486
487 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
488 memcpy(tx_info->control.rates, rates, sizeof(rates));
489 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, true);
490 rc_update = false;
491 } else {
492 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, false);
493 }
494
495 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
496 !txfail, sendbar);
497 } else {
498 /* retry the un-acked ones */
499 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
500 if (bf->bf_next == NULL && bf_last->bf_stale) {
501 struct ath_buf *tbf;
502
503 tbf = ath_clone_txbuf(sc, bf_last);
504 /*
505 * Update tx baw and complete the
506 * frame with failed status if we
507 * run out of tx buf.
508 */
509 if (!tbf) {
510 spin_lock_bh(&txq->axq_lock);
511 ath_tx_update_baw(sc, tid, fi->seqno);
512 spin_unlock_bh(&txq->axq_lock);
513
514 bf->bf_state.bf_type |=
515 BUF_XRETRY;
516 ath_tx_rc_status(sc, bf, ts, nframes,
517 nbad, 0, false);
518 ath_tx_complete_buf(sc, bf, txq,
519 &bf_head,
520 ts, 0, 0);
521 break;
522 }
523
524 ath9k_hw_cleartxdesc(sc->sc_ah,
525 tbf->bf_desc);
526 list_add_tail(&tbf->list, &bf_head);
527 } else {
528 /*
529 * Clear descriptor status words for
530 * software retry
531 */
532 ath9k_hw_cleartxdesc(sc->sc_ah,
533 bf->bf_desc);
534 }
535 }
536
537 /*
538 * Put this buffer to the temporary pending
539 * queue to retain ordering
540 */
541 list_splice_tail_init(&bf_head, &bf_pending);
542 }
543
544 bf = bf_next;
545 }
546
547 /* prepend un-acked frames to the beginning of the pending frame queue */
548 if (!list_empty(&bf_pending)) {
549 spin_lock_bh(&txq->axq_lock);
550 list_splice(&bf_pending, &tid->buf_q);
551 ath_tx_queue_tid(txq, tid);
552 spin_unlock_bh(&txq->axq_lock);
553 }
554
555 if (tid->state & AGGR_CLEANUP) {
556 ath_tx_flush_tid(sc, tid);
557
558 if (tid->baw_head == tid->baw_tail) {
559 tid->state &= ~AGGR_ADDBA_COMPLETE;
560 tid->state &= ~AGGR_CLEANUP;
561 }
562 }
563
564 rcu_read_unlock();
565
566 if (needreset) {
567 spin_unlock_bh(&sc->sc_pcu_lock);
568 ath_reset(sc, false);
569 spin_lock_bh(&sc->sc_pcu_lock);
570 }
571 }
572
573 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
574 struct ath_atx_tid *tid)
575 {
576 struct sk_buff *skb;
577 struct ieee80211_tx_info *tx_info;
578 struct ieee80211_tx_rate *rates;
579 u32 max_4ms_framelen, frmlen;
580 u16 aggr_limit, legacy = 0;
581 int i;
582
583 skb = bf->bf_mpdu;
584 tx_info = IEEE80211_SKB_CB(skb);
585 rates = tx_info->control.rates;
586
587 /*
588 * Find the lowest frame length among the rate series that will have a
589 * 4ms transmit duration.
590 * TODO - TXOP limit needs to be considered.
591 */
592 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
593
594 for (i = 0; i < 4; i++) {
595 if (rates[i].count) {
596 int modeidx;
597 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
598 legacy = 1;
599 break;
600 }
601
602 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
603 modeidx = MCS_HT40;
604 else
605 modeidx = MCS_HT20;
606
607 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
608 modeidx++;
609
610 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
611 max_4ms_framelen = min(max_4ms_framelen, frmlen);
612 }
613 }
614
615 /*
616 * limit aggregate size by the minimum rate if rate selected is
617 * not a probe rate, if rate selected is a probe rate then
618 * avoid aggregation of this packet.
619 */
620 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
621 return 0;
622
623 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
624 aggr_limit = min((max_4ms_framelen * 3) / 8,
625 (u32)ATH_AMPDU_LIMIT_MAX);
626 else
627 aggr_limit = min(max_4ms_framelen,
628 (u32)ATH_AMPDU_LIMIT_MAX);
629
630 /*
631 * h/w can accept aggregates upto 16 bit lengths (65535).
632 * The IE, however can hold upto 65536, which shows up here
633 * as zero. Ignore 65536 since we are constrained by hw.
634 */
635 if (tid->an->maxampdu)
636 aggr_limit = min(aggr_limit, tid->an->maxampdu);
637
638 return aggr_limit;
639 }
640
641 /*
642 * Returns the number of delimiters to be added to
643 * meet the minimum required mpdudensity.
644 */
645 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
646 struct ath_buf *bf, u16 frmlen)
647 {
648 struct sk_buff *skb = bf->bf_mpdu;
649 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
650 u32 nsymbits, nsymbols;
651 u16 minlen;
652 u8 flags, rix;
653 int width, streams, half_gi, ndelim, mindelim;
654 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
655
656 /* Select standard number of delimiters based on frame length alone */
657 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
658
659 /*
660 * If encryption enabled, hardware requires some more padding between
661 * subframes.
662 * TODO - this could be improved to be dependent on the rate.
663 * The hardware can keep up at lower rates, but not higher rates
664 */
665 if (fi->keyix != ATH9K_TXKEYIX_INVALID)
666 ndelim += ATH_AGGR_ENCRYPTDELIM;
667
668 /*
669 * Convert desired mpdu density from microeconds to bytes based
670 * on highest rate in rate series (i.e. first rate) to determine
671 * required minimum length for subframe. Take into account
672 * whether high rate is 20 or 40Mhz and half or full GI.
673 *
674 * If there is no mpdu density restriction, no further calculation
675 * is needed.
676 */
677
678 if (tid->an->mpdudensity == 0)
679 return ndelim;
680
681 rix = tx_info->control.rates[0].idx;
682 flags = tx_info->control.rates[0].flags;
683 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
684 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
685
686 if (half_gi)
687 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
688 else
689 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
690
691 if (nsymbols == 0)
692 nsymbols = 1;
693
694 streams = HT_RC_2_STREAMS(rix);
695 nsymbits = bits_per_symbol[rix % 8][width] * streams;
696 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
697
698 if (frmlen < minlen) {
699 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
700 ndelim = max(mindelim, ndelim);
701 }
702
703 return ndelim;
704 }
705
706 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
707 struct ath_txq *txq,
708 struct ath_atx_tid *tid,
709 struct list_head *bf_q,
710 int *aggr_len)
711 {
712 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
713 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
714 int rl = 0, nframes = 0, ndelim, prev_al = 0;
715 u16 aggr_limit = 0, al = 0, bpad = 0,
716 al_delta, h_baw = tid->baw_size / 2;
717 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
718 struct ieee80211_tx_info *tx_info;
719 struct ath_frame_info *fi;
720
721 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
722
723 do {
724 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
725 fi = get_frame_info(bf->bf_mpdu);
726
727 /* do not step over block-ack window */
728 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno)) {
729 status = ATH_AGGR_BAW_CLOSED;
730 break;
731 }
732
733 if (!rl) {
734 aggr_limit = ath_lookup_rate(sc, bf, tid);
735 rl = 1;
736 }
737
738 /* do not exceed aggregation limit */
739 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
740
741 if (nframes &&
742 (aggr_limit < (al + bpad + al_delta + prev_al))) {
743 status = ATH_AGGR_LIMITED;
744 break;
745 }
746
747 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
748 if (nframes && ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
749 !(tx_info->control.rates[0].flags & IEEE80211_TX_RC_MCS)))
750 break;
751
752 /* do not exceed subframe limit */
753 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
754 status = ATH_AGGR_LIMITED;
755 break;
756 }
757 nframes++;
758
759 /* add padding for previous frame to aggregation length */
760 al += bpad + al_delta;
761
762 /*
763 * Get the delimiters needed to meet the MPDU
764 * density for this node.
765 */
766 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen);
767 bpad = PADBYTES(al_delta) + (ndelim << 2);
768
769 bf->bf_next = NULL;
770 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
771
772 /* link buffers of this frame to the aggregate */
773 if (!fi->retries)
774 ath_tx_addto_baw(sc, tid, fi->seqno);
775 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
776 list_move_tail(&bf->list, bf_q);
777 if (bf_prev) {
778 bf_prev->bf_next = bf;
779 ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
780 bf->bf_daddr);
781 }
782 bf_prev = bf;
783
784 } while (!list_empty(&tid->buf_q));
785
786 *aggr_len = al;
787
788 return status;
789 #undef PADBYTES
790 }
791
792 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
793 struct ath_atx_tid *tid)
794 {
795 struct ath_buf *bf;
796 enum ATH_AGGR_STATUS status;
797 struct ath_frame_info *fi;
798 struct list_head bf_q;
799 int aggr_len;
800
801 do {
802 if (list_empty(&tid->buf_q))
803 return;
804
805 INIT_LIST_HEAD(&bf_q);
806
807 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
808
809 /*
810 * no frames picked up to be aggregated;
811 * block-ack window is not open.
812 */
813 if (list_empty(&bf_q))
814 break;
815
816 bf = list_first_entry(&bf_q, struct ath_buf, list);
817 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
818
819 /* if only one frame, send as non-aggregate */
820 if (bf == bf->bf_lastbf) {
821 fi = get_frame_info(bf->bf_mpdu);
822
823 bf->bf_state.bf_type &= ~BUF_AGGR;
824 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
825 ath_buf_set_rate(sc, bf, fi->framelen);
826 ath_tx_txqaddbuf(sc, txq, &bf_q);
827 continue;
828 }
829
830 /* setup first desc of aggregate */
831 bf->bf_state.bf_type |= BUF_AGGR;
832 ath_buf_set_rate(sc, bf, aggr_len);
833 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, aggr_len);
834
835 /* anchor last desc of aggregate */
836 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
837
838 ath_tx_txqaddbuf(sc, txq, &bf_q);
839 TX_STAT_INC(txq->axq_qnum, a_aggr);
840
841 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
842 status != ATH_AGGR_BAW_CLOSED);
843 }
844
845 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
846 u16 tid, u16 *ssn)
847 {
848 struct ath_atx_tid *txtid;
849 struct ath_node *an;
850
851 an = (struct ath_node *)sta->drv_priv;
852 txtid = ATH_AN_2_TID(an, tid);
853
854 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
855 return -EAGAIN;
856
857 txtid->state |= AGGR_ADDBA_PROGRESS;
858 txtid->paused = true;
859 *ssn = txtid->seq_start = txtid->seq_next;
860
861 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
862 txtid->baw_head = txtid->baw_tail = 0;
863
864 return 0;
865 }
866
867 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
868 {
869 struct ath_node *an = (struct ath_node *)sta->drv_priv;
870 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
871 struct ath_txq *txq = txtid->ac->txq;
872
873 if (txtid->state & AGGR_CLEANUP)
874 return;
875
876 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
877 txtid->state &= ~AGGR_ADDBA_PROGRESS;
878 return;
879 }
880
881 spin_lock_bh(&txq->axq_lock);
882 txtid->paused = true;
883
884 /*
885 * If frames are still being transmitted for this TID, they will be
886 * cleaned up during tx completion. To prevent race conditions, this
887 * TID can only be reused after all in-progress subframes have been
888 * completed.
889 */
890 if (txtid->baw_head != txtid->baw_tail)
891 txtid->state |= AGGR_CLEANUP;
892 else
893 txtid->state &= ~AGGR_ADDBA_COMPLETE;
894 spin_unlock_bh(&txq->axq_lock);
895
896 ath_tx_flush_tid(sc, txtid);
897 }
898
899 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
900 {
901 struct ath_atx_tid *txtid;
902 struct ath_node *an;
903
904 an = (struct ath_node *)sta->drv_priv;
905
906 if (sc->sc_flags & SC_OP_TXAGGR) {
907 txtid = ATH_AN_2_TID(an, tid);
908 txtid->baw_size =
909 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
910 txtid->state |= AGGR_ADDBA_COMPLETE;
911 txtid->state &= ~AGGR_ADDBA_PROGRESS;
912 ath_tx_resume_tid(sc, txtid);
913 }
914 }
915
916 /********************/
917 /* Queue Management */
918 /********************/
919
920 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
921 struct ath_txq *txq)
922 {
923 struct ath_atx_ac *ac, *ac_tmp;
924 struct ath_atx_tid *tid, *tid_tmp;
925
926 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
927 list_del(&ac->list);
928 ac->sched = false;
929 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
930 list_del(&tid->list);
931 tid->sched = false;
932 ath_tid_drain(sc, txq, tid);
933 }
934 }
935 }
936
937 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
938 {
939 struct ath_hw *ah = sc->sc_ah;
940 struct ath_common *common = ath9k_hw_common(ah);
941 struct ath9k_tx_queue_info qi;
942 static const int subtype_txq_to_hwq[] = {
943 [WME_AC_BE] = ATH_TXQ_AC_BE,
944 [WME_AC_BK] = ATH_TXQ_AC_BK,
945 [WME_AC_VI] = ATH_TXQ_AC_VI,
946 [WME_AC_VO] = ATH_TXQ_AC_VO,
947 };
948 int axq_qnum, i;
949
950 memset(&qi, 0, sizeof(qi));
951 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
952 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
953 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
954 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
955 qi.tqi_physCompBuf = 0;
956
957 /*
958 * Enable interrupts only for EOL and DESC conditions.
959 * We mark tx descriptors to receive a DESC interrupt
960 * when a tx queue gets deep; otherwise waiting for the
961 * EOL to reap descriptors. Note that this is done to
962 * reduce interrupt load and this only defers reaping
963 * descriptors, never transmitting frames. Aside from
964 * reducing interrupts this also permits more concurrency.
965 * The only potential downside is if the tx queue backs
966 * up in which case the top half of the kernel may backup
967 * due to a lack of tx descriptors.
968 *
969 * The UAPSD queue is an exception, since we take a desc-
970 * based intr on the EOSP frames.
971 */
972 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
973 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
974 TXQ_FLAG_TXERRINT_ENABLE;
975 } else {
976 if (qtype == ATH9K_TX_QUEUE_UAPSD)
977 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
978 else
979 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
980 TXQ_FLAG_TXDESCINT_ENABLE;
981 }
982 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
983 if (axq_qnum == -1) {
984 /*
985 * NB: don't print a message, this happens
986 * normally on parts with too few tx queues
987 */
988 return NULL;
989 }
990 if (axq_qnum >= ARRAY_SIZE(sc->tx.txq)) {
991 ath_err(common, "qnum %u out of range, max %zu!\n",
992 axq_qnum, ARRAY_SIZE(sc->tx.txq));
993 ath9k_hw_releasetxqueue(ah, axq_qnum);
994 return NULL;
995 }
996 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
997 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
998
999 txq->axq_qnum = axq_qnum;
1000 txq->mac80211_qnum = -1;
1001 txq->axq_link = NULL;
1002 INIT_LIST_HEAD(&txq->axq_q);
1003 INIT_LIST_HEAD(&txq->axq_acq);
1004 spin_lock_init(&txq->axq_lock);
1005 txq->axq_depth = 0;
1006 txq->axq_ampdu_depth = 0;
1007 txq->axq_tx_inprogress = false;
1008 sc->tx.txqsetup |= 1<<axq_qnum;
1009
1010 txq->txq_headidx = txq->txq_tailidx = 0;
1011 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1012 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1013 INIT_LIST_HEAD(&txq->txq_fifo_pending);
1014 }
1015 return &sc->tx.txq[axq_qnum];
1016 }
1017
1018 int ath_txq_update(struct ath_softc *sc, int qnum,
1019 struct ath9k_tx_queue_info *qinfo)
1020 {
1021 struct ath_hw *ah = sc->sc_ah;
1022 int error = 0;
1023 struct ath9k_tx_queue_info qi;
1024
1025 if (qnum == sc->beacon.beaconq) {
1026 /*
1027 * XXX: for beacon queue, we just save the parameter.
1028 * It will be picked up by ath_beaconq_config when
1029 * it's necessary.
1030 */
1031 sc->beacon.beacon_qi = *qinfo;
1032 return 0;
1033 }
1034
1035 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1036
1037 ath9k_hw_get_txq_props(ah, qnum, &qi);
1038 qi.tqi_aifs = qinfo->tqi_aifs;
1039 qi.tqi_cwmin = qinfo->tqi_cwmin;
1040 qi.tqi_cwmax = qinfo->tqi_cwmax;
1041 qi.tqi_burstTime = qinfo->tqi_burstTime;
1042 qi.tqi_readyTime = qinfo->tqi_readyTime;
1043
1044 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1045 ath_err(ath9k_hw_common(sc->sc_ah),
1046 "Unable to update hardware queue %u!\n", qnum);
1047 error = -EIO;
1048 } else {
1049 ath9k_hw_resettxqueue(ah, qnum);
1050 }
1051
1052 return error;
1053 }
1054
1055 int ath_cabq_update(struct ath_softc *sc)
1056 {
1057 struct ath9k_tx_queue_info qi;
1058 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1059 int qnum = sc->beacon.cabq->axq_qnum;
1060
1061 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1062 /*
1063 * Ensure the readytime % is within the bounds.
1064 */
1065 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1066 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1067 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1068 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1069
1070 qi.tqi_readyTime = (cur_conf->beacon_interval *
1071 sc->config.cabqReadytime) / 100;
1072 ath_txq_update(sc, qnum, &qi);
1073
1074 return 0;
1075 }
1076
1077 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
1078 {
1079 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
1080 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1081 }
1082
1083 /*
1084 * Drain a given TX queue (could be Beacon or Data)
1085 *
1086 * This assumes output has been stopped and
1087 * we do not need to block ath_tx_tasklet.
1088 */
1089 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1090 {
1091 struct ath_buf *bf, *lastbf;
1092 struct list_head bf_head;
1093 struct ath_tx_status ts;
1094
1095 memset(&ts, 0, sizeof(ts));
1096 INIT_LIST_HEAD(&bf_head);
1097
1098 for (;;) {
1099 spin_lock_bh(&txq->axq_lock);
1100
1101 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1102 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
1103 txq->txq_headidx = txq->txq_tailidx = 0;
1104 spin_unlock_bh(&txq->axq_lock);
1105 break;
1106 } else {
1107 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
1108 struct ath_buf, list);
1109 }
1110 } else {
1111 if (list_empty(&txq->axq_q)) {
1112 txq->axq_link = NULL;
1113 spin_unlock_bh(&txq->axq_lock);
1114 break;
1115 }
1116 bf = list_first_entry(&txq->axq_q, struct ath_buf,
1117 list);
1118
1119 if (bf->bf_stale) {
1120 list_del(&bf->list);
1121 spin_unlock_bh(&txq->axq_lock);
1122
1123 ath_tx_return_buffer(sc, bf);
1124 continue;
1125 }
1126 }
1127
1128 lastbf = bf->bf_lastbf;
1129
1130 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1131 list_cut_position(&bf_head,
1132 &txq->txq_fifo[txq->txq_tailidx],
1133 &lastbf->list);
1134 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
1135 } else {
1136 /* remove ath_buf's of the same mpdu from txq */
1137 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1138 }
1139
1140 txq->axq_depth--;
1141 if (bf_is_ampdu_not_probing(bf))
1142 txq->axq_ampdu_depth--;
1143 spin_unlock_bh(&txq->axq_lock);
1144
1145 if (bf_isampdu(bf))
1146 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1147 retry_tx);
1148 else
1149 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1150 }
1151
1152 spin_lock_bh(&txq->axq_lock);
1153 txq->axq_tx_inprogress = false;
1154 spin_unlock_bh(&txq->axq_lock);
1155
1156 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1157 spin_lock_bh(&txq->axq_lock);
1158 while (!list_empty(&txq->txq_fifo_pending)) {
1159 bf = list_first_entry(&txq->txq_fifo_pending,
1160 struct ath_buf, list);
1161 list_cut_position(&bf_head,
1162 &txq->txq_fifo_pending,
1163 &bf->bf_lastbf->list);
1164 spin_unlock_bh(&txq->axq_lock);
1165
1166 if (bf_isampdu(bf))
1167 ath_tx_complete_aggr(sc, txq, bf, &bf_head,
1168 &ts, 0, retry_tx);
1169 else
1170 ath_tx_complete_buf(sc, bf, txq, &bf_head,
1171 &ts, 0, 0);
1172 spin_lock_bh(&txq->axq_lock);
1173 }
1174 spin_unlock_bh(&txq->axq_lock);
1175 }
1176
1177 /* flush any pending frames if aggregation is enabled */
1178 if (sc->sc_flags & SC_OP_TXAGGR) {
1179 if (!retry_tx) {
1180 spin_lock_bh(&txq->axq_lock);
1181 ath_txq_drain_pending_buffers(sc, txq);
1182 spin_unlock_bh(&txq->axq_lock);
1183 }
1184 }
1185 }
1186
1187 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1188 {
1189 struct ath_hw *ah = sc->sc_ah;
1190 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1191 struct ath_txq *txq;
1192 int i, npend = 0;
1193
1194 if (sc->sc_flags & SC_OP_INVALID)
1195 return true;
1196
1197 ath9k_hw_abort_tx_dma(ah);
1198
1199 /* Check if any queue remains active */
1200 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1201 if (!ATH_TXQ_SETUP(sc, i))
1202 continue;
1203
1204 npend += ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum);
1205 }
1206
1207 if (npend)
1208 ath_err(common, "Failed to stop TX DMA!\n");
1209
1210 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1211 if (!ATH_TXQ_SETUP(sc, i))
1212 continue;
1213
1214 /*
1215 * The caller will resume queues with ieee80211_wake_queues.
1216 * Mark the queue as not stopped to prevent ath_tx_complete
1217 * from waking the queue too early.
1218 */
1219 txq = &sc->tx.txq[i];
1220 txq->stopped = false;
1221 ath_draintxq(sc, txq, retry_tx);
1222 }
1223
1224 return !npend;
1225 }
1226
1227 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1228 {
1229 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1230 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1231 }
1232
1233 /* For each axq_acq entry, for each tid, try to schedule packets
1234 * for transmit until ampdu_depth has reached min Q depth.
1235 */
1236 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1237 {
1238 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1239 struct ath_atx_tid *tid, *last_tid;
1240
1241 if (list_empty(&txq->axq_acq) ||
1242 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1243 return;
1244
1245 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1246 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1247
1248 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1249 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1250 list_del(&ac->list);
1251 ac->sched = false;
1252
1253 while (!list_empty(&ac->tid_q)) {
1254 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1255 list);
1256 list_del(&tid->list);
1257 tid->sched = false;
1258
1259 if (tid->paused)
1260 continue;
1261
1262 ath_tx_sched_aggr(sc, txq, tid);
1263
1264 /*
1265 * add tid to round-robin queue if more frames
1266 * are pending for the tid
1267 */
1268 if (!list_empty(&tid->buf_q))
1269 ath_tx_queue_tid(txq, tid);
1270
1271 if (tid == last_tid ||
1272 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1273 break;
1274 }
1275
1276 if (!list_empty(&ac->tid_q)) {
1277 if (!ac->sched) {
1278 ac->sched = true;
1279 list_add_tail(&ac->list, &txq->axq_acq);
1280 }
1281 }
1282
1283 if (ac == last_ac ||
1284 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1285 return;
1286 }
1287 }
1288
1289 /***********/
1290 /* TX, DMA */
1291 /***********/
1292
1293 /*
1294 * Insert a chain of ath_buf (descriptors) on a txq and
1295 * assume the descriptors are already chained together by caller.
1296 */
1297 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1298 struct list_head *head)
1299 {
1300 struct ath_hw *ah = sc->sc_ah;
1301 struct ath_common *common = ath9k_hw_common(ah);
1302 struct ath_buf *bf;
1303
1304 /*
1305 * Insert the frame on the outbound list and
1306 * pass it on to the hardware.
1307 */
1308
1309 if (list_empty(head))
1310 return;
1311
1312 bf = list_first_entry(head, struct ath_buf, list);
1313
1314 ath_dbg(common, ATH_DBG_QUEUE,
1315 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1316
1317 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1318 if (txq->axq_depth >= ATH_TXFIFO_DEPTH) {
1319 list_splice_tail_init(head, &txq->txq_fifo_pending);
1320 return;
1321 }
1322 if (!list_empty(&txq->txq_fifo[txq->txq_headidx]))
1323 ath_dbg(common, ATH_DBG_XMIT,
1324 "Initializing tx fifo %d which is non-empty\n",
1325 txq->txq_headidx);
1326 INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]);
1327 list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]);
1328 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1329 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1330 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1331 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1332 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1333 } else {
1334 list_splice_tail_init(head, &txq->axq_q);
1335
1336 if (txq->axq_link == NULL) {
1337 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1338 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1339 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1340 txq->axq_qnum, ito64(bf->bf_daddr),
1341 bf->bf_desc);
1342 } else {
1343 *txq->axq_link = bf->bf_daddr;
1344 ath_dbg(common, ATH_DBG_XMIT,
1345 "link[%u] (%p)=%llx (%p)\n",
1346 txq->axq_qnum, txq->axq_link,
1347 ito64(bf->bf_daddr), bf->bf_desc);
1348 }
1349 ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc,
1350 &txq->axq_link);
1351 TX_STAT_INC(txq->axq_qnum, txstart);
1352 ath9k_hw_txstart(ah, txq->axq_qnum);
1353 }
1354 txq->axq_depth++;
1355 if (bf_is_ampdu_not_probing(bf))
1356 txq->axq_ampdu_depth++;
1357 }
1358
1359 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1360 struct ath_buf *bf, struct ath_tx_control *txctl)
1361 {
1362 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1363 struct list_head bf_head;
1364
1365 bf->bf_state.bf_type |= BUF_AMPDU;
1366
1367 /*
1368 * Do not queue to h/w when any of the following conditions is true:
1369 * - there are pending frames in software queue
1370 * - the TID is currently paused for ADDBA/BAR request
1371 * - seqno is not within block-ack window
1372 * - h/w queue depth exceeds low water mark
1373 */
1374 if (!list_empty(&tid->buf_q) || tid->paused ||
1375 !BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno) ||
1376 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1377 /*
1378 * Add this frame to software queue for scheduling later
1379 * for aggregation.
1380 */
1381 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
1382 list_add_tail(&bf->list, &tid->buf_q);
1383 ath_tx_queue_tid(txctl->txq, tid);
1384 return;
1385 }
1386
1387 INIT_LIST_HEAD(&bf_head);
1388 list_add(&bf->list, &bf_head);
1389
1390 /* Add sub-frame to BAW */
1391 if (!fi->retries)
1392 ath_tx_addto_baw(sc, tid, fi->seqno);
1393
1394 /* Queue to h/w without aggregation */
1395 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1396 bf->bf_lastbf = bf;
1397 ath_buf_set_rate(sc, bf, fi->framelen);
1398 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head);
1399 }
1400
1401 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1402 struct ath_atx_tid *tid,
1403 struct list_head *bf_head)
1404 {
1405 struct ath_frame_info *fi;
1406 struct ath_buf *bf;
1407
1408 bf = list_first_entry(bf_head, struct ath_buf, list);
1409 bf->bf_state.bf_type &= ~BUF_AMPDU;
1410
1411 /* update starting sequence number for subsequent ADDBA request */
1412 if (tid)
1413 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1414
1415 bf->bf_lastbf = bf;
1416 fi = get_frame_info(bf->bf_mpdu);
1417 ath_buf_set_rate(sc, bf, fi->framelen);
1418 ath_tx_txqaddbuf(sc, txq, bf_head);
1419 TX_STAT_INC(txq->axq_qnum, queued);
1420 }
1421
1422 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1423 {
1424 struct ieee80211_hdr *hdr;
1425 enum ath9k_pkt_type htype;
1426 __le16 fc;
1427
1428 hdr = (struct ieee80211_hdr *)skb->data;
1429 fc = hdr->frame_control;
1430
1431 if (ieee80211_is_beacon(fc))
1432 htype = ATH9K_PKT_TYPE_BEACON;
1433 else if (ieee80211_is_probe_resp(fc))
1434 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1435 else if (ieee80211_is_atim(fc))
1436 htype = ATH9K_PKT_TYPE_ATIM;
1437 else if (ieee80211_is_pspoll(fc))
1438 htype = ATH9K_PKT_TYPE_PSPOLL;
1439 else
1440 htype = ATH9K_PKT_TYPE_NORMAL;
1441
1442 return htype;
1443 }
1444
1445 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1446 int framelen)
1447 {
1448 struct ath_softc *sc = hw->priv;
1449 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1450 struct ieee80211_sta *sta = tx_info->control.sta;
1451 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1452 struct ieee80211_hdr *hdr;
1453 struct ath_frame_info *fi = get_frame_info(skb);
1454 struct ath_node *an;
1455 struct ath_atx_tid *tid;
1456 enum ath9k_key_type keytype;
1457 u16 seqno = 0;
1458 u8 tidno;
1459
1460 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1461
1462 hdr = (struct ieee80211_hdr *)skb->data;
1463 if (sta && ieee80211_is_data_qos(hdr->frame_control) &&
1464 conf_is_ht(&hw->conf) && (sc->sc_flags & SC_OP_TXAGGR)) {
1465
1466 an = (struct ath_node *) sta->drv_priv;
1467 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
1468
1469 /*
1470 * Override seqno set by upper layer with the one
1471 * in tx aggregation state.
1472 */
1473 tid = ATH_AN_2_TID(an, tidno);
1474 seqno = tid->seq_next;
1475 hdr->seq_ctrl = cpu_to_le16(seqno << IEEE80211_SEQ_SEQ_SHIFT);
1476 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1477 }
1478
1479 memset(fi, 0, sizeof(*fi));
1480 if (hw_key)
1481 fi->keyix = hw_key->hw_key_idx;
1482 else
1483 fi->keyix = ATH9K_TXKEYIX_INVALID;
1484 fi->keytype = keytype;
1485 fi->framelen = framelen;
1486 fi->seqno = seqno;
1487 }
1488
1489 static int setup_tx_flags(struct sk_buff *skb)
1490 {
1491 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1492 int flags = 0;
1493
1494 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1495 flags |= ATH9K_TXDESC_INTREQ;
1496
1497 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1498 flags |= ATH9K_TXDESC_NOACK;
1499
1500 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1501 flags |= ATH9K_TXDESC_LDPC;
1502
1503 return flags;
1504 }
1505
1506 /*
1507 * rix - rate index
1508 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1509 * width - 0 for 20 MHz, 1 for 40 MHz
1510 * half_gi - to use 4us v/s 3.6 us for symbol time
1511 */
1512 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1513 int width, int half_gi, bool shortPreamble)
1514 {
1515 u32 nbits, nsymbits, duration, nsymbols;
1516 int streams;
1517
1518 /* find number of symbols: PLCP + data */
1519 streams = HT_RC_2_STREAMS(rix);
1520 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1521 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1522 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1523
1524 if (!half_gi)
1525 duration = SYMBOL_TIME(nsymbols);
1526 else
1527 duration = SYMBOL_TIME_HALFGI(nsymbols);
1528
1529 /* addup duration for legacy/ht training and signal fields */
1530 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1531
1532 return duration;
1533 }
1534
1535 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1536 {
1537 struct ath_hw *ah = sc->sc_ah;
1538 struct ath9k_channel *curchan = ah->curchan;
1539 if ((sc->sc_flags & SC_OP_ENABLE_APM) &&
1540 (curchan->channelFlags & CHANNEL_5GHZ) &&
1541 (chainmask == 0x7) && (rate < 0x90))
1542 return 0x3;
1543 else
1544 return chainmask;
1545 }
1546
1547 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len)
1548 {
1549 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1550 struct ath9k_11n_rate_series series[4];
1551 struct sk_buff *skb;
1552 struct ieee80211_tx_info *tx_info;
1553 struct ieee80211_tx_rate *rates;
1554 const struct ieee80211_rate *rate;
1555 struct ieee80211_hdr *hdr;
1556 int i, flags = 0;
1557 u8 rix = 0, ctsrate = 0;
1558 bool is_pspoll;
1559
1560 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1561
1562 skb = bf->bf_mpdu;
1563 tx_info = IEEE80211_SKB_CB(skb);
1564 rates = tx_info->control.rates;
1565 hdr = (struct ieee80211_hdr *)skb->data;
1566 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1567
1568 /*
1569 * We check if Short Preamble is needed for the CTS rate by
1570 * checking the BSS's global flag.
1571 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1572 */
1573 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
1574 ctsrate = rate->hw_value;
1575 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1576 ctsrate |= rate->hw_value_short;
1577
1578 for (i = 0; i < 4; i++) {
1579 bool is_40, is_sgi, is_sp;
1580 int phy;
1581
1582 if (!rates[i].count || (rates[i].idx < 0))
1583 continue;
1584
1585 rix = rates[i].idx;
1586 series[i].Tries = rates[i].count;
1587
1588 if ((sc->config.ath_aggr_prot && bf_isaggr(bf)) ||
1589 (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)) {
1590 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1591 flags |= ATH9K_TXDESC_RTSENA;
1592 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1593 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1594 flags |= ATH9K_TXDESC_CTSENA;
1595 }
1596
1597 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1598 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1599 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1600 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1601
1602 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1603 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1604 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1605
1606 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1607 /* MCS rates */
1608 series[i].Rate = rix | 0x80;
1609 series[i].ChSel = ath_txchainmask_reduction(sc,
1610 common->tx_chainmask, series[i].Rate);
1611 series[i].PktDuration = ath_pkt_duration(sc, rix, len,
1612 is_40, is_sgi, is_sp);
1613 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1614 series[i].RateFlags |= ATH9K_RATESERIES_STBC;
1615 continue;
1616 }
1617
1618 /* legacy rates */
1619 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1620 !(rate->flags & IEEE80211_RATE_ERP_G))
1621 phy = WLAN_RC_PHY_CCK;
1622 else
1623 phy = WLAN_RC_PHY_OFDM;
1624
1625 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1626 series[i].Rate = rate->hw_value;
1627 if (rate->hw_value_short) {
1628 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1629 series[i].Rate |= rate->hw_value_short;
1630 } else {
1631 is_sp = false;
1632 }
1633
1634 if (bf->bf_state.bfs_paprd)
1635 series[i].ChSel = common->tx_chainmask;
1636 else
1637 series[i].ChSel = ath_txchainmask_reduction(sc,
1638 common->tx_chainmask, series[i].Rate);
1639
1640 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1641 phy, rate->bitrate * 100, len, rix, is_sp);
1642 }
1643
1644 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1645 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1646 flags &= ~ATH9K_TXDESC_RTSENA;
1647
1648 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1649 if (flags & ATH9K_TXDESC_RTSENA)
1650 flags &= ~ATH9K_TXDESC_CTSENA;
1651
1652 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1653 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1654 bf->bf_lastbf->bf_desc,
1655 !is_pspoll, ctsrate,
1656 0, series, 4, flags);
1657
1658 if (sc->config.ath_aggr_prot && flags)
1659 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1660 }
1661
1662 static struct ath_buf *ath_tx_setup_buffer(struct ieee80211_hw *hw,
1663 struct ath_txq *txq,
1664 struct sk_buff *skb)
1665 {
1666 struct ath_softc *sc = hw->priv;
1667 struct ath_hw *ah = sc->sc_ah;
1668 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1669 struct ath_frame_info *fi = get_frame_info(skb);
1670 struct ath_buf *bf;
1671 struct ath_desc *ds;
1672 int frm_type;
1673
1674 bf = ath_tx_get_buffer(sc);
1675 if (!bf) {
1676 ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
1677 return NULL;
1678 }
1679
1680 ATH_TXBUF_RESET(bf);
1681
1682 bf->bf_flags = setup_tx_flags(skb);
1683 bf->bf_mpdu = skb;
1684
1685 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1686 skb->len, DMA_TO_DEVICE);
1687 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1688 bf->bf_mpdu = NULL;
1689 bf->bf_buf_addr = 0;
1690 ath_err(ath9k_hw_common(sc->sc_ah),
1691 "dma_mapping_error() on TX\n");
1692 ath_tx_return_buffer(sc, bf);
1693 return NULL;
1694 }
1695
1696 frm_type = get_hw_packet_type(skb);
1697
1698 ds = bf->bf_desc;
1699 ath9k_hw_set_desc_link(ah, ds, 0);
1700
1701 ath9k_hw_set11n_txdesc(ah, ds, fi->framelen, frm_type, MAX_RATE_POWER,
1702 fi->keyix, fi->keytype, bf->bf_flags);
1703
1704 ath9k_hw_filltxdesc(ah, ds,
1705 skb->len, /* segment length */
1706 true, /* first segment */
1707 true, /* last segment */
1708 ds, /* first descriptor */
1709 bf->bf_buf_addr,
1710 txq->axq_qnum);
1711
1712
1713 return bf;
1714 }
1715
1716 /* FIXME: tx power */
1717 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1718 struct ath_tx_control *txctl)
1719 {
1720 struct sk_buff *skb = bf->bf_mpdu;
1721 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1722 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1723 struct list_head bf_head;
1724 struct ath_atx_tid *tid = NULL;
1725 u8 tidno;
1726
1727 spin_lock_bh(&txctl->txq->axq_lock);
1728 if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an &&
1729 ieee80211_is_data_qos(hdr->frame_control)) {
1730 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1731 IEEE80211_QOS_CTL_TID_MASK;
1732 tid = ATH_AN_2_TID(txctl->an, tidno);
1733
1734 WARN_ON(tid->ac->txq != txctl->txq);
1735 }
1736
1737 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1738 /*
1739 * Try aggregation if it's a unicast data frame
1740 * and the destination is HT capable.
1741 */
1742 ath_tx_send_ampdu(sc, tid, bf, txctl);
1743 } else {
1744 INIT_LIST_HEAD(&bf_head);
1745 list_add_tail(&bf->list, &bf_head);
1746
1747 bf->bf_state.bfs_ftype = txctl->frame_type;
1748 bf->bf_state.bfs_paprd = txctl->paprd;
1749
1750 if (bf->bf_state.bfs_paprd)
1751 ar9003_hw_set_paprd_txdesc(sc->sc_ah, bf->bf_desc,
1752 bf->bf_state.bfs_paprd);
1753
1754 if (txctl->paprd)
1755 bf->bf_state.bfs_paprd_timestamp = jiffies;
1756
1757 ath_tx_send_normal(sc, txctl->txq, tid, &bf_head);
1758 }
1759
1760 spin_unlock_bh(&txctl->txq->axq_lock);
1761 }
1762
1763 /* Upon failure caller should free skb */
1764 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1765 struct ath_tx_control *txctl)
1766 {
1767 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1768 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1769 struct ieee80211_sta *sta = info->control.sta;
1770 struct ath_softc *sc = hw->priv;
1771 struct ath_txq *txq = txctl->txq;
1772 struct ath_buf *bf;
1773 int padpos, padsize;
1774 int frmlen = skb->len + FCS_LEN;
1775 int q;
1776
1777 /* NOTE: sta can be NULL according to net/mac80211.h */
1778 if (sta)
1779 txctl->an = (struct ath_node *)sta->drv_priv;
1780
1781 if (info->control.hw_key)
1782 frmlen += info->control.hw_key->icv_len;
1783
1784 /*
1785 * As a temporary workaround, assign seq# here; this will likely need
1786 * to be cleaned up to work better with Beacon transmission and virtual
1787 * BSSes.
1788 */
1789 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1790 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1791 sc->tx.seq_no += 0x10;
1792 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1793 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1794 }
1795
1796 /* Add the padding after the header if this is not already done */
1797 padpos = ath9k_cmn_padpos(hdr->frame_control);
1798 padsize = padpos & 3;
1799 if (padsize && skb->len > padpos) {
1800 if (skb_headroom(skb) < padsize)
1801 return -ENOMEM;
1802
1803 skb_push(skb, padsize);
1804 memmove(skb->data, skb->data + padsize, padpos);
1805 }
1806
1807 setup_frame_info(hw, skb, frmlen);
1808
1809 /*
1810 * At this point, the vif, hw_key and sta pointers in the tx control
1811 * info are no longer valid (overwritten by the ath_frame_info data.
1812 */
1813
1814 bf = ath_tx_setup_buffer(hw, txctl->txq, skb);
1815 if (unlikely(!bf))
1816 return -ENOMEM;
1817
1818 q = skb_get_queue_mapping(skb);
1819 spin_lock_bh(&txq->axq_lock);
1820 if (txq == sc->tx.txq_map[q] &&
1821 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1822 ieee80211_stop_queue(sc->hw, q);
1823 txq->stopped = 1;
1824 }
1825 spin_unlock_bh(&txq->axq_lock);
1826
1827 ath_tx_start_dma(sc, bf, txctl);
1828
1829 return 0;
1830 }
1831
1832 /*****************/
1833 /* TX Completion */
1834 /*****************/
1835
1836 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1837 int tx_flags, int ftype, struct ath_txq *txq)
1838 {
1839 struct ieee80211_hw *hw = sc->hw;
1840 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1841 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1842 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1843 int q, padpos, padsize;
1844
1845 ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1846
1847 if (tx_flags & ATH_TX_BAR)
1848 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1849
1850 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1851 /* Frame was ACKed */
1852 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1853 }
1854
1855 padpos = ath9k_cmn_padpos(hdr->frame_control);
1856 padsize = padpos & 3;
1857 if (padsize && skb->len>padpos+padsize) {
1858 /*
1859 * Remove MAC header padding before giving the frame back to
1860 * mac80211.
1861 */
1862 memmove(skb->data + padsize, skb->data, padpos);
1863 skb_pull(skb, padsize);
1864 }
1865
1866 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1867 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1868 ath_dbg(common, ATH_DBG_PS,
1869 "Going back to sleep after having received TX status (0x%lx)\n",
1870 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1871 PS_WAIT_FOR_CAB |
1872 PS_WAIT_FOR_PSPOLL_DATA |
1873 PS_WAIT_FOR_TX_ACK));
1874 }
1875
1876 q = skb_get_queue_mapping(skb);
1877 if (txq == sc->tx.txq_map[q]) {
1878 spin_lock_bh(&txq->axq_lock);
1879 if (WARN_ON(--txq->pending_frames < 0))
1880 txq->pending_frames = 0;
1881
1882 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
1883 ieee80211_wake_queue(sc->hw, q);
1884 txq->stopped = 0;
1885 }
1886 spin_unlock_bh(&txq->axq_lock);
1887 }
1888
1889 ieee80211_tx_status(hw, skb);
1890 }
1891
1892 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1893 struct ath_txq *txq, struct list_head *bf_q,
1894 struct ath_tx_status *ts, int txok, int sendbar)
1895 {
1896 struct sk_buff *skb = bf->bf_mpdu;
1897 unsigned long flags;
1898 int tx_flags = 0;
1899
1900 if (sendbar)
1901 tx_flags = ATH_TX_BAR;
1902
1903 if (!txok) {
1904 tx_flags |= ATH_TX_ERROR;
1905
1906 if (bf_isxretried(bf))
1907 tx_flags |= ATH_TX_XRETRY;
1908 }
1909
1910 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
1911 bf->bf_buf_addr = 0;
1912
1913 if (bf->bf_state.bfs_paprd) {
1914 if (time_after(jiffies,
1915 bf->bf_state.bfs_paprd_timestamp +
1916 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
1917 dev_kfree_skb_any(skb);
1918 else
1919 complete(&sc->paprd_complete);
1920 } else {
1921 ath_debug_stat_tx(sc, bf, ts, txq);
1922 ath_tx_complete(sc, skb, tx_flags,
1923 bf->bf_state.bfs_ftype, txq);
1924 }
1925 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
1926 * accidentally reference it later.
1927 */
1928 bf->bf_mpdu = NULL;
1929
1930 /*
1931 * Return the list of ath_buf of this mpdu to free queue
1932 */
1933 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1934 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1935 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1936 }
1937
1938 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
1939 struct ath_tx_status *ts, int nframes, int nbad,
1940 int txok, bool update_rc)
1941 {
1942 struct sk_buff *skb = bf->bf_mpdu;
1943 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1944 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1945 struct ieee80211_hw *hw = sc->hw;
1946 struct ath_hw *ah = sc->sc_ah;
1947 u8 i, tx_rateindex;
1948
1949 if (txok)
1950 tx_info->status.ack_signal = ts->ts_rssi;
1951
1952 tx_rateindex = ts->ts_rateindex;
1953 WARN_ON(tx_rateindex >= hw->max_rates);
1954
1955 if (ts->ts_status & ATH9K_TXERR_FILT)
1956 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1957 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) {
1958 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
1959
1960 BUG_ON(nbad > nframes);
1961
1962 tx_info->status.ampdu_len = nframes;
1963 tx_info->status.ampdu_ack_len = nframes - nbad;
1964 }
1965
1966 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
1967 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
1968 /*
1969 * If an underrun error is seen assume it as an excessive
1970 * retry only if max frame trigger level has been reached
1971 * (2 KB for single stream, and 4 KB for dual stream).
1972 * Adjust the long retry as if the frame was tried
1973 * hw->max_rate_tries times to affect how rate control updates
1974 * PER for the failed rate.
1975 * In case of congestion on the bus penalizing this type of
1976 * underruns should help hardware actually transmit new frames
1977 * successfully by eventually preferring slower rates.
1978 * This itself should also alleviate congestion on the bus.
1979 */
1980 if (ieee80211_is_data(hdr->frame_control) &&
1981 (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
1982 ATH9K_TX_DELIM_UNDERRUN)) &&
1983 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
1984 tx_info->status.rates[tx_rateindex].count =
1985 hw->max_rate_tries;
1986 }
1987
1988 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
1989 tx_info->status.rates[i].count = 0;
1990 tx_info->status.rates[i].idx = -1;
1991 }
1992
1993 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
1994 }
1995
1996 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1997 {
1998 struct ath_hw *ah = sc->sc_ah;
1999 struct ath_common *common = ath9k_hw_common(ah);
2000 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2001 struct list_head bf_head;
2002 struct ath_desc *ds;
2003 struct ath_tx_status ts;
2004 int txok;
2005 int status;
2006
2007 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2008 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2009 txq->axq_link);
2010
2011 for (;;) {
2012 spin_lock_bh(&txq->axq_lock);
2013 if (list_empty(&txq->axq_q)) {
2014 txq->axq_link = NULL;
2015 if (sc->sc_flags & SC_OP_TXAGGR)
2016 ath_txq_schedule(sc, txq);
2017 spin_unlock_bh(&txq->axq_lock);
2018 break;
2019 }
2020 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2021
2022 /*
2023 * There is a race condition that a BH gets scheduled
2024 * after sw writes TxE and before hw re-load the last
2025 * descriptor to get the newly chained one.
2026 * Software must keep the last DONE descriptor as a
2027 * holding descriptor - software does so by marking
2028 * it with the STALE flag.
2029 */
2030 bf_held = NULL;
2031 if (bf->bf_stale) {
2032 bf_held = bf;
2033 if (list_is_last(&bf_held->list, &txq->axq_q)) {
2034 spin_unlock_bh(&txq->axq_lock);
2035 break;
2036 } else {
2037 bf = list_entry(bf_held->list.next,
2038 struct ath_buf, list);
2039 }
2040 }
2041
2042 lastbf = bf->bf_lastbf;
2043 ds = lastbf->bf_desc;
2044
2045 memset(&ts, 0, sizeof(ts));
2046 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2047 if (status == -EINPROGRESS) {
2048 spin_unlock_bh(&txq->axq_lock);
2049 break;
2050 }
2051 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2052
2053 /*
2054 * Remove ath_buf's of the same transmit unit from txq,
2055 * however leave the last descriptor back as the holding
2056 * descriptor for hw.
2057 */
2058 lastbf->bf_stale = true;
2059 INIT_LIST_HEAD(&bf_head);
2060 if (!list_is_singular(&lastbf->list))
2061 list_cut_position(&bf_head,
2062 &txq->axq_q, lastbf->list.prev);
2063
2064 txq->axq_depth--;
2065 txok = !(ts.ts_status & ATH9K_TXERR_MASK);
2066 txq->axq_tx_inprogress = false;
2067 if (bf_held)
2068 list_del(&bf_held->list);
2069
2070 if (bf_is_ampdu_not_probing(bf))
2071 txq->axq_ampdu_depth--;
2072
2073 spin_unlock_bh(&txq->axq_lock);
2074
2075 if (bf_held)
2076 ath_tx_return_buffer(sc, bf_held);
2077
2078 if (!bf_isampdu(bf)) {
2079 /*
2080 * This frame is sent out as a single frame.
2081 * Use hardware retry status for this frame.
2082 */
2083 if (ts.ts_status & ATH9K_TXERR_XRETRY)
2084 bf->bf_state.bf_type |= BUF_XRETRY;
2085 ath_tx_rc_status(sc, bf, &ts, 1, txok ? 0 : 1, txok, true);
2086 }
2087
2088 if (bf_isampdu(bf))
2089 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok,
2090 true);
2091 else
2092 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, txok, 0);
2093
2094 spin_lock_bh(&txq->axq_lock);
2095
2096 if (sc->sc_flags & SC_OP_TXAGGR)
2097 ath_txq_schedule(sc, txq);
2098 spin_unlock_bh(&txq->axq_lock);
2099 }
2100 }
2101
2102 static void ath_hw_pll_work(struct work_struct *work)
2103 {
2104 struct ath_softc *sc = container_of(work, struct ath_softc,
2105 hw_pll_work.work);
2106 static int count;
2107
2108 if (AR_SREV_9485(sc->sc_ah)) {
2109 if (ar9003_get_pll_sqsum_dvc(sc->sc_ah) >= 0x40000) {
2110 count++;
2111
2112 if (count == 3) {
2113 /* Rx is hung for more than 500ms. Reset it */
2114 ath_reset(sc, true);
2115 count = 0;
2116 }
2117 } else
2118 count = 0;
2119
2120 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
2121 }
2122 }
2123
2124 static void ath_tx_complete_poll_work(struct work_struct *work)
2125 {
2126 struct ath_softc *sc = container_of(work, struct ath_softc,
2127 tx_complete_work.work);
2128 struct ath_txq *txq;
2129 int i;
2130 bool needreset = false;
2131 #ifdef CONFIG_ATH9K_DEBUGFS
2132 sc->tx_complete_poll_work_seen++;
2133 #endif
2134
2135 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2136 if (ATH_TXQ_SETUP(sc, i)) {
2137 txq = &sc->tx.txq[i];
2138 spin_lock_bh(&txq->axq_lock);
2139 if (txq->axq_depth) {
2140 if (txq->axq_tx_inprogress) {
2141 needreset = true;
2142 spin_unlock_bh(&txq->axq_lock);
2143 break;
2144 } else {
2145 txq->axq_tx_inprogress = true;
2146 }
2147 }
2148 spin_unlock_bh(&txq->axq_lock);
2149 }
2150
2151 if (needreset) {
2152 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2153 "tx hung, resetting the chip\n");
2154 ath_reset(sc, true);
2155 }
2156
2157 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2158 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2159 }
2160
2161
2162
2163 void ath_tx_tasklet(struct ath_softc *sc)
2164 {
2165 int i;
2166 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2167
2168 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2169
2170 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2171 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2172 ath_tx_processq(sc, &sc->tx.txq[i]);
2173 }
2174 }
2175
2176 void ath_tx_edma_tasklet(struct ath_softc *sc)
2177 {
2178 struct ath_tx_status txs;
2179 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2180 struct ath_hw *ah = sc->sc_ah;
2181 struct ath_txq *txq;
2182 struct ath_buf *bf, *lastbf;
2183 struct list_head bf_head;
2184 int status;
2185 int txok;
2186
2187 for (;;) {
2188 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&txs);
2189 if (status == -EINPROGRESS)
2190 break;
2191 if (status == -EIO) {
2192 ath_dbg(common, ATH_DBG_XMIT,
2193 "Error processing tx status\n");
2194 break;
2195 }
2196
2197 /* Skip beacon completions */
2198 if (txs.qid == sc->beacon.beaconq)
2199 continue;
2200
2201 txq = &sc->tx.txq[txs.qid];
2202
2203 spin_lock_bh(&txq->axq_lock);
2204 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2205 spin_unlock_bh(&txq->axq_lock);
2206 return;
2207 }
2208
2209 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2210 struct ath_buf, list);
2211 lastbf = bf->bf_lastbf;
2212
2213 INIT_LIST_HEAD(&bf_head);
2214 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2215 &lastbf->list);
2216 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2217 txq->axq_depth--;
2218 txq->axq_tx_inprogress = false;
2219 if (bf_is_ampdu_not_probing(bf))
2220 txq->axq_ampdu_depth--;
2221 spin_unlock_bh(&txq->axq_lock);
2222
2223 txok = !(txs.ts_status & ATH9K_TXERR_MASK);
2224
2225 if (!bf_isampdu(bf)) {
2226 if (txs.ts_status & ATH9K_TXERR_XRETRY)
2227 bf->bf_state.bf_type |= BUF_XRETRY;
2228 ath_tx_rc_status(sc, bf, &txs, 1, txok ? 0 : 1, txok, true);
2229 }
2230
2231 if (bf_isampdu(bf))
2232 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs,
2233 txok, true);
2234 else
2235 ath_tx_complete_buf(sc, bf, txq, &bf_head,
2236 &txs, txok, 0);
2237
2238 spin_lock_bh(&txq->axq_lock);
2239
2240 if (!list_empty(&txq->txq_fifo_pending)) {
2241 INIT_LIST_HEAD(&bf_head);
2242 bf = list_first_entry(&txq->txq_fifo_pending,
2243 struct ath_buf, list);
2244 list_cut_position(&bf_head,
2245 &txq->txq_fifo_pending,
2246 &bf->bf_lastbf->list);
2247 ath_tx_txqaddbuf(sc, txq, &bf_head);
2248 } else if (sc->sc_flags & SC_OP_TXAGGR)
2249 ath_txq_schedule(sc, txq);
2250
2251 spin_unlock_bh(&txq->axq_lock);
2252 }
2253 }
2254
2255 /*****************/
2256 /* Init, Cleanup */
2257 /*****************/
2258
2259 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2260 {
2261 struct ath_descdma *dd = &sc->txsdma;
2262 u8 txs_len = sc->sc_ah->caps.txs_len;
2263
2264 dd->dd_desc_len = size * txs_len;
2265 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2266 &dd->dd_desc_paddr, GFP_KERNEL);
2267 if (!dd->dd_desc)
2268 return -ENOMEM;
2269
2270 return 0;
2271 }
2272
2273 static int ath_tx_edma_init(struct ath_softc *sc)
2274 {
2275 int err;
2276
2277 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2278 if (!err)
2279 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2280 sc->txsdma.dd_desc_paddr,
2281 ATH_TXSTATUS_RING_SIZE);
2282
2283 return err;
2284 }
2285
2286 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2287 {
2288 struct ath_descdma *dd = &sc->txsdma;
2289
2290 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2291 dd->dd_desc_paddr);
2292 }
2293
2294 int ath_tx_init(struct ath_softc *sc, int nbufs)
2295 {
2296 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2297 int error = 0;
2298
2299 spin_lock_init(&sc->tx.txbuflock);
2300
2301 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2302 "tx", nbufs, 1, 1);
2303 if (error != 0) {
2304 ath_err(common,
2305 "Failed to allocate tx descriptors: %d\n", error);
2306 goto err;
2307 }
2308
2309 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2310 "beacon", ATH_BCBUF, 1, 1);
2311 if (error != 0) {
2312 ath_err(common,
2313 "Failed to allocate beacon descriptors: %d\n", error);
2314 goto err;
2315 }
2316
2317 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2318 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
2319
2320 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2321 error = ath_tx_edma_init(sc);
2322 if (error)
2323 goto err;
2324 }
2325
2326 err:
2327 if (error != 0)
2328 ath_tx_cleanup(sc);
2329
2330 return error;
2331 }
2332
2333 void ath_tx_cleanup(struct ath_softc *sc)
2334 {
2335 if (sc->beacon.bdma.dd_desc_len != 0)
2336 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2337
2338 if (sc->tx.txdma.dd_desc_len != 0)
2339 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2340
2341 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2342 ath_tx_edma_cleanup(sc);
2343 }
2344
2345 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2346 {
2347 struct ath_atx_tid *tid;
2348 struct ath_atx_ac *ac;
2349 int tidno, acno;
2350
2351 for (tidno = 0, tid = &an->tid[tidno];
2352 tidno < WME_NUM_TID;
2353 tidno++, tid++) {
2354 tid->an = an;
2355 tid->tidno = tidno;
2356 tid->seq_start = tid->seq_next = 0;
2357 tid->baw_size = WME_MAX_BA;
2358 tid->baw_head = tid->baw_tail = 0;
2359 tid->sched = false;
2360 tid->paused = false;
2361 tid->state &= ~AGGR_CLEANUP;
2362 INIT_LIST_HEAD(&tid->buf_q);
2363 acno = TID_TO_WME_AC(tidno);
2364 tid->ac = &an->ac[acno];
2365 tid->state &= ~AGGR_ADDBA_COMPLETE;
2366 tid->state &= ~AGGR_ADDBA_PROGRESS;
2367 }
2368
2369 for (acno = 0, ac = &an->ac[acno];
2370 acno < WME_NUM_AC; acno++, ac++) {
2371 ac->sched = false;
2372 ac->txq = sc->tx.txq_map[acno];
2373 INIT_LIST_HEAD(&ac->tid_q);
2374 }
2375 }
2376
2377 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2378 {
2379 struct ath_atx_ac *ac;
2380 struct ath_atx_tid *tid;
2381 struct ath_txq *txq;
2382 int tidno;
2383
2384 for (tidno = 0, tid = &an->tid[tidno];
2385 tidno < WME_NUM_TID; tidno++, tid++) {
2386
2387 ac = tid->ac;
2388 txq = ac->txq;
2389
2390 spin_lock_bh(&txq->axq_lock);
2391
2392 if (tid->sched) {
2393 list_del(&tid->list);
2394 tid->sched = false;
2395 }
2396
2397 if (ac->sched) {
2398 list_del(&ac->list);
2399 tid->ac->sched = false;
2400 }
2401
2402 ath_tid_drain(sc, txq, tid);
2403 tid->state &= ~AGGR_ADDBA_COMPLETE;
2404 tid->state &= ~AGGR_CLEANUP;
2405
2406 spin_unlock_bh(&txq->axq_lock);
2407 }
2408 }
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