2 * Faraday FTGMAC100 Gigabit Ethernet
4 * (C) Copyright 2009-2011 Faraday Technology
5 * Po-Yu Chuang <ratbert@faraday-tech.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24 #include <linux/dma-mapping.h>
25 #include <linux/etherdevice.h>
26 #include <linux/ethtool.h>
27 #include <linux/interrupt.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
32 #include <linux/phy.h>
33 #include <linux/platform_device.h>
34 #include <linux/property.h>
38 #include "ftgmac100.h"
40 #define DRV_NAME "ftgmac100"
41 #define DRV_VERSION "0.7"
43 #define RX_QUEUE_ENTRIES 256 /* must be power of 2 */
44 #define TX_QUEUE_ENTRIES 512 /* must be power of 2 */
46 #define MAX_PKT_SIZE 1536
47 #define RX_BUF_SIZE MAX_PKT_SIZE /* must be smaller than 0x3fff */
49 struct ftgmac100_descs
{
50 struct ftgmac100_rxdes rxdes
[RX_QUEUE_ENTRIES
];
51 struct ftgmac100_txdes txdes
[TX_QUEUE_ENTRIES
];
59 struct ftgmac100_descs
*descs
;
60 dma_addr_t descs_dma_addr
;
63 struct sk_buff
*rx_skbs
[RX_QUEUE_ENTRIES
];
64 unsigned int rx_pointer
;
65 u32 rxdes0_edorr_mask
;
68 struct sk_buff
*tx_skbs
[TX_QUEUE_ENTRIES
];
69 unsigned int tx_clean_pointer
;
70 unsigned int tx_pointer
;
71 unsigned int tx_pending
;
72 u32 txdes0_edotr_mask
;
75 /* Scratch page to use when rx skb alloc fails */
77 dma_addr_t rx_scratch_dma
;
79 /* Component structures */
80 struct net_device
*netdev
;
82 struct ncsi_dev
*ndev
;
83 struct napi_struct napi
;
84 struct work_struct reset_task
;
85 struct mii_bus
*mii_bus
;
93 bool need_mac_restart
;
96 static void ftgmac100_set_rx_ring_base(struct ftgmac100
*priv
, dma_addr_t addr
)
98 iowrite32(addr
, priv
->base
+ FTGMAC100_OFFSET_RXR_BADR
);
101 static void ftgmac100_set_rx_buffer_size(struct ftgmac100
*priv
,
104 size
= FTGMAC100_RBSR_SIZE(size
);
105 iowrite32(size
, priv
->base
+ FTGMAC100_OFFSET_RBSR
);
108 static void ftgmac100_set_normal_prio_tx_ring_base(struct ftgmac100
*priv
,
111 iowrite32(addr
, priv
->base
+ FTGMAC100_OFFSET_NPTXR_BADR
);
114 static void ftgmac100_txdma_normal_prio_start_polling(struct ftgmac100
*priv
)
116 iowrite32(1, priv
->base
+ FTGMAC100_OFFSET_NPTXPD
);
119 static int ftgmac100_reset_mac(struct ftgmac100
*priv
, u32 maccr
)
121 struct net_device
*netdev
= priv
->netdev
;
124 /* NOTE: reset clears all registers */
125 iowrite32(maccr
, priv
->base
+ FTGMAC100_OFFSET_MACCR
);
126 iowrite32(maccr
| FTGMAC100_MACCR_SW_RST
,
127 priv
->base
+ FTGMAC100_OFFSET_MACCR
);
128 for (i
= 0; i
< 50; i
++) {
131 maccr
= ioread32(priv
->base
+ FTGMAC100_OFFSET_MACCR
);
132 if (!(maccr
& FTGMAC100_MACCR_SW_RST
))
138 netdev_err(netdev
, "Hardware reset failed\n");
142 static int ftgmac100_reset_and_config_mac(struct ftgmac100
*priv
)
146 switch (priv
->cur_speed
) {
148 case 0: /* no link */
152 maccr
|= FTGMAC100_MACCR_FAST_MODE
;
156 maccr
|= FTGMAC100_MACCR_GIGA_MODE
;
159 netdev_err(priv
->netdev
, "Unknown speed %d !\n",
164 /* (Re)initialize the queue pointers */
165 priv
->rx_pointer
= 0;
166 priv
->tx_clean_pointer
= 0;
167 priv
->tx_pointer
= 0;
168 priv
->tx_pending
= 0;
170 /* The doc says reset twice with 10us interval */
171 if (ftgmac100_reset_mac(priv
, maccr
))
173 usleep_range(10, 1000);
174 return ftgmac100_reset_mac(priv
, maccr
);
177 static void ftgmac100_set_mac(struct ftgmac100
*priv
, const unsigned char *mac
)
179 unsigned int maddr
= mac
[0] << 8 | mac
[1];
180 unsigned int laddr
= mac
[2] << 24 | mac
[3] << 16 | mac
[4] << 8 | mac
[5];
182 iowrite32(maddr
, priv
->base
+ FTGMAC100_OFFSET_MAC_MADR
);
183 iowrite32(laddr
, priv
->base
+ FTGMAC100_OFFSET_MAC_LADR
);
186 static void ftgmac100_setup_mac(struct ftgmac100
*priv
)
193 addr
= device_get_mac_address(priv
->dev
, mac
, ETH_ALEN
);
195 ether_addr_copy(priv
->netdev
->dev_addr
, mac
);
196 dev_info(priv
->dev
, "Read MAC address %pM from device tree\n",
201 m
= ioread32(priv
->base
+ FTGMAC100_OFFSET_MAC_MADR
);
202 l
= ioread32(priv
->base
+ FTGMAC100_OFFSET_MAC_LADR
);
204 mac
[0] = (m
>> 8) & 0xff;
206 mac
[2] = (l
>> 24) & 0xff;
207 mac
[3] = (l
>> 16) & 0xff;
208 mac
[4] = (l
>> 8) & 0xff;
211 if (is_valid_ether_addr(mac
)) {
212 ether_addr_copy(priv
->netdev
->dev_addr
, mac
);
213 dev_info(priv
->dev
, "Read MAC address %pM from chip\n", mac
);
215 eth_hw_addr_random(priv
->netdev
);
216 dev_info(priv
->dev
, "Generated random MAC address %pM\n",
217 priv
->netdev
->dev_addr
);
221 static int ftgmac100_set_mac_addr(struct net_device
*dev
, void *p
)
225 ret
= eth_prepare_mac_addr_change(dev
, p
);
229 eth_commit_mac_addr_change(dev
, p
);
230 ftgmac100_set_mac(netdev_priv(dev
), dev
->dev_addr
);
235 static void ftgmac100_init_hw(struct ftgmac100
*priv
)
237 /* setup ring buffer base registers */
238 ftgmac100_set_rx_ring_base(priv
,
239 priv
->descs_dma_addr
+
240 offsetof(struct ftgmac100_descs
, rxdes
));
241 ftgmac100_set_normal_prio_tx_ring_base(priv
,
242 priv
->descs_dma_addr
+
243 offsetof(struct ftgmac100_descs
, txdes
));
245 ftgmac100_set_rx_buffer_size(priv
, RX_BUF_SIZE
);
247 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), priv
->base
+ FTGMAC100_OFFSET_APTC
);
249 ftgmac100_set_mac(priv
, priv
->netdev
->dev_addr
);
252 static void ftgmac100_start_hw(struct ftgmac100
*priv
)
254 u32 maccr
= ioread32(priv
->base
+ FTGMAC100_OFFSET_MACCR
);
256 /* Keep the original GMAC and FAST bits */
257 maccr
&= (FTGMAC100_MACCR_FAST_MODE
| FTGMAC100_MACCR_GIGA_MODE
);
259 /* Add all the main enable bits */
260 maccr
|= FTGMAC100_MACCR_TXDMA_EN
|
261 FTGMAC100_MACCR_RXDMA_EN
|
262 FTGMAC100_MACCR_TXMAC_EN
|
263 FTGMAC100_MACCR_RXMAC_EN
|
264 FTGMAC100_MACCR_CRC_APD
|
265 FTGMAC100_MACCR_PHY_LINK_LEVEL
|
266 FTGMAC100_MACCR_RX_RUNT
|
267 FTGMAC100_MACCR_RX_BROADPKT
;
269 /* Add other bits as needed */
270 if (priv
->cur_duplex
== DUPLEX_FULL
)
271 maccr
|= FTGMAC100_MACCR_FULLDUP
;
274 iowrite32(maccr
, priv
->base
+ FTGMAC100_OFFSET_MACCR
);
277 static void ftgmac100_stop_hw(struct ftgmac100
*priv
)
279 iowrite32(0, priv
->base
+ FTGMAC100_OFFSET_MACCR
);
282 static int ftgmac100_alloc_rx_buf(struct ftgmac100
*priv
, unsigned int entry
,
283 struct ftgmac100_rxdes
*rxdes
, gfp_t gfp
)
285 struct net_device
*netdev
= priv
->netdev
;
290 skb
= netdev_alloc_skb_ip_align(netdev
, RX_BUF_SIZE
);
291 if (unlikely(!skb
)) {
293 netdev_warn(netdev
, "failed to allocate rx skb\n");
295 map
= priv
->rx_scratch_dma
;
297 map
= dma_map_single(priv
->dev
, skb
->data
, RX_BUF_SIZE
,
299 if (unlikely(dma_mapping_error(priv
->dev
, map
))) {
301 netdev_err(netdev
, "failed to map rx page\n");
302 dev_kfree_skb_any(skb
);
303 map
= priv
->rx_scratch_dma
;
310 priv
->rx_skbs
[entry
] = skb
;
312 /* Store DMA address into RX desc */
313 rxdes
->rxdes3
= cpu_to_le32(map
);
315 /* Ensure the above is ordered vs clearing the OWN bit */
318 /* Clean status (which resets own bit) */
319 if (entry
== (RX_QUEUE_ENTRIES
- 1))
320 rxdes
->rxdes0
= cpu_to_le32(priv
->rxdes0_edorr_mask
);
327 static int ftgmac100_next_rx_pointer(int pointer
)
329 return (pointer
+ 1) & (RX_QUEUE_ENTRIES
- 1);
332 static void ftgmac100_rx_packet_error(struct ftgmac100
*priv
, u32 status
)
334 struct net_device
*netdev
= priv
->netdev
;
336 if (status
& FTGMAC100_RXDES0_RX_ERR
)
337 netdev
->stats
.rx_errors
++;
339 if (status
& FTGMAC100_RXDES0_CRC_ERR
)
340 netdev
->stats
.rx_crc_errors
++;
342 if (status
& (FTGMAC100_RXDES0_FTL
|
343 FTGMAC100_RXDES0_RUNT
|
344 FTGMAC100_RXDES0_RX_ODD_NB
))
345 netdev
->stats
.rx_length_errors
++;
348 static bool ftgmac100_rx_packet(struct ftgmac100
*priv
, int *processed
)
350 struct net_device
*netdev
= priv
->netdev
;
351 struct ftgmac100_rxdes
*rxdes
;
353 unsigned int pointer
, size
;
354 u32 status
, csum_vlan
;
357 /* Grab next RX descriptor */
358 pointer
= priv
->rx_pointer
;
359 rxdes
= &priv
->descs
->rxdes
[pointer
];
361 /* Grab descriptor status */
362 status
= le32_to_cpu(rxdes
->rxdes0
);
364 /* Do we have a packet ? */
365 if (!(status
& FTGMAC100_RXDES0_RXPKT_RDY
))
368 /* Order subsequent reads with the test for the ready bit */
371 /* We don't cope with fragmented RX packets */
372 if (unlikely(!(status
& FTGMAC100_RXDES0_FRS
) ||
373 !(status
& FTGMAC100_RXDES0_LRS
)))
376 /* Grab received size and csum vlan field in the descriptor */
377 size
= status
& FTGMAC100_RXDES0_VDBC
;
378 csum_vlan
= le32_to_cpu(rxdes
->rxdes1
);
380 /* Any error (other than csum offload) flagged ? */
381 if (unlikely(status
& RXDES0_ANY_ERROR
)) {
382 /* Correct for incorrect flagging of runt packets
383 * with vlan tags... Just accept a runt packet that
384 * has been flagged as vlan and whose size is at
387 if ((status
& FTGMAC100_RXDES0_RUNT
) &&
388 (csum_vlan
& FTGMAC100_RXDES1_VLANTAG_AVAIL
) &&
390 status
&= ~FTGMAC100_RXDES0_RUNT
;
392 /* Any error still in there ? */
393 if (status
& RXDES0_ANY_ERROR
) {
394 ftgmac100_rx_packet_error(priv
, status
);
399 /* If the packet had no skb (failed to allocate earlier)
400 * then try to allocate one and skip
402 skb
= priv
->rx_skbs
[pointer
];
403 if (!unlikely(skb
)) {
404 ftgmac100_alloc_rx_buf(priv
, pointer
, rxdes
, GFP_ATOMIC
);
408 if (unlikely(status
& FTGMAC100_RXDES0_MULTICAST
))
409 netdev
->stats
.multicast
++;
411 /* If the HW found checksum errors, bounce it to software.
413 * If we didn't, we need to see if the packet was recognized
414 * by HW as one of the supported checksummed protocols before
415 * we accept the HW test results.
417 if (netdev
->features
& NETIF_F_RXCSUM
) {
418 u32 err_bits
= FTGMAC100_RXDES1_TCP_CHKSUM_ERR
|
419 FTGMAC100_RXDES1_UDP_CHKSUM_ERR
|
420 FTGMAC100_RXDES1_IP_CHKSUM_ERR
;
421 if ((csum_vlan
& err_bits
) ||
422 !(csum_vlan
& FTGMAC100_RXDES1_PROT_MASK
))
423 skb
->ip_summed
= CHECKSUM_NONE
;
425 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
428 /* Transfer received size to skb */
431 /* Tear down DMA mapping, do necessary cache management */
432 map
= le32_to_cpu(rxdes
->rxdes3
);
434 #if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU)
435 /* When we don't have an iommu, we can save cycles by not
436 * invalidating the cache for the part of the packet that
439 dma_unmap_single(priv
->dev
, map
, size
, DMA_FROM_DEVICE
);
441 dma_unmap_single(priv
->dev
, map
, RX_BUF_SIZE
, DMA_FROM_DEVICE
);
445 /* Resplenish rx ring */
446 ftgmac100_alloc_rx_buf(priv
, pointer
, rxdes
, GFP_ATOMIC
);
447 priv
->rx_pointer
= ftgmac100_next_rx_pointer(pointer
);
449 skb
->protocol
= eth_type_trans(skb
, netdev
);
451 netdev
->stats
.rx_packets
++;
452 netdev
->stats
.rx_bytes
+= size
;
454 /* push packet to protocol stack */
455 if (skb
->ip_summed
== CHECKSUM_NONE
)
456 netif_receive_skb(skb
);
458 napi_gro_receive(&priv
->napi
, skb
);
464 /* Clean rxdes0 (which resets own bit) */
465 rxdes
->rxdes0
= cpu_to_le32(status
& priv
->rxdes0_edorr_mask
);
466 priv
->rx_pointer
= ftgmac100_next_rx_pointer(pointer
);
467 netdev
->stats
.rx_dropped
++;
471 static void ftgmac100_txdes_reset(const struct ftgmac100
*priv
,
472 struct ftgmac100_txdes
*txdes
)
474 /* clear all except end of ring bit */
475 txdes
->txdes0
&= cpu_to_le32(priv
->txdes0_edotr_mask
);
481 static bool ftgmac100_txdes_owned_by_dma(struct ftgmac100_txdes
*txdes
)
483 return txdes
->txdes0
& cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN
);
486 static void ftgmac100_txdes_set_dma_own(struct ftgmac100_txdes
*txdes
)
489 * Make sure dma own bit will not be set before any other
493 txdes
->txdes0
|= cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN
);
496 static void ftgmac100_txdes_set_end_of_ring(const struct ftgmac100
*priv
,
497 struct ftgmac100_txdes
*txdes
)
499 txdes
->txdes0
|= cpu_to_le32(priv
->txdes0_edotr_mask
);
502 static void ftgmac100_txdes_set_first_segment(struct ftgmac100_txdes
*txdes
)
504 txdes
->txdes0
|= cpu_to_le32(FTGMAC100_TXDES0_FTS
);
507 static void ftgmac100_txdes_set_last_segment(struct ftgmac100_txdes
*txdes
)
509 txdes
->txdes0
|= cpu_to_le32(FTGMAC100_TXDES0_LTS
);
512 static void ftgmac100_txdes_set_buffer_size(struct ftgmac100_txdes
*txdes
,
515 txdes
->txdes0
|= cpu_to_le32(FTGMAC100_TXDES0_TXBUF_SIZE(len
));
518 static void ftgmac100_txdes_set_txint(struct ftgmac100_txdes
*txdes
)
520 txdes
->txdes1
|= cpu_to_le32(FTGMAC100_TXDES1_TXIC
);
523 static void ftgmac100_txdes_set_tcpcs(struct ftgmac100_txdes
*txdes
)
525 txdes
->txdes1
|= cpu_to_le32(FTGMAC100_TXDES1_TCP_CHKSUM
);
528 static void ftgmac100_txdes_set_udpcs(struct ftgmac100_txdes
*txdes
)
530 txdes
->txdes1
|= cpu_to_le32(FTGMAC100_TXDES1_UDP_CHKSUM
);
533 static void ftgmac100_txdes_set_ipcs(struct ftgmac100_txdes
*txdes
)
535 txdes
->txdes1
|= cpu_to_le32(FTGMAC100_TXDES1_IP_CHKSUM
);
538 static void ftgmac100_txdes_set_dma_addr(struct ftgmac100_txdes
*txdes
,
541 txdes
->txdes3
= cpu_to_le32(addr
);
544 static dma_addr_t
ftgmac100_txdes_get_dma_addr(struct ftgmac100_txdes
*txdes
)
546 return le32_to_cpu(txdes
->txdes3
);
549 static int ftgmac100_next_tx_pointer(int pointer
)
551 return (pointer
+ 1) & (TX_QUEUE_ENTRIES
- 1);
554 static bool ftgmac100_tx_complete_packet(struct ftgmac100
*priv
)
556 struct net_device
*netdev
= priv
->netdev
;
557 struct ftgmac100_txdes
*txdes
;
558 unsigned int pointer
;
562 if (priv
->tx_pending
== 0)
565 pointer
= priv
->tx_clean_pointer
;
566 txdes
= &priv
->descs
->txdes
[pointer
];
568 if (ftgmac100_txdes_owned_by_dma(txdes
))
571 skb
= priv
->tx_skbs
[pointer
];
572 map
= ftgmac100_txdes_get_dma_addr(txdes
);
574 netdev
->stats
.tx_packets
++;
575 netdev
->stats
.tx_bytes
+= skb
->len
;
577 dma_unmap_single(priv
->dev
, map
, skb_headlen(skb
), DMA_TO_DEVICE
);
580 priv
->tx_skbs
[pointer
] = NULL
;
582 ftgmac100_txdes_reset(priv
, txdes
);
584 priv
->tx_clean_pointer
= ftgmac100_next_tx_pointer(pointer
);
586 spin_lock(&priv
->tx_lock
);
588 spin_unlock(&priv
->tx_lock
);
589 netif_wake_queue(netdev
);
594 static void ftgmac100_tx_complete(struct ftgmac100
*priv
)
596 while (ftgmac100_tx_complete_packet(priv
))
600 static int ftgmac100_hard_start_xmit(struct sk_buff
*skb
,
601 struct net_device
*netdev
)
603 struct ftgmac100
*priv
= netdev_priv(netdev
);
604 struct ftgmac100_txdes
*txdes
;
605 unsigned int pointer
;
608 /* The HW doesn't pad small frames */
609 if (eth_skb_pad(skb
)) {
610 netdev
->stats
.tx_dropped
++;
614 /* Reject oversize packets */
615 if (unlikely(skb
->len
> MAX_PKT_SIZE
)) {
617 netdev_dbg(netdev
, "tx packet too big\n");
621 map
= dma_map_single(priv
->dev
, skb
->data
, skb_headlen(skb
), DMA_TO_DEVICE
);
622 if (unlikely(dma_mapping_error(priv
->dev
, map
))) {
625 netdev_err(netdev
, "map socket buffer failed\n");
629 /* Grab the next free tx descriptor */
630 pointer
= priv
->tx_pointer
;
631 txdes
= &priv
->descs
->txdes
[pointer
];
633 /* setup TX descriptor */
634 priv
->tx_skbs
[pointer
] = skb
;
635 ftgmac100_txdes_set_dma_addr(txdes
, map
);
636 ftgmac100_txdes_set_buffer_size(txdes
, skb
->len
);
638 ftgmac100_txdes_set_first_segment(txdes
);
639 ftgmac100_txdes_set_last_segment(txdes
);
640 ftgmac100_txdes_set_txint(txdes
);
641 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
642 __be16 protocol
= skb
->protocol
;
644 if (protocol
== cpu_to_be16(ETH_P_IP
)) {
645 u8 ip_proto
= ip_hdr(skb
)->protocol
;
647 ftgmac100_txdes_set_ipcs(txdes
);
648 if (ip_proto
== IPPROTO_TCP
)
649 ftgmac100_txdes_set_tcpcs(txdes
);
650 else if (ip_proto
== IPPROTO_UDP
)
651 ftgmac100_txdes_set_udpcs(txdes
);
655 /* Update next TX pointer */
656 priv
->tx_pointer
= ftgmac100_next_tx_pointer(pointer
);
658 spin_lock(&priv
->tx_lock
);
660 if (priv
->tx_pending
== TX_QUEUE_ENTRIES
)
661 netif_stop_queue(netdev
);
664 ftgmac100_txdes_set_dma_own(txdes
);
665 spin_unlock(&priv
->tx_lock
);
667 ftgmac100_txdma_normal_prio_start_polling(priv
);
672 /* Drop the packet */
673 dev_kfree_skb_any(skb
);
674 netdev
->stats
.tx_dropped
++;
679 static void ftgmac100_free_buffers(struct ftgmac100
*priv
)
683 /* Free all RX buffers */
684 for (i
= 0; i
< RX_QUEUE_ENTRIES
; i
++) {
685 struct ftgmac100_rxdes
*rxdes
= &priv
->descs
->rxdes
[i
];
686 struct sk_buff
*skb
= priv
->rx_skbs
[i
];
687 dma_addr_t map
= le32_to_cpu(rxdes
->rxdes3
);
692 priv
->rx_skbs
[i
] = NULL
;
693 dma_unmap_single(priv
->dev
, map
, RX_BUF_SIZE
, DMA_FROM_DEVICE
);
694 dev_kfree_skb_any(skb
);
697 /* Free all TX buffers */
698 for (i
= 0; i
< TX_QUEUE_ENTRIES
; i
++) {
699 struct ftgmac100_txdes
*txdes
= &priv
->descs
->txdes
[i
];
700 struct sk_buff
*skb
= priv
->tx_skbs
[i
];
701 dma_addr_t map
= ftgmac100_txdes_get_dma_addr(txdes
);
706 dma_unmap_single(priv
->dev
, map
, skb_headlen(skb
), DMA_TO_DEVICE
);
711 static void ftgmac100_free_rings(struct ftgmac100
*priv
)
713 /* Free descriptors */
715 dma_free_coherent(priv
->dev
, sizeof(struct ftgmac100_descs
),
716 priv
->descs
, priv
->descs_dma_addr
);
718 /* Free scratch packet buffer */
719 if (priv
->rx_scratch
)
720 dma_free_coherent(priv
->dev
, RX_BUF_SIZE
,
721 priv
->rx_scratch
, priv
->rx_scratch_dma
);
724 static int ftgmac100_alloc_rings(struct ftgmac100
*priv
)
726 /* Allocate descriptors */
727 priv
->descs
= dma_zalloc_coherent(priv
->dev
,
728 sizeof(struct ftgmac100_descs
),
729 &priv
->descs_dma_addr
, GFP_KERNEL
);
733 /* Allocate scratch packet buffer */
734 priv
->rx_scratch
= dma_alloc_coherent(priv
->dev
,
736 &priv
->rx_scratch_dma
,
738 if (!priv
->rx_scratch
)
744 static void ftgmac100_init_rings(struct ftgmac100
*priv
)
746 struct ftgmac100_rxdes
*rxdes
;
749 /* Initialize RX ring */
750 for (i
= 0; i
< RX_QUEUE_ENTRIES
; i
++) {
751 rxdes
= &priv
->descs
->rxdes
[i
];
753 rxdes
->rxdes3
= cpu_to_le32(priv
->rx_scratch_dma
);
755 /* Mark the end of the ring */
756 rxdes
->rxdes0
|= cpu_to_le32(priv
->rxdes0_edorr_mask
);
758 /* Initialize TX ring */
759 for (i
= 0; i
< TX_QUEUE_ENTRIES
; i
++)
760 priv
->descs
->txdes
[i
].txdes0
= 0;
761 ftgmac100_txdes_set_end_of_ring(priv
, &priv
->descs
->txdes
[i
-1]);
764 static int ftgmac100_alloc_rx_buffers(struct ftgmac100
*priv
)
768 for (i
= 0; i
< RX_QUEUE_ENTRIES
; i
++) {
769 struct ftgmac100_rxdes
*rxdes
= &priv
->descs
->rxdes
[i
];
771 if (ftgmac100_alloc_rx_buf(priv
, i
, rxdes
, GFP_KERNEL
))
777 static void ftgmac100_adjust_link(struct net_device
*netdev
)
779 struct ftgmac100
*priv
= netdev_priv(netdev
);
780 struct phy_device
*phydev
= netdev
->phydev
;
783 /* We store "no link" as speed 0 */
787 new_speed
= phydev
->speed
;
789 if (phydev
->speed
== priv
->cur_speed
&&
790 phydev
->duplex
== priv
->cur_duplex
)
793 /* Print status if we have a link or we had one and just lost it,
794 * don't print otherwise.
796 if (new_speed
|| priv
->cur_speed
)
797 phy_print_status(phydev
);
799 priv
->cur_speed
= new_speed
;
800 priv
->cur_duplex
= phydev
->duplex
;
802 /* Link is down, do nothing else */
806 /* Disable all interrupts */
807 iowrite32(0, priv
->base
+ FTGMAC100_OFFSET_IER
);
809 /* Reset the adapter asynchronously */
810 schedule_work(&priv
->reset_task
);
813 static int ftgmac100_mii_probe(struct ftgmac100
*priv
)
815 struct net_device
*netdev
= priv
->netdev
;
816 struct phy_device
*phydev
;
818 phydev
= phy_find_first(priv
->mii_bus
);
820 netdev_info(netdev
, "%s: no PHY found\n", netdev
->name
);
824 phydev
= phy_connect(netdev
, phydev_name(phydev
),
825 &ftgmac100_adjust_link
, PHY_INTERFACE_MODE_GMII
);
827 if (IS_ERR(phydev
)) {
828 netdev_err(netdev
, "%s: Could not attach to PHY\n", netdev
->name
);
829 return PTR_ERR(phydev
);
835 static int ftgmac100_mdiobus_read(struct mii_bus
*bus
, int phy_addr
, int regnum
)
837 struct net_device
*netdev
= bus
->priv
;
838 struct ftgmac100
*priv
= netdev_priv(netdev
);
842 phycr
= ioread32(priv
->base
+ FTGMAC100_OFFSET_PHYCR
);
844 /* preserve MDC cycle threshold */
845 phycr
&= FTGMAC100_PHYCR_MDC_CYCTHR_MASK
;
847 phycr
|= FTGMAC100_PHYCR_PHYAD(phy_addr
) |
848 FTGMAC100_PHYCR_REGAD(regnum
) |
849 FTGMAC100_PHYCR_MIIRD
;
851 iowrite32(phycr
, priv
->base
+ FTGMAC100_OFFSET_PHYCR
);
853 for (i
= 0; i
< 10; i
++) {
854 phycr
= ioread32(priv
->base
+ FTGMAC100_OFFSET_PHYCR
);
856 if ((phycr
& FTGMAC100_PHYCR_MIIRD
) == 0) {
859 data
= ioread32(priv
->base
+ FTGMAC100_OFFSET_PHYDATA
);
860 return FTGMAC100_PHYDATA_MIIRDATA(data
);
866 netdev_err(netdev
, "mdio read timed out\n");
870 static int ftgmac100_mdiobus_write(struct mii_bus
*bus
, int phy_addr
,
871 int regnum
, u16 value
)
873 struct net_device
*netdev
= bus
->priv
;
874 struct ftgmac100
*priv
= netdev_priv(netdev
);
879 phycr
= ioread32(priv
->base
+ FTGMAC100_OFFSET_PHYCR
);
881 /* preserve MDC cycle threshold */
882 phycr
&= FTGMAC100_PHYCR_MDC_CYCTHR_MASK
;
884 phycr
|= FTGMAC100_PHYCR_PHYAD(phy_addr
) |
885 FTGMAC100_PHYCR_REGAD(regnum
) |
886 FTGMAC100_PHYCR_MIIWR
;
888 data
= FTGMAC100_PHYDATA_MIIWDATA(value
);
890 iowrite32(data
, priv
->base
+ FTGMAC100_OFFSET_PHYDATA
);
891 iowrite32(phycr
, priv
->base
+ FTGMAC100_OFFSET_PHYCR
);
893 for (i
= 0; i
< 10; i
++) {
894 phycr
= ioread32(priv
->base
+ FTGMAC100_OFFSET_PHYCR
);
896 if ((phycr
& FTGMAC100_PHYCR_MIIWR
) == 0)
902 netdev_err(netdev
, "mdio write timed out\n");
906 static void ftgmac100_get_drvinfo(struct net_device
*netdev
,
907 struct ethtool_drvinfo
*info
)
909 strlcpy(info
->driver
, DRV_NAME
, sizeof(info
->driver
));
910 strlcpy(info
->version
, DRV_VERSION
, sizeof(info
->version
));
911 strlcpy(info
->bus_info
, dev_name(&netdev
->dev
), sizeof(info
->bus_info
));
914 static const struct ethtool_ops ftgmac100_ethtool_ops
= {
915 .get_drvinfo
= ftgmac100_get_drvinfo
,
916 .get_link
= ethtool_op_get_link
,
917 .get_link_ksettings
= phy_ethtool_get_link_ksettings
,
918 .set_link_ksettings
= phy_ethtool_set_link_ksettings
,
921 static irqreturn_t
ftgmac100_interrupt(int irq
, void *dev_id
)
923 struct net_device
*netdev
= dev_id
;
924 struct ftgmac100
*priv
= netdev_priv(netdev
);
925 unsigned int status
, new_mask
= FTGMAC100_INT_BAD
;
927 /* Fetch and clear interrupt bits, process abnormal ones */
928 status
= ioread32(priv
->base
+ FTGMAC100_OFFSET_ISR
);
929 iowrite32(status
, priv
->base
+ FTGMAC100_OFFSET_ISR
);
930 if (unlikely(status
& FTGMAC100_INT_BAD
)) {
932 /* RX buffer unavailable */
933 if (status
& FTGMAC100_INT_NO_RXBUF
)
934 netdev
->stats
.rx_over_errors
++;
936 /* received packet lost due to RX FIFO full */
937 if (status
& FTGMAC100_INT_RPKT_LOST
)
938 netdev
->stats
.rx_fifo_errors
++;
940 /* sent packet lost due to excessive TX collision */
941 if (status
& FTGMAC100_INT_XPKT_LOST
)
942 netdev
->stats
.tx_fifo_errors
++;
944 /* AHB error -> Reset the chip */
945 if (status
& FTGMAC100_INT_AHB_ERR
) {
948 "AHB bus error ! Resetting chip.\n");
949 iowrite32(0, priv
->base
+ FTGMAC100_OFFSET_IER
);
950 schedule_work(&priv
->reset_task
);
954 /* We may need to restart the MAC after such errors, delay
955 * this until after we have freed some Rx buffers though
957 priv
->need_mac_restart
= true;
959 /* Disable those errors until we restart */
963 /* Only enable "bad" interrupts while NAPI is on */
964 iowrite32(new_mask
, priv
->base
+ FTGMAC100_OFFSET_IER
);
966 /* Schedule NAPI bh */
967 napi_schedule_irqoff(&priv
->napi
);
972 static bool ftgmac100_check_rx(struct ftgmac100
*priv
)
974 struct ftgmac100_rxdes
*rxdes
= &priv
->descs
->rxdes
[priv
->rx_pointer
];
976 /* Do we have a packet ? */
977 return !!(rxdes
->rxdes0
& cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY
));
980 static int ftgmac100_poll(struct napi_struct
*napi
, int budget
)
982 struct ftgmac100
*priv
= container_of(napi
, struct ftgmac100
, napi
);
983 bool more
, completed
= true;
986 ftgmac100_tx_complete(priv
);
989 more
= ftgmac100_rx_packet(priv
, &rx
);
990 } while (more
&& rx
< budget
);
992 if (more
&& rx
== budget
)
996 /* The interrupt is telling us to kick the MAC back to life
997 * after an RX overflow
999 if (unlikely(priv
->need_mac_restart
)) {
1000 ftgmac100_start_hw(priv
);
1002 /* Re-enable "bad" interrupts */
1003 iowrite32(FTGMAC100_INT_BAD
,
1004 priv
->base
+ FTGMAC100_OFFSET_IER
);
1007 /* Keep NAPI going if we have still packets to reclaim */
1008 if (priv
->tx_pending
)
1012 /* We are about to re-enable all interrupts. However
1013 * the HW has been latching RX/TX packet interrupts while
1014 * they were masked. So we clear them first, then we need
1015 * to re-check if there's something to process
1017 iowrite32(FTGMAC100_INT_RXTX
,
1018 priv
->base
+ FTGMAC100_OFFSET_ISR
);
1019 if (ftgmac100_check_rx(priv
) || priv
->tx_pending
)
1022 /* deschedule NAPI */
1023 napi_complete(napi
);
1025 /* enable all interrupts */
1026 iowrite32(FTGMAC100_INT_ALL
,
1027 priv
->base
+ FTGMAC100_OFFSET_IER
);
1033 static int ftgmac100_init_all(struct ftgmac100
*priv
, bool ignore_alloc_err
)
1037 /* Re-init descriptors (adjust queue sizes) */
1038 ftgmac100_init_rings(priv
);
1040 /* Realloc rx descriptors */
1041 err
= ftgmac100_alloc_rx_buffers(priv
);
1042 if (err
&& !ignore_alloc_err
)
1045 /* Reinit and restart HW */
1046 ftgmac100_init_hw(priv
);
1047 ftgmac100_start_hw(priv
);
1049 /* Re-enable the device */
1050 napi_enable(&priv
->napi
);
1051 netif_start_queue(priv
->netdev
);
1053 /* Enable all interrupts */
1054 iowrite32(FTGMAC100_INT_ALL
, priv
->base
+ FTGMAC100_OFFSET_IER
);
1059 static void ftgmac100_reset_task(struct work_struct
*work
)
1061 struct ftgmac100
*priv
= container_of(work
, struct ftgmac100
,
1063 struct net_device
*netdev
= priv
->netdev
;
1066 netdev_dbg(netdev
, "Resetting NIC...\n");
1068 /* Lock the world */
1071 mutex_lock(&netdev
->phydev
->lock
);
1073 mutex_lock(&priv
->mii_bus
->mdio_lock
);
1076 /* Check if the interface is still up */
1077 if (!netif_running(netdev
))
1080 /* Stop the network stack */
1081 netif_trans_update(netdev
);
1082 napi_disable(&priv
->napi
);
1083 netif_tx_disable(netdev
);
1085 /* Stop and reset the MAC */
1086 ftgmac100_stop_hw(priv
);
1087 err
= ftgmac100_reset_and_config_mac(priv
);
1089 /* Not much we can do ... it might come back... */
1090 netdev_err(netdev
, "attempting to continue...\n");
1093 /* Free all rx and tx buffers */
1094 ftgmac100_free_buffers(priv
);
1096 /* Setup everything again and restart chip */
1097 ftgmac100_init_all(priv
, true);
1099 netdev_dbg(netdev
, "Reset done !\n");
1102 mutex_unlock(&priv
->mii_bus
->mdio_lock
);
1104 mutex_unlock(&netdev
->phydev
->lock
);
1108 static int ftgmac100_open(struct net_device
*netdev
)
1110 struct ftgmac100
*priv
= netdev_priv(netdev
);
1113 /* Allocate ring buffers */
1114 err
= ftgmac100_alloc_rings(priv
);
1116 netdev_err(netdev
, "Failed to allocate descriptors\n");
1120 /* When using NC-SI we force the speed to 100Mbit/s full duplex,
1122 * Otherwise we leave it set to 0 (no link), the link
1123 * message from the PHY layer will handle setting it up to
1124 * something else if needed.
1126 if (priv
->use_ncsi
) {
1127 priv
->cur_duplex
= DUPLEX_FULL
;
1128 priv
->cur_speed
= SPEED_100
;
1130 priv
->cur_duplex
= 0;
1131 priv
->cur_speed
= 0;
1134 /* Reset the hardware */
1135 err
= ftgmac100_reset_and_config_mac(priv
);
1139 /* Initialize NAPI */
1140 netif_napi_add(netdev
, &priv
->napi
, ftgmac100_poll
, 64);
1142 /* Grab our interrupt */
1143 err
= request_irq(netdev
->irq
, ftgmac100_interrupt
, 0, netdev
->name
, netdev
);
1145 netdev_err(netdev
, "failed to request irq %d\n", netdev
->irq
);
1149 /* Start things up */
1150 err
= ftgmac100_init_all(priv
, false);
1152 netdev_err(netdev
, "Failed to allocate packet buffers\n");
1156 if (netdev
->phydev
) {
1157 /* If we have a PHY, start polling */
1158 phy_start(netdev
->phydev
);
1159 } else if (priv
->use_ncsi
) {
1160 /* If using NC-SI, set our carrier on and start the stack */
1161 netif_carrier_on(netdev
);
1163 /* Start the NCSI device */
1164 err
= ncsi_start_dev(priv
->ndev
);
1172 napi_disable(&priv
->napi
);
1173 netif_stop_queue(netdev
);
1175 ftgmac100_free_buffers(priv
);
1176 free_irq(netdev
->irq
, netdev
);
1178 netif_napi_del(&priv
->napi
);
1180 iowrite32(0, priv
->base
+ FTGMAC100_OFFSET_IER
);
1181 ftgmac100_free_rings(priv
);
1185 static int ftgmac100_stop(struct net_device
*netdev
)
1187 struct ftgmac100
*priv
= netdev_priv(netdev
);
1189 /* Note about the reset task: We are called with the rtnl lock
1190 * held, so we are synchronized against the core of the reset
1191 * task. We must not try to synchronously cancel it otherwise
1192 * we can deadlock. But since it will test for netif_running()
1193 * which has already been cleared by the net core, we don't
1194 * anything special to do.
1197 /* disable all interrupts */
1198 iowrite32(0, priv
->base
+ FTGMAC100_OFFSET_IER
);
1200 netif_stop_queue(netdev
);
1201 napi_disable(&priv
->napi
);
1202 netif_napi_del(&priv
->napi
);
1204 phy_stop(netdev
->phydev
);
1205 else if (priv
->use_ncsi
)
1206 ncsi_stop_dev(priv
->ndev
);
1208 ftgmac100_stop_hw(priv
);
1209 free_irq(netdev
->irq
, netdev
);
1210 ftgmac100_free_buffers(priv
);
1211 ftgmac100_free_rings(priv
);
1217 static int ftgmac100_do_ioctl(struct net_device
*netdev
, struct ifreq
*ifr
, int cmd
)
1219 if (!netdev
->phydev
)
1222 return phy_mii_ioctl(netdev
->phydev
, ifr
, cmd
);
1225 static void ftgmac100_tx_timeout(struct net_device
*netdev
)
1227 struct ftgmac100
*priv
= netdev_priv(netdev
);
1229 /* Disable all interrupts */
1230 iowrite32(0, priv
->base
+ FTGMAC100_OFFSET_IER
);
1232 /* Do the reset outside of interrupt context */
1233 schedule_work(&priv
->reset_task
);
1236 static const struct net_device_ops ftgmac100_netdev_ops
= {
1237 .ndo_open
= ftgmac100_open
,
1238 .ndo_stop
= ftgmac100_stop
,
1239 .ndo_start_xmit
= ftgmac100_hard_start_xmit
,
1240 .ndo_set_mac_address
= ftgmac100_set_mac_addr
,
1241 .ndo_validate_addr
= eth_validate_addr
,
1242 .ndo_do_ioctl
= ftgmac100_do_ioctl
,
1243 .ndo_tx_timeout
= ftgmac100_tx_timeout
,
1246 static int ftgmac100_setup_mdio(struct net_device
*netdev
)
1248 struct ftgmac100
*priv
= netdev_priv(netdev
);
1249 struct platform_device
*pdev
= to_platform_device(priv
->dev
);
1253 /* initialize mdio bus */
1254 priv
->mii_bus
= mdiobus_alloc();
1258 if (of_machine_is_compatible("aspeed,ast2400") ||
1259 of_machine_is_compatible("aspeed,ast2500")) {
1260 /* This driver supports the old MDIO interface */
1261 reg
= ioread32(priv
->base
+ FTGMAC100_OFFSET_REVR
);
1262 reg
&= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE
;
1263 iowrite32(reg
, priv
->base
+ FTGMAC100_OFFSET_REVR
);
1266 priv
->mii_bus
->name
= "ftgmac100_mdio";
1267 snprintf(priv
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%s-%d",
1268 pdev
->name
, pdev
->id
);
1269 priv
->mii_bus
->priv
= priv
->netdev
;
1270 priv
->mii_bus
->read
= ftgmac100_mdiobus_read
;
1271 priv
->mii_bus
->write
= ftgmac100_mdiobus_write
;
1273 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1274 priv
->mii_bus
->irq
[i
] = PHY_POLL
;
1276 err
= mdiobus_register(priv
->mii_bus
);
1278 dev_err(priv
->dev
, "Cannot register MDIO bus!\n");
1279 goto err_register_mdiobus
;
1282 err
= ftgmac100_mii_probe(priv
);
1284 dev_err(priv
->dev
, "MII Probe failed!\n");
1291 mdiobus_unregister(priv
->mii_bus
);
1292 err_register_mdiobus
:
1293 mdiobus_free(priv
->mii_bus
);
1297 static void ftgmac100_destroy_mdio(struct net_device
*netdev
)
1299 struct ftgmac100
*priv
= netdev_priv(netdev
);
1301 if (!netdev
->phydev
)
1304 phy_disconnect(netdev
->phydev
);
1305 mdiobus_unregister(priv
->mii_bus
);
1306 mdiobus_free(priv
->mii_bus
);
1309 static void ftgmac100_ncsi_handler(struct ncsi_dev
*nd
)
1311 if (unlikely(nd
->state
!= ncsi_dev_state_functional
))
1314 netdev_info(nd
->dev
, "NCSI interface %s\n",
1315 nd
->link_up
? "up" : "down");
1318 static int ftgmac100_probe(struct platform_device
*pdev
)
1320 struct resource
*res
;
1322 struct net_device
*netdev
;
1323 struct ftgmac100
*priv
;
1329 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1333 irq
= platform_get_irq(pdev
, 0);
1337 /* setup net_device */
1338 netdev
= alloc_etherdev(sizeof(*priv
));
1341 goto err_alloc_etherdev
;
1344 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
1346 netdev
->ethtool_ops
= &ftgmac100_ethtool_ops
;
1347 netdev
->netdev_ops
= &ftgmac100_netdev_ops
;
1348 netdev
->watchdog_timeo
= 5 * HZ
;
1350 platform_set_drvdata(pdev
, netdev
);
1352 /* setup private data */
1353 priv
= netdev_priv(netdev
);
1354 priv
->netdev
= netdev
;
1355 priv
->dev
= &pdev
->dev
;
1356 INIT_WORK(&priv
->reset_task
, ftgmac100_reset_task
);
1358 spin_lock_init(&priv
->tx_lock
);
1361 priv
->res
= request_mem_region(res
->start
, resource_size(res
),
1362 dev_name(&pdev
->dev
));
1364 dev_err(&pdev
->dev
, "Could not reserve memory region\n");
1369 priv
->base
= ioremap(res
->start
, resource_size(res
));
1371 dev_err(&pdev
->dev
, "Failed to ioremap ethernet registers\n");
1378 /* MAC address from chip or random one */
1379 ftgmac100_setup_mac(priv
);
1381 if (of_machine_is_compatible("aspeed,ast2400") ||
1382 of_machine_is_compatible("aspeed,ast2500")) {
1383 priv
->rxdes0_edorr_mask
= BIT(30);
1384 priv
->txdes0_edotr_mask
= BIT(30);
1386 priv
->rxdes0_edorr_mask
= BIT(15);
1387 priv
->txdes0_edotr_mask
= BIT(15);
1390 if (pdev
->dev
.of_node
&&
1391 of_get_property(pdev
->dev
.of_node
, "use-ncsi", NULL
)) {
1392 if (!IS_ENABLED(CONFIG_NET_NCSI
)) {
1393 dev_err(&pdev
->dev
, "NCSI stack not enabled\n");
1397 dev_info(&pdev
->dev
, "Using NCSI interface\n");
1398 priv
->use_ncsi
= true;
1399 priv
->ndev
= ncsi_register_dev(netdev
, ftgmac100_ncsi_handler
);
1403 priv
->use_ncsi
= false;
1404 err
= ftgmac100_setup_mdio(netdev
);
1406 goto err_setup_mdio
;
1409 /* We have to disable on-chip IP checksum functionality
1410 * when NCSI is enabled on the interface. It doesn't work
1413 netdev
->features
= NETIF_F_RXCSUM
| NETIF_F_IP_CSUM
| NETIF_F_GRO
;
1414 if (priv
->use_ncsi
&&
1415 of_get_property(pdev
->dev
.of_node
, "no-hw-checksum", NULL
))
1416 netdev
->features
&= ~NETIF_F_IP_CSUM
;
1419 /* register network device */
1420 err
= register_netdev(netdev
);
1422 dev_err(&pdev
->dev
, "Failed to register netdev\n");
1423 goto err_register_netdev
;
1426 netdev_info(netdev
, "irq %d, mapped at %p\n", netdev
->irq
, priv
->base
);
1431 err_register_netdev
:
1432 ftgmac100_destroy_mdio(netdev
);
1434 iounmap(priv
->base
);
1436 release_resource(priv
->res
);
1438 netif_napi_del(&priv
->napi
);
1439 free_netdev(netdev
);
1444 static int ftgmac100_remove(struct platform_device
*pdev
)
1446 struct net_device
*netdev
;
1447 struct ftgmac100
*priv
;
1449 netdev
= platform_get_drvdata(pdev
);
1450 priv
= netdev_priv(netdev
);
1452 unregister_netdev(netdev
);
1454 /* There's a small chance the reset task will have been re-queued,
1455 * during stop, make sure it's gone before we free the structure.
1457 cancel_work_sync(&priv
->reset_task
);
1459 ftgmac100_destroy_mdio(netdev
);
1461 iounmap(priv
->base
);
1462 release_resource(priv
->res
);
1464 netif_napi_del(&priv
->napi
);
1465 free_netdev(netdev
);
1469 static const struct of_device_id ftgmac100_of_match
[] = {
1470 { .compatible
= "faraday,ftgmac100" },
1473 MODULE_DEVICE_TABLE(of
, ftgmac100_of_match
);
1475 static struct platform_driver ftgmac100_driver
= {
1476 .probe
= ftgmac100_probe
,
1477 .remove
= ftgmac100_remove
,
1480 .of_match_table
= ftgmac100_of_match
,
1483 module_platform_driver(ftgmac100_driver
);
1485 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
1486 MODULE_DESCRIPTION("FTGMAC100 driver");
1487 MODULE_LICENSE("GPL");