2 * Generic device tree based pinctrl driver for one register per pin
3 * type pinmux controllers
5 * Copyright (C) 2012 Texas Instruments, Inc.
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
12 #include <linux/init.h>
13 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/list.h>
20 #include <linux/of_device.h>
21 #include <linux/of_address.h>
23 #include <linux/pinctrl/pinctrl.h>
24 #include <linux/pinctrl/pinmux.h>
25 #include <linux/pinctrl/pinconf-generic.h>
30 #define DRIVER_NAME "pinctrl-single"
31 #define PCS_MUX_PINS_NAME "pinctrl-single,pins"
32 #define PCS_MUX_BITS_NAME "pinctrl-single,bits"
33 #define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 1)
34 #define PCS_OFF_DISABLED ~0U
37 * struct pcs_pingroup - pingroups for a function
38 * @np: pingroup device node pointer
39 * @name: pingroup name
40 * @gpins: array of the pins in the group
41 * @ngpins: number of pins in the group
45 struct device_node
*np
;
49 struct list_head node
;
53 * struct pcs_func_vals - mux function register offset and value pair
54 * @reg: register virtual address
55 * @val: register value
57 struct pcs_func_vals
{
64 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
65 * and value, enable, disable, mask
66 * @param: config parameter
67 * @val: user input bits in the pinconf register
68 * @enable: enable bits in the pinconf register
69 * @disable: disable bits in the pinconf register
70 * @mask: mask bits in the register value
72 struct pcs_conf_vals
{
73 enum pin_config_param param
;
81 * struct pcs_conf_type - pinconf property name, pinconf param pair
82 * @name: property name in DTS file
83 * @param: config parameter
85 struct pcs_conf_type
{
87 enum pin_config_param param
;
91 * struct pcs_function - pinctrl function
92 * @name: pinctrl function name
93 * @vals: register and vals array
94 * @nvals: number of entries in vals array
95 * @pgnames: array of pingroup names the function uses
96 * @npgnames: number of pingroup names the function uses
101 struct pcs_func_vals
*vals
;
103 const char **pgnames
;
105 struct pcs_conf_vals
*conf
;
107 struct list_head node
;
111 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
112 * @offset: offset base of pins
113 * @npins: number pins with the same mux value of gpio function
114 * @gpiofunc: mux value of gpio function
117 struct pcs_gpiofunc_range
{
121 struct list_head node
;
125 * struct pcs_data - wrapper for data needed by pinctrl framework
127 * @cur: index to current element
129 * REVISIT: We should be able to drop this eventually by adding
130 * support for registering pins individually in the pinctrl
131 * framework for those drivers that don't need a static array.
134 struct pinctrl_pin_desc
*pa
;
139 * struct pcs_name - register name for a pin
140 * @name: name of the pinctrl register
142 * REVISIT: We may want to make names optional in the pinctrl
143 * framework as some drivers may not care about pin names to
144 * avoid kernel bloat. The pin names can be deciphered by user
145 * space tools using debugfs based on the register address and
146 * SoC packaging information.
149 char name
[PCS_REG_NAME_LEN
];
153 * struct pcs_device - pinctrl device instance
155 * @base: virtual address of the controller
156 * @size: size of the ioremapped area
158 * @pctl: pin controller device
159 * @mutex: mutex protecting the lists
160 * @width: bits per mux register
161 * @fmask: function register mask
162 * @fshift: function register shift
163 * @foff: value to turn mux off
164 * @fmax: max number of functions in fmask
165 * @is_pinconf: whether supports pinconf
166 * @names: array of register names for pins
167 * @pins: physical pins on the SoC
168 * @pgtree: pingroup index radix tree
169 * @ftree: function index radix tree
170 * @pingroups: list of pingroups
171 * @functions: list of functions
172 * @gpiofuncs: list of gpio functions
173 * @ngroups: number of pingroups
174 * @nfuncs: number of functions
175 * @desc: pin controller descriptor
176 * @read: register read function to use
177 * @write: register write function to use
180 struct resource
*res
;
184 struct pinctrl_dev
*pctl
;
193 struct pcs_name
*names
;
194 struct pcs_data pins
;
195 struct radix_tree_root pgtree
;
196 struct radix_tree_root ftree
;
197 struct list_head pingroups
;
198 struct list_head functions
;
199 struct list_head gpiofuncs
;
202 struct pinctrl_desc desc
;
203 unsigned (*read
)(void __iomem
*reg
);
204 void (*write
)(unsigned val
, void __iomem
*reg
);
207 static int pcs_pinconf_get(struct pinctrl_dev
*pctldev
, unsigned pin
,
208 unsigned long *config
);
209 static int pcs_pinconf_set(struct pinctrl_dev
*pctldev
, unsigned pin
,
210 unsigned long config
);
212 static enum pin_config_param pcs_bias
[] = {
213 PIN_CONFIG_BIAS_PULL_DOWN
,
214 PIN_CONFIG_BIAS_PULL_UP
,
218 * REVISIT: Reads and writes could eventually use regmap or something
219 * generic. But at least on omaps, some mux registers are performance
220 * critical as they may need to be remuxed every time before and after
221 * idle. Adding tests for register access width for every read and
222 * write like regmap is doing is not desired, and caching the registers
223 * does not help in this case.
226 static unsigned __maybe_unused
pcs_readb(void __iomem
*reg
)
231 static unsigned __maybe_unused
pcs_readw(void __iomem
*reg
)
236 static unsigned __maybe_unused
pcs_readl(void __iomem
*reg
)
241 static void __maybe_unused
pcs_writeb(unsigned val
, void __iomem
*reg
)
246 static void __maybe_unused
pcs_writew(unsigned val
, void __iomem
*reg
)
251 static void __maybe_unused
pcs_writel(unsigned val
, void __iomem
*reg
)
256 static int pcs_get_groups_count(struct pinctrl_dev
*pctldev
)
258 struct pcs_device
*pcs
;
260 pcs
= pinctrl_dev_get_drvdata(pctldev
);
265 static const char *pcs_get_group_name(struct pinctrl_dev
*pctldev
,
268 struct pcs_device
*pcs
;
269 struct pcs_pingroup
*group
;
271 pcs
= pinctrl_dev_get_drvdata(pctldev
);
272 group
= radix_tree_lookup(&pcs
->pgtree
, gselector
);
274 dev_err(pcs
->dev
, "%s could not find pingroup%i\n",
275 __func__
, gselector
);
282 static int pcs_get_group_pins(struct pinctrl_dev
*pctldev
,
284 const unsigned **pins
,
287 struct pcs_device
*pcs
;
288 struct pcs_pingroup
*group
;
290 pcs
= pinctrl_dev_get_drvdata(pctldev
);
291 group
= radix_tree_lookup(&pcs
->pgtree
, gselector
);
293 dev_err(pcs
->dev
, "%s could not find pingroup%i\n",
294 __func__
, gselector
);
298 *pins
= group
->gpins
;
299 *npins
= group
->ngpins
;
304 static void pcs_pin_dbg_show(struct pinctrl_dev
*pctldev
,
308 struct pcs_device
*pcs
;
309 unsigned val
, mux_bytes
;
311 pcs
= pinctrl_dev_get_drvdata(pctldev
);
313 mux_bytes
= pcs
->width
/ BITS_PER_BYTE
;
314 val
= pcs
->read(pcs
->base
+ pin
* mux_bytes
);
316 seq_printf(s
, "%08x %s " , val
, DRIVER_NAME
);
319 static void pcs_dt_free_map(struct pinctrl_dev
*pctldev
,
320 struct pinctrl_map
*map
, unsigned num_maps
)
322 struct pcs_device
*pcs
;
324 pcs
= pinctrl_dev_get_drvdata(pctldev
);
325 devm_kfree(pcs
->dev
, map
);
328 static int pcs_dt_node_to_map(struct pinctrl_dev
*pctldev
,
329 struct device_node
*np_config
,
330 struct pinctrl_map
**map
, unsigned *num_maps
);
332 static const struct pinctrl_ops pcs_pinctrl_ops
= {
333 .get_groups_count
= pcs_get_groups_count
,
334 .get_group_name
= pcs_get_group_name
,
335 .get_group_pins
= pcs_get_group_pins
,
336 .pin_dbg_show
= pcs_pin_dbg_show
,
337 .dt_node_to_map
= pcs_dt_node_to_map
,
338 .dt_free_map
= pcs_dt_free_map
,
341 static int pcs_get_functions_count(struct pinctrl_dev
*pctldev
)
343 struct pcs_device
*pcs
;
345 pcs
= pinctrl_dev_get_drvdata(pctldev
);
350 static const char *pcs_get_function_name(struct pinctrl_dev
*pctldev
,
353 struct pcs_device
*pcs
;
354 struct pcs_function
*func
;
356 pcs
= pinctrl_dev_get_drvdata(pctldev
);
357 func
= radix_tree_lookup(&pcs
->ftree
, fselector
);
359 dev_err(pcs
->dev
, "%s could not find function%i\n",
360 __func__
, fselector
);
367 static int pcs_get_function_groups(struct pinctrl_dev
*pctldev
,
369 const char * const **groups
,
370 unsigned * const ngroups
)
372 struct pcs_device
*pcs
;
373 struct pcs_function
*func
;
375 pcs
= pinctrl_dev_get_drvdata(pctldev
);
376 func
= radix_tree_lookup(&pcs
->ftree
, fselector
);
378 dev_err(pcs
->dev
, "%s could not find function%i\n",
379 __func__
, fselector
);
382 *groups
= func
->pgnames
;
383 *ngroups
= func
->npgnames
;
388 static int pcs_get_function(struct pinctrl_dev
*pctldev
, unsigned pin
,
389 struct pcs_function
**func
)
391 struct pcs_device
*pcs
= pinctrl_dev_get_drvdata(pctldev
);
392 struct pin_desc
*pdesc
= pin_desc_get(pctldev
, pin
);
393 const struct pinctrl_setting_mux
*setting
;
396 /* If pin is not described in DTS & enabled, mux_setting is NULL. */
397 setting
= pdesc
->mux_setting
;
400 fselector
= setting
->func
;
401 *func
= radix_tree_lookup(&pcs
->ftree
, fselector
);
403 dev_err(pcs
->dev
, "%s could not find function%i\n",
404 __func__
, fselector
);
410 static int pcs_enable(struct pinctrl_dev
*pctldev
, unsigned fselector
,
413 struct pcs_device
*pcs
;
414 struct pcs_function
*func
;
417 pcs
= pinctrl_dev_get_drvdata(pctldev
);
418 /* If function mask is null, needn't enable it. */
421 func
= radix_tree_lookup(&pcs
->ftree
, fselector
);
425 dev_dbg(pcs
->dev
, "enabling %s function%i\n",
426 func
->name
, fselector
);
428 for (i
= 0; i
< func
->nvals
; i
++) {
429 struct pcs_func_vals
*vals
;
432 vals
= &func
->vals
[i
];
433 val
= pcs
->read(vals
->reg
);
437 mask
= pcs
->fmask
& vals
->mask
;
440 val
|= (vals
->val
& mask
);
441 pcs
->write(val
, vals
->reg
);
447 static void pcs_disable(struct pinctrl_dev
*pctldev
, unsigned fselector
,
450 struct pcs_device
*pcs
;
451 struct pcs_function
*func
;
454 pcs
= pinctrl_dev_get_drvdata(pctldev
);
455 /* If function mask is null, needn't disable it. */
459 func
= radix_tree_lookup(&pcs
->ftree
, fselector
);
461 dev_err(pcs
->dev
, "%s could not find function%i\n",
462 __func__
, fselector
);
467 * Ignore disable if function-off is not specified. Some hardware
468 * does not have clearly defined disable function. For pin specific
469 * off modes, you can use alternate named states as described in
470 * pinctrl-bindings.txt.
472 if (pcs
->foff
== PCS_OFF_DISABLED
) {
473 dev_dbg(pcs
->dev
, "ignoring disable for %s function%i\n",
474 func
->name
, fselector
);
478 dev_dbg(pcs
->dev
, "disabling function%i %s\n",
479 fselector
, func
->name
);
481 for (i
= 0; i
< func
->nvals
; i
++) {
482 struct pcs_func_vals
*vals
;
485 vals
= &func
->vals
[i
];
486 val
= pcs
->read(vals
->reg
);
488 val
|= pcs
->foff
<< pcs
->fshift
;
489 pcs
->write(val
, vals
->reg
);
493 static int pcs_request_gpio(struct pinctrl_dev
*pctldev
,
494 struct pinctrl_gpio_range
*range
, unsigned pin
)
496 struct pcs_device
*pcs
= pinctrl_dev_get_drvdata(pctldev
);
497 struct pcs_gpiofunc_range
*frange
= NULL
;
498 struct list_head
*pos
, *tmp
;
502 /* If function mask is null, return directly. */
506 list_for_each_safe(pos
, tmp
, &pcs
->gpiofuncs
) {
507 frange
= list_entry(pos
, struct pcs_gpiofunc_range
, node
);
508 if (pin
>= frange
->offset
+ frange
->npins
509 || pin
< frange
->offset
)
511 mux_bytes
= pcs
->width
/ BITS_PER_BYTE
;
512 data
= pcs
->read(pcs
->base
+ pin
* mux_bytes
) & ~pcs
->fmask
;
513 data
|= frange
->gpiofunc
;
514 pcs
->write(data
, pcs
->base
+ pin
* mux_bytes
);
520 static const struct pinmux_ops pcs_pinmux_ops
= {
521 .get_functions_count
= pcs_get_functions_count
,
522 .get_function_name
= pcs_get_function_name
,
523 .get_function_groups
= pcs_get_function_groups
,
524 .enable
= pcs_enable
,
525 .disable
= pcs_disable
,
526 .gpio_request_enable
= pcs_request_gpio
,
529 /* Clear BIAS value */
530 static void pcs_pinconf_clear_bias(struct pinctrl_dev
*pctldev
, unsigned pin
)
532 unsigned long config
;
534 for (i
= 0; i
< ARRAY_SIZE(pcs_bias
); i
++) {
535 config
= pinconf_to_config_packed(pcs_bias
[i
], 0);
536 pcs_pinconf_set(pctldev
, pin
, config
);
541 * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
542 * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
544 static bool pcs_pinconf_bias_disable(struct pinctrl_dev
*pctldev
, unsigned pin
)
546 unsigned long config
;
549 for (i
= 0; i
< ARRAY_SIZE(pcs_bias
); i
++) {
550 config
= pinconf_to_config_packed(pcs_bias
[i
], 0);
551 if (!pcs_pinconf_get(pctldev
, pin
, &config
))
559 static int pcs_pinconf_get(struct pinctrl_dev
*pctldev
,
560 unsigned pin
, unsigned long *config
)
562 struct pcs_device
*pcs
= pinctrl_dev_get_drvdata(pctldev
);
563 struct pcs_function
*func
;
564 enum pin_config_param param
;
565 unsigned offset
= 0, data
= 0, i
, j
, ret
;
567 ret
= pcs_get_function(pctldev
, pin
, &func
);
571 for (i
= 0; i
< func
->nconfs
; i
++) {
572 param
= pinconf_to_config_param(*config
);
573 if (param
== PIN_CONFIG_BIAS_DISABLE
) {
574 if (pcs_pinconf_bias_disable(pctldev
, pin
)) {
580 } else if (param
!= func
->conf
[i
].param
) {
584 offset
= pin
* (pcs
->width
/ BITS_PER_BYTE
);
585 data
= pcs
->read(pcs
->base
+ offset
) & func
->conf
[i
].mask
;
586 switch (func
->conf
[i
].param
) {
588 case PIN_CONFIG_BIAS_PULL_DOWN
:
589 case PIN_CONFIG_BIAS_PULL_UP
:
590 case PIN_CONFIG_INPUT_SCHMITT_ENABLE
:
591 if ((data
!= func
->conf
[i
].enable
) ||
592 (data
== func
->conf
[i
].disable
))
597 case PIN_CONFIG_INPUT_SCHMITT
:
598 for (j
= 0; j
< func
->nconfs
; j
++) {
599 switch (func
->conf
[j
].param
) {
600 case PIN_CONFIG_INPUT_SCHMITT_ENABLE
:
601 if (data
!= func
->conf
[j
].enable
)
610 case PIN_CONFIG_DRIVE_STRENGTH
:
611 case PIN_CONFIG_SLEW_RATE
:
621 static int pcs_pinconf_set(struct pinctrl_dev
*pctldev
,
622 unsigned pin
, unsigned long config
)
624 struct pcs_device
*pcs
= pinctrl_dev_get_drvdata(pctldev
);
625 struct pcs_function
*func
;
626 unsigned offset
= 0, shift
= 0, i
, data
, ret
;
629 ret
= pcs_get_function(pctldev
, pin
, &func
);
633 for (i
= 0; i
< func
->nconfs
; i
++) {
634 if (pinconf_to_config_param(config
) == func
->conf
[i
].param
) {
635 offset
= pin
* (pcs
->width
/ BITS_PER_BYTE
);
636 data
= pcs
->read(pcs
->base
+ offset
);
637 arg
= pinconf_to_config_argument(config
);
638 switch (func
->conf
[i
].param
) {
640 case PIN_CONFIG_INPUT_SCHMITT
:
641 case PIN_CONFIG_DRIVE_STRENGTH
:
642 case PIN_CONFIG_SLEW_RATE
:
643 shift
= ffs(func
->conf
[i
].mask
) - 1;
644 data
&= ~func
->conf
[i
].mask
;
645 data
|= (arg
<< shift
) & func
->conf
[i
].mask
;
648 case PIN_CONFIG_BIAS_DISABLE
:
649 pcs_pinconf_clear_bias(pctldev
, pin
);
651 case PIN_CONFIG_BIAS_PULL_DOWN
:
652 case PIN_CONFIG_BIAS_PULL_UP
:
654 pcs_pinconf_clear_bias(pctldev
, pin
);
656 case PIN_CONFIG_INPUT_SCHMITT_ENABLE
:
657 data
&= ~func
->conf
[i
].mask
;
659 data
|= func
->conf
[i
].enable
;
661 data
|= func
->conf
[i
].disable
;
666 pcs
->write(data
, pcs
->base
+ offset
);
673 static int pcs_pinconf_group_get(struct pinctrl_dev
*pctldev
,
674 unsigned group
, unsigned long *config
)
676 const unsigned *pins
;
677 unsigned npins
, old
= 0;
680 ret
= pcs_get_group_pins(pctldev
, group
, &pins
, &npins
);
683 for (i
= 0; i
< npins
; i
++) {
684 if (pcs_pinconf_get(pctldev
, pins
[i
], config
))
686 /* configs do not match between two pins */
687 if (i
&& (old
!= *config
))
694 static int pcs_pinconf_group_set(struct pinctrl_dev
*pctldev
,
695 unsigned group
, unsigned long config
)
697 const unsigned *pins
;
701 ret
= pcs_get_group_pins(pctldev
, group
, &pins
, &npins
);
704 for (i
= 0; i
< npins
; i
++) {
705 if (pcs_pinconf_set(pctldev
, pins
[i
], config
))
711 static void pcs_pinconf_dbg_show(struct pinctrl_dev
*pctldev
,
712 struct seq_file
*s
, unsigned pin
)
716 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev
*pctldev
,
717 struct seq_file
*s
, unsigned selector
)
721 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev
*pctldev
,
723 unsigned long config
)
725 pinconf_generic_dump_config(pctldev
, s
, config
);
728 static const struct pinconf_ops pcs_pinconf_ops
= {
729 .pin_config_get
= pcs_pinconf_get
,
730 .pin_config_set
= pcs_pinconf_set
,
731 .pin_config_group_get
= pcs_pinconf_group_get
,
732 .pin_config_group_set
= pcs_pinconf_group_set
,
733 .pin_config_dbg_show
= pcs_pinconf_dbg_show
,
734 .pin_config_group_dbg_show
= pcs_pinconf_group_dbg_show
,
735 .pin_config_config_dbg_show
= pcs_pinconf_config_dbg_show
,
740 * pcs_add_pin() - add a pin to the static per controller pin array
741 * @pcs: pcs driver instance
742 * @offset: register offset from base
744 static int pcs_add_pin(struct pcs_device
*pcs
, unsigned offset
)
746 struct pinctrl_pin_desc
*pin
;
751 if (i
>= pcs
->desc
.npins
) {
752 dev_err(pcs
->dev
, "too many pins, max %i\n",
757 pin
= &pcs
->pins
.pa
[i
];
759 sprintf(pn
->name
, "%lx",
760 (unsigned long)pcs
->res
->start
+ offset
);
761 pin
->name
= pn
->name
;
769 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
770 * @pcs: pcs driver instance
772 * In case of errors, resources are freed in pcs_free_resources.
774 * If your hardware needs holes in the address space, then just set
775 * up multiple driver instances.
777 static int pcs_allocate_pin_table(struct pcs_device
*pcs
)
779 int mux_bytes
, nr_pins
, i
;
781 mux_bytes
= pcs
->width
/ BITS_PER_BYTE
;
782 nr_pins
= pcs
->size
/ mux_bytes
;
784 dev_dbg(pcs
->dev
, "allocating %i pins\n", nr_pins
);
785 pcs
->pins
.pa
= devm_kzalloc(pcs
->dev
,
786 sizeof(*pcs
->pins
.pa
) * nr_pins
,
791 pcs
->names
= devm_kzalloc(pcs
->dev
,
792 sizeof(struct pcs_name
) * nr_pins
,
797 pcs
->desc
.pins
= pcs
->pins
.pa
;
798 pcs
->desc
.npins
= nr_pins
;
800 for (i
= 0; i
< pcs
->desc
.npins
; i
++) {
804 offset
= i
* mux_bytes
;
805 res
= pcs_add_pin(pcs
, offset
);
807 dev_err(pcs
->dev
, "error adding pins: %i\n", res
);
816 * pcs_add_function() - adds a new function to the function list
817 * @pcs: pcs driver instance
818 * @np: device node of the mux entry
819 * @name: name of the function
820 * @vals: array of mux register value pairs used by the function
821 * @nvals: number of mux register value pairs
822 * @pgnames: array of pingroup names for the function
823 * @npgnames: number of pingroup names
825 static struct pcs_function
*pcs_add_function(struct pcs_device
*pcs
,
826 struct device_node
*np
,
828 struct pcs_func_vals
*vals
,
830 const char **pgnames
,
833 struct pcs_function
*function
;
835 function
= devm_kzalloc(pcs
->dev
, sizeof(*function
), GFP_KERNEL
);
839 function
->name
= name
;
840 function
->vals
= vals
;
841 function
->nvals
= nvals
;
842 function
->pgnames
= pgnames
;
843 function
->npgnames
= npgnames
;
845 mutex_lock(&pcs
->mutex
);
846 list_add_tail(&function
->node
, &pcs
->functions
);
847 radix_tree_insert(&pcs
->ftree
, pcs
->nfuncs
, function
);
849 mutex_unlock(&pcs
->mutex
);
854 static void pcs_remove_function(struct pcs_device
*pcs
,
855 struct pcs_function
*function
)
859 mutex_lock(&pcs
->mutex
);
860 for (i
= 0; i
< pcs
->nfuncs
; i
++) {
861 struct pcs_function
*found
;
863 found
= radix_tree_lookup(&pcs
->ftree
, i
);
864 if (found
== function
)
865 radix_tree_delete(&pcs
->ftree
, i
);
867 list_del(&function
->node
);
868 mutex_unlock(&pcs
->mutex
);
872 * pcs_add_pingroup() - add a pingroup to the pingroup list
873 * @pcs: pcs driver instance
874 * @np: device node of the mux entry
875 * @name: name of the pingroup
876 * @gpins: array of the pins that belong to the group
877 * @ngpins: number of pins in the group
879 static int pcs_add_pingroup(struct pcs_device
*pcs
,
880 struct device_node
*np
,
885 struct pcs_pingroup
*pingroup
;
887 pingroup
= devm_kzalloc(pcs
->dev
, sizeof(*pingroup
), GFP_KERNEL
);
891 pingroup
->name
= name
;
893 pingroup
->gpins
= gpins
;
894 pingroup
->ngpins
= ngpins
;
896 mutex_lock(&pcs
->mutex
);
897 list_add_tail(&pingroup
->node
, &pcs
->pingroups
);
898 radix_tree_insert(&pcs
->pgtree
, pcs
->ngroups
, pingroup
);
900 mutex_unlock(&pcs
->mutex
);
906 * pcs_get_pin_by_offset() - get a pin index based on the register offset
907 * @pcs: pcs driver instance
908 * @offset: register offset from the base
910 * Note that this is OK as long as the pins are in a static array.
912 static int pcs_get_pin_by_offset(struct pcs_device
*pcs
, unsigned offset
)
916 if (offset
>= pcs
->size
) {
917 dev_err(pcs
->dev
, "mux offset out of range: 0x%x (0x%x)\n",
922 index
= offset
/ (pcs
->width
/ BITS_PER_BYTE
);
928 * check whether data matches enable bits or disable bits
929 * Return value: 1 for matching enable bits, 0 for matching disable bits,
930 * and negative value for matching failure.
932 static int pcs_config_match(unsigned data
, unsigned enable
, unsigned disable
)
938 else if (data
== disable
)
943 static void add_config(struct pcs_conf_vals
**conf
, enum pin_config_param param
,
944 unsigned value
, unsigned enable
, unsigned disable
,
947 (*conf
)->param
= param
;
948 (*conf
)->val
= value
;
949 (*conf
)->enable
= enable
;
950 (*conf
)->disable
= disable
;
951 (*conf
)->mask
= mask
;
955 static void add_setting(unsigned long **setting
, enum pin_config_param param
,
958 **setting
= pinconf_to_config_packed(param
, arg
);
962 /* add pinconf setting with 2 parameters */
963 static void pcs_add_conf2(struct pcs_device
*pcs
, struct device_node
*np
,
964 const char *name
, enum pin_config_param param
,
965 struct pcs_conf_vals
**conf
, unsigned long **settings
)
967 unsigned value
[2], shift
;
970 ret
= of_property_read_u32_array(np
, name
, value
, 2);
973 /* set value & mask */
974 value
[0] &= value
[1];
975 shift
= ffs(value
[1]) - 1;
976 /* skip enable & disable */
977 add_config(conf
, param
, value
[0], 0, 0, value
[1]);
978 add_setting(settings
, param
, value
[0] >> shift
);
981 /* add pinconf setting with 4 parameters */
982 static void pcs_add_conf4(struct pcs_device
*pcs
, struct device_node
*np
,
983 const char *name
, enum pin_config_param param
,
984 struct pcs_conf_vals
**conf
, unsigned long **settings
)
989 /* value to set, enable, disable, mask */
990 ret
= of_property_read_u32_array(np
, name
, value
, 4);
994 dev_err(pcs
->dev
, "mask field of the property can't be 0\n");
997 value
[0] &= value
[3];
998 value
[1] &= value
[3];
999 value
[2] &= value
[3];
1000 ret
= pcs_config_match(value
[0], value
[1], value
[2]);
1002 dev_dbg(pcs
->dev
, "failed to match enable or disable bits\n");
1003 add_config(conf
, param
, value
[0], value
[1], value
[2], value
[3]);
1004 add_setting(settings
, param
, ret
);
1007 static int pcs_parse_pinconf(struct pcs_device
*pcs
, struct device_node
*np
,
1008 struct pcs_function
*func
,
1009 struct pinctrl_map
**map
)
1012 struct pinctrl_map
*m
= *map
;
1013 int i
= 0, nconfs
= 0;
1014 unsigned long *settings
= NULL
, *s
= NULL
;
1015 struct pcs_conf_vals
*conf
= NULL
;
1016 struct pcs_conf_type prop2
[] = {
1017 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH
, },
1018 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE
, },
1019 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT
, },
1021 struct pcs_conf_type prop4
[] = {
1022 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP
, },
1023 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN
, },
1024 { "pinctrl-single,input-schmitt-enable",
1025 PIN_CONFIG_INPUT_SCHMITT_ENABLE
, },
1028 /* If pinconf isn't supported, don't parse properties in below. */
1029 if (!pcs
->is_pinconf
)
1032 /* cacluate how much properties are supported in current node */
1033 for (i
= 0; i
< ARRAY_SIZE(prop2
); i
++) {
1034 if (of_find_property(np
, prop2
[i
].name
, NULL
))
1037 for (i
= 0; i
< ARRAY_SIZE(prop4
); i
++) {
1038 if (of_find_property(np
, prop4
[i
].name
, NULL
))
1044 func
->conf
= devm_kzalloc(pcs
->dev
,
1045 sizeof(struct pcs_conf_vals
) * nconfs
,
1049 func
->nconfs
= nconfs
;
1050 conf
= &(func
->conf
[0]);
1052 settings
= devm_kzalloc(pcs
->dev
, sizeof(unsigned long) * nconfs
,
1058 for (i
= 0; i
< ARRAY_SIZE(prop2
); i
++)
1059 pcs_add_conf2(pcs
, np
, prop2
[i
].name
, prop2
[i
].param
,
1061 for (i
= 0; i
< ARRAY_SIZE(prop4
); i
++)
1062 pcs_add_conf4(pcs
, np
, prop4
[i
].name
, prop4
[i
].param
,
1064 m
->type
= PIN_MAP_TYPE_CONFIGS_GROUP
;
1065 m
->data
.configs
.group_or_pin
= np
->name
;
1066 m
->data
.configs
.configs
= settings
;
1067 m
->data
.configs
.num_configs
= nconfs
;
1071 static void pcs_free_pingroups(struct pcs_device
*pcs
);
1074 * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
1075 * @pcs: pinctrl driver instance
1076 * @np: device node of the mux entry
1078 * @num_maps: number of map
1079 * @pgnames: pingroup names
1081 * Note that this binding currently supports only sets of one register + value.
1083 * Also note that this driver tries to avoid understanding pin and function
1084 * names because of the extra bloat they would cause especially in the case of
1085 * a large number of pins. This driver just sets what is specified for the board
1086 * in the .dts file. Further user space debugging tools can be developed to
1087 * decipher the pin and function names using debugfs.
1089 * If you are concerned about the boot time, set up the static pins in
1090 * the bootloader, and only set up selected pins as device tree entries.
1092 static int pcs_parse_one_pinctrl_entry(struct pcs_device
*pcs
,
1093 struct device_node
*np
,
1094 struct pinctrl_map
**map
,
1096 const char **pgnames
)
1098 struct pcs_func_vals
*vals
;
1100 int size
, params
, rows
, *pins
, index
= 0, found
= 0, res
= -ENOMEM
;
1101 struct pcs_function
*function
;
1103 if (pcs
->bits_per_mux
) {
1105 mux
= of_get_property(np
, PCS_MUX_BITS_NAME
, &size
);
1108 mux
= of_get_property(np
, PCS_MUX_PINS_NAME
, &size
);
1112 dev_err(pcs
->dev
, "no valid property for %s\n", np
->name
);
1116 if (size
< (sizeof(*mux
) * params
)) {
1117 dev_err(pcs
->dev
, "bad data for %s\n", np
->name
);
1121 size
/= sizeof(*mux
); /* Number of elements in array */
1122 rows
= size
/ params
;
1124 vals
= devm_kzalloc(pcs
->dev
, sizeof(*vals
) * rows
, GFP_KERNEL
);
1128 pins
= devm_kzalloc(pcs
->dev
, sizeof(*pins
) * rows
, GFP_KERNEL
);
1132 while (index
< size
) {
1133 unsigned offset
, val
;
1136 offset
= be32_to_cpup(mux
+ index
++);
1137 val
= be32_to_cpup(mux
+ index
++);
1138 vals
[found
].reg
= pcs
->base
+ offset
;
1139 vals
[found
].val
= val
;
1141 val
= be32_to_cpup(mux
+ index
++);
1142 vals
[found
].mask
= val
;
1145 pin
= pcs_get_pin_by_offset(pcs
, offset
);
1148 "could not add functions for %s %ux\n",
1152 pins
[found
++] = pin
;
1155 pgnames
[0] = np
->name
;
1156 function
= pcs_add_function(pcs
, np
, np
->name
, vals
, found
, pgnames
, 1);
1160 res
= pcs_add_pingroup(pcs
, np
, np
->name
, pins
, found
);
1164 (*map
)->type
= PIN_MAP_TYPE_MUX_GROUP
;
1165 (*map
)->data
.mux
.group
= np
->name
;
1166 (*map
)->data
.mux
.function
= np
->name
;
1168 if (pcs
->is_pinconf
) {
1169 res
= pcs_parse_pinconf(pcs
, np
, function
, map
);
1171 goto free_pingroups
;
1179 pcs_free_pingroups(pcs
);
1182 pcs_remove_function(pcs
, function
);
1185 devm_kfree(pcs
->dev
, pins
);
1188 devm_kfree(pcs
->dev
, vals
);
1193 * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1194 * @pctldev: pinctrl instance
1195 * @np_config: device tree pinmux entry
1196 * @map: array of map entries
1197 * @num_maps: number of maps
1199 static int pcs_dt_node_to_map(struct pinctrl_dev
*pctldev
,
1200 struct device_node
*np_config
,
1201 struct pinctrl_map
**map
, unsigned *num_maps
)
1203 struct pcs_device
*pcs
;
1204 const char **pgnames
;
1207 pcs
= pinctrl_dev_get_drvdata(pctldev
);
1209 /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1210 *map
= devm_kzalloc(pcs
->dev
, sizeof(**map
) * 2, GFP_KERNEL
);
1216 pgnames
= devm_kzalloc(pcs
->dev
, sizeof(*pgnames
), GFP_KERNEL
);
1222 ret
= pcs_parse_one_pinctrl_entry(pcs
, np_config
, map
, num_maps
,
1225 dev_err(pcs
->dev
, "no pins entries for %s\n",
1233 devm_kfree(pcs
->dev
, pgnames
);
1235 devm_kfree(pcs
->dev
, *map
);
1241 * pcs_free_funcs() - free memory used by functions
1242 * @pcs: pcs driver instance
1244 static void pcs_free_funcs(struct pcs_device
*pcs
)
1246 struct list_head
*pos
, *tmp
;
1249 mutex_lock(&pcs
->mutex
);
1250 for (i
= 0; i
< pcs
->nfuncs
; i
++) {
1251 struct pcs_function
*func
;
1253 func
= radix_tree_lookup(&pcs
->ftree
, i
);
1256 radix_tree_delete(&pcs
->ftree
, i
);
1258 list_for_each_safe(pos
, tmp
, &pcs
->functions
) {
1259 struct pcs_function
*function
;
1261 function
= list_entry(pos
, struct pcs_function
, node
);
1262 list_del(&function
->node
);
1264 mutex_unlock(&pcs
->mutex
);
1268 * pcs_free_pingroups() - free memory used by pingroups
1269 * @pcs: pcs driver instance
1271 static void pcs_free_pingroups(struct pcs_device
*pcs
)
1273 struct list_head
*pos
, *tmp
;
1276 mutex_lock(&pcs
->mutex
);
1277 for (i
= 0; i
< pcs
->ngroups
; i
++) {
1278 struct pcs_pingroup
*pingroup
;
1280 pingroup
= radix_tree_lookup(&pcs
->pgtree
, i
);
1283 radix_tree_delete(&pcs
->pgtree
, i
);
1285 list_for_each_safe(pos
, tmp
, &pcs
->pingroups
) {
1286 struct pcs_pingroup
*pingroup
;
1288 pingroup
= list_entry(pos
, struct pcs_pingroup
, node
);
1289 list_del(&pingroup
->node
);
1291 mutex_unlock(&pcs
->mutex
);
1295 * pcs_free_resources() - free memory used by this driver
1296 * @pcs: pcs driver instance
1298 static void pcs_free_resources(struct pcs_device
*pcs
)
1301 pinctrl_unregister(pcs
->pctl
);
1303 pcs_free_funcs(pcs
);
1304 pcs_free_pingroups(pcs
);
1307 #define PCS_GET_PROP_U32(name, reg, err) \
1309 ret = of_property_read_u32(np, name, reg); \
1311 dev_err(pcs->dev, err); \
1316 static struct of_device_id pcs_of_match
[];
1318 static int pcs_add_gpio_func(struct device_node
*node
, struct pcs_device
*pcs
)
1320 const char *propname
= "pinctrl-single,gpio-range";
1321 const char *cellname
= "#pinctrl-single,gpio-range-cells";
1322 struct of_phandle_args gpiospec
;
1323 struct pcs_gpiofunc_range
*range
;
1326 for (i
= 0; ; i
++) {
1327 ret
= of_parse_phandle_with_args(node
, propname
, cellname
,
1329 /* Do not treat it as error. Only treat it as end condition. */
1334 range
= devm_kzalloc(pcs
->dev
, sizeof(*range
), GFP_KERNEL
);
1339 range
->offset
= gpiospec
.args
[0];
1340 range
->npins
= gpiospec
.args
[1];
1341 range
->gpiofunc
= gpiospec
.args
[2];
1342 mutex_lock(&pcs
->mutex
);
1343 list_add_tail(&range
->node
, &pcs
->gpiofuncs
);
1344 mutex_unlock(&pcs
->mutex
);
1349 static int pcs_probe(struct platform_device
*pdev
)
1351 struct device_node
*np
= pdev
->dev
.of_node
;
1352 const struct of_device_id
*match
;
1353 struct resource
*res
;
1354 struct pcs_device
*pcs
;
1357 match
= of_match_device(pcs_of_match
, &pdev
->dev
);
1361 pcs
= devm_kzalloc(&pdev
->dev
, sizeof(*pcs
), GFP_KERNEL
);
1363 dev_err(&pdev
->dev
, "could not allocate\n");
1366 pcs
->dev
= &pdev
->dev
;
1367 mutex_init(&pcs
->mutex
);
1368 INIT_LIST_HEAD(&pcs
->pingroups
);
1369 INIT_LIST_HEAD(&pcs
->functions
);
1370 INIT_LIST_HEAD(&pcs
->gpiofuncs
);
1371 pcs
->is_pinconf
= match
->data
;
1373 PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs
->width
,
1374 "register width not specified\n");
1376 ret
= of_property_read_u32(np
, "pinctrl-single,function-mask",
1379 pcs
->fshift
= ffs(pcs
->fmask
) - 1;
1380 pcs
->fmax
= pcs
->fmask
>> pcs
->fshift
;
1382 /* If mask property doesn't exist, function mux is invalid. */
1388 ret
= of_property_read_u32(np
, "pinctrl-single,function-off",
1391 pcs
->foff
= PCS_OFF_DISABLED
;
1393 pcs
->bits_per_mux
= of_property_read_bool(np
,
1394 "pinctrl-single,bit-per-mux");
1396 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1398 dev_err(pcs
->dev
, "could not get resource\n");
1402 pcs
->res
= devm_request_mem_region(pcs
->dev
, res
->start
,
1403 resource_size(res
), DRIVER_NAME
);
1405 dev_err(pcs
->dev
, "could not get mem_region\n");
1409 pcs
->size
= resource_size(pcs
->res
);
1410 pcs
->base
= devm_ioremap(pcs
->dev
, pcs
->res
->start
, pcs
->size
);
1412 dev_err(pcs
->dev
, "could not ioremap\n");
1416 INIT_RADIX_TREE(&pcs
->pgtree
, GFP_KERNEL
);
1417 INIT_RADIX_TREE(&pcs
->ftree
, GFP_KERNEL
);
1418 platform_set_drvdata(pdev
, pcs
);
1420 switch (pcs
->width
) {
1422 pcs
->read
= pcs_readb
;
1423 pcs
->write
= pcs_writeb
;
1426 pcs
->read
= pcs_readw
;
1427 pcs
->write
= pcs_writew
;
1430 pcs
->read
= pcs_readl
;
1431 pcs
->write
= pcs_writel
;
1437 pcs
->desc
.name
= DRIVER_NAME
;
1438 pcs
->desc
.pctlops
= &pcs_pinctrl_ops
;
1439 pcs
->desc
.pmxops
= &pcs_pinmux_ops
;
1440 if (pcs
->is_pinconf
)
1441 pcs
->desc
.confops
= &pcs_pinconf_ops
;
1442 pcs
->desc
.owner
= THIS_MODULE
;
1444 ret
= pcs_allocate_pin_table(pcs
);
1448 pcs
->pctl
= pinctrl_register(&pcs
->desc
, pcs
->dev
, pcs
);
1450 dev_err(pcs
->dev
, "could not register single pinctrl driver\n");
1455 ret
= pcs_add_gpio_func(np
, pcs
);
1459 dev_info(pcs
->dev
, "%i pins at pa %p size %u\n",
1460 pcs
->desc
.npins
, pcs
->base
, pcs
->size
);
1465 pcs_free_resources(pcs
);
1470 static int pcs_remove(struct platform_device
*pdev
)
1472 struct pcs_device
*pcs
= platform_get_drvdata(pdev
);
1477 pcs_free_resources(pcs
);
1482 static struct of_device_id pcs_of_match
[] = {
1483 { .compatible
= "pinctrl-single", .data
= (void *)false },
1484 { .compatible
= "pinconf-single", .data
= (void *)true },
1487 MODULE_DEVICE_TABLE(of
, pcs_of_match
);
1489 static struct platform_driver pcs_driver
= {
1491 .remove
= pcs_remove
,
1493 .owner
= THIS_MODULE
,
1494 .name
= DRIVER_NAME
,
1495 .of_match_table
= pcs_of_match
,
1499 module_platform_driver(pcs_driver
);
1501 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
1502 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
1503 MODULE_LICENSE("GPL v2");