2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 * We suspect that on some hardware no TX done interrupts are generated.
34 * This means recovery from netif_stop_queue only happens if the hw timer
35 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37 * If your hardware reliably generates tx done interrupts, then you can remove
38 * DEV_NEED_TIMERIRQ from the driver_data flags.
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic.
42 #define FORCEDETH_VERSION "0.64"
43 #define DRV_NAME "forcedeth"
45 #include <linux/module.h>
46 #include <linux/types.h>
47 #include <linux/pci.h>
48 #include <linux/interrupt.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/delay.h>
52 #include <linux/sched.h>
53 #include <linux/spinlock.h>
54 #include <linux/ethtool.h>
55 #include <linux/timer.h>
56 #include <linux/skbuff.h>
57 #include <linux/mii.h>
58 #include <linux/random.h>
59 #include <linux/init.h>
60 #include <linux/if_vlan.h>
61 #include <linux/dma-mapping.h>
62 #include <linux/slab.h>
66 #include <asm/uaccess.h>
67 #include <asm/system.h>
70 #define dprintk printk
72 #define dprintk(x...) do { } while (0)
75 #define TX_WORK_PER_LOOP 64
76 #define RX_WORK_PER_LOOP 64
82 #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
83 #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
84 #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
85 #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
86 #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
87 #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
88 #define DEV_HAS_MSI 0x0000040 /* device supports MSI */
89 #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
90 #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
91 #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
92 #define DEV_HAS_STATISTICS_V2 0x0000600 /* device supports hw statistics version 2 */
93 #define DEV_HAS_STATISTICS_V3 0x0000e00 /* device supports hw statistics version 3 */
94 #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
95 #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
96 #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
97 #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
98 #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
99 #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
100 #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
101 #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
102 #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
103 #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
104 #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
105 #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
106 #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
109 NvRegIrqStatus
= 0x000,
110 #define NVREG_IRQSTAT_MIIEVENT 0x040
111 #define NVREG_IRQSTAT_MASK 0x83ff
112 NvRegIrqMask
= 0x004,
113 #define NVREG_IRQ_RX_ERROR 0x0001
114 #define NVREG_IRQ_RX 0x0002
115 #define NVREG_IRQ_RX_NOBUF 0x0004
116 #define NVREG_IRQ_TX_ERR 0x0008
117 #define NVREG_IRQ_TX_OK 0x0010
118 #define NVREG_IRQ_TIMER 0x0020
119 #define NVREG_IRQ_LINK 0x0040
120 #define NVREG_IRQ_RX_FORCED 0x0080
121 #define NVREG_IRQ_TX_FORCED 0x0100
122 #define NVREG_IRQ_RECOVER_ERROR 0x8200
123 #define NVREG_IRQMASK_THROUGHPUT 0x00df
124 #define NVREG_IRQMASK_CPU 0x0060
125 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
126 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
127 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
129 NvRegUnknownSetupReg6
= 0x008,
130 #define NVREG_UNKSETUP6_VAL 3
133 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
134 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
136 NvRegPollingInterval
= 0x00c,
137 #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
138 #define NVREG_POLL_DEFAULT_CPU 13
139 NvRegMSIMap0
= 0x020,
140 NvRegMSIMap1
= 0x024,
141 NvRegMSIIrqMask
= 0x030,
142 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
144 #define NVREG_MISC1_PAUSE_TX 0x01
145 #define NVREG_MISC1_HD 0x02
146 #define NVREG_MISC1_FORCE 0x3b0f3c
148 NvRegMacReset
= 0x34,
149 #define NVREG_MAC_RESET_ASSERT 0x0F3
150 NvRegTransmitterControl
= 0x084,
151 #define NVREG_XMITCTL_START 0x01
152 #define NVREG_XMITCTL_MGMT_ST 0x40000000
153 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
154 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
155 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
156 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
157 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
158 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
159 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
160 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
161 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
162 #define NVREG_XMITCTL_DATA_START 0x00100000
163 #define NVREG_XMITCTL_DATA_READY 0x00010000
164 #define NVREG_XMITCTL_DATA_ERROR 0x00020000
165 NvRegTransmitterStatus
= 0x088,
166 #define NVREG_XMITSTAT_BUSY 0x01
168 NvRegPacketFilterFlags
= 0x8c,
169 #define NVREG_PFF_PAUSE_RX 0x08
170 #define NVREG_PFF_ALWAYS 0x7F0000
171 #define NVREG_PFF_PROMISC 0x80
172 #define NVREG_PFF_MYADDR 0x20
173 #define NVREG_PFF_LOOPBACK 0x10
175 NvRegOffloadConfig
= 0x90,
176 #define NVREG_OFFLOAD_HOMEPHY 0x601
177 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
178 NvRegReceiverControl
= 0x094,
179 #define NVREG_RCVCTL_START 0x01
180 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
181 NvRegReceiverStatus
= 0x98,
182 #define NVREG_RCVSTAT_BUSY 0x01
184 NvRegSlotTime
= 0x9c,
185 #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
186 #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
187 #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
188 #define NVREG_SLOTTIME_HALF 0x0000ff00
189 #define NVREG_SLOTTIME_DEFAULT 0x00007f00
190 #define NVREG_SLOTTIME_MASK 0x000000ff
192 NvRegTxDeferral
= 0xA0,
193 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
194 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
195 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
196 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
197 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
198 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
199 NvRegRxDeferral
= 0xA4,
200 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
201 NvRegMacAddrA
= 0xA8,
202 NvRegMacAddrB
= 0xAC,
203 NvRegMulticastAddrA
= 0xB0,
204 #define NVREG_MCASTADDRA_FORCE 0x01
205 NvRegMulticastAddrB
= 0xB4,
206 NvRegMulticastMaskA
= 0xB8,
207 #define NVREG_MCASTMASKA_NONE 0xffffffff
208 NvRegMulticastMaskB
= 0xBC,
209 #define NVREG_MCASTMASKB_NONE 0xffff
211 NvRegPhyInterface
= 0xC0,
212 #define PHY_RGMII 0x10000000
213 NvRegBackOffControl
= 0xC4,
214 #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
215 #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
216 #define NVREG_BKOFFCTRL_SELECT 24
217 #define NVREG_BKOFFCTRL_GEAR 12
219 NvRegTxRingPhysAddr
= 0x100,
220 NvRegRxRingPhysAddr
= 0x104,
221 NvRegRingSizes
= 0x108,
222 #define NVREG_RINGSZ_TXSHIFT 0
223 #define NVREG_RINGSZ_RXSHIFT 16
224 NvRegTransmitPoll
= 0x10c,
225 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
226 NvRegLinkSpeed
= 0x110,
227 #define NVREG_LINKSPEED_FORCE 0x10000
228 #define NVREG_LINKSPEED_10 1000
229 #define NVREG_LINKSPEED_100 100
230 #define NVREG_LINKSPEED_1000 50
231 #define NVREG_LINKSPEED_MASK (0xFFF)
232 NvRegUnknownSetupReg5
= 0x130,
233 #define NVREG_UNKSETUP5_BIT31 (1<<31)
234 NvRegTxWatermark
= 0x13c,
235 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
236 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
237 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
238 NvRegTxRxControl
= 0x144,
239 #define NVREG_TXRXCTL_KICK 0x0001
240 #define NVREG_TXRXCTL_BIT1 0x0002
241 #define NVREG_TXRXCTL_BIT2 0x0004
242 #define NVREG_TXRXCTL_IDLE 0x0008
243 #define NVREG_TXRXCTL_RESET 0x0010
244 #define NVREG_TXRXCTL_RXCHECK 0x0400
245 #define NVREG_TXRXCTL_DESC_1 0
246 #define NVREG_TXRXCTL_DESC_2 0x002100
247 #define NVREG_TXRXCTL_DESC_3 0xc02200
248 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
249 #define NVREG_TXRXCTL_VLANINS 0x00080
250 NvRegTxRingPhysAddrHigh
= 0x148,
251 NvRegRxRingPhysAddrHigh
= 0x14C,
252 NvRegTxPauseFrame
= 0x170,
253 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
254 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
255 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
256 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
257 NvRegTxPauseFrameLimit
= 0x174,
258 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
259 NvRegMIIStatus
= 0x180,
260 #define NVREG_MIISTAT_ERROR 0x0001
261 #define NVREG_MIISTAT_LINKCHANGE 0x0008
262 #define NVREG_MIISTAT_MASK_RW 0x0007
263 #define NVREG_MIISTAT_MASK_ALL 0x000f
264 NvRegMIIMask
= 0x184,
265 #define NVREG_MII_LINKCHANGE 0x0008
267 NvRegAdapterControl
= 0x188,
268 #define NVREG_ADAPTCTL_START 0x02
269 #define NVREG_ADAPTCTL_LINKUP 0x04
270 #define NVREG_ADAPTCTL_PHYVALID 0x40000
271 #define NVREG_ADAPTCTL_RUNNING 0x100000
272 #define NVREG_ADAPTCTL_PHYSHIFT 24
273 NvRegMIISpeed
= 0x18c,
274 #define NVREG_MIISPEED_BIT8 (1<<8)
275 #define NVREG_MIIDELAY 5
276 NvRegMIIControl
= 0x190,
277 #define NVREG_MIICTL_INUSE 0x08000
278 #define NVREG_MIICTL_WRITE 0x00400
279 #define NVREG_MIICTL_ADDRSHIFT 5
280 NvRegMIIData
= 0x194,
281 NvRegTxUnicast
= 0x1a0,
282 NvRegTxMulticast
= 0x1a4,
283 NvRegTxBroadcast
= 0x1a8,
284 NvRegWakeUpFlags
= 0x200,
285 #define NVREG_WAKEUPFLAGS_VAL 0x7770
286 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
287 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
288 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
289 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
290 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
291 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
292 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
293 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
294 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
295 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
297 NvRegMgmtUnitGetVersion
= 0x204,
298 #define NVREG_MGMTUNITGETVERSION 0x01
299 NvRegMgmtUnitVersion
= 0x208,
300 #define NVREG_MGMTUNITVERSION 0x08
301 NvRegPowerCap
= 0x268,
302 #define NVREG_POWERCAP_D3SUPP (1<<30)
303 #define NVREG_POWERCAP_D2SUPP (1<<26)
304 #define NVREG_POWERCAP_D1SUPP (1<<25)
305 NvRegPowerState
= 0x26c,
306 #define NVREG_POWERSTATE_POWEREDUP 0x8000
307 #define NVREG_POWERSTATE_VALID 0x0100
308 #define NVREG_POWERSTATE_MASK 0x0003
309 #define NVREG_POWERSTATE_D0 0x0000
310 #define NVREG_POWERSTATE_D1 0x0001
311 #define NVREG_POWERSTATE_D2 0x0002
312 #define NVREG_POWERSTATE_D3 0x0003
313 NvRegMgmtUnitControl
= 0x278,
314 #define NVREG_MGMTUNITCONTROL_INUSE 0x20000
316 NvRegTxZeroReXmt
= 0x284,
317 NvRegTxOneReXmt
= 0x288,
318 NvRegTxManyReXmt
= 0x28c,
319 NvRegTxLateCol
= 0x290,
320 NvRegTxUnderflow
= 0x294,
321 NvRegTxLossCarrier
= 0x298,
322 NvRegTxExcessDef
= 0x29c,
323 NvRegTxRetryErr
= 0x2a0,
324 NvRegRxFrameErr
= 0x2a4,
325 NvRegRxExtraByte
= 0x2a8,
326 NvRegRxLateCol
= 0x2ac,
328 NvRegRxFrameTooLong
= 0x2b4,
329 NvRegRxOverflow
= 0x2b8,
330 NvRegRxFCSErr
= 0x2bc,
331 NvRegRxFrameAlignErr
= 0x2c0,
332 NvRegRxLenErr
= 0x2c4,
333 NvRegRxUnicast
= 0x2c8,
334 NvRegRxMulticast
= 0x2cc,
335 NvRegRxBroadcast
= 0x2d0,
337 NvRegTxFrame
= 0x2d8,
339 NvRegTxPause
= 0x2e0,
340 NvRegRxPause
= 0x2e4,
341 NvRegRxDropFrame
= 0x2e8,
342 NvRegVlanControl
= 0x300,
343 #define NVREG_VLANCONTROL_ENABLE 0x2000
344 NvRegMSIXMap0
= 0x3e0,
345 NvRegMSIXMap1
= 0x3e4,
346 NvRegMSIXIrqStatus
= 0x3f0,
348 NvRegPowerState2
= 0x600,
349 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
350 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
351 #define NVREG_POWERSTATE2_PHY_RESET 0x0004
352 #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
355 /* Big endian: should work, but is untested */
361 struct ring_desc_ex
{
369 struct ring_desc
* orig
;
370 struct ring_desc_ex
* ex
;
373 #define FLAG_MASK_V1 0xffff0000
374 #define FLAG_MASK_V2 0xffffc000
375 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
376 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
378 #define NV_TX_LASTPACKET (1<<16)
379 #define NV_TX_RETRYERROR (1<<19)
380 #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
381 #define NV_TX_FORCED_INTERRUPT (1<<24)
382 #define NV_TX_DEFERRED (1<<26)
383 #define NV_TX_CARRIERLOST (1<<27)
384 #define NV_TX_LATECOLLISION (1<<28)
385 #define NV_TX_UNDERFLOW (1<<29)
386 #define NV_TX_ERROR (1<<30)
387 #define NV_TX_VALID (1<<31)
389 #define NV_TX2_LASTPACKET (1<<29)
390 #define NV_TX2_RETRYERROR (1<<18)
391 #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
392 #define NV_TX2_FORCED_INTERRUPT (1<<30)
393 #define NV_TX2_DEFERRED (1<<25)
394 #define NV_TX2_CARRIERLOST (1<<26)
395 #define NV_TX2_LATECOLLISION (1<<27)
396 #define NV_TX2_UNDERFLOW (1<<28)
397 /* error and valid are the same for both */
398 #define NV_TX2_ERROR (1<<30)
399 #define NV_TX2_VALID (1<<31)
400 #define NV_TX2_TSO (1<<28)
401 #define NV_TX2_TSO_SHIFT 14
402 #define NV_TX2_TSO_MAX_SHIFT 14
403 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
404 #define NV_TX2_CHECKSUM_L3 (1<<27)
405 #define NV_TX2_CHECKSUM_L4 (1<<26)
407 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
409 #define NV_RX_DESCRIPTORVALID (1<<16)
410 #define NV_RX_MISSEDFRAME (1<<17)
411 #define NV_RX_SUBSTRACT1 (1<<18)
412 #define NV_RX_ERROR1 (1<<23)
413 #define NV_RX_ERROR2 (1<<24)
414 #define NV_RX_ERROR3 (1<<25)
415 #define NV_RX_ERROR4 (1<<26)
416 #define NV_RX_CRCERR (1<<27)
417 #define NV_RX_OVERFLOW (1<<28)
418 #define NV_RX_FRAMINGERR (1<<29)
419 #define NV_RX_ERROR (1<<30)
420 #define NV_RX_AVAIL (1<<31)
421 #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
423 #define NV_RX2_CHECKSUMMASK (0x1C000000)
424 #define NV_RX2_CHECKSUM_IP (0x10000000)
425 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
426 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
427 #define NV_RX2_DESCRIPTORVALID (1<<29)
428 #define NV_RX2_SUBSTRACT1 (1<<25)
429 #define NV_RX2_ERROR1 (1<<18)
430 #define NV_RX2_ERROR2 (1<<19)
431 #define NV_RX2_ERROR3 (1<<20)
432 #define NV_RX2_ERROR4 (1<<21)
433 #define NV_RX2_CRCERR (1<<22)
434 #define NV_RX2_OVERFLOW (1<<23)
435 #define NV_RX2_FRAMINGERR (1<<24)
436 /* error and avail are the same for both */
437 #define NV_RX2_ERROR (1<<30)
438 #define NV_RX2_AVAIL (1<<31)
439 #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
441 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
442 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
444 /* Miscelaneous hardware related defines: */
445 #define NV_PCI_REGSZ_VER1 0x270
446 #define NV_PCI_REGSZ_VER2 0x2d4
447 #define NV_PCI_REGSZ_VER3 0x604
448 #define NV_PCI_REGSZ_MAX 0x604
450 /* various timeout delays: all in usec */
451 #define NV_TXRX_RESET_DELAY 4
452 #define NV_TXSTOP_DELAY1 10
453 #define NV_TXSTOP_DELAY1MAX 500000
454 #define NV_TXSTOP_DELAY2 100
455 #define NV_RXSTOP_DELAY1 10
456 #define NV_RXSTOP_DELAY1MAX 500000
457 #define NV_RXSTOP_DELAY2 100
458 #define NV_SETUP5_DELAY 5
459 #define NV_SETUP5_DELAYMAX 50000
460 #define NV_POWERUP_DELAY 5
461 #define NV_POWERUP_DELAYMAX 5000
462 #define NV_MIIBUSY_DELAY 50
463 #define NV_MIIPHY_DELAY 10
464 #define NV_MIIPHY_DELAYMAX 10000
465 #define NV_MAC_RESET_DELAY 64
467 #define NV_WAKEUPPATTERNS 5
468 #define NV_WAKEUPMASKENTRIES 4
470 /* General driver defaults */
471 #define NV_WATCHDOG_TIMEO (5*HZ)
473 #define RX_RING_DEFAULT 512
474 #define TX_RING_DEFAULT 256
475 #define RX_RING_MIN 128
476 #define TX_RING_MIN 64
477 #define RING_MAX_DESC_VER_1 1024
478 #define RING_MAX_DESC_VER_2_3 16384
480 /* rx/tx mac addr + type + vlan + align + slack*/
481 #define NV_RX_HEADERS (64)
482 /* even more slack. */
483 #define NV_RX_ALLOC_PAD (64)
485 /* maximum mtu size */
486 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
487 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
489 #define OOM_REFILL (1+HZ/20)
490 #define POLL_WAIT (1+HZ/100)
491 #define LINK_TIMEOUT (3*HZ)
492 #define STATS_INTERVAL (10*HZ)
496 * The nic supports three different descriptor types:
497 * - DESC_VER_1: Original
498 * - DESC_VER_2: support for jumbo frames.
499 * - DESC_VER_3: 64-bit format.
506 #define PHY_OUI_MARVELL 0x5043
507 #define PHY_OUI_CICADA 0x03f1
508 #define PHY_OUI_VITESSE 0x01c1
509 #define PHY_OUI_REALTEK 0x0732
510 #define PHY_OUI_REALTEK2 0x0020
511 #define PHYID1_OUI_MASK 0x03ff
512 #define PHYID1_OUI_SHFT 6
513 #define PHYID2_OUI_MASK 0xfc00
514 #define PHYID2_OUI_SHFT 10
515 #define PHYID2_MODEL_MASK 0x03f0
516 #define PHY_MODEL_REALTEK_8211 0x0110
517 #define PHY_REV_MASK 0x0001
518 #define PHY_REV_REALTEK_8211B 0x0000
519 #define PHY_REV_REALTEK_8211C 0x0001
520 #define PHY_MODEL_REALTEK_8201 0x0200
521 #define PHY_MODEL_MARVELL_E3016 0x0220
522 #define PHY_MARVELL_E3016_INITMASK 0x0300
523 #define PHY_CICADA_INIT1 0x0f000
524 #define PHY_CICADA_INIT2 0x0e00
525 #define PHY_CICADA_INIT3 0x01000
526 #define PHY_CICADA_INIT4 0x0200
527 #define PHY_CICADA_INIT5 0x0004
528 #define PHY_CICADA_INIT6 0x02000
529 #define PHY_VITESSE_INIT_REG1 0x1f
530 #define PHY_VITESSE_INIT_REG2 0x10
531 #define PHY_VITESSE_INIT_REG3 0x11
532 #define PHY_VITESSE_INIT_REG4 0x12
533 #define PHY_VITESSE_INIT_MSK1 0xc
534 #define PHY_VITESSE_INIT_MSK2 0x0180
535 #define PHY_VITESSE_INIT1 0x52b5
536 #define PHY_VITESSE_INIT2 0xaf8a
537 #define PHY_VITESSE_INIT3 0x8
538 #define PHY_VITESSE_INIT4 0x8f8a
539 #define PHY_VITESSE_INIT5 0xaf86
540 #define PHY_VITESSE_INIT6 0x8f86
541 #define PHY_VITESSE_INIT7 0xaf82
542 #define PHY_VITESSE_INIT8 0x0100
543 #define PHY_VITESSE_INIT9 0x8f82
544 #define PHY_VITESSE_INIT10 0x0
545 #define PHY_REALTEK_INIT_REG1 0x1f
546 #define PHY_REALTEK_INIT_REG2 0x19
547 #define PHY_REALTEK_INIT_REG3 0x13
548 #define PHY_REALTEK_INIT_REG4 0x14
549 #define PHY_REALTEK_INIT_REG5 0x18
550 #define PHY_REALTEK_INIT_REG6 0x11
551 #define PHY_REALTEK_INIT_REG7 0x01
552 #define PHY_REALTEK_INIT1 0x0000
553 #define PHY_REALTEK_INIT2 0x8e00
554 #define PHY_REALTEK_INIT3 0x0001
555 #define PHY_REALTEK_INIT4 0xad17
556 #define PHY_REALTEK_INIT5 0xfb54
557 #define PHY_REALTEK_INIT6 0xf5c7
558 #define PHY_REALTEK_INIT7 0x1000
559 #define PHY_REALTEK_INIT8 0x0003
560 #define PHY_REALTEK_INIT9 0x0008
561 #define PHY_REALTEK_INIT10 0x0005
562 #define PHY_REALTEK_INIT11 0x0200
563 #define PHY_REALTEK_INIT_MSK1 0x0003
565 #define PHY_GIGABIT 0x0100
567 #define PHY_TIMEOUT 0x1
568 #define PHY_ERROR 0x2
572 #define PHY_HALF 0x100
574 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
575 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
576 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
577 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
578 #define NV_PAUSEFRAME_RX_REQ 0x0010
579 #define NV_PAUSEFRAME_TX_REQ 0x0020
580 #define NV_PAUSEFRAME_AUTONEG 0x0040
582 /* MSI/MSI-X defines */
583 #define NV_MSI_X_MAX_VECTORS 8
584 #define NV_MSI_X_VECTORS_MASK 0x000f
585 #define NV_MSI_CAPABLE 0x0010
586 #define NV_MSI_X_CAPABLE 0x0020
587 #define NV_MSI_ENABLED 0x0040
588 #define NV_MSI_X_ENABLED 0x0080
590 #define NV_MSI_X_VECTOR_ALL 0x0
591 #define NV_MSI_X_VECTOR_RX 0x0
592 #define NV_MSI_X_VECTOR_TX 0x1
593 #define NV_MSI_X_VECTOR_OTHER 0x2
595 #define NV_MSI_PRIV_OFFSET 0x68
596 #define NV_MSI_PRIV_VALUE 0xffffffff
598 #define NV_RESTART_TX 0x1
599 #define NV_RESTART_RX 0x2
601 #define NV_TX_LIMIT_COUNT 16
603 #define NV_DYNAMIC_THRESHOLD 4
604 #define NV_DYNAMIC_MAX_QUIET_COUNT 2048
607 struct nv_ethtool_str
{
608 char name
[ETH_GSTRING_LEN
];
611 static const struct nv_ethtool_str nv_estats_str
[] = {
616 { "tx_late_collision" },
617 { "tx_fifo_errors" },
618 { "tx_carrier_errors" },
619 { "tx_excess_deferral" },
620 { "tx_retry_error" },
621 { "rx_frame_error" },
623 { "rx_late_collision" },
625 { "rx_frame_too_long" },
626 { "rx_over_errors" },
628 { "rx_frame_align_error" },
629 { "rx_length_error" },
634 { "rx_errors_total" },
635 { "tx_errors_total" },
637 /* version 2 stats */
645 /* version 3 stats */
651 struct nv_ethtool_stats
{
656 u64 tx_late_collision
;
658 u64 tx_carrier_errors
;
659 u64 tx_excess_deferral
;
663 u64 rx_late_collision
;
665 u64 rx_frame_too_long
;
668 u64 rx_frame_align_error
;
677 /* version 2 stats */
685 /* version 3 stats */
691 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
692 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
693 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
696 #define NV_TEST_COUNT_BASE 3
697 #define NV_TEST_COUNT_EXTENDED 4
699 static const struct nv_ethtool_str nv_etests_str
[] = {
700 { "link (online/offline)" },
701 { "register (offline) " },
702 { "interrupt (offline) " },
703 { "loopback (offline) " }
706 struct register_test
{
711 static const struct register_test nv_registers_test
[] = {
712 { NvRegUnknownSetupReg6
, 0x01 },
713 { NvRegMisc1
, 0x03c },
714 { NvRegOffloadConfig
, 0x03ff },
715 { NvRegMulticastAddrA
, 0xffffffff },
716 { NvRegTxWatermark
, 0x0ff },
717 { NvRegWakeUpFlags
, 0x07777 },
724 unsigned int dma_len
:31;
725 unsigned int dma_single
:1;
726 struct ring_desc_ex
*first_tx_desc
;
727 struct nv_skb_map
*next_tx_ctx
;
732 * All hardware access under netdev_priv(dev)->lock, except the performance
734 * - rx is (pseudo-) lockless: it relies on the single-threading provided
735 * by the arch code for interrupts.
736 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
737 * needs netdev_priv(dev)->lock :-(
738 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
741 /* in dev: base, irq */
745 struct net_device
*dev
;
746 struct napi_struct napi
;
749 * Locking: spin_lock(&np->lock); */
750 struct nv_ethtool_stats estats
;
758 unsigned int phy_oui
;
759 unsigned int phy_model
;
760 unsigned int phy_rev
;
766 /* General data: RO fields */
767 dma_addr_t ring_addr
;
768 struct pci_dev
*pci_dev
;
785 /* rx specific fields.
786 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
788 union ring_type get_rx
, put_rx
, first_rx
, last_rx
;
789 struct nv_skb_map
*get_rx_ctx
, *put_rx_ctx
;
790 struct nv_skb_map
*first_rx_ctx
, *last_rx_ctx
;
791 struct nv_skb_map
*rx_skb
;
793 union ring_type rx_ring
;
794 unsigned int rx_buf_sz
;
795 unsigned int pkt_limit
;
796 struct timer_list oom_kick
;
797 struct timer_list nic_poll
;
798 struct timer_list stats_poll
;
802 /* media detection workaround.
803 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
806 unsigned long link_timeout
;
808 * tx specific fields.
810 union ring_type get_tx
, put_tx
, first_tx
, last_tx
;
811 struct nv_skb_map
*get_tx_ctx
, *put_tx_ctx
;
812 struct nv_skb_map
*first_tx_ctx
, *last_tx_ctx
;
813 struct nv_skb_map
*tx_skb
;
815 union ring_type tx_ring
;
819 u32 tx_pkts_in_progress
;
820 struct nv_skb_map
*tx_change_owner
;
821 struct nv_skb_map
*tx_end_flip
;
825 struct vlan_group
*vlangrp
;
827 /* msi/msi-x fields */
829 struct msix_entry msi_x_entry
[NV_MSI_X_MAX_VECTORS
];
834 /* power saved state */
835 u32 saved_config_space
[NV_PCI_REGSZ_MAX
/4];
837 /* for different msi-x irq type */
838 char name_rx
[IFNAMSIZ
+ 3]; /* -rx */
839 char name_tx
[IFNAMSIZ
+ 3]; /* -tx */
840 char name_other
[IFNAMSIZ
+ 6]; /* -other */
844 * Maximum number of loops until we assume that a bit in the irq mask
845 * is stuck. Overridable with module param.
847 static int max_interrupt_work
= 4;
850 * Optimization can be either throuput mode or cpu mode
852 * Throughput Mode: Every tx and rx packet will generate an interrupt.
853 * CPU Mode: Interrupts are controlled by a timer.
856 NV_OPTIMIZATION_MODE_THROUGHPUT
,
857 NV_OPTIMIZATION_MODE_CPU
,
858 NV_OPTIMIZATION_MODE_DYNAMIC
860 static int optimization_mode
= NV_OPTIMIZATION_MODE_DYNAMIC
;
863 * Poll interval for timer irq
865 * This interval determines how frequent an interrupt is generated.
866 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
867 * Min = 0, and Max = 65535
869 static int poll_interval
= -1;
878 static int msi
= NV_MSI_INT_ENABLED
;
884 NV_MSIX_INT_DISABLED
,
887 static int msix
= NV_MSIX_INT_ENABLED
;
893 NV_DMA_64BIT_DISABLED
,
896 static int dma_64bit
= NV_DMA_64BIT_ENABLED
;
899 * Crossover Detection
900 * Realtek 8201 phy + some OEM boards do not work properly.
903 NV_CROSSOVER_DETECTION_DISABLED
,
904 NV_CROSSOVER_DETECTION_ENABLED
906 static int phy_cross
= NV_CROSSOVER_DETECTION_DISABLED
;
909 * Power down phy when interface is down (persists through reboot;
910 * older Linux and other OSes may not power it up again)
912 static int phy_power_down
= 0;
914 static inline struct fe_priv
*get_nvpriv(struct net_device
*dev
)
916 return netdev_priv(dev
);
919 static inline u8 __iomem
*get_hwbase(struct net_device
*dev
)
921 return ((struct fe_priv
*)netdev_priv(dev
))->base
;
924 static inline void pci_push(u8 __iomem
*base
)
926 /* force out pending posted writes */
930 static inline u32
nv_descr_getlength(struct ring_desc
*prd
, u32 v
)
932 return le32_to_cpu(prd
->flaglen
)
933 & ((v
== DESC_VER_1
) ? LEN_MASK_V1
: LEN_MASK_V2
);
936 static inline u32
nv_descr_getlength_ex(struct ring_desc_ex
*prd
, u32 v
)
938 return le32_to_cpu(prd
->flaglen
) & LEN_MASK_V2
;
941 static bool nv_optimized(struct fe_priv
*np
)
943 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
948 static int reg_delay(struct net_device
*dev
, int offset
, u32 mask
, u32 target
,
949 int delay
, int delaymax
, const char *msg
)
951 u8 __iomem
*base
= get_hwbase(dev
);
962 } while ((readl(base
+ offset
) & mask
) != target
);
966 #define NV_SETUP_RX_RING 0x01
967 #define NV_SETUP_TX_RING 0x02
969 static inline u32
dma_low(dma_addr_t addr
)
974 static inline u32
dma_high(dma_addr_t addr
)
976 return addr
>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
979 static void setup_hw_rings(struct net_device
*dev
, int rxtx_flags
)
981 struct fe_priv
*np
= get_nvpriv(dev
);
982 u8 __iomem
*base
= get_hwbase(dev
);
984 if (!nv_optimized(np
)) {
985 if (rxtx_flags
& NV_SETUP_RX_RING
) {
986 writel(dma_low(np
->ring_addr
), base
+ NvRegRxRingPhysAddr
);
988 if (rxtx_flags
& NV_SETUP_TX_RING
) {
989 writel(dma_low(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc
)), base
+ NvRegTxRingPhysAddr
);
992 if (rxtx_flags
& NV_SETUP_RX_RING
) {
993 writel(dma_low(np
->ring_addr
), base
+ NvRegRxRingPhysAddr
);
994 writel(dma_high(np
->ring_addr
), base
+ NvRegRxRingPhysAddrHigh
);
996 if (rxtx_flags
& NV_SETUP_TX_RING
) {
997 writel(dma_low(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc_ex
)), base
+ NvRegTxRingPhysAddr
);
998 writel(dma_high(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc_ex
)), base
+ NvRegTxRingPhysAddrHigh
);
1003 static void free_rings(struct net_device
*dev
)
1005 struct fe_priv
*np
= get_nvpriv(dev
);
1007 if (!nv_optimized(np
)) {
1008 if (np
->rx_ring
.orig
)
1009 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
1010 np
->rx_ring
.orig
, np
->ring_addr
);
1013 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc_ex
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
1014 np
->rx_ring
.ex
, np
->ring_addr
);
1022 static int using_multi_irqs(struct net_device
*dev
)
1024 struct fe_priv
*np
= get_nvpriv(dev
);
1026 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
) ||
1027 ((np
->msi_flags
& NV_MSI_X_ENABLED
) &&
1028 ((np
->msi_flags
& NV_MSI_X_VECTORS_MASK
) == 0x1)))
1034 static void nv_txrx_gate(struct net_device
*dev
, bool gate
)
1036 struct fe_priv
*np
= get_nvpriv(dev
);
1037 u8 __iomem
*base
= get_hwbase(dev
);
1040 if (!np
->mac_in_use
&&
1041 (np
->driver_data
& DEV_HAS_POWER_CNTRL
)) {
1042 powerstate
= readl(base
+ NvRegPowerState2
);
1044 powerstate
|= NVREG_POWERSTATE2_GATE_CLOCKS
;
1046 powerstate
&= ~NVREG_POWERSTATE2_GATE_CLOCKS
;
1047 writel(powerstate
, base
+ NvRegPowerState2
);
1051 static void nv_enable_irq(struct net_device
*dev
)
1053 struct fe_priv
*np
= get_nvpriv(dev
);
1055 if (!using_multi_irqs(dev
)) {
1056 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1057 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1059 enable_irq(np
->pci_dev
->irq
);
1061 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1062 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
1063 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
1067 static void nv_disable_irq(struct net_device
*dev
)
1069 struct fe_priv
*np
= get_nvpriv(dev
);
1071 if (!using_multi_irqs(dev
)) {
1072 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1073 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1075 disable_irq(np
->pci_dev
->irq
);
1077 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1078 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
1079 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
1083 /* In MSIX mode, a write to irqmask behaves as XOR */
1084 static void nv_enable_hw_interrupts(struct net_device
*dev
, u32 mask
)
1086 u8 __iomem
*base
= get_hwbase(dev
);
1088 writel(mask
, base
+ NvRegIrqMask
);
1091 static void nv_disable_hw_interrupts(struct net_device
*dev
, u32 mask
)
1093 struct fe_priv
*np
= get_nvpriv(dev
);
1094 u8 __iomem
*base
= get_hwbase(dev
);
1096 if (np
->msi_flags
& NV_MSI_X_ENABLED
) {
1097 writel(mask
, base
+ NvRegIrqMask
);
1099 if (np
->msi_flags
& NV_MSI_ENABLED
)
1100 writel(0, base
+ NvRegMSIIrqMask
);
1101 writel(0, base
+ NvRegIrqMask
);
1105 static void nv_napi_enable(struct net_device
*dev
)
1107 #ifdef CONFIG_FORCEDETH_NAPI
1108 struct fe_priv
*np
= get_nvpriv(dev
);
1110 napi_enable(&np
->napi
);
1114 static void nv_napi_disable(struct net_device
*dev
)
1116 #ifdef CONFIG_FORCEDETH_NAPI
1117 struct fe_priv
*np
= get_nvpriv(dev
);
1119 napi_disable(&np
->napi
);
1123 #define MII_READ (-1)
1124 /* mii_rw: read/write a register on the PHY.
1126 * Caller must guarantee serialization
1128 static int mii_rw(struct net_device
*dev
, int addr
, int miireg
, int value
)
1130 u8 __iomem
*base
= get_hwbase(dev
);
1134 writel(NVREG_MIISTAT_MASK_RW
, base
+ NvRegMIIStatus
);
1136 reg
= readl(base
+ NvRegMIIControl
);
1137 if (reg
& NVREG_MIICTL_INUSE
) {
1138 writel(NVREG_MIICTL_INUSE
, base
+ NvRegMIIControl
);
1139 udelay(NV_MIIBUSY_DELAY
);
1142 reg
= (addr
<< NVREG_MIICTL_ADDRSHIFT
) | miireg
;
1143 if (value
!= MII_READ
) {
1144 writel(value
, base
+ NvRegMIIData
);
1145 reg
|= NVREG_MIICTL_WRITE
;
1147 writel(reg
, base
+ NvRegMIIControl
);
1149 if (reg_delay(dev
, NvRegMIIControl
, NVREG_MIICTL_INUSE
, 0,
1150 NV_MIIPHY_DELAY
, NV_MIIPHY_DELAYMAX
, NULL
)) {
1151 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d timed out.\n",
1152 dev
->name
, miireg
, addr
);
1154 } else if (value
!= MII_READ
) {
1155 /* it was a write operation - fewer failures are detectable */
1156 dprintk(KERN_DEBUG
"%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1157 dev
->name
, value
, miireg
, addr
);
1159 } else if (readl(base
+ NvRegMIIStatus
) & NVREG_MIISTAT_ERROR
) {
1160 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d failed.\n",
1161 dev
->name
, miireg
, addr
);
1164 retval
= readl(base
+ NvRegMIIData
);
1165 dprintk(KERN_DEBUG
"%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1166 dev
->name
, miireg
, addr
, retval
);
1172 static int phy_reset(struct net_device
*dev
, u32 bmcr_setup
)
1174 struct fe_priv
*np
= netdev_priv(dev
);
1176 unsigned int tries
= 0;
1178 miicontrol
= BMCR_RESET
| bmcr_setup
;
1179 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, miicontrol
)) {
1183 /* wait for 500ms */
1186 /* must wait till reset is deasserted */
1187 while (miicontrol
& BMCR_RESET
) {
1189 miicontrol
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1190 /* FIXME: 100 tries seem excessive */
1197 static int phy_init(struct net_device
*dev
)
1199 struct fe_priv
*np
= get_nvpriv(dev
);
1200 u8 __iomem
*base
= get_hwbase(dev
);
1201 u32 phyinterface
, phy_reserved
, mii_status
, mii_control
, mii_control_1000
,reg
;
1203 /* phy errata for E3016 phy */
1204 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
1205 reg
= mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, MII_READ
);
1206 reg
&= ~PHY_MARVELL_E3016_INITMASK
;
1207 if (mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, reg
)) {
1208 printk(KERN_INFO
"%s: phy write to errata reg failed.\n", pci_name(np
->pci_dev
));
1212 if (np
->phy_oui
== PHY_OUI_REALTEK
) {
1213 if (np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1214 np
->phy_rev
== PHY_REV_REALTEK_8211B
) {
1215 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1216 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1219 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, PHY_REALTEK_INIT2
)) {
1220 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1223 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
)) {
1224 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1227 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG3
, PHY_REALTEK_INIT4
)) {
1228 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1231 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG4
, PHY_REALTEK_INIT5
)) {
1232 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1235 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG5
, PHY_REALTEK_INIT6
)) {
1236 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1239 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1240 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1244 if (np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1245 np
->phy_rev
== PHY_REV_REALTEK_8211C
) {
1246 u32 powerstate
= readl(base
+ NvRegPowerState2
);
1248 /* need to perform hw phy reset */
1249 powerstate
|= NVREG_POWERSTATE2_PHY_RESET
;
1250 writel(powerstate
, base
+ NvRegPowerState2
);
1253 powerstate
&= ~NVREG_POWERSTATE2_PHY_RESET
;
1254 writel(powerstate
, base
+ NvRegPowerState2
);
1257 reg
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, MII_READ
);
1258 reg
|= PHY_REALTEK_INIT9
;
1259 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, reg
)) {
1260 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1263 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT10
)) {
1264 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1267 reg
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG7
, MII_READ
);
1268 if (!(reg
& PHY_REALTEK_INIT11
)) {
1269 reg
|= PHY_REALTEK_INIT11
;
1270 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG7
, reg
)) {
1271 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1275 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1276 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1280 if (np
->phy_model
== PHY_MODEL_REALTEK_8201
) {
1281 if (np
->driver_data
& DEV_NEED_PHY_INIT_FIX
) {
1282 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, MII_READ
);
1283 phy_reserved
|= PHY_REALTEK_INIT7
;
1284 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, phy_reserved
)) {
1285 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1292 /* set advertise register */
1293 reg
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
1294 reg
|= (ADVERTISE_10HALF
|ADVERTISE_10FULL
|ADVERTISE_100HALF
|ADVERTISE_100FULL
|ADVERTISE_PAUSE_ASYM
|ADVERTISE_PAUSE_CAP
);
1295 if (mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, reg
)) {
1296 printk(KERN_INFO
"%s: phy write to advertise failed.\n", pci_name(np
->pci_dev
));
1300 /* get phy interface type */
1301 phyinterface
= readl(base
+ NvRegPhyInterface
);
1303 /* see if gigabit phy */
1304 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
1305 if (mii_status
& PHY_GIGABIT
) {
1306 np
->gigabit
= PHY_GIGABIT
;
1307 mii_control_1000
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
1308 mii_control_1000
&= ~ADVERTISE_1000HALF
;
1309 if (phyinterface
& PHY_RGMII
)
1310 mii_control_1000
|= ADVERTISE_1000FULL
;
1312 mii_control_1000
&= ~ADVERTISE_1000FULL
;
1314 if (mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, mii_control_1000
)) {
1315 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1322 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1323 mii_control
|= BMCR_ANENABLE
;
1325 if (np
->phy_oui
== PHY_OUI_REALTEK
&&
1326 np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1327 np
->phy_rev
== PHY_REV_REALTEK_8211C
) {
1328 /* start autoneg since we already performed hw reset above */
1329 mii_control
|= BMCR_ANRESTART
;
1330 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
)) {
1331 printk(KERN_INFO
"%s: phy init failed\n", pci_name(np
->pci_dev
));
1336 * (certain phys need bmcr to be setup with reset)
1338 if (phy_reset(dev
, mii_control
)) {
1339 printk(KERN_INFO
"%s: phy reset failed\n", pci_name(np
->pci_dev
));
1344 /* phy vendor specific configuration */
1345 if ((np
->phy_oui
== PHY_OUI_CICADA
) && (phyinterface
& PHY_RGMII
) ) {
1346 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_RESV1
, MII_READ
);
1347 phy_reserved
&= ~(PHY_CICADA_INIT1
| PHY_CICADA_INIT2
);
1348 phy_reserved
|= (PHY_CICADA_INIT3
| PHY_CICADA_INIT4
);
1349 if (mii_rw(dev
, np
->phyaddr
, MII_RESV1
, phy_reserved
)) {
1350 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1353 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, MII_READ
);
1354 phy_reserved
|= PHY_CICADA_INIT5
;
1355 if (mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, phy_reserved
)) {
1356 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1360 if (np
->phy_oui
== PHY_OUI_CICADA
) {
1361 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, MII_READ
);
1362 phy_reserved
|= PHY_CICADA_INIT6
;
1363 if (mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, phy_reserved
)) {
1364 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1368 if (np
->phy_oui
== PHY_OUI_VITESSE
) {
1369 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG1
, PHY_VITESSE_INIT1
)) {
1370 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1373 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT2
)) {
1374 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1377 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, MII_READ
);
1378 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, phy_reserved
)) {
1379 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1382 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, MII_READ
);
1383 phy_reserved
&= ~PHY_VITESSE_INIT_MSK1
;
1384 phy_reserved
|= PHY_VITESSE_INIT3
;
1385 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, phy_reserved
)) {
1386 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1389 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT4
)) {
1390 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1393 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT5
)) {
1394 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1397 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, MII_READ
);
1398 phy_reserved
&= ~PHY_VITESSE_INIT_MSK1
;
1399 phy_reserved
|= PHY_VITESSE_INIT3
;
1400 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, phy_reserved
)) {
1401 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1404 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, MII_READ
);
1405 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, phy_reserved
)) {
1406 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1409 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT6
)) {
1410 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1413 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT7
)) {
1414 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1417 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, MII_READ
);
1418 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, phy_reserved
)) {
1419 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1422 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, MII_READ
);
1423 phy_reserved
&= ~PHY_VITESSE_INIT_MSK2
;
1424 phy_reserved
|= PHY_VITESSE_INIT8
;
1425 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, phy_reserved
)) {
1426 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1429 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT9
)) {
1430 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1433 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG1
, PHY_VITESSE_INIT10
)) {
1434 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1438 if (np
->phy_oui
== PHY_OUI_REALTEK
) {
1439 if (np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1440 np
->phy_rev
== PHY_REV_REALTEK_8211B
) {
1441 /* reset could have cleared these out, set them back */
1442 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1443 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1446 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, PHY_REALTEK_INIT2
)) {
1447 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1450 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
)) {
1451 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1454 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG3
, PHY_REALTEK_INIT4
)) {
1455 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1458 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG4
, PHY_REALTEK_INIT5
)) {
1459 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1462 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG5
, PHY_REALTEK_INIT6
)) {
1463 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1466 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1467 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1471 if (np
->phy_model
== PHY_MODEL_REALTEK_8201
) {
1472 if (np
->driver_data
& DEV_NEED_PHY_INIT_FIX
) {
1473 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, MII_READ
);
1474 phy_reserved
|= PHY_REALTEK_INIT7
;
1475 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, phy_reserved
)) {
1476 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1480 if (phy_cross
== NV_CROSSOVER_DETECTION_DISABLED
) {
1481 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
)) {
1482 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1485 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, MII_READ
);
1486 phy_reserved
&= ~PHY_REALTEK_INIT_MSK1
;
1487 phy_reserved
|= PHY_REALTEK_INIT3
;
1488 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, phy_reserved
)) {
1489 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1492 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1493 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1500 /* some phys clear out pause advertisment on reset, set it back */
1501 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, reg
);
1503 /* restart auto negotiation, power down phy */
1504 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1505 mii_control
|= (BMCR_ANRESTART
| BMCR_ANENABLE
);
1506 if (phy_power_down
) {
1507 mii_control
|= BMCR_PDOWN
;
1509 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
)) {
1516 static void nv_start_rx(struct net_device
*dev
)
1518 struct fe_priv
*np
= netdev_priv(dev
);
1519 u8 __iomem
*base
= get_hwbase(dev
);
1520 u32 rx_ctrl
= readl(base
+ NvRegReceiverControl
);
1522 dprintk(KERN_DEBUG
"%s: nv_start_rx\n", dev
->name
);
1523 /* Already running? Stop it. */
1524 if ((readl(base
+ NvRegReceiverControl
) & NVREG_RCVCTL_START
) && !np
->mac_in_use
) {
1525 rx_ctrl
&= ~NVREG_RCVCTL_START
;
1526 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1529 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
1531 rx_ctrl
|= NVREG_RCVCTL_START
;
1533 rx_ctrl
&= ~NVREG_RCVCTL_RX_PATH_EN
;
1534 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1535 dprintk(KERN_DEBUG
"%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1536 dev
->name
, np
->duplex
, np
->linkspeed
);
1540 static void nv_stop_rx(struct net_device
*dev
)
1542 struct fe_priv
*np
= netdev_priv(dev
);
1543 u8 __iomem
*base
= get_hwbase(dev
);
1544 u32 rx_ctrl
= readl(base
+ NvRegReceiverControl
);
1546 dprintk(KERN_DEBUG
"%s: nv_stop_rx\n", dev
->name
);
1547 if (!np
->mac_in_use
)
1548 rx_ctrl
&= ~NVREG_RCVCTL_START
;
1550 rx_ctrl
|= NVREG_RCVCTL_RX_PATH_EN
;
1551 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1552 reg_delay(dev
, NvRegReceiverStatus
, NVREG_RCVSTAT_BUSY
, 0,
1553 NV_RXSTOP_DELAY1
, NV_RXSTOP_DELAY1MAX
,
1554 KERN_INFO
"nv_stop_rx: ReceiverStatus remained busy");
1556 udelay(NV_RXSTOP_DELAY2
);
1557 if (!np
->mac_in_use
)
1558 writel(0, base
+ NvRegLinkSpeed
);
1561 static void nv_start_tx(struct net_device
*dev
)
1563 struct fe_priv
*np
= netdev_priv(dev
);
1564 u8 __iomem
*base
= get_hwbase(dev
);
1565 u32 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
1567 dprintk(KERN_DEBUG
"%s: nv_start_tx\n", dev
->name
);
1568 tx_ctrl
|= NVREG_XMITCTL_START
;
1570 tx_ctrl
&= ~NVREG_XMITCTL_TX_PATH_EN
;
1571 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
1575 static void nv_stop_tx(struct net_device
*dev
)
1577 struct fe_priv
*np
= netdev_priv(dev
);
1578 u8 __iomem
*base
= get_hwbase(dev
);
1579 u32 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
1581 dprintk(KERN_DEBUG
"%s: nv_stop_tx\n", dev
->name
);
1582 if (!np
->mac_in_use
)
1583 tx_ctrl
&= ~NVREG_XMITCTL_START
;
1585 tx_ctrl
|= NVREG_XMITCTL_TX_PATH_EN
;
1586 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
1587 reg_delay(dev
, NvRegTransmitterStatus
, NVREG_XMITSTAT_BUSY
, 0,
1588 NV_TXSTOP_DELAY1
, NV_TXSTOP_DELAY1MAX
,
1589 KERN_INFO
"nv_stop_tx: TransmitterStatus remained busy");
1591 udelay(NV_TXSTOP_DELAY2
);
1592 if (!np
->mac_in_use
)
1593 writel(readl(base
+ NvRegTransmitPoll
) & NVREG_TRANSMITPOLL_MAC_ADDR_REV
,
1594 base
+ NvRegTransmitPoll
);
1597 static void nv_start_rxtx(struct net_device
*dev
)
1603 static void nv_stop_rxtx(struct net_device
*dev
)
1609 static void nv_txrx_reset(struct net_device
*dev
)
1611 struct fe_priv
*np
= netdev_priv(dev
);
1612 u8 __iomem
*base
= get_hwbase(dev
);
1614 dprintk(KERN_DEBUG
"%s: nv_txrx_reset\n", dev
->name
);
1615 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1617 udelay(NV_TXRX_RESET_DELAY
);
1618 writel(NVREG_TXRXCTL_BIT2
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1622 static void nv_mac_reset(struct net_device
*dev
)
1624 struct fe_priv
*np
= netdev_priv(dev
);
1625 u8 __iomem
*base
= get_hwbase(dev
);
1626 u32 temp1
, temp2
, temp3
;
1628 dprintk(KERN_DEBUG
"%s: nv_mac_reset\n", dev
->name
);
1630 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1633 /* save registers since they will be cleared on reset */
1634 temp1
= readl(base
+ NvRegMacAddrA
);
1635 temp2
= readl(base
+ NvRegMacAddrB
);
1636 temp3
= readl(base
+ NvRegTransmitPoll
);
1638 writel(NVREG_MAC_RESET_ASSERT
, base
+ NvRegMacReset
);
1640 udelay(NV_MAC_RESET_DELAY
);
1641 writel(0, base
+ NvRegMacReset
);
1643 udelay(NV_MAC_RESET_DELAY
);
1645 /* restore saved registers */
1646 writel(temp1
, base
+ NvRegMacAddrA
);
1647 writel(temp2
, base
+ NvRegMacAddrB
);
1648 writel(temp3
, base
+ NvRegTransmitPoll
);
1650 writel(NVREG_TXRXCTL_BIT2
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1654 static void nv_get_hw_stats(struct net_device
*dev
)
1656 struct fe_priv
*np
= netdev_priv(dev
);
1657 u8 __iomem
*base
= get_hwbase(dev
);
1659 np
->estats
.tx_bytes
+= readl(base
+ NvRegTxCnt
);
1660 np
->estats
.tx_zero_rexmt
+= readl(base
+ NvRegTxZeroReXmt
);
1661 np
->estats
.tx_one_rexmt
+= readl(base
+ NvRegTxOneReXmt
);
1662 np
->estats
.tx_many_rexmt
+= readl(base
+ NvRegTxManyReXmt
);
1663 np
->estats
.tx_late_collision
+= readl(base
+ NvRegTxLateCol
);
1664 np
->estats
.tx_fifo_errors
+= readl(base
+ NvRegTxUnderflow
);
1665 np
->estats
.tx_carrier_errors
+= readl(base
+ NvRegTxLossCarrier
);
1666 np
->estats
.tx_excess_deferral
+= readl(base
+ NvRegTxExcessDef
);
1667 np
->estats
.tx_retry_error
+= readl(base
+ NvRegTxRetryErr
);
1668 np
->estats
.rx_frame_error
+= readl(base
+ NvRegRxFrameErr
);
1669 np
->estats
.rx_extra_byte
+= readl(base
+ NvRegRxExtraByte
);
1670 np
->estats
.rx_late_collision
+= readl(base
+ NvRegRxLateCol
);
1671 np
->estats
.rx_runt
+= readl(base
+ NvRegRxRunt
);
1672 np
->estats
.rx_frame_too_long
+= readl(base
+ NvRegRxFrameTooLong
);
1673 np
->estats
.rx_over_errors
+= readl(base
+ NvRegRxOverflow
);
1674 np
->estats
.rx_crc_errors
+= readl(base
+ NvRegRxFCSErr
);
1675 np
->estats
.rx_frame_align_error
+= readl(base
+ NvRegRxFrameAlignErr
);
1676 np
->estats
.rx_length_error
+= readl(base
+ NvRegRxLenErr
);
1677 np
->estats
.rx_unicast
+= readl(base
+ NvRegRxUnicast
);
1678 np
->estats
.rx_multicast
+= readl(base
+ NvRegRxMulticast
);
1679 np
->estats
.rx_broadcast
+= readl(base
+ NvRegRxBroadcast
);
1680 np
->estats
.rx_packets
=
1681 np
->estats
.rx_unicast
+
1682 np
->estats
.rx_multicast
+
1683 np
->estats
.rx_broadcast
;
1684 np
->estats
.rx_errors_total
=
1685 np
->estats
.rx_crc_errors
+
1686 np
->estats
.rx_over_errors
+
1687 np
->estats
.rx_frame_error
+
1688 (np
->estats
.rx_frame_align_error
- np
->estats
.rx_extra_byte
) +
1689 np
->estats
.rx_late_collision
+
1690 np
->estats
.rx_runt
+
1691 np
->estats
.rx_frame_too_long
;
1692 np
->estats
.tx_errors_total
=
1693 np
->estats
.tx_late_collision
+
1694 np
->estats
.tx_fifo_errors
+
1695 np
->estats
.tx_carrier_errors
+
1696 np
->estats
.tx_excess_deferral
+
1697 np
->estats
.tx_retry_error
;
1699 if (np
->driver_data
& DEV_HAS_STATISTICS_V2
) {
1700 np
->estats
.tx_deferral
+= readl(base
+ NvRegTxDef
);
1701 np
->estats
.tx_packets
+= readl(base
+ NvRegTxFrame
);
1702 np
->estats
.rx_bytes
+= readl(base
+ NvRegRxCnt
);
1703 np
->estats
.tx_pause
+= readl(base
+ NvRegTxPause
);
1704 np
->estats
.rx_pause
+= readl(base
+ NvRegRxPause
);
1705 np
->estats
.rx_drop_frame
+= readl(base
+ NvRegRxDropFrame
);
1708 if (np
->driver_data
& DEV_HAS_STATISTICS_V3
) {
1709 np
->estats
.tx_unicast
+= readl(base
+ NvRegTxUnicast
);
1710 np
->estats
.tx_multicast
+= readl(base
+ NvRegTxMulticast
);
1711 np
->estats
.tx_broadcast
+= readl(base
+ NvRegTxBroadcast
);
1716 * nv_get_stats: dev->get_stats function
1717 * Get latest stats value from the nic.
1718 * Called with read_lock(&dev_base_lock) held for read -
1719 * only synchronized against unregister_netdevice.
1721 static struct net_device_stats
*nv_get_stats(struct net_device
*dev
)
1723 struct fe_priv
*np
= netdev_priv(dev
);
1725 /* If the nic supports hw counters then retrieve latest values */
1726 if (np
->driver_data
& (DEV_HAS_STATISTICS_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_STATISTICS_V3
)) {
1727 nv_get_hw_stats(dev
);
1729 /* copy to net_device stats */
1730 dev
->stats
.tx_bytes
= np
->estats
.tx_bytes
;
1731 dev
->stats
.tx_fifo_errors
= np
->estats
.tx_fifo_errors
;
1732 dev
->stats
.tx_carrier_errors
= np
->estats
.tx_carrier_errors
;
1733 dev
->stats
.rx_crc_errors
= np
->estats
.rx_crc_errors
;
1734 dev
->stats
.rx_over_errors
= np
->estats
.rx_over_errors
;
1735 dev
->stats
.rx_errors
= np
->estats
.rx_errors_total
;
1736 dev
->stats
.tx_errors
= np
->estats
.tx_errors_total
;
1743 * nv_alloc_rx: fill rx ring entries.
1744 * Return 1 if the allocations for the skbs failed and the
1745 * rx engine is without Available descriptors
1747 static int nv_alloc_rx(struct net_device
*dev
)
1749 struct fe_priv
*np
= netdev_priv(dev
);
1750 struct ring_desc
* less_rx
;
1752 less_rx
= np
->get_rx
.orig
;
1753 if (less_rx
-- == np
->first_rx
.orig
)
1754 less_rx
= np
->last_rx
.orig
;
1756 while (np
->put_rx
.orig
!= less_rx
) {
1757 struct sk_buff
*skb
= dev_alloc_skb(np
->rx_buf_sz
+ NV_RX_ALLOC_PAD
);
1759 np
->put_rx_ctx
->skb
= skb
;
1760 np
->put_rx_ctx
->dma
= pci_map_single(np
->pci_dev
,
1763 PCI_DMA_FROMDEVICE
);
1764 np
->put_rx_ctx
->dma_len
= skb_tailroom(skb
);
1765 np
->put_rx
.orig
->buf
= cpu_to_le32(np
->put_rx_ctx
->dma
);
1767 np
->put_rx
.orig
->flaglen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX_AVAIL
);
1768 if (unlikely(np
->put_rx
.orig
++ == np
->last_rx
.orig
))
1769 np
->put_rx
.orig
= np
->first_rx
.orig
;
1770 if (unlikely(np
->put_rx_ctx
++ == np
->last_rx_ctx
))
1771 np
->put_rx_ctx
= np
->first_rx_ctx
;
1779 static int nv_alloc_rx_optimized(struct net_device
*dev
)
1781 struct fe_priv
*np
= netdev_priv(dev
);
1782 struct ring_desc_ex
* less_rx
;
1784 less_rx
= np
->get_rx
.ex
;
1785 if (less_rx
-- == np
->first_rx
.ex
)
1786 less_rx
= np
->last_rx
.ex
;
1788 while (np
->put_rx
.ex
!= less_rx
) {
1789 struct sk_buff
*skb
= dev_alloc_skb(np
->rx_buf_sz
+ NV_RX_ALLOC_PAD
);
1791 np
->put_rx_ctx
->skb
= skb
;
1792 np
->put_rx_ctx
->dma
= pci_map_single(np
->pci_dev
,
1795 PCI_DMA_FROMDEVICE
);
1796 np
->put_rx_ctx
->dma_len
= skb_tailroom(skb
);
1797 np
->put_rx
.ex
->bufhigh
= cpu_to_le32(dma_high(np
->put_rx_ctx
->dma
));
1798 np
->put_rx
.ex
->buflow
= cpu_to_le32(dma_low(np
->put_rx_ctx
->dma
));
1800 np
->put_rx
.ex
->flaglen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX2_AVAIL
);
1801 if (unlikely(np
->put_rx
.ex
++ == np
->last_rx
.ex
))
1802 np
->put_rx
.ex
= np
->first_rx
.ex
;
1803 if (unlikely(np
->put_rx_ctx
++ == np
->last_rx_ctx
))
1804 np
->put_rx_ctx
= np
->first_rx_ctx
;
1812 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1813 #ifdef CONFIG_FORCEDETH_NAPI
1814 static void nv_do_rx_refill(unsigned long data
)
1816 struct net_device
*dev
= (struct net_device
*) data
;
1817 struct fe_priv
*np
= netdev_priv(dev
);
1819 /* Just reschedule NAPI rx processing */
1820 napi_schedule(&np
->napi
);
1823 static void nv_do_rx_refill(unsigned long data
)
1825 struct net_device
*dev
= (struct net_device
*) data
;
1826 struct fe_priv
*np
= netdev_priv(dev
);
1829 if (!using_multi_irqs(dev
)) {
1830 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1831 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1833 disable_irq(np
->pci_dev
->irq
);
1835 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1837 if (!nv_optimized(np
))
1838 retcode
= nv_alloc_rx(dev
);
1840 retcode
= nv_alloc_rx_optimized(dev
);
1842 spin_lock_irq(&np
->lock
);
1843 if (!np
->in_shutdown
)
1844 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
1845 spin_unlock_irq(&np
->lock
);
1847 if (!using_multi_irqs(dev
)) {
1848 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1849 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1851 enable_irq(np
->pci_dev
->irq
);
1853 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1858 static void nv_init_rx(struct net_device
*dev
)
1860 struct fe_priv
*np
= netdev_priv(dev
);
1863 np
->get_rx
= np
->put_rx
= np
->first_rx
= np
->rx_ring
;
1865 if (!nv_optimized(np
))
1866 np
->last_rx
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
-1];
1868 np
->last_rx
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
-1];
1869 np
->get_rx_ctx
= np
->put_rx_ctx
= np
->first_rx_ctx
= np
->rx_skb
;
1870 np
->last_rx_ctx
= &np
->rx_skb
[np
->rx_ring_size
-1];
1872 for (i
= 0; i
< np
->rx_ring_size
; i
++) {
1873 if (!nv_optimized(np
)) {
1874 np
->rx_ring
.orig
[i
].flaglen
= 0;
1875 np
->rx_ring
.orig
[i
].buf
= 0;
1877 np
->rx_ring
.ex
[i
].flaglen
= 0;
1878 np
->rx_ring
.ex
[i
].txvlan
= 0;
1879 np
->rx_ring
.ex
[i
].bufhigh
= 0;
1880 np
->rx_ring
.ex
[i
].buflow
= 0;
1882 np
->rx_skb
[i
].skb
= NULL
;
1883 np
->rx_skb
[i
].dma
= 0;
1887 static void nv_init_tx(struct net_device
*dev
)
1889 struct fe_priv
*np
= netdev_priv(dev
);
1892 np
->get_tx
= np
->put_tx
= np
->first_tx
= np
->tx_ring
;
1894 if (!nv_optimized(np
))
1895 np
->last_tx
.orig
= &np
->tx_ring
.orig
[np
->tx_ring_size
-1];
1897 np
->last_tx
.ex
= &np
->tx_ring
.ex
[np
->tx_ring_size
-1];
1898 np
->get_tx_ctx
= np
->put_tx_ctx
= np
->first_tx_ctx
= np
->tx_skb
;
1899 np
->last_tx_ctx
= &np
->tx_skb
[np
->tx_ring_size
-1];
1900 np
->tx_pkts_in_progress
= 0;
1901 np
->tx_change_owner
= NULL
;
1902 np
->tx_end_flip
= NULL
;
1905 for (i
= 0; i
< np
->tx_ring_size
; i
++) {
1906 if (!nv_optimized(np
)) {
1907 np
->tx_ring
.orig
[i
].flaglen
= 0;
1908 np
->tx_ring
.orig
[i
].buf
= 0;
1910 np
->tx_ring
.ex
[i
].flaglen
= 0;
1911 np
->tx_ring
.ex
[i
].txvlan
= 0;
1912 np
->tx_ring
.ex
[i
].bufhigh
= 0;
1913 np
->tx_ring
.ex
[i
].buflow
= 0;
1915 np
->tx_skb
[i
].skb
= NULL
;
1916 np
->tx_skb
[i
].dma
= 0;
1917 np
->tx_skb
[i
].dma_len
= 0;
1918 np
->tx_skb
[i
].dma_single
= 0;
1919 np
->tx_skb
[i
].first_tx_desc
= NULL
;
1920 np
->tx_skb
[i
].next_tx_ctx
= NULL
;
1924 static int nv_init_ring(struct net_device
*dev
)
1926 struct fe_priv
*np
= netdev_priv(dev
);
1931 if (!nv_optimized(np
))
1932 return nv_alloc_rx(dev
);
1934 return nv_alloc_rx_optimized(dev
);
1937 static void nv_unmap_txskb(struct fe_priv
*np
, struct nv_skb_map
*tx_skb
)
1940 if (tx_skb
->dma_single
)
1941 pci_unmap_single(np
->pci_dev
, tx_skb
->dma
,
1945 pci_unmap_page(np
->pci_dev
, tx_skb
->dma
,
1952 static int nv_release_txskb(struct fe_priv
*np
, struct nv_skb_map
*tx_skb
)
1954 nv_unmap_txskb(np
, tx_skb
);
1956 dev_kfree_skb_any(tx_skb
->skb
);
1963 static void nv_drain_tx(struct net_device
*dev
)
1965 struct fe_priv
*np
= netdev_priv(dev
);
1968 for (i
= 0; i
< np
->tx_ring_size
; i
++) {
1969 if (!nv_optimized(np
)) {
1970 np
->tx_ring
.orig
[i
].flaglen
= 0;
1971 np
->tx_ring
.orig
[i
].buf
= 0;
1973 np
->tx_ring
.ex
[i
].flaglen
= 0;
1974 np
->tx_ring
.ex
[i
].txvlan
= 0;
1975 np
->tx_ring
.ex
[i
].bufhigh
= 0;
1976 np
->tx_ring
.ex
[i
].buflow
= 0;
1978 if (nv_release_txskb(np
, &np
->tx_skb
[i
]))
1979 dev
->stats
.tx_dropped
++;
1980 np
->tx_skb
[i
].dma
= 0;
1981 np
->tx_skb
[i
].dma_len
= 0;
1982 np
->tx_skb
[i
].dma_single
= 0;
1983 np
->tx_skb
[i
].first_tx_desc
= NULL
;
1984 np
->tx_skb
[i
].next_tx_ctx
= NULL
;
1986 np
->tx_pkts_in_progress
= 0;
1987 np
->tx_change_owner
= NULL
;
1988 np
->tx_end_flip
= NULL
;
1991 static void nv_drain_rx(struct net_device
*dev
)
1993 struct fe_priv
*np
= netdev_priv(dev
);
1996 for (i
= 0; i
< np
->rx_ring_size
; i
++) {
1997 if (!nv_optimized(np
)) {
1998 np
->rx_ring
.orig
[i
].flaglen
= 0;
1999 np
->rx_ring
.orig
[i
].buf
= 0;
2001 np
->rx_ring
.ex
[i
].flaglen
= 0;
2002 np
->rx_ring
.ex
[i
].txvlan
= 0;
2003 np
->rx_ring
.ex
[i
].bufhigh
= 0;
2004 np
->rx_ring
.ex
[i
].buflow
= 0;
2007 if (np
->rx_skb
[i
].skb
) {
2008 pci_unmap_single(np
->pci_dev
, np
->rx_skb
[i
].dma
,
2009 (skb_end_pointer(np
->rx_skb
[i
].skb
) -
2010 np
->rx_skb
[i
].skb
->data
),
2011 PCI_DMA_FROMDEVICE
);
2012 dev_kfree_skb(np
->rx_skb
[i
].skb
);
2013 np
->rx_skb
[i
].skb
= NULL
;
2018 static void nv_drain_rxtx(struct net_device
*dev
)
2024 static inline u32
nv_get_empty_tx_slots(struct fe_priv
*np
)
2026 return (u32
)(np
->tx_ring_size
- ((np
->tx_ring_size
+ (np
->put_tx_ctx
- np
->get_tx_ctx
)) % np
->tx_ring_size
));
2029 static void nv_legacybackoff_reseed(struct net_device
*dev
)
2031 u8 __iomem
*base
= get_hwbase(dev
);
2036 reg
= readl(base
+ NvRegSlotTime
) & ~NVREG_SLOTTIME_MASK
;
2037 get_random_bytes(&low
, sizeof(low
));
2038 reg
|= low
& NVREG_SLOTTIME_MASK
;
2040 /* Need to stop tx before change takes effect.
2041 * Caller has already gained np->lock.
2043 tx_status
= readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_START
;
2047 writel(reg
, base
+ NvRegSlotTime
);
2053 /* Gear Backoff Seeds */
2054 #define BACKOFF_SEEDSET_ROWS 8
2055 #define BACKOFF_SEEDSET_LFSRS 15
2057 /* Known Good seed sets */
2058 static const u32 main_seedset
[BACKOFF_SEEDSET_ROWS
][BACKOFF_SEEDSET_LFSRS
] = {
2059 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2060 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2061 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2062 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2063 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2064 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2065 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
2066 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
2068 static const u32 gear_seedset
[BACKOFF_SEEDSET_ROWS
][BACKOFF_SEEDSET_LFSRS
] = {
2069 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2070 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2071 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2072 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2073 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2074 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2075 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2076 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
2078 static void nv_gear_backoff_reseed(struct net_device
*dev
)
2080 u8 __iomem
*base
= get_hwbase(dev
);
2081 u32 miniseed1
, miniseed2
, miniseed2_reversed
, miniseed3
, miniseed3_reversed
;
2082 u32 temp
, seedset
, combinedSeed
;
2085 /* Setup seed for free running LFSR */
2086 /* We are going to read the time stamp counter 3 times
2087 and swizzle bits around to increase randomness */
2088 get_random_bytes(&miniseed1
, sizeof(miniseed1
));
2089 miniseed1
&= 0x0fff;
2093 get_random_bytes(&miniseed2
, sizeof(miniseed2
));
2094 miniseed2
&= 0x0fff;
2097 miniseed2_reversed
=
2098 ((miniseed2
& 0xF00) >> 8) |
2099 (miniseed2
& 0x0F0) |
2100 ((miniseed2
& 0x00F) << 8);
2102 get_random_bytes(&miniseed3
, sizeof(miniseed3
));
2103 miniseed3
&= 0x0fff;
2106 miniseed3_reversed
=
2107 ((miniseed3
& 0xF00) >> 8) |
2108 (miniseed3
& 0x0F0) |
2109 ((miniseed3
& 0x00F) << 8);
2111 combinedSeed
= ((miniseed1
^ miniseed2_reversed
) << 12) |
2112 (miniseed2
^ miniseed3_reversed
);
2114 /* Seeds can not be zero */
2115 if ((combinedSeed
& NVREG_BKOFFCTRL_SEED_MASK
) == 0)
2116 combinedSeed
|= 0x08;
2117 if ((combinedSeed
& (NVREG_BKOFFCTRL_SEED_MASK
<< NVREG_BKOFFCTRL_GEAR
)) == 0)
2118 combinedSeed
|= 0x8000;
2120 /* No need to disable tx here */
2121 temp
= NVREG_BKOFFCTRL_DEFAULT
| (0 << NVREG_BKOFFCTRL_SELECT
);
2122 temp
|= combinedSeed
& NVREG_BKOFFCTRL_SEED_MASK
;
2123 temp
|= combinedSeed
>> NVREG_BKOFFCTRL_GEAR
;
2124 writel(temp
,base
+ NvRegBackOffControl
);
2126 /* Setup seeds for all gear LFSRs. */
2127 get_random_bytes(&seedset
, sizeof(seedset
));
2128 seedset
= seedset
% BACKOFF_SEEDSET_ROWS
;
2129 for (i
= 1; i
<= BACKOFF_SEEDSET_LFSRS
; i
++)
2131 temp
= NVREG_BKOFFCTRL_DEFAULT
| (i
<< NVREG_BKOFFCTRL_SELECT
);
2132 temp
|= main_seedset
[seedset
][i
-1] & 0x3ff;
2133 temp
|= ((gear_seedset
[seedset
][i
-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR
);
2134 writel(temp
, base
+ NvRegBackOffControl
);
2139 * nv_start_xmit: dev->hard_start_xmit function
2140 * Called with netif_tx_lock held.
2142 static netdev_tx_t
nv_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2144 struct fe_priv
*np
= netdev_priv(dev
);
2146 u32 tx_flags_extra
= (np
->desc_ver
== DESC_VER_1
? NV_TX_LASTPACKET
: NV_TX2_LASTPACKET
);
2147 unsigned int fragments
= skb_shinfo(skb
)->nr_frags
;
2151 u32 size
= skb_headlen(skb
);
2152 u32 entries
= (size
>> NV_TX2_TSO_MAX_SHIFT
) + ((size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2154 struct ring_desc
* put_tx
;
2155 struct ring_desc
* start_tx
;
2156 struct ring_desc
* prev_tx
;
2157 struct nv_skb_map
* prev_tx_ctx
;
2158 unsigned long flags
;
2160 /* add fragments to entries count */
2161 for (i
= 0; i
< fragments
; i
++) {
2162 entries
+= (skb_shinfo(skb
)->frags
[i
].size
>> NV_TX2_TSO_MAX_SHIFT
) +
2163 ((skb_shinfo(skb
)->frags
[i
].size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2166 spin_lock_irqsave(&np
->lock
, flags
);
2167 empty_slots
= nv_get_empty_tx_slots(np
);
2168 if (unlikely(empty_slots
<= entries
)) {
2169 netif_stop_queue(dev
);
2171 spin_unlock_irqrestore(&np
->lock
, flags
);
2172 return NETDEV_TX_BUSY
;
2174 spin_unlock_irqrestore(&np
->lock
, flags
);
2176 start_tx
= put_tx
= np
->put_tx
.orig
;
2178 /* setup the header buffer */
2181 prev_tx_ctx
= np
->put_tx_ctx
;
2182 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2183 np
->put_tx_ctx
->dma
= pci_map_single(np
->pci_dev
, skb
->data
+ offset
, bcnt
,
2185 np
->put_tx_ctx
->dma_len
= bcnt
;
2186 np
->put_tx_ctx
->dma_single
= 1;
2187 put_tx
->buf
= cpu_to_le32(np
->put_tx_ctx
->dma
);
2188 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2190 tx_flags
= np
->tx_flags
;
2193 if (unlikely(put_tx
++ == np
->last_tx
.orig
))
2194 put_tx
= np
->first_tx
.orig
;
2195 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2196 np
->put_tx_ctx
= np
->first_tx_ctx
;
2199 /* setup the fragments */
2200 for (i
= 0; i
< fragments
; i
++) {
2201 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2202 u32 size
= frag
->size
;
2207 prev_tx_ctx
= np
->put_tx_ctx
;
2208 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2209 np
->put_tx_ctx
->dma
= pci_map_page(np
->pci_dev
, frag
->page
, frag
->page_offset
+offset
, bcnt
,
2211 np
->put_tx_ctx
->dma_len
= bcnt
;
2212 np
->put_tx_ctx
->dma_single
= 0;
2213 put_tx
->buf
= cpu_to_le32(np
->put_tx_ctx
->dma
);
2214 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2218 if (unlikely(put_tx
++ == np
->last_tx
.orig
))
2219 put_tx
= np
->first_tx
.orig
;
2220 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2221 np
->put_tx_ctx
= np
->first_tx_ctx
;
2225 /* set last fragment flag */
2226 prev_tx
->flaglen
|= cpu_to_le32(tx_flags_extra
);
2228 /* save skb in this slot's context area */
2229 prev_tx_ctx
->skb
= skb
;
2231 if (skb_is_gso(skb
))
2232 tx_flags_extra
= NV_TX2_TSO
| (skb_shinfo(skb
)->gso_size
<< NV_TX2_TSO_SHIFT
);
2234 tx_flags_extra
= skb
->ip_summed
== CHECKSUM_PARTIAL
?
2235 NV_TX2_CHECKSUM_L3
| NV_TX2_CHECKSUM_L4
: 0;
2237 spin_lock_irqsave(&np
->lock
, flags
);
2240 start_tx
->flaglen
|= cpu_to_le32(tx_flags
| tx_flags_extra
);
2241 np
->put_tx
.orig
= put_tx
;
2243 spin_unlock_irqrestore(&np
->lock
, flags
);
2245 dprintk(KERN_DEBUG
"%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2246 dev
->name
, entries
, tx_flags_extra
);
2249 for (j
=0; j
<64; j
++) {
2251 dprintk("\n%03x:", j
);
2252 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
2257 dev
->trans_start
= jiffies
;
2258 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2259 return NETDEV_TX_OK
;
2262 static netdev_tx_t
nv_start_xmit_optimized(struct sk_buff
*skb
,
2263 struct net_device
*dev
)
2265 struct fe_priv
*np
= netdev_priv(dev
);
2268 unsigned int fragments
= skb_shinfo(skb
)->nr_frags
;
2272 u32 size
= skb_headlen(skb
);
2273 u32 entries
= (size
>> NV_TX2_TSO_MAX_SHIFT
) + ((size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2275 struct ring_desc_ex
* put_tx
;
2276 struct ring_desc_ex
* start_tx
;
2277 struct ring_desc_ex
* prev_tx
;
2278 struct nv_skb_map
* prev_tx_ctx
;
2279 struct nv_skb_map
* start_tx_ctx
;
2280 unsigned long flags
;
2282 /* add fragments to entries count */
2283 for (i
= 0; i
< fragments
; i
++) {
2284 entries
+= (skb_shinfo(skb
)->frags
[i
].size
>> NV_TX2_TSO_MAX_SHIFT
) +
2285 ((skb_shinfo(skb
)->frags
[i
].size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2288 spin_lock_irqsave(&np
->lock
, flags
);
2289 empty_slots
= nv_get_empty_tx_slots(np
);
2290 if (unlikely(empty_slots
<= entries
)) {
2291 netif_stop_queue(dev
);
2293 spin_unlock_irqrestore(&np
->lock
, flags
);
2294 return NETDEV_TX_BUSY
;
2296 spin_unlock_irqrestore(&np
->lock
, flags
);
2298 start_tx
= put_tx
= np
->put_tx
.ex
;
2299 start_tx_ctx
= np
->put_tx_ctx
;
2301 /* setup the header buffer */
2304 prev_tx_ctx
= np
->put_tx_ctx
;
2305 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2306 np
->put_tx_ctx
->dma
= pci_map_single(np
->pci_dev
, skb
->data
+ offset
, bcnt
,
2308 np
->put_tx_ctx
->dma_len
= bcnt
;
2309 np
->put_tx_ctx
->dma_single
= 1;
2310 put_tx
->bufhigh
= cpu_to_le32(dma_high(np
->put_tx_ctx
->dma
));
2311 put_tx
->buflow
= cpu_to_le32(dma_low(np
->put_tx_ctx
->dma
));
2312 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2314 tx_flags
= NV_TX2_VALID
;
2317 if (unlikely(put_tx
++ == np
->last_tx
.ex
))
2318 put_tx
= np
->first_tx
.ex
;
2319 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2320 np
->put_tx_ctx
= np
->first_tx_ctx
;
2323 /* setup the fragments */
2324 for (i
= 0; i
< fragments
; i
++) {
2325 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2326 u32 size
= frag
->size
;
2331 prev_tx_ctx
= np
->put_tx_ctx
;
2332 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2333 np
->put_tx_ctx
->dma
= pci_map_page(np
->pci_dev
, frag
->page
, frag
->page_offset
+offset
, bcnt
,
2335 np
->put_tx_ctx
->dma_len
= bcnt
;
2336 np
->put_tx_ctx
->dma_single
= 0;
2337 put_tx
->bufhigh
= cpu_to_le32(dma_high(np
->put_tx_ctx
->dma
));
2338 put_tx
->buflow
= cpu_to_le32(dma_low(np
->put_tx_ctx
->dma
));
2339 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2343 if (unlikely(put_tx
++ == np
->last_tx
.ex
))
2344 put_tx
= np
->first_tx
.ex
;
2345 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2346 np
->put_tx_ctx
= np
->first_tx_ctx
;
2350 /* set last fragment flag */
2351 prev_tx
->flaglen
|= cpu_to_le32(NV_TX2_LASTPACKET
);
2353 /* save skb in this slot's context area */
2354 prev_tx_ctx
->skb
= skb
;
2356 if (skb_is_gso(skb
))
2357 tx_flags_extra
= NV_TX2_TSO
| (skb_shinfo(skb
)->gso_size
<< NV_TX2_TSO_SHIFT
);
2359 tx_flags_extra
= skb
->ip_summed
== CHECKSUM_PARTIAL
?
2360 NV_TX2_CHECKSUM_L3
| NV_TX2_CHECKSUM_L4
: 0;
2363 if (likely(!np
->vlangrp
)) {
2364 start_tx
->txvlan
= 0;
2366 if (vlan_tx_tag_present(skb
))
2367 start_tx
->txvlan
= cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT
| vlan_tx_tag_get(skb
));
2369 start_tx
->txvlan
= 0;
2372 spin_lock_irqsave(&np
->lock
, flags
);
2375 /* Limit the number of outstanding tx. Setup all fragments, but
2376 * do not set the VALID bit on the first descriptor. Save a pointer
2377 * to that descriptor and also for next skb_map element.
2380 if (np
->tx_pkts_in_progress
== NV_TX_LIMIT_COUNT
) {
2381 if (!np
->tx_change_owner
)
2382 np
->tx_change_owner
= start_tx_ctx
;
2384 /* remove VALID bit */
2385 tx_flags
&= ~NV_TX2_VALID
;
2386 start_tx_ctx
->first_tx_desc
= start_tx
;
2387 start_tx_ctx
->next_tx_ctx
= np
->put_tx_ctx
;
2388 np
->tx_end_flip
= np
->put_tx_ctx
;
2390 np
->tx_pkts_in_progress
++;
2395 start_tx
->flaglen
|= cpu_to_le32(tx_flags
| tx_flags_extra
);
2396 np
->put_tx
.ex
= put_tx
;
2398 spin_unlock_irqrestore(&np
->lock
, flags
);
2400 dprintk(KERN_DEBUG
"%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2401 dev
->name
, entries
, tx_flags_extra
);
2404 for (j
=0; j
<64; j
++) {
2406 dprintk("\n%03x:", j
);
2407 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
2412 dev
->trans_start
= jiffies
;
2413 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2414 return NETDEV_TX_OK
;
2417 static inline void nv_tx_flip_ownership(struct net_device
*dev
)
2419 struct fe_priv
*np
= netdev_priv(dev
);
2421 np
->tx_pkts_in_progress
--;
2422 if (np
->tx_change_owner
) {
2423 np
->tx_change_owner
->first_tx_desc
->flaglen
|=
2424 cpu_to_le32(NV_TX2_VALID
);
2425 np
->tx_pkts_in_progress
++;
2427 np
->tx_change_owner
= np
->tx_change_owner
->next_tx_ctx
;
2428 if (np
->tx_change_owner
== np
->tx_end_flip
)
2429 np
->tx_change_owner
= NULL
;
2431 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2436 * nv_tx_done: check for completed packets, release the skbs.
2438 * Caller must own np->lock.
2440 static int nv_tx_done(struct net_device
*dev
, int limit
)
2442 struct fe_priv
*np
= netdev_priv(dev
);
2445 struct ring_desc
* orig_get_tx
= np
->get_tx
.orig
;
2447 while ((np
->get_tx
.orig
!= np
->put_tx
.orig
) &&
2448 !((flags
= le32_to_cpu(np
->get_tx
.orig
->flaglen
)) & NV_TX_VALID
) &&
2449 (tx_work
< limit
)) {
2451 dprintk(KERN_DEBUG
"%s: nv_tx_done: flags 0x%x.\n",
2454 nv_unmap_txskb(np
, np
->get_tx_ctx
);
2456 if (np
->desc_ver
== DESC_VER_1
) {
2457 if (flags
& NV_TX_LASTPACKET
) {
2458 if (flags
& NV_TX_ERROR
) {
2459 if (flags
& NV_TX_UNDERFLOW
)
2460 dev
->stats
.tx_fifo_errors
++;
2461 if (flags
& NV_TX_CARRIERLOST
)
2462 dev
->stats
.tx_carrier_errors
++;
2463 if ((flags
& NV_TX_RETRYERROR
) && !(flags
& NV_TX_RETRYCOUNT_MASK
))
2464 nv_legacybackoff_reseed(dev
);
2465 dev
->stats
.tx_errors
++;
2467 dev
->stats
.tx_packets
++;
2468 dev
->stats
.tx_bytes
+= np
->get_tx_ctx
->skb
->len
;
2470 dev_kfree_skb_any(np
->get_tx_ctx
->skb
);
2471 np
->get_tx_ctx
->skb
= NULL
;
2475 if (flags
& NV_TX2_LASTPACKET
) {
2476 if (flags
& NV_TX2_ERROR
) {
2477 if (flags
& NV_TX2_UNDERFLOW
)
2478 dev
->stats
.tx_fifo_errors
++;
2479 if (flags
& NV_TX2_CARRIERLOST
)
2480 dev
->stats
.tx_carrier_errors
++;
2481 if ((flags
& NV_TX2_RETRYERROR
) && !(flags
& NV_TX2_RETRYCOUNT_MASK
))
2482 nv_legacybackoff_reseed(dev
);
2483 dev
->stats
.tx_errors
++;
2485 dev
->stats
.tx_packets
++;
2486 dev
->stats
.tx_bytes
+= np
->get_tx_ctx
->skb
->len
;
2488 dev_kfree_skb_any(np
->get_tx_ctx
->skb
);
2489 np
->get_tx_ctx
->skb
= NULL
;
2493 if (unlikely(np
->get_tx
.orig
++ == np
->last_tx
.orig
))
2494 np
->get_tx
.orig
= np
->first_tx
.orig
;
2495 if (unlikely(np
->get_tx_ctx
++ == np
->last_tx_ctx
))
2496 np
->get_tx_ctx
= np
->first_tx_ctx
;
2498 if (unlikely((np
->tx_stop
== 1) && (np
->get_tx
.orig
!= orig_get_tx
))) {
2500 netif_wake_queue(dev
);
2505 static int nv_tx_done_optimized(struct net_device
*dev
, int limit
)
2507 struct fe_priv
*np
= netdev_priv(dev
);
2510 struct ring_desc_ex
* orig_get_tx
= np
->get_tx
.ex
;
2512 while ((np
->get_tx
.ex
!= np
->put_tx
.ex
) &&
2513 !((flags
= le32_to_cpu(np
->get_tx
.ex
->flaglen
)) & NV_TX_VALID
) &&
2514 (tx_work
< limit
)) {
2516 dprintk(KERN_DEBUG
"%s: nv_tx_done_optimized: flags 0x%x.\n",
2519 nv_unmap_txskb(np
, np
->get_tx_ctx
);
2521 if (flags
& NV_TX2_LASTPACKET
) {
2522 if (!(flags
& NV_TX2_ERROR
))
2523 dev
->stats
.tx_packets
++;
2525 if ((flags
& NV_TX2_RETRYERROR
) && !(flags
& NV_TX2_RETRYCOUNT_MASK
)) {
2526 if (np
->driver_data
& DEV_HAS_GEAR_MODE
)
2527 nv_gear_backoff_reseed(dev
);
2529 nv_legacybackoff_reseed(dev
);
2533 dev_kfree_skb_any(np
->get_tx_ctx
->skb
);
2534 np
->get_tx_ctx
->skb
= NULL
;
2538 nv_tx_flip_ownership(dev
);
2541 if (unlikely(np
->get_tx
.ex
++ == np
->last_tx
.ex
))
2542 np
->get_tx
.ex
= np
->first_tx
.ex
;
2543 if (unlikely(np
->get_tx_ctx
++ == np
->last_tx_ctx
))
2544 np
->get_tx_ctx
= np
->first_tx_ctx
;
2546 if (unlikely((np
->tx_stop
== 1) && (np
->get_tx
.ex
!= orig_get_tx
))) {
2548 netif_wake_queue(dev
);
2554 * nv_tx_timeout: dev->tx_timeout function
2555 * Called with netif_tx_lock held.
2557 static void nv_tx_timeout(struct net_device
*dev
)
2559 struct fe_priv
*np
= netdev_priv(dev
);
2560 u8 __iomem
*base
= get_hwbase(dev
);
2562 union ring_type put_tx
;
2565 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
2566 status
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
2568 status
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
2570 printk(KERN_INFO
"%s: Got tx_timeout. irq: %08x\n", dev
->name
, status
);
2575 printk(KERN_INFO
"%s: Ring at %lx\n",
2576 dev
->name
, (unsigned long)np
->ring_addr
);
2577 printk(KERN_INFO
"%s: Dumping tx registers\n", dev
->name
);
2578 for (i
=0;i
<=np
->register_size
;i
+= 32) {
2579 printk(KERN_INFO
"%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2581 readl(base
+ i
+ 0), readl(base
+ i
+ 4),
2582 readl(base
+ i
+ 8), readl(base
+ i
+ 12),
2583 readl(base
+ i
+ 16), readl(base
+ i
+ 20),
2584 readl(base
+ i
+ 24), readl(base
+ i
+ 28));
2586 printk(KERN_INFO
"%s: Dumping tx ring\n", dev
->name
);
2587 for (i
=0;i
<np
->tx_ring_size
;i
+= 4) {
2588 if (!nv_optimized(np
)) {
2589 printk(KERN_INFO
"%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2591 le32_to_cpu(np
->tx_ring
.orig
[i
].buf
),
2592 le32_to_cpu(np
->tx_ring
.orig
[i
].flaglen
),
2593 le32_to_cpu(np
->tx_ring
.orig
[i
+1].buf
),
2594 le32_to_cpu(np
->tx_ring
.orig
[i
+1].flaglen
),
2595 le32_to_cpu(np
->tx_ring
.orig
[i
+2].buf
),
2596 le32_to_cpu(np
->tx_ring
.orig
[i
+2].flaglen
),
2597 le32_to_cpu(np
->tx_ring
.orig
[i
+3].buf
),
2598 le32_to_cpu(np
->tx_ring
.orig
[i
+3].flaglen
));
2600 printk(KERN_INFO
"%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2602 le32_to_cpu(np
->tx_ring
.ex
[i
].bufhigh
),
2603 le32_to_cpu(np
->tx_ring
.ex
[i
].buflow
),
2604 le32_to_cpu(np
->tx_ring
.ex
[i
].flaglen
),
2605 le32_to_cpu(np
->tx_ring
.ex
[i
+1].bufhigh
),
2606 le32_to_cpu(np
->tx_ring
.ex
[i
+1].buflow
),
2607 le32_to_cpu(np
->tx_ring
.ex
[i
+1].flaglen
),
2608 le32_to_cpu(np
->tx_ring
.ex
[i
+2].bufhigh
),
2609 le32_to_cpu(np
->tx_ring
.ex
[i
+2].buflow
),
2610 le32_to_cpu(np
->tx_ring
.ex
[i
+2].flaglen
),
2611 le32_to_cpu(np
->tx_ring
.ex
[i
+3].bufhigh
),
2612 le32_to_cpu(np
->tx_ring
.ex
[i
+3].buflow
),
2613 le32_to_cpu(np
->tx_ring
.ex
[i
+3].flaglen
));
2618 spin_lock_irq(&np
->lock
);
2620 /* 1) stop tx engine */
2623 /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2624 saved_tx_limit
= np
->tx_limit
;
2625 np
->tx_limit
= 0; /* prevent giving HW any limited pkts */
2626 np
->tx_stop
= 0; /* prevent waking tx queue */
2627 if (!nv_optimized(np
))
2628 nv_tx_done(dev
, np
->tx_ring_size
);
2630 nv_tx_done_optimized(dev
, np
->tx_ring_size
);
2632 /* save current HW postion */
2633 if (np
->tx_change_owner
)
2634 put_tx
.ex
= np
->tx_change_owner
->first_tx_desc
;
2636 put_tx
= np
->put_tx
;
2638 /* 3) clear all tx state */
2642 /* 4) restore state to current HW position */
2643 np
->get_tx
= np
->put_tx
= put_tx
;
2644 np
->tx_limit
= saved_tx_limit
;
2646 /* 5) restart tx engine */
2648 netif_wake_queue(dev
);
2649 spin_unlock_irq(&np
->lock
);
2653 * Called when the nic notices a mismatch between the actual data len on the
2654 * wire and the len indicated in the 802 header
2656 static int nv_getlen(struct net_device
*dev
, void *packet
, int datalen
)
2658 int hdrlen
; /* length of the 802 header */
2659 int protolen
; /* length as stored in the proto field */
2661 /* 1) calculate len according to header */
2662 if ( ((struct vlan_ethhdr
*)packet
)->h_vlan_proto
== htons(ETH_P_8021Q
)) {
2663 protolen
= ntohs( ((struct vlan_ethhdr
*)packet
)->h_vlan_encapsulated_proto
);
2666 protolen
= ntohs( ((struct ethhdr
*)packet
)->h_proto
);
2669 dprintk(KERN_DEBUG
"%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2670 dev
->name
, datalen
, protolen
, hdrlen
);
2671 if (protolen
> ETH_DATA_LEN
)
2672 return datalen
; /* Value in proto field not a len, no checks possible */
2675 /* consistency checks: */
2676 if (datalen
> ETH_ZLEN
) {
2677 if (datalen
>= protolen
) {
2678 /* more data on wire than in 802 header, trim of
2681 dprintk(KERN_DEBUG
"%s: nv_getlen: accepting %d bytes.\n",
2682 dev
->name
, protolen
);
2685 /* less data on wire than mentioned in header.
2686 * Discard the packet.
2688 dprintk(KERN_DEBUG
"%s: nv_getlen: discarding long packet.\n",
2693 /* short packet. Accept only if 802 values are also short */
2694 if (protolen
> ETH_ZLEN
) {
2695 dprintk(KERN_DEBUG
"%s: nv_getlen: discarding short packet.\n",
2699 dprintk(KERN_DEBUG
"%s: nv_getlen: accepting %d bytes.\n",
2700 dev
->name
, datalen
);
2705 static int nv_rx_process(struct net_device
*dev
, int limit
)
2707 struct fe_priv
*np
= netdev_priv(dev
);
2710 struct sk_buff
*skb
;
2713 while((np
->get_rx
.orig
!= np
->put_rx
.orig
) &&
2714 !((flags
= le32_to_cpu(np
->get_rx
.orig
->flaglen
)) & NV_RX_AVAIL
) &&
2715 (rx_work
< limit
)) {
2717 dprintk(KERN_DEBUG
"%s: nv_rx_process: flags 0x%x.\n",
2721 * the packet is for us - immediately tear down the pci mapping.
2722 * TODO: check if a prefetch of the first cacheline improves
2725 pci_unmap_single(np
->pci_dev
, np
->get_rx_ctx
->dma
,
2726 np
->get_rx_ctx
->dma_len
,
2727 PCI_DMA_FROMDEVICE
);
2728 skb
= np
->get_rx_ctx
->skb
;
2729 np
->get_rx_ctx
->skb
= NULL
;
2733 dprintk(KERN_DEBUG
"Dumping packet (flags 0x%x).",flags
);
2734 for (j
=0; j
<64; j
++) {
2736 dprintk("\n%03x:", j
);
2737 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
2741 /* look at what we actually got: */
2742 if (np
->desc_ver
== DESC_VER_1
) {
2743 if (likely(flags
& NV_RX_DESCRIPTORVALID
)) {
2744 len
= flags
& LEN_MASK_V1
;
2745 if (unlikely(flags
& NV_RX_ERROR
)) {
2746 if ((flags
& NV_RX_ERROR_MASK
) == NV_RX_ERROR4
) {
2747 len
= nv_getlen(dev
, skb
->data
, len
);
2749 dev
->stats
.rx_errors
++;
2754 /* framing errors are soft errors */
2755 else if ((flags
& NV_RX_ERROR_MASK
) == NV_RX_FRAMINGERR
) {
2756 if (flags
& NV_RX_SUBSTRACT1
) {
2760 /* the rest are hard errors */
2762 if (flags
& NV_RX_MISSEDFRAME
)
2763 dev
->stats
.rx_missed_errors
++;
2764 if (flags
& NV_RX_CRCERR
)
2765 dev
->stats
.rx_crc_errors
++;
2766 if (flags
& NV_RX_OVERFLOW
)
2767 dev
->stats
.rx_over_errors
++;
2768 dev
->stats
.rx_errors
++;
2778 if (likely(flags
& NV_RX2_DESCRIPTORVALID
)) {
2779 len
= flags
& LEN_MASK_V2
;
2780 if (unlikely(flags
& NV_RX2_ERROR
)) {
2781 if ((flags
& NV_RX2_ERROR_MASK
) == NV_RX2_ERROR4
) {
2782 len
= nv_getlen(dev
, skb
->data
, len
);
2784 dev
->stats
.rx_errors
++;
2789 /* framing errors are soft errors */
2790 else if ((flags
& NV_RX2_ERROR_MASK
) == NV_RX2_FRAMINGERR
) {
2791 if (flags
& NV_RX2_SUBSTRACT1
) {
2795 /* the rest are hard errors */
2797 if (flags
& NV_RX2_CRCERR
)
2798 dev
->stats
.rx_crc_errors
++;
2799 if (flags
& NV_RX2_OVERFLOW
)
2800 dev
->stats
.rx_over_errors
++;
2801 dev
->stats
.rx_errors
++;
2806 if (((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_TCP
) || /*ip and tcp */
2807 ((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_UDP
)) /*ip and udp */
2808 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2814 /* got a valid packet - forward it to the network core */
2816 skb
->protocol
= eth_type_trans(skb
, dev
);
2817 dprintk(KERN_DEBUG
"%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2818 dev
->name
, len
, skb
->protocol
);
2819 #ifdef CONFIG_FORCEDETH_NAPI
2820 netif_receive_skb(skb
);
2824 dev
->stats
.rx_packets
++;
2825 dev
->stats
.rx_bytes
+= len
;
2827 if (unlikely(np
->get_rx
.orig
++ == np
->last_rx
.orig
))
2828 np
->get_rx
.orig
= np
->first_rx
.orig
;
2829 if (unlikely(np
->get_rx_ctx
++ == np
->last_rx_ctx
))
2830 np
->get_rx_ctx
= np
->first_rx_ctx
;
2838 static int nv_rx_process_optimized(struct net_device
*dev
, int limit
)
2840 struct fe_priv
*np
= netdev_priv(dev
);
2844 struct sk_buff
*skb
;
2847 while((np
->get_rx
.ex
!= np
->put_rx
.ex
) &&
2848 !((flags
= le32_to_cpu(np
->get_rx
.ex
->flaglen
)) & NV_RX2_AVAIL
) &&
2849 (rx_work
< limit
)) {
2851 dprintk(KERN_DEBUG
"%s: nv_rx_process_optimized: flags 0x%x.\n",
2855 * the packet is for us - immediately tear down the pci mapping.
2856 * TODO: check if a prefetch of the first cacheline improves
2859 pci_unmap_single(np
->pci_dev
, np
->get_rx_ctx
->dma
,
2860 np
->get_rx_ctx
->dma_len
,
2861 PCI_DMA_FROMDEVICE
);
2862 skb
= np
->get_rx_ctx
->skb
;
2863 np
->get_rx_ctx
->skb
= NULL
;
2867 dprintk(KERN_DEBUG
"Dumping packet (flags 0x%x).",flags
);
2868 for (j
=0; j
<64; j
++) {
2870 dprintk("\n%03x:", j
);
2871 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
2875 /* look at what we actually got: */
2876 if (likely(flags
& NV_RX2_DESCRIPTORVALID
)) {
2877 len
= flags
& LEN_MASK_V2
;
2878 if (unlikely(flags
& NV_RX2_ERROR
)) {
2879 if ((flags
& NV_RX2_ERROR_MASK
) == NV_RX2_ERROR4
) {
2880 len
= nv_getlen(dev
, skb
->data
, len
);
2886 /* framing errors are soft errors */
2887 else if ((flags
& NV_RX2_ERROR_MASK
) == NV_RX2_FRAMINGERR
) {
2888 if (flags
& NV_RX2_SUBSTRACT1
) {
2892 /* the rest are hard errors */
2899 if (((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_TCP
) || /*ip and tcp */
2900 ((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_UDP
)) /*ip and udp */
2901 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2903 /* got a valid packet - forward it to the network core */
2905 skb
->protocol
= eth_type_trans(skb
, dev
);
2906 prefetch(skb
->data
);
2908 dprintk(KERN_DEBUG
"%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2909 dev
->name
, len
, skb
->protocol
);
2911 if (likely(!np
->vlangrp
)) {
2912 #ifdef CONFIG_FORCEDETH_NAPI
2913 netif_receive_skb(skb
);
2918 vlanflags
= le32_to_cpu(np
->get_rx
.ex
->buflow
);
2919 if (vlanflags
& NV_RX3_VLAN_TAG_PRESENT
) {
2920 #ifdef CONFIG_FORCEDETH_NAPI
2921 vlan_hwaccel_receive_skb(skb
, np
->vlangrp
,
2922 vlanflags
& NV_RX3_VLAN_TAG_MASK
);
2924 vlan_hwaccel_rx(skb
, np
->vlangrp
,
2925 vlanflags
& NV_RX3_VLAN_TAG_MASK
);
2928 #ifdef CONFIG_FORCEDETH_NAPI
2929 netif_receive_skb(skb
);
2936 dev
->stats
.rx_packets
++;
2937 dev
->stats
.rx_bytes
+= len
;
2942 if (unlikely(np
->get_rx
.ex
++ == np
->last_rx
.ex
))
2943 np
->get_rx
.ex
= np
->first_rx
.ex
;
2944 if (unlikely(np
->get_rx_ctx
++ == np
->last_rx_ctx
))
2945 np
->get_rx_ctx
= np
->first_rx_ctx
;
2953 static void set_bufsize(struct net_device
*dev
)
2955 struct fe_priv
*np
= netdev_priv(dev
);
2957 if (dev
->mtu
<= ETH_DATA_LEN
)
2958 np
->rx_buf_sz
= ETH_DATA_LEN
+ NV_RX_HEADERS
;
2960 np
->rx_buf_sz
= dev
->mtu
+ NV_RX_HEADERS
;
2964 * nv_change_mtu: dev->change_mtu function
2965 * Called with dev_base_lock held for read.
2967 static int nv_change_mtu(struct net_device
*dev
, int new_mtu
)
2969 struct fe_priv
*np
= netdev_priv(dev
);
2972 if (new_mtu
< 64 || new_mtu
> np
->pkt_limit
)
2978 /* return early if the buffer sizes will not change */
2979 if (old_mtu
<= ETH_DATA_LEN
&& new_mtu
<= ETH_DATA_LEN
)
2981 if (old_mtu
== new_mtu
)
2984 /* synchronized against open : rtnl_lock() held by caller */
2985 if (netif_running(dev
)) {
2986 u8 __iomem
*base
= get_hwbase(dev
);
2988 * It seems that the nic preloads valid ring entries into an
2989 * internal buffer. The procedure for flushing everything is
2990 * guessed, there is probably a simpler approach.
2991 * Changing the MTU is a rare event, it shouldn't matter.
2993 nv_disable_irq(dev
);
2994 nv_napi_disable(dev
);
2995 netif_tx_lock_bh(dev
);
2996 netif_addr_lock(dev
);
2997 spin_lock(&np
->lock
);
3001 /* drain rx queue */
3003 /* reinit driver view of the rx queue */
3005 if (nv_init_ring(dev
)) {
3006 if (!np
->in_shutdown
)
3007 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3009 /* reinit nic view of the rx queue */
3010 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
3011 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
3012 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
3013 base
+ NvRegRingSizes
);
3015 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
3018 /* restart rx engine */
3020 spin_unlock(&np
->lock
);
3021 netif_addr_unlock(dev
);
3022 netif_tx_unlock_bh(dev
);
3023 nv_napi_enable(dev
);
3029 static void nv_copy_mac_to_hw(struct net_device
*dev
)
3031 u8 __iomem
*base
= get_hwbase(dev
);
3034 mac
[0] = (dev
->dev_addr
[0] << 0) + (dev
->dev_addr
[1] << 8) +
3035 (dev
->dev_addr
[2] << 16) + (dev
->dev_addr
[3] << 24);
3036 mac
[1] = (dev
->dev_addr
[4] << 0) + (dev
->dev_addr
[5] << 8);
3038 writel(mac
[0], base
+ NvRegMacAddrA
);
3039 writel(mac
[1], base
+ NvRegMacAddrB
);
3043 * nv_set_mac_address: dev->set_mac_address function
3044 * Called with rtnl_lock() held.
3046 static int nv_set_mac_address(struct net_device
*dev
, void *addr
)
3048 struct fe_priv
*np
= netdev_priv(dev
);
3049 struct sockaddr
*macaddr
= (struct sockaddr
*)addr
;
3051 if (!is_valid_ether_addr(macaddr
->sa_data
))
3052 return -EADDRNOTAVAIL
;
3054 /* synchronized against open : rtnl_lock() held by caller */
3055 memcpy(dev
->dev_addr
, macaddr
->sa_data
, ETH_ALEN
);
3057 if (netif_running(dev
)) {
3058 netif_tx_lock_bh(dev
);
3059 netif_addr_lock(dev
);
3060 spin_lock_irq(&np
->lock
);
3062 /* stop rx engine */
3065 /* set mac address */
3066 nv_copy_mac_to_hw(dev
);
3068 /* restart rx engine */
3070 spin_unlock_irq(&np
->lock
);
3071 netif_addr_unlock(dev
);
3072 netif_tx_unlock_bh(dev
);
3074 nv_copy_mac_to_hw(dev
);
3080 * nv_set_multicast: dev->set_multicast function
3081 * Called with netif_tx_lock held.
3083 static void nv_set_multicast(struct net_device
*dev
)
3085 struct fe_priv
*np
= netdev_priv(dev
);
3086 u8 __iomem
*base
= get_hwbase(dev
);
3089 u32 pff
= readl(base
+ NvRegPacketFilterFlags
) & NVREG_PFF_PAUSE_RX
;
3091 memset(addr
, 0, sizeof(addr
));
3092 memset(mask
, 0, sizeof(mask
));
3094 if (dev
->flags
& IFF_PROMISC
) {
3095 pff
|= NVREG_PFF_PROMISC
;
3097 pff
|= NVREG_PFF_MYADDR
;
3099 if (dev
->flags
& IFF_ALLMULTI
|| !netdev_mc_empty(dev
)) {
3103 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0xffffffff;
3104 if (dev
->flags
& IFF_ALLMULTI
) {
3105 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0;
3107 struct netdev_hw_addr
*ha
;
3109 netdev_for_each_mc_addr(ha
, dev
) {
3110 unsigned char *addr
= ha
->addr
;
3113 a
= le32_to_cpu(*(__le32
*) addr
);
3114 b
= le16_to_cpu(*(__le16
*) (&addr
[4]));
3121 addr
[0] = alwaysOn
[0];
3122 addr
[1] = alwaysOn
[1];
3123 mask
[0] = alwaysOn
[0] | alwaysOff
[0];
3124 mask
[1] = alwaysOn
[1] | alwaysOff
[1];
3126 mask
[0] = NVREG_MCASTMASKA_NONE
;
3127 mask
[1] = NVREG_MCASTMASKB_NONE
;
3130 addr
[0] |= NVREG_MCASTADDRA_FORCE
;
3131 pff
|= NVREG_PFF_ALWAYS
;
3132 spin_lock_irq(&np
->lock
);
3134 writel(addr
[0], base
+ NvRegMulticastAddrA
);
3135 writel(addr
[1], base
+ NvRegMulticastAddrB
);
3136 writel(mask
[0], base
+ NvRegMulticastMaskA
);
3137 writel(mask
[1], base
+ NvRegMulticastMaskB
);
3138 writel(pff
, base
+ NvRegPacketFilterFlags
);
3139 dprintk(KERN_INFO
"%s: reconfiguration for multicast lists.\n",
3142 spin_unlock_irq(&np
->lock
);
3145 static void nv_update_pause(struct net_device
*dev
, u32 pause_flags
)
3147 struct fe_priv
*np
= netdev_priv(dev
);
3148 u8 __iomem
*base
= get_hwbase(dev
);
3150 np
->pause_flags
&= ~(NV_PAUSEFRAME_TX_ENABLE
| NV_PAUSEFRAME_RX_ENABLE
);
3152 if (np
->pause_flags
& NV_PAUSEFRAME_RX_CAPABLE
) {
3153 u32 pff
= readl(base
+ NvRegPacketFilterFlags
) & ~NVREG_PFF_PAUSE_RX
;
3154 if (pause_flags
& NV_PAUSEFRAME_RX_ENABLE
) {
3155 writel(pff
|NVREG_PFF_PAUSE_RX
, base
+ NvRegPacketFilterFlags
);
3156 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3158 writel(pff
, base
+ NvRegPacketFilterFlags
);
3161 if (np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
) {
3162 u32 regmisc
= readl(base
+ NvRegMisc1
) & ~NVREG_MISC1_PAUSE_TX
;
3163 if (pause_flags
& NV_PAUSEFRAME_TX_ENABLE
) {
3164 u32 pause_enable
= NVREG_TX_PAUSEFRAME_ENABLE_V1
;
3165 if (np
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V2
)
3166 pause_enable
= NVREG_TX_PAUSEFRAME_ENABLE_V2
;
3167 if (np
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V3
) {
3168 pause_enable
= NVREG_TX_PAUSEFRAME_ENABLE_V3
;
3169 /* limit the number of tx pause frames to a default of 8 */
3170 writel(readl(base
+ NvRegTxPauseFrameLimit
)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE
, base
+ NvRegTxPauseFrameLimit
);
3172 writel(pause_enable
, base
+ NvRegTxPauseFrame
);
3173 writel(regmisc
|NVREG_MISC1_PAUSE_TX
, base
+ NvRegMisc1
);
3174 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3176 writel(NVREG_TX_PAUSEFRAME_DISABLE
, base
+ NvRegTxPauseFrame
);
3177 writel(regmisc
, base
+ NvRegMisc1
);
3183 * nv_update_linkspeed: Setup the MAC according to the link partner
3184 * @dev: Network device to be configured
3186 * The function queries the PHY and checks if there is a link partner.
3187 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3188 * set to 10 MBit HD.
3190 * The function returns 0 if there is no link partner and 1 if there is
3191 * a good link partner.
3193 static int nv_update_linkspeed(struct net_device
*dev
)
3195 struct fe_priv
*np
= netdev_priv(dev
);
3196 u8 __iomem
*base
= get_hwbase(dev
);
3199 int adv_lpa
, adv_pause
, lpa_pause
;
3200 int newls
= np
->linkspeed
;
3201 int newdup
= np
->duplex
;
3204 u32 control_1000
, status_1000
, phyreg
, pause_flags
, txreg
;
3208 /* BMSR_LSTATUS is latched, read it twice:
3209 * we want the current value.
3211 mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
3212 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
3214 if (!(mii_status
& BMSR_LSTATUS
)) {
3215 dprintk(KERN_DEBUG
"%s: no link detected by phy - falling back to 10HD.\n",
3217 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3223 if (np
->autoneg
== 0) {
3224 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3225 dev
->name
, np
->fixed_mode
);
3226 if (np
->fixed_mode
& LPA_100FULL
) {
3227 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3229 } else if (np
->fixed_mode
& LPA_100HALF
) {
3230 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3232 } else if (np
->fixed_mode
& LPA_10FULL
) {
3233 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3236 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3242 /* check auto negotiation is complete */
3243 if (!(mii_status
& BMSR_ANEGCOMPLETE
)) {
3244 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3245 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3248 dprintk(KERN_DEBUG
"%s: autoneg not completed - falling back to 10HD.\n", dev
->name
);
3252 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
3253 lpa
= mii_rw(dev
, np
->phyaddr
, MII_LPA
, MII_READ
);
3254 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3255 dev
->name
, adv
, lpa
);
3258 if (np
->gigabit
== PHY_GIGABIT
) {
3259 control_1000
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
3260 status_1000
= mii_rw(dev
, np
->phyaddr
, MII_STAT1000
, MII_READ
);
3262 if ((control_1000
& ADVERTISE_1000FULL
) &&
3263 (status_1000
& LPA_1000FULL
)) {
3264 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: GBit ethernet detected.\n",
3266 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_1000
;
3272 /* FIXME: handle parallel detection properly */
3273 adv_lpa
= lpa
& adv
;
3274 if (adv_lpa
& LPA_100FULL
) {
3275 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3277 } else if (adv_lpa
& LPA_100HALF
) {
3278 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3280 } else if (adv_lpa
& LPA_10FULL
) {
3281 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3283 } else if (adv_lpa
& LPA_10HALF
) {
3284 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3287 dprintk(KERN_DEBUG
"%s: bad ability %04x - falling back to 10HD.\n", dev
->name
, adv_lpa
);
3288 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3293 if (np
->duplex
== newdup
&& np
->linkspeed
== newls
)
3296 dprintk(KERN_INFO
"%s: changing link setting from %d/%d to %d/%d.\n",
3297 dev
->name
, np
->linkspeed
, np
->duplex
, newls
, newdup
);
3299 np
->duplex
= newdup
;
3300 np
->linkspeed
= newls
;
3302 /* The transmitter and receiver must be restarted for safe update */
3303 if (readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_START
) {
3304 txrxFlags
|= NV_RESTART_TX
;
3307 if (readl(base
+ NvRegReceiverControl
) & NVREG_RCVCTL_START
) {
3308 txrxFlags
|= NV_RESTART_RX
;
3312 if (np
->gigabit
== PHY_GIGABIT
) {
3313 phyreg
= readl(base
+ NvRegSlotTime
);
3314 phyreg
&= ~(0x3FF00);
3315 if (((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_10
) ||
3316 ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_100
))
3317 phyreg
|= NVREG_SLOTTIME_10_100_FULL
;
3318 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_1000
)
3319 phyreg
|= NVREG_SLOTTIME_1000_FULL
;
3320 writel(phyreg
, base
+ NvRegSlotTime
);
3323 phyreg
= readl(base
+ NvRegPhyInterface
);
3324 phyreg
&= ~(PHY_HALF
|PHY_100
|PHY_1000
);
3325 if (np
->duplex
== 0)
3327 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_100
)
3329 else if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
3331 writel(phyreg
, base
+ NvRegPhyInterface
);
3333 phy_exp
= mii_rw(dev
, np
->phyaddr
, MII_EXPANSION
, MII_READ
) & EXPANSION_NWAY
; /* autoneg capable */
3334 if (phyreg
& PHY_RGMII
) {
3335 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
) {
3336 txreg
= NVREG_TX_DEFERRAL_RGMII_1000
;
3338 if (!phy_exp
&& !np
->duplex
&& (np
->driver_data
& DEV_HAS_COLLISION_FIX
)) {
3339 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_10
)
3340 txreg
= NVREG_TX_DEFERRAL_RGMII_STRETCH_10
;
3342 txreg
= NVREG_TX_DEFERRAL_RGMII_STRETCH_100
;
3344 txreg
= NVREG_TX_DEFERRAL_RGMII_10_100
;
3348 if (!phy_exp
&& !np
->duplex
&& (np
->driver_data
& DEV_HAS_COLLISION_FIX
))
3349 txreg
= NVREG_TX_DEFERRAL_MII_STRETCH
;
3351 txreg
= NVREG_TX_DEFERRAL_DEFAULT
;
3353 writel(txreg
, base
+ NvRegTxDeferral
);
3355 if (np
->desc_ver
== DESC_VER_1
) {
3356 txreg
= NVREG_TX_WM_DESC1_DEFAULT
;
3358 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
3359 txreg
= NVREG_TX_WM_DESC2_3_1000
;
3361 txreg
= NVREG_TX_WM_DESC2_3_DEFAULT
;
3363 writel(txreg
, base
+ NvRegTxWatermark
);
3365 writel(NVREG_MISC1_FORCE
| ( np
->duplex
? 0 : NVREG_MISC1_HD
),
3368 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
3372 /* setup pause frame */
3373 if (np
->duplex
!= 0) {
3374 if (np
->autoneg
&& np
->pause_flags
& NV_PAUSEFRAME_AUTONEG
) {
3375 adv_pause
= adv
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
3376 lpa_pause
= lpa
& (LPA_PAUSE_CAP
| LPA_PAUSE_ASYM
);
3378 switch (adv_pause
) {
3379 case ADVERTISE_PAUSE_CAP
:
3380 if (lpa_pause
& LPA_PAUSE_CAP
) {
3381 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3382 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
3383 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3386 case ADVERTISE_PAUSE_ASYM
:
3387 if (lpa_pause
== (LPA_PAUSE_CAP
| LPA_PAUSE_ASYM
))
3389 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3392 case ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
:
3393 if (lpa_pause
& LPA_PAUSE_CAP
)
3395 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3396 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
3397 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3399 if (lpa_pause
== LPA_PAUSE_ASYM
)
3401 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3406 pause_flags
= np
->pause_flags
;
3409 nv_update_pause(dev
, pause_flags
);
3411 if (txrxFlags
& NV_RESTART_TX
)
3413 if (txrxFlags
& NV_RESTART_RX
)
3419 static void nv_linkchange(struct net_device
*dev
)
3421 if (nv_update_linkspeed(dev
)) {
3422 if (!netif_carrier_ok(dev
)) {
3423 netif_carrier_on(dev
);
3424 printk(KERN_INFO
"%s: link up.\n", dev
->name
);
3425 nv_txrx_gate(dev
, false);
3429 if (netif_carrier_ok(dev
)) {
3430 netif_carrier_off(dev
);
3431 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
3432 nv_txrx_gate(dev
, true);
3438 static void nv_link_irq(struct net_device
*dev
)
3440 u8 __iomem
*base
= get_hwbase(dev
);
3443 miistat
= readl(base
+ NvRegMIIStatus
);
3444 writel(NVREG_MIISTAT_LINKCHANGE
, base
+ NvRegMIIStatus
);
3445 dprintk(KERN_INFO
"%s: link change irq, status 0x%x.\n", dev
->name
, miistat
);
3447 if (miistat
& (NVREG_MIISTAT_LINKCHANGE
))
3449 dprintk(KERN_DEBUG
"%s: link change notification done.\n", dev
->name
);
3452 static void nv_msi_workaround(struct fe_priv
*np
)
3455 /* Need to toggle the msi irq mask within the ethernet device,
3456 * otherwise, future interrupts will not be detected.
3458 if (np
->msi_flags
& NV_MSI_ENABLED
) {
3459 u8 __iomem
*base
= np
->base
;
3461 writel(0, base
+ NvRegMSIIrqMask
);
3462 writel(NVREG_MSI_VECTOR_0_ENABLED
, base
+ NvRegMSIIrqMask
);
3466 static inline int nv_change_interrupt_mode(struct net_device
*dev
, int total_work
)
3468 struct fe_priv
*np
= netdev_priv(dev
);
3470 if (optimization_mode
== NV_OPTIMIZATION_MODE_DYNAMIC
) {
3471 if (total_work
> NV_DYNAMIC_THRESHOLD
) {
3472 /* transition to poll based interrupts */
3473 np
->quiet_count
= 0;
3474 if (np
->irqmask
!= NVREG_IRQMASK_CPU
) {
3475 np
->irqmask
= NVREG_IRQMASK_CPU
;
3479 if (np
->quiet_count
< NV_DYNAMIC_MAX_QUIET_COUNT
) {
3482 /* reached a period of low activity, switch
3483 to per tx/rx packet interrupts */
3484 if (np
->irqmask
!= NVREG_IRQMASK_THROUGHPUT
) {
3485 np
->irqmask
= NVREG_IRQMASK_THROUGHPUT
;
3494 static irqreturn_t
nv_nic_irq(int foo
, void *data
)
3496 struct net_device
*dev
= (struct net_device
*) data
;
3497 struct fe_priv
*np
= netdev_priv(dev
);
3498 u8 __iomem
*base
= get_hwbase(dev
);
3499 #ifndef CONFIG_FORCEDETH_NAPI
3504 dprintk(KERN_DEBUG
"%s: nv_nic_irq\n", dev
->name
);
3506 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
3507 np
->events
= readl(base
+ NvRegIrqStatus
);
3508 writel(np
->events
, base
+ NvRegIrqStatus
);
3510 np
->events
= readl(base
+ NvRegMSIXIrqStatus
);
3511 writel(np
->events
, base
+ NvRegMSIXIrqStatus
);
3513 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, np
->events
);
3514 if (!(np
->events
& np
->irqmask
))
3517 nv_msi_workaround(np
);
3519 #ifdef CONFIG_FORCEDETH_NAPI
3520 if (napi_schedule_prep(&np
->napi
)) {
3522 * Disable further irq's (msix not enabled with napi)
3524 writel(0, base
+ NvRegIrqMask
);
3525 __napi_schedule(&np
->napi
);
3532 if ((work
= nv_rx_process(dev
, RX_WORK_PER_LOOP
))) {
3533 if (unlikely(nv_alloc_rx(dev
))) {
3534 spin_lock(&np
->lock
);
3535 if (!np
->in_shutdown
)
3536 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3537 spin_unlock(&np
->lock
);
3541 spin_lock(&np
->lock
);
3542 work
+= nv_tx_done(dev
, TX_WORK_PER_LOOP
);
3543 spin_unlock(&np
->lock
);
3552 while (loop_count
< max_interrupt_work
);
3554 if (nv_change_interrupt_mode(dev
, total_work
)) {
3555 /* setup new irq mask */
3556 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3559 if (unlikely(np
->events
& NVREG_IRQ_LINK
)) {
3560 spin_lock(&np
->lock
);
3562 spin_unlock(&np
->lock
);
3564 if (unlikely(np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
))) {
3565 spin_lock(&np
->lock
);
3567 spin_unlock(&np
->lock
);
3568 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
3570 if (unlikely(np
->events
& NVREG_IRQ_RECOVER_ERROR
)) {
3571 spin_lock(&np
->lock
);
3572 /* disable interrupts on the nic */
3573 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
3574 writel(0, base
+ NvRegIrqMask
);
3576 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3579 if (!np
->in_shutdown
) {
3580 np
->nic_poll_irq
= np
->irqmask
;
3581 np
->recover_error
= 1;
3582 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3584 spin_unlock(&np
->lock
);
3587 dprintk(KERN_DEBUG
"%s: nv_nic_irq completed\n", dev
->name
);
3593 * All _optimized functions are used to help increase performance
3594 * (reduce CPU and increase throughput). They use descripter version 3,
3595 * compiler directives, and reduce memory accesses.
3597 static irqreturn_t
nv_nic_irq_optimized(int foo
, void *data
)
3599 struct net_device
*dev
= (struct net_device
*) data
;
3600 struct fe_priv
*np
= netdev_priv(dev
);
3601 u8 __iomem
*base
= get_hwbase(dev
);
3602 #ifndef CONFIG_FORCEDETH_NAPI
3607 dprintk(KERN_DEBUG
"%s: nv_nic_irq_optimized\n", dev
->name
);
3609 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
3610 np
->events
= readl(base
+ NvRegIrqStatus
);
3611 writel(np
->events
, base
+ NvRegIrqStatus
);
3613 np
->events
= readl(base
+ NvRegMSIXIrqStatus
);
3614 writel(np
->events
, base
+ NvRegMSIXIrqStatus
);
3616 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, np
->events
);
3617 if (!(np
->events
& np
->irqmask
))
3620 nv_msi_workaround(np
);
3622 #ifdef CONFIG_FORCEDETH_NAPI
3623 if (napi_schedule_prep(&np
->napi
)) {
3625 * Disable further irq's (msix not enabled with napi)
3627 writel(0, base
+ NvRegIrqMask
);
3628 __napi_schedule(&np
->napi
);
3634 if ((work
= nv_rx_process_optimized(dev
, RX_WORK_PER_LOOP
))) {
3635 if (unlikely(nv_alloc_rx_optimized(dev
))) {
3636 spin_lock(&np
->lock
);
3637 if (!np
->in_shutdown
)
3638 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3639 spin_unlock(&np
->lock
);
3643 spin_lock(&np
->lock
);
3644 work
+= nv_tx_done_optimized(dev
, TX_WORK_PER_LOOP
);
3645 spin_unlock(&np
->lock
);
3654 while (loop_count
< max_interrupt_work
);
3656 if (nv_change_interrupt_mode(dev
, total_work
)) {
3657 /* setup new irq mask */
3658 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3661 if (unlikely(np
->events
& NVREG_IRQ_LINK
)) {
3662 spin_lock(&np
->lock
);
3664 spin_unlock(&np
->lock
);
3666 if (unlikely(np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
))) {
3667 spin_lock(&np
->lock
);
3669 spin_unlock(&np
->lock
);
3670 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
3672 if (unlikely(np
->events
& NVREG_IRQ_RECOVER_ERROR
)) {
3673 spin_lock(&np
->lock
);
3674 /* disable interrupts on the nic */
3675 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
3676 writel(0, base
+ NvRegIrqMask
);
3678 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3681 if (!np
->in_shutdown
) {
3682 np
->nic_poll_irq
= np
->irqmask
;
3683 np
->recover_error
= 1;
3684 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3686 spin_unlock(&np
->lock
);
3690 dprintk(KERN_DEBUG
"%s: nv_nic_irq_optimized completed\n", dev
->name
);
3695 static irqreturn_t
nv_nic_irq_tx(int foo
, void *data
)
3697 struct net_device
*dev
= (struct net_device
*) data
;
3698 struct fe_priv
*np
= netdev_priv(dev
);
3699 u8 __iomem
*base
= get_hwbase(dev
);
3702 unsigned long flags
;
3704 dprintk(KERN_DEBUG
"%s: nv_nic_irq_tx\n", dev
->name
);
3707 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_TX_ALL
;
3708 writel(NVREG_IRQ_TX_ALL
, base
+ NvRegMSIXIrqStatus
);
3709 dprintk(KERN_DEBUG
"%s: tx irq: %08x\n", dev
->name
, events
);
3710 if (!(events
& np
->irqmask
))
3713 spin_lock_irqsave(&np
->lock
, flags
);
3714 nv_tx_done_optimized(dev
, TX_WORK_PER_LOOP
);
3715 spin_unlock_irqrestore(&np
->lock
, flags
);
3717 if (unlikely(i
> max_interrupt_work
)) {
3718 spin_lock_irqsave(&np
->lock
, flags
);
3719 /* disable interrupts on the nic */
3720 writel(NVREG_IRQ_TX_ALL
, base
+ NvRegIrqMask
);
3723 if (!np
->in_shutdown
) {
3724 np
->nic_poll_irq
|= NVREG_IRQ_TX_ALL
;
3725 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3727 spin_unlock_irqrestore(&np
->lock
, flags
);
3728 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev
->name
, i
);
3733 dprintk(KERN_DEBUG
"%s: nv_nic_irq_tx completed\n", dev
->name
);
3735 return IRQ_RETVAL(i
);
3738 #ifdef CONFIG_FORCEDETH_NAPI
3739 static int nv_napi_poll(struct napi_struct
*napi
, int budget
)
3741 struct fe_priv
*np
= container_of(napi
, struct fe_priv
, napi
);
3742 struct net_device
*dev
= np
->dev
;
3743 u8 __iomem
*base
= get_hwbase(dev
);
3744 unsigned long flags
;
3746 int rx_count
, tx_work
=0, rx_work
=0;
3749 if (!nv_optimized(np
)) {
3750 spin_lock_irqsave(&np
->lock
, flags
);
3751 tx_work
+= nv_tx_done(dev
, np
->tx_ring_size
);
3752 spin_unlock_irqrestore(&np
->lock
, flags
);
3754 rx_count
= nv_rx_process(dev
, budget
);
3755 retcode
= nv_alloc_rx(dev
);
3757 spin_lock_irqsave(&np
->lock
, flags
);
3758 tx_work
+= nv_tx_done_optimized(dev
, np
->tx_ring_size
);
3759 spin_unlock_irqrestore(&np
->lock
, flags
);
3761 rx_count
= nv_rx_process_optimized(dev
, budget
);
3762 retcode
= nv_alloc_rx_optimized(dev
);
3764 } while (retcode
== 0 &&
3765 rx_count
> 0 && (rx_work
+= rx_count
) < budget
);
3768 spin_lock_irqsave(&np
->lock
, flags
);
3769 if (!np
->in_shutdown
)
3770 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3771 spin_unlock_irqrestore(&np
->lock
, flags
);
3774 nv_change_interrupt_mode(dev
, tx_work
+ rx_work
);
3776 if (unlikely(np
->events
& NVREG_IRQ_LINK
)) {
3777 spin_lock_irqsave(&np
->lock
, flags
);
3779 spin_unlock_irqrestore(&np
->lock
, flags
);
3781 if (unlikely(np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
))) {
3782 spin_lock_irqsave(&np
->lock
, flags
);
3784 spin_unlock_irqrestore(&np
->lock
, flags
);
3785 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
3787 if (unlikely(np
->events
& NVREG_IRQ_RECOVER_ERROR
)) {
3788 spin_lock_irqsave(&np
->lock
, flags
);
3789 if (!np
->in_shutdown
) {
3790 np
->nic_poll_irq
= np
->irqmask
;
3791 np
->recover_error
= 1;
3792 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3794 spin_unlock_irqrestore(&np
->lock
, flags
);
3795 napi_complete(napi
);
3799 if (rx_work
< budget
) {
3800 /* re-enable interrupts
3801 (msix not enabled in napi) */
3802 napi_complete(napi
);
3804 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3810 static irqreturn_t
nv_nic_irq_rx(int foo
, void *data
)
3812 struct net_device
*dev
= (struct net_device
*) data
;
3813 struct fe_priv
*np
= netdev_priv(dev
);
3814 u8 __iomem
*base
= get_hwbase(dev
);
3817 unsigned long flags
;
3819 dprintk(KERN_DEBUG
"%s: nv_nic_irq_rx\n", dev
->name
);
3822 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_RX_ALL
;
3823 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegMSIXIrqStatus
);
3824 dprintk(KERN_DEBUG
"%s: rx irq: %08x\n", dev
->name
, events
);
3825 if (!(events
& np
->irqmask
))
3828 if (nv_rx_process_optimized(dev
, RX_WORK_PER_LOOP
)) {
3829 if (unlikely(nv_alloc_rx_optimized(dev
))) {
3830 spin_lock_irqsave(&np
->lock
, flags
);
3831 if (!np
->in_shutdown
)
3832 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3833 spin_unlock_irqrestore(&np
->lock
, flags
);
3837 if (unlikely(i
> max_interrupt_work
)) {
3838 spin_lock_irqsave(&np
->lock
, flags
);
3839 /* disable interrupts on the nic */
3840 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
3843 if (!np
->in_shutdown
) {
3844 np
->nic_poll_irq
|= NVREG_IRQ_RX_ALL
;
3845 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3847 spin_unlock_irqrestore(&np
->lock
, flags
);
3848 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev
->name
, i
);
3852 dprintk(KERN_DEBUG
"%s: nv_nic_irq_rx completed\n", dev
->name
);
3854 return IRQ_RETVAL(i
);
3857 static irqreturn_t
nv_nic_irq_other(int foo
, void *data
)
3859 struct net_device
*dev
= (struct net_device
*) data
;
3860 struct fe_priv
*np
= netdev_priv(dev
);
3861 u8 __iomem
*base
= get_hwbase(dev
);
3864 unsigned long flags
;
3866 dprintk(KERN_DEBUG
"%s: nv_nic_irq_other\n", dev
->name
);
3869 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_OTHER
;
3870 writel(NVREG_IRQ_OTHER
, base
+ NvRegMSIXIrqStatus
);
3871 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
3872 if (!(events
& np
->irqmask
))
3875 /* check tx in case we reached max loop limit in tx isr */
3876 spin_lock_irqsave(&np
->lock
, flags
);
3877 nv_tx_done_optimized(dev
, TX_WORK_PER_LOOP
);
3878 spin_unlock_irqrestore(&np
->lock
, flags
);
3880 if (events
& NVREG_IRQ_LINK
) {
3881 spin_lock_irqsave(&np
->lock
, flags
);
3883 spin_unlock_irqrestore(&np
->lock
, flags
);
3885 if (np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
)) {
3886 spin_lock_irqsave(&np
->lock
, flags
);
3888 spin_unlock_irqrestore(&np
->lock
, flags
);
3889 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
3891 if (events
& NVREG_IRQ_RECOVER_ERROR
) {
3892 spin_lock_irq(&np
->lock
);
3893 /* disable interrupts on the nic */
3894 writel(NVREG_IRQ_OTHER
, base
+ NvRegIrqMask
);
3897 if (!np
->in_shutdown
) {
3898 np
->nic_poll_irq
|= NVREG_IRQ_OTHER
;
3899 np
->recover_error
= 1;
3900 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3902 spin_unlock_irq(&np
->lock
);
3905 if (unlikely(i
> max_interrupt_work
)) {
3906 spin_lock_irqsave(&np
->lock
, flags
);
3907 /* disable interrupts on the nic */
3908 writel(NVREG_IRQ_OTHER
, base
+ NvRegIrqMask
);
3911 if (!np
->in_shutdown
) {
3912 np
->nic_poll_irq
|= NVREG_IRQ_OTHER
;
3913 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3915 spin_unlock_irqrestore(&np
->lock
, flags
);
3916 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_other.\n", dev
->name
, i
);
3921 dprintk(KERN_DEBUG
"%s: nv_nic_irq_other completed\n", dev
->name
);
3923 return IRQ_RETVAL(i
);
3926 static irqreturn_t
nv_nic_irq_test(int foo
, void *data
)
3928 struct net_device
*dev
= (struct net_device
*) data
;
3929 struct fe_priv
*np
= netdev_priv(dev
);
3930 u8 __iomem
*base
= get_hwbase(dev
);
3933 dprintk(KERN_DEBUG
"%s: nv_nic_irq_test\n", dev
->name
);
3935 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
3936 events
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
3937 writel(NVREG_IRQ_TIMER
, base
+ NvRegIrqStatus
);
3939 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
3940 writel(NVREG_IRQ_TIMER
, base
+ NvRegMSIXIrqStatus
);
3943 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
3944 if (!(events
& NVREG_IRQ_TIMER
))
3945 return IRQ_RETVAL(0);
3947 nv_msi_workaround(np
);
3949 spin_lock(&np
->lock
);
3951 spin_unlock(&np
->lock
);
3953 dprintk(KERN_DEBUG
"%s: nv_nic_irq_test completed\n", dev
->name
);
3955 return IRQ_RETVAL(1);
3958 static void set_msix_vector_map(struct net_device
*dev
, u32 vector
, u32 irqmask
)
3960 u8 __iomem
*base
= get_hwbase(dev
);
3964 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3965 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3966 * the remaining 8 interrupts.
3968 for (i
= 0; i
< 8; i
++) {
3969 if ((irqmask
>> i
) & 0x1) {
3970 msixmap
|= vector
<< (i
<< 2);
3973 writel(readl(base
+ NvRegMSIXMap0
) | msixmap
, base
+ NvRegMSIXMap0
);
3976 for (i
= 0; i
< 8; i
++) {
3977 if ((irqmask
>> (i
+ 8)) & 0x1) {
3978 msixmap
|= vector
<< (i
<< 2);
3981 writel(readl(base
+ NvRegMSIXMap1
) | msixmap
, base
+ NvRegMSIXMap1
);
3984 static int nv_request_irq(struct net_device
*dev
, int intr_test
)
3986 struct fe_priv
*np
= get_nvpriv(dev
);
3987 u8 __iomem
*base
= get_hwbase(dev
);
3990 irqreturn_t (*handler
)(int foo
, void *data
);
3993 handler
= nv_nic_irq_test
;
3995 if (nv_optimized(np
))
3996 handler
= nv_nic_irq_optimized
;
3998 handler
= nv_nic_irq
;
4001 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) {
4002 for (i
= 0; i
< (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
); i
++) {
4003 np
->msi_x_entry
[i
].entry
= i
;
4005 if ((ret
= pci_enable_msix(np
->pci_dev
, np
->msi_x_entry
, (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
))) == 0) {
4006 np
->msi_flags
|= NV_MSI_X_ENABLED
;
4007 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
&& !intr_test
) {
4008 /* Request irq for rx handling */
4009 sprintf(np
->name_rx
, "%s-rx", dev
->name
);
4010 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
,
4011 nv_nic_irq_rx
, IRQF_SHARED
, np
->name_rx
, dev
) != 0) {
4012 printk(KERN_INFO
"forcedeth: request_irq failed for rx %d\n", ret
);
4013 pci_disable_msix(np
->pci_dev
);
4014 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
4017 /* Request irq for tx handling */
4018 sprintf(np
->name_tx
, "%s-tx", dev
->name
);
4019 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
,
4020 nv_nic_irq_tx
, IRQF_SHARED
, np
->name_tx
, dev
) != 0) {
4021 printk(KERN_INFO
"forcedeth: request_irq failed for tx %d\n", ret
);
4022 pci_disable_msix(np
->pci_dev
);
4023 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
4026 /* Request irq for link and timer handling */
4027 sprintf(np
->name_other
, "%s-other", dev
->name
);
4028 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
,
4029 nv_nic_irq_other
, IRQF_SHARED
, np
->name_other
, dev
) != 0) {
4030 printk(KERN_INFO
"forcedeth: request_irq failed for link %d\n", ret
);
4031 pci_disable_msix(np
->pci_dev
);
4032 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
4035 /* map interrupts to their respective vector */
4036 writel(0, base
+ NvRegMSIXMap0
);
4037 writel(0, base
+ NvRegMSIXMap1
);
4038 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_RX
, NVREG_IRQ_RX_ALL
);
4039 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_TX
, NVREG_IRQ_TX_ALL
);
4040 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_OTHER
, NVREG_IRQ_OTHER
);
4042 /* Request irq for all interrupts */
4043 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
, handler
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
4044 printk(KERN_INFO
"forcedeth: request_irq failed %d\n", ret
);
4045 pci_disable_msix(np
->pci_dev
);
4046 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
4050 /* map interrupts to vector 0 */
4051 writel(0, base
+ NvRegMSIXMap0
);
4052 writel(0, base
+ NvRegMSIXMap1
);
4056 if (ret
!= 0 && np
->msi_flags
& NV_MSI_CAPABLE
) {
4057 if ((ret
= pci_enable_msi(np
->pci_dev
)) == 0) {
4058 np
->msi_flags
|= NV_MSI_ENABLED
;
4059 dev
->irq
= np
->pci_dev
->irq
;
4060 if (request_irq(np
->pci_dev
->irq
, handler
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
4061 printk(KERN_INFO
"forcedeth: request_irq failed %d\n", ret
);
4062 pci_disable_msi(np
->pci_dev
);
4063 np
->msi_flags
&= ~NV_MSI_ENABLED
;
4064 dev
->irq
= np
->pci_dev
->irq
;
4068 /* map interrupts to vector 0 */
4069 writel(0, base
+ NvRegMSIMap0
);
4070 writel(0, base
+ NvRegMSIMap1
);
4071 /* enable msi vector 0 */
4072 writel(NVREG_MSI_VECTOR_0_ENABLED
, base
+ NvRegMSIIrqMask
);
4076 if (request_irq(np
->pci_dev
->irq
, handler
, IRQF_SHARED
, dev
->name
, dev
) != 0)
4083 free_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
, dev
);
4085 free_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
, dev
);
4090 static void nv_free_irq(struct net_device
*dev
)
4092 struct fe_priv
*np
= get_nvpriv(dev
);
4095 if (np
->msi_flags
& NV_MSI_X_ENABLED
) {
4096 for (i
= 0; i
< (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
); i
++) {
4097 free_irq(np
->msi_x_entry
[i
].vector
, dev
);
4099 pci_disable_msix(np
->pci_dev
);
4100 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
4102 free_irq(np
->pci_dev
->irq
, dev
);
4103 if (np
->msi_flags
& NV_MSI_ENABLED
) {
4104 pci_disable_msi(np
->pci_dev
);
4105 np
->msi_flags
&= ~NV_MSI_ENABLED
;
4110 static void nv_do_nic_poll(unsigned long data
)
4112 struct net_device
*dev
= (struct net_device
*) data
;
4113 struct fe_priv
*np
= netdev_priv(dev
);
4114 u8 __iomem
*base
= get_hwbase(dev
);
4118 * First disable irq(s) and then
4119 * reenable interrupts on the nic, we have to do this before calling
4120 * nv_nic_irq because that may decide to do otherwise
4123 if (!using_multi_irqs(dev
)) {
4124 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
4125 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
4127 disable_irq_lockdep(np
->pci_dev
->irq
);
4130 if (np
->nic_poll_irq
& NVREG_IRQ_RX_ALL
) {
4131 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
4132 mask
|= NVREG_IRQ_RX_ALL
;
4134 if (np
->nic_poll_irq
& NVREG_IRQ_TX_ALL
) {
4135 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
4136 mask
|= NVREG_IRQ_TX_ALL
;
4138 if (np
->nic_poll_irq
& NVREG_IRQ_OTHER
) {
4139 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
4140 mask
|= NVREG_IRQ_OTHER
;
4143 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4145 if (np
->recover_error
) {
4146 np
->recover_error
= 0;
4147 printk(KERN_INFO
"%s: MAC in recoverable error state\n", dev
->name
);
4148 if (netif_running(dev
)) {
4149 netif_tx_lock_bh(dev
);
4150 netif_addr_lock(dev
);
4151 spin_lock(&np
->lock
);
4154 if (np
->driver_data
& DEV_HAS_POWER_CNTRL
)
4157 /* drain rx queue */
4159 /* reinit driver view of the rx queue */
4161 if (nv_init_ring(dev
)) {
4162 if (!np
->in_shutdown
)
4163 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
4165 /* reinit nic view of the rx queue */
4166 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
4167 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
4168 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
4169 base
+ NvRegRingSizes
);
4171 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
4173 /* clear interrupts */
4174 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
4175 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
4177 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
4179 /* restart rx engine */
4181 spin_unlock(&np
->lock
);
4182 netif_addr_unlock(dev
);
4183 netif_tx_unlock_bh(dev
);
4187 writel(mask
, base
+ NvRegIrqMask
);
4190 if (!using_multi_irqs(dev
)) {
4191 np
->nic_poll_irq
= 0;
4192 if (nv_optimized(np
))
4193 nv_nic_irq_optimized(0, dev
);
4196 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
4197 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
4199 enable_irq_lockdep(np
->pci_dev
->irq
);
4201 if (np
->nic_poll_irq
& NVREG_IRQ_RX_ALL
) {
4202 np
->nic_poll_irq
&= ~NVREG_IRQ_RX_ALL
;
4203 nv_nic_irq_rx(0, dev
);
4204 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
4206 if (np
->nic_poll_irq
& NVREG_IRQ_TX_ALL
) {
4207 np
->nic_poll_irq
&= ~NVREG_IRQ_TX_ALL
;
4208 nv_nic_irq_tx(0, dev
);
4209 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
4211 if (np
->nic_poll_irq
& NVREG_IRQ_OTHER
) {
4212 np
->nic_poll_irq
&= ~NVREG_IRQ_OTHER
;
4213 nv_nic_irq_other(0, dev
);
4214 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
4220 #ifdef CONFIG_NET_POLL_CONTROLLER
4221 static void nv_poll_controller(struct net_device
*dev
)
4223 nv_do_nic_poll((unsigned long) dev
);
4227 static void nv_do_stats_poll(unsigned long data
)
4229 struct net_device
*dev
= (struct net_device
*) data
;
4230 struct fe_priv
*np
= netdev_priv(dev
);
4232 nv_get_hw_stats(dev
);
4234 if (!np
->in_shutdown
)
4235 mod_timer(&np
->stats_poll
,
4236 round_jiffies(jiffies
+ STATS_INTERVAL
));
4239 static void nv_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
4241 struct fe_priv
*np
= netdev_priv(dev
);
4242 strcpy(info
->driver
, DRV_NAME
);
4243 strcpy(info
->version
, FORCEDETH_VERSION
);
4244 strcpy(info
->bus_info
, pci_name(np
->pci_dev
));
4247 static void nv_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
4249 struct fe_priv
*np
= netdev_priv(dev
);
4250 wolinfo
->supported
= WAKE_MAGIC
;
4252 spin_lock_irq(&np
->lock
);
4254 wolinfo
->wolopts
= WAKE_MAGIC
;
4255 spin_unlock_irq(&np
->lock
);
4258 static int nv_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
4260 struct fe_priv
*np
= netdev_priv(dev
);
4261 u8 __iomem
*base
= get_hwbase(dev
);
4264 if (wolinfo
->wolopts
== 0) {
4266 } else if (wolinfo
->wolopts
& WAKE_MAGIC
) {
4268 flags
= NVREG_WAKEUPFLAGS_ENABLE
;
4270 if (netif_running(dev
)) {
4271 spin_lock_irq(&np
->lock
);
4272 writel(flags
, base
+ NvRegWakeUpFlags
);
4273 spin_unlock_irq(&np
->lock
);
4278 static int nv_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
4280 struct fe_priv
*np
= netdev_priv(dev
);
4283 spin_lock_irq(&np
->lock
);
4284 ecmd
->port
= PORT_MII
;
4285 if (!netif_running(dev
)) {
4286 /* We do not track link speed / duplex setting if the
4287 * interface is disabled. Force a link check */
4288 if (nv_update_linkspeed(dev
)) {
4289 if (!netif_carrier_ok(dev
))
4290 netif_carrier_on(dev
);
4292 if (netif_carrier_ok(dev
))
4293 netif_carrier_off(dev
);
4297 if (netif_carrier_ok(dev
)) {
4298 switch(np
->linkspeed
& (NVREG_LINKSPEED_MASK
)) {
4299 case NVREG_LINKSPEED_10
:
4300 ecmd
->speed
= SPEED_10
;
4302 case NVREG_LINKSPEED_100
:
4303 ecmd
->speed
= SPEED_100
;
4305 case NVREG_LINKSPEED_1000
:
4306 ecmd
->speed
= SPEED_1000
;
4309 ecmd
->duplex
= DUPLEX_HALF
;
4311 ecmd
->duplex
= DUPLEX_FULL
;
4317 ecmd
->autoneg
= np
->autoneg
;
4319 ecmd
->advertising
= ADVERTISED_MII
;
4321 ecmd
->advertising
|= ADVERTISED_Autoneg
;
4322 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4323 if (adv
& ADVERTISE_10HALF
)
4324 ecmd
->advertising
|= ADVERTISED_10baseT_Half
;
4325 if (adv
& ADVERTISE_10FULL
)
4326 ecmd
->advertising
|= ADVERTISED_10baseT_Full
;
4327 if (adv
& ADVERTISE_100HALF
)
4328 ecmd
->advertising
|= ADVERTISED_100baseT_Half
;
4329 if (adv
& ADVERTISE_100FULL
)
4330 ecmd
->advertising
|= ADVERTISED_100baseT_Full
;
4331 if (np
->gigabit
== PHY_GIGABIT
) {
4332 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
4333 if (adv
& ADVERTISE_1000FULL
)
4334 ecmd
->advertising
|= ADVERTISED_1000baseT_Full
;
4337 ecmd
->supported
= (SUPPORTED_Autoneg
|
4338 SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full
|
4339 SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
|
4341 if (np
->gigabit
== PHY_GIGABIT
)
4342 ecmd
->supported
|= SUPPORTED_1000baseT_Full
;
4344 ecmd
->phy_address
= np
->phyaddr
;
4345 ecmd
->transceiver
= XCVR_EXTERNAL
;
4347 /* ignore maxtxpkt, maxrxpkt for now */
4348 spin_unlock_irq(&np
->lock
);
4352 static int nv_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
4354 struct fe_priv
*np
= netdev_priv(dev
);
4356 if (ecmd
->port
!= PORT_MII
)
4358 if (ecmd
->transceiver
!= XCVR_EXTERNAL
)
4360 if (ecmd
->phy_address
!= np
->phyaddr
) {
4361 /* TODO: support switching between multiple phys. Should be
4362 * trivial, but not enabled due to lack of test hardware. */
4365 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
4368 mask
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
4369 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
;
4370 if (np
->gigabit
== PHY_GIGABIT
)
4371 mask
|= ADVERTISED_1000baseT_Full
;
4373 if ((ecmd
->advertising
& mask
) == 0)
4376 } else if (ecmd
->autoneg
== AUTONEG_DISABLE
) {
4377 /* Note: autonegotiation disable, speed 1000 intentionally
4378 * forbidden - noone should need that. */
4380 if (ecmd
->speed
!= SPEED_10
&& ecmd
->speed
!= SPEED_100
)
4382 if (ecmd
->duplex
!= DUPLEX_HALF
&& ecmd
->duplex
!= DUPLEX_FULL
)
4388 netif_carrier_off(dev
);
4389 if (netif_running(dev
)) {
4390 unsigned long flags
;
4392 nv_disable_irq(dev
);
4393 netif_tx_lock_bh(dev
);
4394 netif_addr_lock(dev
);
4395 /* with plain spinlock lockdep complains */
4396 spin_lock_irqsave(&np
->lock
, flags
);
4399 * this can take some time, and interrupts are disabled
4400 * due to spin_lock_irqsave, but let's hope no daemon
4401 * is going to change the settings very often...
4403 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4404 * + some minor delays, which is up to a second approximately
4407 spin_unlock_irqrestore(&np
->lock
, flags
);
4408 netif_addr_unlock(dev
);
4409 netif_tx_unlock_bh(dev
);
4412 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
4417 /* advertise only what has been requested */
4418 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4419 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
4420 if (ecmd
->advertising
& ADVERTISED_10baseT_Half
)
4421 adv
|= ADVERTISE_10HALF
;
4422 if (ecmd
->advertising
& ADVERTISED_10baseT_Full
)
4423 adv
|= ADVERTISE_10FULL
;
4424 if (ecmd
->advertising
& ADVERTISED_100baseT_Half
)
4425 adv
|= ADVERTISE_100HALF
;
4426 if (ecmd
->advertising
& ADVERTISED_100baseT_Full
)
4427 adv
|= ADVERTISE_100FULL
;
4428 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) /* for rx we set both advertisments but disable tx pause */
4429 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
4430 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
4431 adv
|= ADVERTISE_PAUSE_ASYM
;
4432 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
4434 if (np
->gigabit
== PHY_GIGABIT
) {
4435 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
4436 adv
&= ~ADVERTISE_1000FULL
;
4437 if (ecmd
->advertising
& ADVERTISED_1000baseT_Full
)
4438 adv
|= ADVERTISE_1000FULL
;
4439 mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, adv
);
4442 if (netif_running(dev
))
4443 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
4444 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4445 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
4446 bmcr
|= BMCR_ANENABLE
;
4447 /* reset the phy in order for settings to stick,
4448 * and cause autoneg to start */
4449 if (phy_reset(dev
, bmcr
)) {
4450 printk(KERN_INFO
"%s: phy reset failed\n", dev
->name
);
4454 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
4455 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4462 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4463 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
4464 if (ecmd
->speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_HALF
)
4465 adv
|= ADVERTISE_10HALF
;
4466 if (ecmd
->speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_FULL
)
4467 adv
|= ADVERTISE_10FULL
;
4468 if (ecmd
->speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_HALF
)
4469 adv
|= ADVERTISE_100HALF
;
4470 if (ecmd
->speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_FULL
)
4471 adv
|= ADVERTISE_100FULL
;
4472 np
->pause_flags
&= ~(NV_PAUSEFRAME_AUTONEG
|NV_PAUSEFRAME_RX_ENABLE
|NV_PAUSEFRAME_TX_ENABLE
);
4473 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) {/* for rx we set both advertisments but disable tx pause */
4474 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
4475 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
4477 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
) {
4478 adv
|= ADVERTISE_PAUSE_ASYM
;
4479 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
4481 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
4482 np
->fixed_mode
= adv
;
4484 if (np
->gigabit
== PHY_GIGABIT
) {
4485 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
4486 adv
&= ~ADVERTISE_1000FULL
;
4487 mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, adv
);
4490 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4491 bmcr
&= ~(BMCR_ANENABLE
|BMCR_SPEED100
|BMCR_SPEED1000
|BMCR_FULLDPLX
);
4492 if (np
->fixed_mode
& (ADVERTISE_10FULL
|ADVERTISE_100FULL
))
4493 bmcr
|= BMCR_FULLDPLX
;
4494 if (np
->fixed_mode
& (ADVERTISE_100HALF
|ADVERTISE_100FULL
))
4495 bmcr
|= BMCR_SPEED100
;
4496 if (np
->phy_oui
== PHY_OUI_MARVELL
) {
4497 /* reset the phy in order for forced mode settings to stick */
4498 if (phy_reset(dev
, bmcr
)) {
4499 printk(KERN_INFO
"%s: phy reset failed\n", dev
->name
);
4503 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4504 if (netif_running(dev
)) {
4505 /* Wait a bit and then reconfigure the nic. */
4512 if (netif_running(dev
)) {
4520 #define FORCEDETH_REGS_VER 1
4522 static int nv_get_regs_len(struct net_device
*dev
)
4524 struct fe_priv
*np
= netdev_priv(dev
);
4525 return np
->register_size
;
4528 static void nv_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
, void *buf
)
4530 struct fe_priv
*np
= netdev_priv(dev
);
4531 u8 __iomem
*base
= get_hwbase(dev
);
4535 regs
->version
= FORCEDETH_REGS_VER
;
4536 spin_lock_irq(&np
->lock
);
4537 for (i
= 0;i
<= np
->register_size
/sizeof(u32
); i
++)
4538 rbuf
[i
] = readl(base
+ i
*sizeof(u32
));
4539 spin_unlock_irq(&np
->lock
);
4542 static int nv_nway_reset(struct net_device
*dev
)
4544 struct fe_priv
*np
= netdev_priv(dev
);
4550 netif_carrier_off(dev
);
4551 if (netif_running(dev
)) {
4552 nv_disable_irq(dev
);
4553 netif_tx_lock_bh(dev
);
4554 netif_addr_lock(dev
);
4555 spin_lock(&np
->lock
);
4558 spin_unlock(&np
->lock
);
4559 netif_addr_unlock(dev
);
4560 netif_tx_unlock_bh(dev
);
4561 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
4564 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4565 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
4566 bmcr
|= BMCR_ANENABLE
;
4567 /* reset the phy in order for settings to stick*/
4568 if (phy_reset(dev
, bmcr
)) {
4569 printk(KERN_INFO
"%s: phy reset failed\n", dev
->name
);
4573 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
4574 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4577 if (netif_running(dev
)) {
4589 static int nv_set_tso(struct net_device
*dev
, u32 value
)
4591 struct fe_priv
*np
= netdev_priv(dev
);
4593 if ((np
->driver_data
& DEV_HAS_CHECKSUM
))
4594 return ethtool_op_set_tso(dev
, value
);
4599 static void nv_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
* ring
)
4601 struct fe_priv
*np
= netdev_priv(dev
);
4603 ring
->rx_max_pending
= (np
->desc_ver
== DESC_VER_1
) ? RING_MAX_DESC_VER_1
: RING_MAX_DESC_VER_2_3
;
4604 ring
->rx_mini_max_pending
= 0;
4605 ring
->rx_jumbo_max_pending
= 0;
4606 ring
->tx_max_pending
= (np
->desc_ver
== DESC_VER_1
) ? RING_MAX_DESC_VER_1
: RING_MAX_DESC_VER_2_3
;
4608 ring
->rx_pending
= np
->rx_ring_size
;
4609 ring
->rx_mini_pending
= 0;
4610 ring
->rx_jumbo_pending
= 0;
4611 ring
->tx_pending
= np
->tx_ring_size
;
4614 static int nv_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
* ring
)
4616 struct fe_priv
*np
= netdev_priv(dev
);
4617 u8 __iomem
*base
= get_hwbase(dev
);
4618 u8
*rxtx_ring
, *rx_skbuff
, *tx_skbuff
;
4619 dma_addr_t ring_addr
;
4621 if (ring
->rx_pending
< RX_RING_MIN
||
4622 ring
->tx_pending
< TX_RING_MIN
||
4623 ring
->rx_mini_pending
!= 0 ||
4624 ring
->rx_jumbo_pending
!= 0 ||
4625 (np
->desc_ver
== DESC_VER_1
&&
4626 (ring
->rx_pending
> RING_MAX_DESC_VER_1
||
4627 ring
->tx_pending
> RING_MAX_DESC_VER_1
)) ||
4628 (np
->desc_ver
!= DESC_VER_1
&&
4629 (ring
->rx_pending
> RING_MAX_DESC_VER_2_3
||
4630 ring
->tx_pending
> RING_MAX_DESC_VER_2_3
))) {
4634 /* allocate new rings */
4635 if (!nv_optimized(np
)) {
4636 rxtx_ring
= pci_alloc_consistent(np
->pci_dev
,
4637 sizeof(struct ring_desc
) * (ring
->rx_pending
+ ring
->tx_pending
),
4640 rxtx_ring
= pci_alloc_consistent(np
->pci_dev
,
4641 sizeof(struct ring_desc_ex
) * (ring
->rx_pending
+ ring
->tx_pending
),
4644 rx_skbuff
= kmalloc(sizeof(struct nv_skb_map
) * ring
->rx_pending
, GFP_KERNEL
);
4645 tx_skbuff
= kmalloc(sizeof(struct nv_skb_map
) * ring
->tx_pending
, GFP_KERNEL
);
4646 if (!rxtx_ring
|| !rx_skbuff
|| !tx_skbuff
) {
4647 /* fall back to old rings */
4648 if (!nv_optimized(np
)) {
4650 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (ring
->rx_pending
+ ring
->tx_pending
),
4651 rxtx_ring
, ring_addr
);
4654 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc_ex
) * (ring
->rx_pending
+ ring
->tx_pending
),
4655 rxtx_ring
, ring_addr
);
4664 if (netif_running(dev
)) {
4665 nv_disable_irq(dev
);
4666 nv_napi_disable(dev
);
4667 netif_tx_lock_bh(dev
);
4668 netif_addr_lock(dev
);
4669 spin_lock(&np
->lock
);
4679 /* set new values */
4680 np
->rx_ring_size
= ring
->rx_pending
;
4681 np
->tx_ring_size
= ring
->tx_pending
;
4683 if (!nv_optimized(np
)) {
4684 np
->rx_ring
.orig
= (struct ring_desc
*)rxtx_ring
;
4685 np
->tx_ring
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
];
4687 np
->rx_ring
.ex
= (struct ring_desc_ex
*)rxtx_ring
;
4688 np
->tx_ring
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
];
4690 np
->rx_skb
= (struct nv_skb_map
*)rx_skbuff
;
4691 np
->tx_skb
= (struct nv_skb_map
*)tx_skbuff
;
4692 np
->ring_addr
= ring_addr
;
4694 memset(np
->rx_skb
, 0, sizeof(struct nv_skb_map
) * np
->rx_ring_size
);
4695 memset(np
->tx_skb
, 0, sizeof(struct nv_skb_map
) * np
->tx_ring_size
);
4697 if (netif_running(dev
)) {
4698 /* reinit driver view of the queues */
4700 if (nv_init_ring(dev
)) {
4701 if (!np
->in_shutdown
)
4702 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
4705 /* reinit nic view of the queues */
4706 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
4707 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
4708 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
4709 base
+ NvRegRingSizes
);
4711 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
4714 /* restart engines */
4716 spin_unlock(&np
->lock
);
4717 netif_addr_unlock(dev
);
4718 netif_tx_unlock_bh(dev
);
4719 nv_napi_enable(dev
);
4727 static void nv_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
* pause
)
4729 struct fe_priv
*np
= netdev_priv(dev
);
4731 pause
->autoneg
= (np
->pause_flags
& NV_PAUSEFRAME_AUTONEG
) != 0;
4732 pause
->rx_pause
= (np
->pause_flags
& NV_PAUSEFRAME_RX_ENABLE
) != 0;
4733 pause
->tx_pause
= (np
->pause_flags
& NV_PAUSEFRAME_TX_ENABLE
) != 0;
4736 static int nv_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
* pause
)
4738 struct fe_priv
*np
= netdev_priv(dev
);
4741 if ((!np
->autoneg
&& np
->duplex
== 0) ||
4742 (np
->autoneg
&& !pause
->autoneg
&& np
->duplex
== 0)) {
4743 printk(KERN_INFO
"%s: can not set pause settings when forced link is in half duplex.\n",
4747 if (pause
->tx_pause
&& !(np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
)) {
4748 printk(KERN_INFO
"%s: hardware does not support tx pause frames.\n", dev
->name
);
4752 netif_carrier_off(dev
);
4753 if (netif_running(dev
)) {
4754 nv_disable_irq(dev
);
4755 netif_tx_lock_bh(dev
);
4756 netif_addr_lock(dev
);
4757 spin_lock(&np
->lock
);
4760 spin_unlock(&np
->lock
);
4761 netif_addr_unlock(dev
);
4762 netif_tx_unlock_bh(dev
);
4765 np
->pause_flags
&= ~(NV_PAUSEFRAME_RX_REQ
|NV_PAUSEFRAME_TX_REQ
);
4766 if (pause
->rx_pause
)
4767 np
->pause_flags
|= NV_PAUSEFRAME_RX_REQ
;
4768 if (pause
->tx_pause
)
4769 np
->pause_flags
|= NV_PAUSEFRAME_TX_REQ
;
4771 if (np
->autoneg
&& pause
->autoneg
) {
4772 np
->pause_flags
|= NV_PAUSEFRAME_AUTONEG
;
4774 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4775 adv
&= ~(ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
4776 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) /* for rx we set both advertisments but disable tx pause */
4777 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
4778 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
4779 adv
|= ADVERTISE_PAUSE_ASYM
;
4780 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
4782 if (netif_running(dev
))
4783 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
4784 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4785 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
4786 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4788 np
->pause_flags
&= ~(NV_PAUSEFRAME_AUTONEG
|NV_PAUSEFRAME_RX_ENABLE
|NV_PAUSEFRAME_TX_ENABLE
);
4789 if (pause
->rx_pause
)
4790 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
4791 if (pause
->tx_pause
)
4792 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
4794 if (!netif_running(dev
))
4795 nv_update_linkspeed(dev
);
4797 nv_update_pause(dev
, np
->pause_flags
);
4800 if (netif_running(dev
)) {
4807 static u32
nv_get_rx_csum(struct net_device
*dev
)
4809 struct fe_priv
*np
= netdev_priv(dev
);
4810 return (np
->rx_csum
) != 0;
4813 static int nv_set_rx_csum(struct net_device
*dev
, u32 data
)
4815 struct fe_priv
*np
= netdev_priv(dev
);
4816 u8 __iomem
*base
= get_hwbase(dev
);
4819 if (np
->driver_data
& DEV_HAS_CHECKSUM
) {
4822 np
->txrxctl_bits
|= NVREG_TXRXCTL_RXCHECK
;
4825 /* vlan is dependent on rx checksum offload */
4826 if (!(np
->vlanctl_bits
& NVREG_VLANCONTROL_ENABLE
))
4827 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_RXCHECK
;
4829 if (netif_running(dev
)) {
4830 spin_lock_irq(&np
->lock
);
4831 writel(np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
4832 spin_unlock_irq(&np
->lock
);
4841 static int nv_set_tx_csum(struct net_device
*dev
, u32 data
)
4843 struct fe_priv
*np
= netdev_priv(dev
);
4845 if (np
->driver_data
& DEV_HAS_CHECKSUM
)
4846 return ethtool_op_set_tx_csum(dev
, data
);
4851 static int nv_set_sg(struct net_device
*dev
, u32 data
)
4853 struct fe_priv
*np
= netdev_priv(dev
);
4855 if (np
->driver_data
& DEV_HAS_CHECKSUM
)
4856 return ethtool_op_set_sg(dev
, data
);
4861 static int nv_get_sset_count(struct net_device
*dev
, int sset
)
4863 struct fe_priv
*np
= netdev_priv(dev
);
4867 if (np
->driver_data
& DEV_HAS_TEST_EXTENDED
)
4868 return NV_TEST_COUNT_EXTENDED
;
4870 return NV_TEST_COUNT_BASE
;
4872 if (np
->driver_data
& DEV_HAS_STATISTICS_V3
)
4873 return NV_DEV_STATISTICS_V3_COUNT
;
4874 else if (np
->driver_data
& DEV_HAS_STATISTICS_V2
)
4875 return NV_DEV_STATISTICS_V2_COUNT
;
4876 else if (np
->driver_data
& DEV_HAS_STATISTICS_V1
)
4877 return NV_DEV_STATISTICS_V1_COUNT
;
4885 static void nv_get_ethtool_stats(struct net_device
*dev
, struct ethtool_stats
*estats
, u64
*buffer
)
4887 struct fe_priv
*np
= netdev_priv(dev
);
4890 nv_do_stats_poll((unsigned long)dev
);
4892 memcpy(buffer
, &np
->estats
, nv_get_sset_count(dev
, ETH_SS_STATS
)*sizeof(u64
));
4895 static int nv_link_test(struct net_device
*dev
)
4897 struct fe_priv
*np
= netdev_priv(dev
);
4900 mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
4901 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
4903 /* check phy link status */
4904 if (!(mii_status
& BMSR_LSTATUS
))
4910 static int nv_register_test(struct net_device
*dev
)
4912 u8 __iomem
*base
= get_hwbase(dev
);
4914 u32 orig_read
, new_read
;
4917 orig_read
= readl(base
+ nv_registers_test
[i
].reg
);
4919 /* xor with mask to toggle bits */
4920 orig_read
^= nv_registers_test
[i
].mask
;
4922 writel(orig_read
, base
+ nv_registers_test
[i
].reg
);
4924 new_read
= readl(base
+ nv_registers_test
[i
].reg
);
4926 if ((new_read
& nv_registers_test
[i
].mask
) != (orig_read
& nv_registers_test
[i
].mask
))
4929 /* restore original value */
4930 orig_read
^= nv_registers_test
[i
].mask
;
4931 writel(orig_read
, base
+ nv_registers_test
[i
].reg
);
4933 } while (nv_registers_test
[++i
].reg
!= 0);
4938 static int nv_interrupt_test(struct net_device
*dev
)
4940 struct fe_priv
*np
= netdev_priv(dev
);
4941 u8 __iomem
*base
= get_hwbase(dev
);
4944 u32 save_msi_flags
, save_poll_interval
= 0;
4946 if (netif_running(dev
)) {
4947 /* free current irq */
4949 save_poll_interval
= readl(base
+NvRegPollingInterval
);
4952 /* flag to test interrupt handler */
4955 /* setup test irq */
4956 save_msi_flags
= np
->msi_flags
;
4957 np
->msi_flags
&= ~NV_MSI_X_VECTORS_MASK
;
4958 np
->msi_flags
|= 0x001; /* setup 1 vector */
4959 if (nv_request_irq(dev
, 1))
4962 /* setup timer interrupt */
4963 writel(NVREG_POLL_DEFAULT_CPU
, base
+ NvRegPollingInterval
);
4964 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
4966 nv_enable_hw_interrupts(dev
, NVREG_IRQ_TIMER
);
4968 /* wait for at least one interrupt */
4971 spin_lock_irq(&np
->lock
);
4973 /* flag should be set within ISR */
4974 testcnt
= np
->intr_test
;
4978 nv_disable_hw_interrupts(dev
, NVREG_IRQ_TIMER
);
4979 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
4980 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
4982 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
4984 spin_unlock_irq(&np
->lock
);
4988 np
->msi_flags
= save_msi_flags
;
4990 if (netif_running(dev
)) {
4991 writel(save_poll_interval
, base
+ NvRegPollingInterval
);
4992 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
4993 /* restore original irq */
4994 if (nv_request_irq(dev
, 0))
5001 static int nv_loopback_test(struct net_device
*dev
)
5003 struct fe_priv
*np
= netdev_priv(dev
);
5004 u8 __iomem
*base
= get_hwbase(dev
);
5005 struct sk_buff
*tx_skb
, *rx_skb
;
5006 dma_addr_t test_dma_addr
;
5007 u32 tx_flags_extra
= (np
->desc_ver
== DESC_VER_1
? NV_TX_LASTPACKET
: NV_TX2_LASTPACKET
);
5009 int len
, i
, pkt_len
;
5011 u32 filter_flags
= 0;
5012 u32 misc1_flags
= 0;
5015 if (netif_running(dev
)) {
5016 nv_disable_irq(dev
);
5017 filter_flags
= readl(base
+ NvRegPacketFilterFlags
);
5018 misc1_flags
= readl(base
+ NvRegMisc1
);
5023 /* reinit driver view of the rx queue */
5027 /* setup hardware for loopback */
5028 writel(NVREG_MISC1_FORCE
, base
+ NvRegMisc1
);
5029 writel(NVREG_PFF_ALWAYS
| NVREG_PFF_LOOPBACK
, base
+ NvRegPacketFilterFlags
);
5031 /* reinit nic view of the rx queue */
5032 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
5033 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
5034 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
5035 base
+ NvRegRingSizes
);
5038 /* restart rx engine */
5041 /* setup packet for tx */
5042 pkt_len
= ETH_DATA_LEN
;
5043 tx_skb
= dev_alloc_skb(pkt_len
);
5045 printk(KERN_ERR
"dev_alloc_skb() failed during loopback test"
5046 " of %s\n", dev
->name
);
5050 test_dma_addr
= pci_map_single(np
->pci_dev
, tx_skb
->data
,
5051 skb_tailroom(tx_skb
),
5052 PCI_DMA_FROMDEVICE
);
5053 pkt_data
= skb_put(tx_skb
, pkt_len
);
5054 for (i
= 0; i
< pkt_len
; i
++)
5055 pkt_data
[i
] = (u8
)(i
& 0xff);
5057 if (!nv_optimized(np
)) {
5058 np
->tx_ring
.orig
[0].buf
= cpu_to_le32(test_dma_addr
);
5059 np
->tx_ring
.orig
[0].flaglen
= cpu_to_le32((pkt_len
-1) | np
->tx_flags
| tx_flags_extra
);
5061 np
->tx_ring
.ex
[0].bufhigh
= cpu_to_le32(dma_high(test_dma_addr
));
5062 np
->tx_ring
.ex
[0].buflow
= cpu_to_le32(dma_low(test_dma_addr
));
5063 np
->tx_ring
.ex
[0].flaglen
= cpu_to_le32((pkt_len
-1) | np
->tx_flags
| tx_flags_extra
);
5065 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
5066 pci_push(get_hwbase(dev
));
5070 /* check for rx of the packet */
5071 if (!nv_optimized(np
)) {
5072 flags
= le32_to_cpu(np
->rx_ring
.orig
[0].flaglen
);
5073 len
= nv_descr_getlength(&np
->rx_ring
.orig
[0], np
->desc_ver
);
5076 flags
= le32_to_cpu(np
->rx_ring
.ex
[0].flaglen
);
5077 len
= nv_descr_getlength_ex(&np
->rx_ring
.ex
[0], np
->desc_ver
);
5080 if (flags
& NV_RX_AVAIL
) {
5082 } else if (np
->desc_ver
== DESC_VER_1
) {
5083 if (flags
& NV_RX_ERROR
)
5086 if (flags
& NV_RX2_ERROR
) {
5092 if (len
!= pkt_len
) {
5094 dprintk(KERN_DEBUG
"%s: loopback len mismatch %d vs %d\n",
5095 dev
->name
, len
, pkt_len
);
5097 rx_skb
= np
->rx_skb
[0].skb
;
5098 for (i
= 0; i
< pkt_len
; i
++) {
5099 if (rx_skb
->data
[i
] != (u8
)(i
& 0xff)) {
5101 dprintk(KERN_DEBUG
"%s: loopback pattern check failed on byte %d\n",
5108 dprintk(KERN_DEBUG
"%s: loopback - did not receive test packet\n", dev
->name
);
5111 pci_unmap_single(np
->pci_dev
, test_dma_addr
,
5112 (skb_end_pointer(tx_skb
) - tx_skb
->data
),
5114 dev_kfree_skb_any(tx_skb
);
5119 /* drain rx queue */
5122 if (netif_running(dev
)) {
5123 writel(misc1_flags
, base
+ NvRegMisc1
);
5124 writel(filter_flags
, base
+ NvRegPacketFilterFlags
);
5131 static void nv_self_test(struct net_device
*dev
, struct ethtool_test
*test
, u64
*buffer
)
5133 struct fe_priv
*np
= netdev_priv(dev
);
5134 u8 __iomem
*base
= get_hwbase(dev
);
5136 memset(buffer
, 0, nv_get_sset_count(dev
, ETH_SS_TEST
)*sizeof(u64
));
5138 if (!nv_link_test(dev
)) {
5139 test
->flags
|= ETH_TEST_FL_FAILED
;
5143 if (test
->flags
& ETH_TEST_FL_OFFLINE
) {
5144 if (netif_running(dev
)) {
5145 netif_stop_queue(dev
);
5146 nv_napi_disable(dev
);
5147 netif_tx_lock_bh(dev
);
5148 netif_addr_lock(dev
);
5149 spin_lock_irq(&np
->lock
);
5150 nv_disable_hw_interrupts(dev
, np
->irqmask
);
5151 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
5152 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
5154 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
5159 /* drain rx queue */
5161 spin_unlock_irq(&np
->lock
);
5162 netif_addr_unlock(dev
);
5163 netif_tx_unlock_bh(dev
);
5166 if (!nv_register_test(dev
)) {
5167 test
->flags
|= ETH_TEST_FL_FAILED
;
5171 result
= nv_interrupt_test(dev
);
5173 test
->flags
|= ETH_TEST_FL_FAILED
;
5181 if (!nv_loopback_test(dev
)) {
5182 test
->flags
|= ETH_TEST_FL_FAILED
;
5186 if (netif_running(dev
)) {
5187 /* reinit driver view of the rx queue */
5189 if (nv_init_ring(dev
)) {
5190 if (!np
->in_shutdown
)
5191 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
5193 /* reinit nic view of the rx queue */
5194 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
5195 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
5196 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
5197 base
+ NvRegRingSizes
);
5199 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
5201 /* restart rx engine */
5203 netif_start_queue(dev
);
5204 nv_napi_enable(dev
);
5205 nv_enable_hw_interrupts(dev
, np
->irqmask
);
5210 static void nv_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buffer
)
5212 switch (stringset
) {
5214 memcpy(buffer
, &nv_estats_str
, nv_get_sset_count(dev
, ETH_SS_STATS
)*sizeof(struct nv_ethtool_str
));
5217 memcpy(buffer
, &nv_etests_str
, nv_get_sset_count(dev
, ETH_SS_TEST
)*sizeof(struct nv_ethtool_str
));
5222 static const struct ethtool_ops ops
= {
5223 .get_drvinfo
= nv_get_drvinfo
,
5224 .get_link
= ethtool_op_get_link
,
5225 .get_wol
= nv_get_wol
,
5226 .set_wol
= nv_set_wol
,
5227 .get_settings
= nv_get_settings
,
5228 .set_settings
= nv_set_settings
,
5229 .get_regs_len
= nv_get_regs_len
,
5230 .get_regs
= nv_get_regs
,
5231 .nway_reset
= nv_nway_reset
,
5232 .set_tso
= nv_set_tso
,
5233 .get_ringparam
= nv_get_ringparam
,
5234 .set_ringparam
= nv_set_ringparam
,
5235 .get_pauseparam
= nv_get_pauseparam
,
5236 .set_pauseparam
= nv_set_pauseparam
,
5237 .get_rx_csum
= nv_get_rx_csum
,
5238 .set_rx_csum
= nv_set_rx_csum
,
5239 .set_tx_csum
= nv_set_tx_csum
,
5240 .set_sg
= nv_set_sg
,
5241 .get_strings
= nv_get_strings
,
5242 .get_ethtool_stats
= nv_get_ethtool_stats
,
5243 .get_sset_count
= nv_get_sset_count
,
5244 .self_test
= nv_self_test
,
5247 static void nv_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
5249 struct fe_priv
*np
= get_nvpriv(dev
);
5251 spin_lock_irq(&np
->lock
);
5253 /* save vlan group */
5257 /* enable vlan on MAC */
5258 np
->txrxctl_bits
|= NVREG_TXRXCTL_VLANSTRIP
| NVREG_TXRXCTL_VLANINS
;
5260 /* disable vlan on MAC */
5261 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_VLANSTRIP
;
5262 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_VLANINS
;
5265 writel(np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
5267 spin_unlock_irq(&np
->lock
);
5270 /* The mgmt unit and driver use a semaphore to access the phy during init */
5271 static int nv_mgmt_acquire_sema(struct net_device
*dev
)
5273 struct fe_priv
*np
= netdev_priv(dev
);
5274 u8 __iomem
*base
= get_hwbase(dev
);
5276 u32 tx_ctrl
, mgmt_sema
;
5278 for (i
= 0; i
< 10; i
++) {
5279 mgmt_sema
= readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_MGMT_SEMA_MASK
;
5280 if (mgmt_sema
== NVREG_XMITCTL_MGMT_SEMA_FREE
)
5285 if (mgmt_sema
!= NVREG_XMITCTL_MGMT_SEMA_FREE
)
5288 for (i
= 0; i
< 2; i
++) {
5289 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
5290 tx_ctrl
|= NVREG_XMITCTL_HOST_SEMA_ACQ
;
5291 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
5293 /* verify that semaphore was acquired */
5294 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
5295 if (((tx_ctrl
& NVREG_XMITCTL_HOST_SEMA_MASK
) == NVREG_XMITCTL_HOST_SEMA_ACQ
) &&
5296 ((tx_ctrl
& NVREG_XMITCTL_MGMT_SEMA_MASK
) == NVREG_XMITCTL_MGMT_SEMA_FREE
)) {
5307 static void nv_mgmt_release_sema(struct net_device
*dev
)
5309 struct fe_priv
*np
= netdev_priv(dev
);
5310 u8 __iomem
*base
= get_hwbase(dev
);
5313 if (np
->driver_data
& DEV_HAS_MGMT_UNIT
) {
5314 if (np
->mgmt_sema
) {
5315 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
5316 tx_ctrl
&= ~NVREG_XMITCTL_HOST_SEMA_ACQ
;
5317 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
5323 static int nv_mgmt_get_version(struct net_device
*dev
)
5325 struct fe_priv
*np
= netdev_priv(dev
);
5326 u8 __iomem
*base
= get_hwbase(dev
);
5327 u32 data_ready
= readl(base
+ NvRegTransmitterControl
);
5328 u32 data_ready2
= 0;
5329 unsigned long start
;
5332 writel(NVREG_MGMTUNITGETVERSION
, base
+ NvRegMgmtUnitGetVersion
);
5333 writel(data_ready
^ NVREG_XMITCTL_DATA_START
, base
+ NvRegTransmitterControl
);
5335 while (time_before(jiffies
, start
+ 5*HZ
)) {
5336 data_ready2
= readl(base
+ NvRegTransmitterControl
);
5337 if ((data_ready
& NVREG_XMITCTL_DATA_READY
) != (data_ready2
& NVREG_XMITCTL_DATA_READY
)) {
5341 schedule_timeout_uninterruptible(1);
5344 if (!ready
|| (data_ready2
& NVREG_XMITCTL_DATA_ERROR
))
5347 np
->mgmt_version
= readl(base
+ NvRegMgmtUnitVersion
) & NVREG_MGMTUNITVERSION
;
5352 static int nv_open(struct net_device
*dev
)
5354 struct fe_priv
*np
= netdev_priv(dev
);
5355 u8 __iomem
*base
= get_hwbase(dev
);
5360 dprintk(KERN_DEBUG
"nv_open: begin\n");
5363 mii_rw(dev
, np
->phyaddr
, MII_BMCR
,
5364 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
) & ~BMCR_PDOWN
);
5366 nv_txrx_gate(dev
, false);
5367 /* erase previous misconfiguration */
5368 if (np
->driver_data
& DEV_HAS_POWER_CNTRL
)
5370 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
5371 writel(0, base
+ NvRegMulticastAddrB
);
5372 writel(NVREG_MCASTMASKA_NONE
, base
+ NvRegMulticastMaskA
);
5373 writel(NVREG_MCASTMASKB_NONE
, base
+ NvRegMulticastMaskB
);
5374 writel(0, base
+ NvRegPacketFilterFlags
);
5376 writel(0, base
+ NvRegTransmitterControl
);
5377 writel(0, base
+ NvRegReceiverControl
);
5379 writel(0, base
+ NvRegAdapterControl
);
5381 if (np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
)
5382 writel(NVREG_TX_PAUSEFRAME_DISABLE
, base
+ NvRegTxPauseFrame
);
5384 /* initialize descriptor rings */
5386 oom
= nv_init_ring(dev
);
5388 writel(0, base
+ NvRegLinkSpeed
);
5389 writel(readl(base
+ NvRegTransmitPoll
) & NVREG_TRANSMITPOLL_MAC_ADDR_REV
, base
+ NvRegTransmitPoll
);
5391 writel(0, base
+ NvRegUnknownSetupReg6
);
5393 np
->in_shutdown
= 0;
5396 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
5397 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
5398 base
+ NvRegRingSizes
);
5400 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
5401 if (np
->desc_ver
== DESC_VER_1
)
5402 writel(NVREG_TX_WM_DESC1_DEFAULT
, base
+ NvRegTxWatermark
);
5404 writel(NVREG_TX_WM_DESC2_3_DEFAULT
, base
+ NvRegTxWatermark
);
5405 writel(np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
5406 writel(np
->vlanctl_bits
, base
+ NvRegVlanControl
);
5408 writel(NVREG_TXRXCTL_BIT1
|np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
5409 reg_delay(dev
, NvRegUnknownSetupReg5
, NVREG_UNKSETUP5_BIT31
, NVREG_UNKSETUP5_BIT31
,
5410 NV_SETUP5_DELAY
, NV_SETUP5_DELAYMAX
,
5411 KERN_INFO
"open: SetupReg5, Bit 31 remained off\n");
5413 writel(0, base
+ NvRegMIIMask
);
5414 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
5415 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5417 writel(NVREG_MISC1_FORCE
| NVREG_MISC1_HD
, base
+ NvRegMisc1
);
5418 writel(readl(base
+ NvRegTransmitterStatus
), base
+ NvRegTransmitterStatus
);
5419 writel(NVREG_PFF_ALWAYS
, base
+ NvRegPacketFilterFlags
);
5420 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
5422 writel(readl(base
+ NvRegReceiverStatus
), base
+ NvRegReceiverStatus
);
5424 get_random_bytes(&low
, sizeof(low
));
5425 low
&= NVREG_SLOTTIME_MASK
;
5426 if (np
->desc_ver
== DESC_VER_1
) {
5427 writel(low
|NVREG_SLOTTIME_DEFAULT
, base
+ NvRegSlotTime
);
5429 if (!(np
->driver_data
& DEV_HAS_GEAR_MODE
)) {
5430 /* setup legacy backoff */
5431 writel(NVREG_SLOTTIME_LEGBF_ENABLED
|NVREG_SLOTTIME_10_100_FULL
|low
, base
+ NvRegSlotTime
);
5433 writel(NVREG_SLOTTIME_10_100_FULL
, base
+ NvRegSlotTime
);
5434 nv_gear_backoff_reseed(dev
);
5437 writel(NVREG_TX_DEFERRAL_DEFAULT
, base
+ NvRegTxDeferral
);
5438 writel(NVREG_RX_DEFERRAL_DEFAULT
, base
+ NvRegRxDeferral
);
5439 if (poll_interval
== -1) {
5440 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
)
5441 writel(NVREG_POLL_DEFAULT_THROUGHPUT
, base
+ NvRegPollingInterval
);
5443 writel(NVREG_POLL_DEFAULT_CPU
, base
+ NvRegPollingInterval
);
5446 writel(poll_interval
& 0xFFFF, base
+ NvRegPollingInterval
);
5447 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
5448 writel((np
->phyaddr
<< NVREG_ADAPTCTL_PHYSHIFT
)|NVREG_ADAPTCTL_PHYVALID
|NVREG_ADAPTCTL_RUNNING
,
5449 base
+ NvRegAdapterControl
);
5450 writel(NVREG_MIISPEED_BIT8
|NVREG_MIIDELAY
, base
+ NvRegMIISpeed
);
5451 writel(NVREG_MII_LINKCHANGE
, base
+ NvRegMIIMask
);
5453 writel(NVREG_WAKEUPFLAGS_ENABLE
, base
+ NvRegWakeUpFlags
);
5455 i
= readl(base
+ NvRegPowerState
);
5456 if ( (i
& NVREG_POWERSTATE_POWEREDUP
) == 0)
5457 writel(NVREG_POWERSTATE_POWEREDUP
|i
, base
+ NvRegPowerState
);
5461 writel(readl(base
+ NvRegPowerState
) | NVREG_POWERSTATE_VALID
, base
+ NvRegPowerState
);
5463 nv_disable_hw_interrupts(dev
, np
->irqmask
);
5465 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5466 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
5469 if (nv_request_irq(dev
, 0)) {
5473 /* ask for interrupts */
5474 nv_enable_hw_interrupts(dev
, np
->irqmask
);
5476 spin_lock_irq(&np
->lock
);
5477 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
5478 writel(0, base
+ NvRegMulticastAddrB
);
5479 writel(NVREG_MCASTMASKA_NONE
, base
+ NvRegMulticastMaskA
);
5480 writel(NVREG_MCASTMASKB_NONE
, base
+ NvRegMulticastMaskB
);
5481 writel(NVREG_PFF_ALWAYS
|NVREG_PFF_MYADDR
, base
+ NvRegPacketFilterFlags
);
5482 /* One manual link speed update: Interrupts are enabled, future link
5483 * speed changes cause interrupts and are handled by nv_link_irq().
5487 miistat
= readl(base
+ NvRegMIIStatus
);
5488 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5489 dprintk(KERN_INFO
"startup: got 0x%08x.\n", miistat
);
5491 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5494 ret
= nv_update_linkspeed(dev
);
5496 netif_start_queue(dev
);
5497 nv_napi_enable(dev
);
5500 netif_carrier_on(dev
);
5502 printk(KERN_INFO
"%s: no link during initialization.\n", dev
->name
);
5503 netif_carrier_off(dev
);
5506 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
5508 /* start statistics timer */
5509 if (np
->driver_data
& (DEV_HAS_STATISTICS_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_STATISTICS_V3
))
5510 mod_timer(&np
->stats_poll
,
5511 round_jiffies(jiffies
+ STATS_INTERVAL
));
5513 spin_unlock_irq(&np
->lock
);
5521 static int nv_close(struct net_device
*dev
)
5523 struct fe_priv
*np
= netdev_priv(dev
);
5526 spin_lock_irq(&np
->lock
);
5527 np
->in_shutdown
= 1;
5528 spin_unlock_irq(&np
->lock
);
5529 nv_napi_disable(dev
);
5530 synchronize_irq(np
->pci_dev
->irq
);
5532 del_timer_sync(&np
->oom_kick
);
5533 del_timer_sync(&np
->nic_poll
);
5534 del_timer_sync(&np
->stats_poll
);
5536 netif_stop_queue(dev
);
5537 spin_lock_irq(&np
->lock
);
5541 /* disable interrupts on the nic or we will lock up */
5542 base
= get_hwbase(dev
);
5543 nv_disable_hw_interrupts(dev
, np
->irqmask
);
5545 dprintk(KERN_INFO
"%s: Irqmask is zero again\n", dev
->name
);
5547 spin_unlock_irq(&np
->lock
);
5553 if (np
->wolenabled
|| !phy_power_down
) {
5554 nv_txrx_gate(dev
, false);
5555 writel(NVREG_PFF_ALWAYS
|NVREG_PFF_MYADDR
, base
+ NvRegPacketFilterFlags
);
5558 /* power down phy */
5559 mii_rw(dev
, np
->phyaddr
, MII_BMCR
,
5560 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
)|BMCR_PDOWN
);
5561 nv_txrx_gate(dev
, true);
5564 /* FIXME: power down nic */
5569 static const struct net_device_ops nv_netdev_ops
= {
5570 .ndo_open
= nv_open
,
5571 .ndo_stop
= nv_close
,
5572 .ndo_get_stats
= nv_get_stats
,
5573 .ndo_start_xmit
= nv_start_xmit
,
5574 .ndo_tx_timeout
= nv_tx_timeout
,
5575 .ndo_change_mtu
= nv_change_mtu
,
5576 .ndo_validate_addr
= eth_validate_addr
,
5577 .ndo_set_mac_address
= nv_set_mac_address
,
5578 .ndo_set_multicast_list
= nv_set_multicast
,
5579 .ndo_vlan_rx_register
= nv_vlan_rx_register
,
5580 #ifdef CONFIG_NET_POLL_CONTROLLER
5581 .ndo_poll_controller
= nv_poll_controller
,
5585 static const struct net_device_ops nv_netdev_ops_optimized
= {
5586 .ndo_open
= nv_open
,
5587 .ndo_stop
= nv_close
,
5588 .ndo_get_stats
= nv_get_stats
,
5589 .ndo_start_xmit
= nv_start_xmit_optimized
,
5590 .ndo_tx_timeout
= nv_tx_timeout
,
5591 .ndo_change_mtu
= nv_change_mtu
,
5592 .ndo_validate_addr
= eth_validate_addr
,
5593 .ndo_set_mac_address
= nv_set_mac_address
,
5594 .ndo_set_multicast_list
= nv_set_multicast
,
5595 .ndo_vlan_rx_register
= nv_vlan_rx_register
,
5596 #ifdef CONFIG_NET_POLL_CONTROLLER
5597 .ndo_poll_controller
= nv_poll_controller
,
5601 static int __devinit
nv_probe(struct pci_dev
*pci_dev
, const struct pci_device_id
*id
)
5603 struct net_device
*dev
;
5608 u32 powerstate
, txreg
;
5609 u32 phystate_orig
= 0, phystate
;
5610 int phyinitialized
= 0;
5611 static int printed_version
;
5613 if (!printed_version
++)
5614 printk(KERN_INFO
"%s: Reverse Engineered nForce ethernet"
5615 " driver. Version %s.\n", DRV_NAME
, FORCEDETH_VERSION
);
5617 dev
= alloc_etherdev(sizeof(struct fe_priv
));
5622 np
= netdev_priv(dev
);
5624 np
->pci_dev
= pci_dev
;
5625 spin_lock_init(&np
->lock
);
5626 SET_NETDEV_DEV(dev
, &pci_dev
->dev
);
5628 init_timer(&np
->oom_kick
);
5629 np
->oom_kick
.data
= (unsigned long) dev
;
5630 np
->oom_kick
.function
= &nv_do_rx_refill
; /* timer handler */
5631 init_timer(&np
->nic_poll
);
5632 np
->nic_poll
.data
= (unsigned long) dev
;
5633 np
->nic_poll
.function
= &nv_do_nic_poll
; /* timer handler */
5634 init_timer(&np
->stats_poll
);
5635 np
->stats_poll
.data
= (unsigned long) dev
;
5636 np
->stats_poll
.function
= &nv_do_stats_poll
; /* timer handler */
5638 err
= pci_enable_device(pci_dev
);
5642 pci_set_master(pci_dev
);
5644 err
= pci_request_regions(pci_dev
, DRV_NAME
);
5648 if (id
->driver_data
& (DEV_HAS_VLAN
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_STATISTICS_V2
|DEV_HAS_STATISTICS_V3
))
5649 np
->register_size
= NV_PCI_REGSZ_VER3
;
5650 else if (id
->driver_data
& DEV_HAS_STATISTICS_V1
)
5651 np
->register_size
= NV_PCI_REGSZ_VER2
;
5653 np
->register_size
= NV_PCI_REGSZ_VER1
;
5657 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
5658 dprintk(KERN_DEBUG
"%s: resource %d start %p len %ld flags 0x%08lx.\n",
5659 pci_name(pci_dev
), i
, (void*)pci_resource_start(pci_dev
, i
),
5660 pci_resource_len(pci_dev
, i
),
5661 pci_resource_flags(pci_dev
, i
));
5662 if (pci_resource_flags(pci_dev
, i
) & IORESOURCE_MEM
&&
5663 pci_resource_len(pci_dev
, i
) >= np
->register_size
) {
5664 addr
= pci_resource_start(pci_dev
, i
);
5668 if (i
== DEVICE_COUNT_RESOURCE
) {
5669 dev_printk(KERN_INFO
, &pci_dev
->dev
,
5670 "Couldn't find register window\n");
5674 /* copy of driver data */
5675 np
->driver_data
= id
->driver_data
;
5676 /* copy of device id */
5677 np
->device_id
= id
->device
;
5679 /* handle different descriptor versions */
5680 if (id
->driver_data
& DEV_HAS_HIGH_DMA
) {
5681 /* packet format 3: supports 40-bit addressing */
5682 np
->desc_ver
= DESC_VER_3
;
5683 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_3
;
5685 if (pci_set_dma_mask(pci_dev
, DMA_BIT_MASK(39)))
5686 dev_printk(KERN_INFO
, &pci_dev
->dev
,
5687 "64-bit DMA failed, using 32-bit addressing\n");
5689 dev
->features
|= NETIF_F_HIGHDMA
;
5690 if (pci_set_consistent_dma_mask(pci_dev
, DMA_BIT_MASK(39))) {
5691 dev_printk(KERN_INFO
, &pci_dev
->dev
,
5692 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5695 } else if (id
->driver_data
& DEV_HAS_LARGEDESC
) {
5696 /* packet format 2: supports jumbo frames */
5697 np
->desc_ver
= DESC_VER_2
;
5698 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_2
;
5700 /* original packet format */
5701 np
->desc_ver
= DESC_VER_1
;
5702 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_1
;
5705 np
->pkt_limit
= NV_PKTLIMIT_1
;
5706 if (id
->driver_data
& DEV_HAS_LARGEDESC
)
5707 np
->pkt_limit
= NV_PKTLIMIT_2
;
5709 if (id
->driver_data
& DEV_HAS_CHECKSUM
) {
5711 np
->txrxctl_bits
|= NVREG_TXRXCTL_RXCHECK
;
5712 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
5713 dev
->features
|= NETIF_F_TSO
;
5716 np
->vlanctl_bits
= 0;
5717 if (id
->driver_data
& DEV_HAS_VLAN
) {
5718 np
->vlanctl_bits
= NVREG_VLANCONTROL_ENABLE
;
5719 dev
->features
|= NETIF_F_HW_VLAN_RX
| NETIF_F_HW_VLAN_TX
;
5722 np
->pause_flags
= NV_PAUSEFRAME_RX_CAPABLE
| NV_PAUSEFRAME_RX_REQ
| NV_PAUSEFRAME_AUTONEG
;
5723 if ((id
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V1
) ||
5724 (id
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V2
) ||
5725 (id
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V3
)) {
5726 np
->pause_flags
|= NV_PAUSEFRAME_TX_CAPABLE
| NV_PAUSEFRAME_TX_REQ
;
5731 np
->base
= ioremap(addr
, np
->register_size
);
5734 dev
->base_addr
= (unsigned long)np
->base
;
5736 dev
->irq
= pci_dev
->irq
;
5738 np
->rx_ring_size
= RX_RING_DEFAULT
;
5739 np
->tx_ring_size
= TX_RING_DEFAULT
;
5741 if (!nv_optimized(np
)) {
5742 np
->rx_ring
.orig
= pci_alloc_consistent(pci_dev
,
5743 sizeof(struct ring_desc
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
5745 if (!np
->rx_ring
.orig
)
5747 np
->tx_ring
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
];
5749 np
->rx_ring
.ex
= pci_alloc_consistent(pci_dev
,
5750 sizeof(struct ring_desc_ex
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
5752 if (!np
->rx_ring
.ex
)
5754 np
->tx_ring
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
];
5756 np
->rx_skb
= kcalloc(np
->rx_ring_size
, sizeof(struct nv_skb_map
), GFP_KERNEL
);
5757 np
->tx_skb
= kcalloc(np
->tx_ring_size
, sizeof(struct nv_skb_map
), GFP_KERNEL
);
5758 if (!np
->rx_skb
|| !np
->tx_skb
)
5761 if (!nv_optimized(np
))
5762 dev
->netdev_ops
= &nv_netdev_ops
;
5764 dev
->netdev_ops
= &nv_netdev_ops_optimized
;
5766 #ifdef CONFIG_FORCEDETH_NAPI
5767 netif_napi_add(dev
, &np
->napi
, nv_napi_poll
, RX_WORK_PER_LOOP
);
5769 SET_ETHTOOL_OPS(dev
, &ops
);
5770 dev
->watchdog_timeo
= NV_WATCHDOG_TIMEO
;
5772 pci_set_drvdata(pci_dev
, dev
);
5774 /* read the mac address */
5775 base
= get_hwbase(dev
);
5776 np
->orig_mac
[0] = readl(base
+ NvRegMacAddrA
);
5777 np
->orig_mac
[1] = readl(base
+ NvRegMacAddrB
);
5779 /* check the workaround bit for correct mac address order */
5780 txreg
= readl(base
+ NvRegTransmitPoll
);
5781 if (id
->driver_data
& DEV_HAS_CORRECT_MACADDR
) {
5782 /* mac address is already in correct order */
5783 dev
->dev_addr
[0] = (np
->orig_mac
[0] >> 0) & 0xff;
5784 dev
->dev_addr
[1] = (np
->orig_mac
[0] >> 8) & 0xff;
5785 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 16) & 0xff;
5786 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 24) & 0xff;
5787 dev
->dev_addr
[4] = (np
->orig_mac
[1] >> 0) & 0xff;
5788 dev
->dev_addr
[5] = (np
->orig_mac
[1] >> 8) & 0xff;
5789 } else if (txreg
& NVREG_TRANSMITPOLL_MAC_ADDR_REV
) {
5790 /* mac address is already in correct order */
5791 dev
->dev_addr
[0] = (np
->orig_mac
[0] >> 0) & 0xff;
5792 dev
->dev_addr
[1] = (np
->orig_mac
[0] >> 8) & 0xff;
5793 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 16) & 0xff;
5794 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 24) & 0xff;
5795 dev
->dev_addr
[4] = (np
->orig_mac
[1] >> 0) & 0xff;
5796 dev
->dev_addr
[5] = (np
->orig_mac
[1] >> 8) & 0xff;
5798 * Set orig mac address back to the reversed version.
5799 * This flag will be cleared during low power transition.
5800 * Therefore, we should always put back the reversed address.
5802 np
->orig_mac
[0] = (dev
->dev_addr
[5] << 0) + (dev
->dev_addr
[4] << 8) +
5803 (dev
->dev_addr
[3] << 16) + (dev
->dev_addr
[2] << 24);
5804 np
->orig_mac
[1] = (dev
->dev_addr
[1] << 0) + (dev
->dev_addr
[0] << 8);
5806 /* need to reverse mac address to correct order */
5807 dev
->dev_addr
[0] = (np
->orig_mac
[1] >> 8) & 0xff;
5808 dev
->dev_addr
[1] = (np
->orig_mac
[1] >> 0) & 0xff;
5809 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 24) & 0xff;
5810 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 16) & 0xff;
5811 dev
->dev_addr
[4] = (np
->orig_mac
[0] >> 8) & 0xff;
5812 dev
->dev_addr
[5] = (np
->orig_mac
[0] >> 0) & 0xff;
5813 writel(txreg
|NVREG_TRANSMITPOLL_MAC_ADDR_REV
, base
+ NvRegTransmitPoll
);
5814 printk(KERN_DEBUG
"nv_probe: set workaround bit for reversed mac addr\n");
5816 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
5818 if (!is_valid_ether_addr(dev
->perm_addr
)) {
5820 * Bad mac address. At least one bios sets the mac address
5821 * to 01:23:45:67:89:ab
5823 dev_printk(KERN_ERR
, &pci_dev
->dev
,
5824 "Invalid Mac address detected: %pM\n",
5826 dev_printk(KERN_ERR
, &pci_dev
->dev
,
5827 "Please complain to your hardware vendor. Switching to a random MAC.\n");
5828 random_ether_addr(dev
->dev_addr
);
5831 dprintk(KERN_DEBUG
"%s: MAC Address %pM\n",
5832 pci_name(pci_dev
), dev
->dev_addr
);
5834 /* set mac address */
5835 nv_copy_mac_to_hw(dev
);
5837 /* Workaround current PCI init glitch: wakeup bits aren't
5838 * being set from PCI PM capability.
5840 device_init_wakeup(&pci_dev
->dev
, 1);
5843 writel(0, base
+ NvRegWakeUpFlags
);
5846 if (id
->driver_data
& DEV_HAS_POWER_CNTRL
) {
5848 /* take phy and nic out of low power mode */
5849 powerstate
= readl(base
+ NvRegPowerState2
);
5850 powerstate
&= ~NVREG_POWERSTATE2_POWERUP_MASK
;
5851 if ((id
->driver_data
& DEV_NEED_LOW_POWER_FIX
) &&
5852 pci_dev
->revision
>= 0xA3)
5853 powerstate
|= NVREG_POWERSTATE2_POWERUP_REV_A3
;
5854 writel(powerstate
, base
+ NvRegPowerState2
);
5857 if (np
->desc_ver
== DESC_VER_1
) {
5858 np
->tx_flags
= NV_TX_VALID
;
5860 np
->tx_flags
= NV_TX2_VALID
;
5864 if ((id
->driver_data
& DEV_HAS_MSI
) && msi
) {
5865 np
->msi_flags
|= NV_MSI_CAPABLE
;
5867 if ((id
->driver_data
& DEV_HAS_MSI_X
) && msix
) {
5868 /* msix has had reported issues when modifying irqmask
5869 as in the case of napi, therefore, disable for now
5871 #ifndef CONFIG_FORCEDETH_NAPI
5872 np
->msi_flags
|= NV_MSI_X_CAPABLE
;
5876 if (optimization_mode
== NV_OPTIMIZATION_MODE_CPU
) {
5877 np
->irqmask
= NVREG_IRQMASK_CPU
;
5878 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) /* set number of vectors */
5879 np
->msi_flags
|= 0x0001;
5880 } else if (optimization_mode
== NV_OPTIMIZATION_MODE_DYNAMIC
&&
5881 !(id
->driver_data
& DEV_NEED_TIMERIRQ
)) {
5882 /* start off in throughput mode */
5883 np
->irqmask
= NVREG_IRQMASK_THROUGHPUT
;
5884 /* remove support for msix mode */
5885 np
->msi_flags
&= ~NV_MSI_X_CAPABLE
;
5887 optimization_mode
= NV_OPTIMIZATION_MODE_THROUGHPUT
;
5888 np
->irqmask
= NVREG_IRQMASK_THROUGHPUT
;
5889 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) /* set number of vectors */
5890 np
->msi_flags
|= 0x0003;
5893 if (id
->driver_data
& DEV_NEED_TIMERIRQ
)
5894 np
->irqmask
|= NVREG_IRQ_TIMER
;
5895 if (id
->driver_data
& DEV_NEED_LINKTIMER
) {
5896 dprintk(KERN_INFO
"%s: link timer on.\n", pci_name(pci_dev
));
5897 np
->need_linktimer
= 1;
5898 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
5900 dprintk(KERN_INFO
"%s: link timer off.\n", pci_name(pci_dev
));
5901 np
->need_linktimer
= 0;
5904 /* Limit the number of tx's outstanding for hw bug */
5905 if (id
->driver_data
& DEV_NEED_TX_LIMIT
) {
5907 if (((id
->driver_data
& DEV_NEED_TX_LIMIT2
) == DEV_NEED_TX_LIMIT2
) &&
5908 pci_dev
->revision
>= 0xA2)
5912 /* clear phy state and temporarily halt phy interrupts */
5913 writel(0, base
+ NvRegMIIMask
);
5914 phystate
= readl(base
+ NvRegAdapterControl
);
5915 if (phystate
& NVREG_ADAPTCTL_RUNNING
) {
5917 phystate
&= ~NVREG_ADAPTCTL_RUNNING
;
5918 writel(phystate
, base
+ NvRegAdapterControl
);
5920 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5922 if (id
->driver_data
& DEV_HAS_MGMT_UNIT
) {
5923 /* management unit running on the mac? */
5924 if ((readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_MGMT_ST
) &&
5925 (readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_SYNC_PHY_INIT
) &&
5926 nv_mgmt_acquire_sema(dev
) &&
5927 nv_mgmt_get_version(dev
)) {
5929 if (np
->mgmt_version
> 0) {
5930 np
->mac_in_use
= readl(base
+ NvRegMgmtUnitControl
) & NVREG_MGMTUNITCONTROL_INUSE
;
5932 dprintk(KERN_INFO
"%s: mgmt unit is running. mac in use %x.\n",
5933 pci_name(pci_dev
), np
->mac_in_use
);
5934 /* management unit setup the phy already? */
5935 if (np
->mac_in_use
&&
5936 ((readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_SYNC_MASK
) ==
5937 NVREG_XMITCTL_SYNC_PHY_INIT
)) {
5938 /* phy is inited by mgmt unit */
5940 dprintk(KERN_INFO
"%s: Phy already initialized by mgmt unit.\n",
5943 /* we need to init the phy */
5948 /* find a suitable phy */
5949 for (i
= 1; i
<= 32; i
++) {
5951 int phyaddr
= i
& 0x1F;
5953 spin_lock_irq(&np
->lock
);
5954 id1
= mii_rw(dev
, phyaddr
, MII_PHYSID1
, MII_READ
);
5955 spin_unlock_irq(&np
->lock
);
5956 if (id1
< 0 || id1
== 0xffff)
5958 spin_lock_irq(&np
->lock
);
5959 id2
= mii_rw(dev
, phyaddr
, MII_PHYSID2
, MII_READ
);
5960 spin_unlock_irq(&np
->lock
);
5961 if (id2
< 0 || id2
== 0xffff)
5964 np
->phy_model
= id2
& PHYID2_MODEL_MASK
;
5965 id1
= (id1
& PHYID1_OUI_MASK
) << PHYID1_OUI_SHFT
;
5966 id2
= (id2
& PHYID2_OUI_MASK
) >> PHYID2_OUI_SHFT
;
5967 dprintk(KERN_DEBUG
"%s: open: Found PHY %04x:%04x at address %d.\n",
5968 pci_name(pci_dev
), id1
, id2
, phyaddr
);
5969 np
->phyaddr
= phyaddr
;
5970 np
->phy_oui
= id1
| id2
;
5972 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5973 if (np
->phy_oui
== PHY_OUI_REALTEK2
)
5974 np
->phy_oui
= PHY_OUI_REALTEK
;
5975 /* Setup phy revision for Realtek */
5976 if (np
->phy_oui
== PHY_OUI_REALTEK
&& np
->phy_model
== PHY_MODEL_REALTEK_8211
)
5977 np
->phy_rev
= mii_rw(dev
, phyaddr
, MII_RESV1
, MII_READ
) & PHY_REV_MASK
;
5982 dev_printk(KERN_INFO
, &pci_dev
->dev
,
5983 "open: Could not find a valid PHY.\n");
5987 if (!phyinitialized
) {
5991 /* see if it is a gigabit phy */
5992 u32 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
5993 if (mii_status
& PHY_GIGABIT
) {
5994 np
->gigabit
= PHY_GIGABIT
;
5998 /* set default link speed settings */
5999 np
->linkspeed
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
6003 err
= register_netdev(dev
);
6005 dev_printk(KERN_INFO
, &pci_dev
->dev
,
6006 "unable to register netdev: %d\n", err
);
6010 dev_printk(KERN_INFO
, &pci_dev
->dev
, "ifname %s, PHY OUI 0x%x @ %d, "
6011 "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
6022 dev_printk(KERN_INFO
, &pci_dev
->dev
, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
6023 dev
->features
& NETIF_F_HIGHDMA
? "highdma " : "",
6024 dev
->features
& (NETIF_F_IP_CSUM
| NETIF_F_SG
) ?
6026 dev
->features
& (NETIF_F_HW_VLAN_RX
| NETIF_F_HW_VLAN_TX
) ?
6028 id
->driver_data
& DEV_HAS_POWER_CNTRL
? "pwrctl " : "",
6029 id
->driver_data
& DEV_HAS_MGMT_UNIT
? "mgmt " : "",
6030 id
->driver_data
& DEV_NEED_TIMERIRQ
? "timirq " : "",
6031 np
->gigabit
== PHY_GIGABIT
? "gbit " : "",
6032 np
->need_linktimer
? "lnktim " : "",
6033 np
->msi_flags
& NV_MSI_CAPABLE
? "msi " : "",
6034 np
->msi_flags
& NV_MSI_X_CAPABLE
? "msi-x " : "",
6041 writel(phystate
|NVREG_ADAPTCTL_RUNNING
, base
+ NvRegAdapterControl
);
6042 pci_set_drvdata(pci_dev
, NULL
);
6046 iounmap(get_hwbase(dev
));
6048 pci_release_regions(pci_dev
);
6050 pci_disable_device(pci_dev
);
6057 static void nv_restore_phy(struct net_device
*dev
)
6059 struct fe_priv
*np
= netdev_priv(dev
);
6060 u16 phy_reserved
, mii_control
;
6062 if (np
->phy_oui
== PHY_OUI_REALTEK
&&
6063 np
->phy_model
== PHY_MODEL_REALTEK_8201
&&
6064 phy_cross
== NV_CROSSOVER_DETECTION_DISABLED
) {
6065 mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
);
6066 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, MII_READ
);
6067 phy_reserved
&= ~PHY_REALTEK_INIT_MSK1
;
6068 phy_reserved
|= PHY_REALTEK_INIT8
;
6069 mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, phy_reserved
);
6070 mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
);
6072 /* restart auto negotiation */
6073 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
6074 mii_control
|= (BMCR_ANRESTART
| BMCR_ANENABLE
);
6075 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
);
6079 static void nv_restore_mac_addr(struct pci_dev
*pci_dev
)
6081 struct net_device
*dev
= pci_get_drvdata(pci_dev
);
6082 struct fe_priv
*np
= netdev_priv(dev
);
6083 u8 __iomem
*base
= get_hwbase(dev
);
6085 /* special op: write back the misordered MAC address - otherwise
6086 * the next nv_probe would see a wrong address.
6088 writel(np
->orig_mac
[0], base
+ NvRegMacAddrA
);
6089 writel(np
->orig_mac
[1], base
+ NvRegMacAddrB
);
6090 writel(readl(base
+ NvRegTransmitPoll
) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV
,
6091 base
+ NvRegTransmitPoll
);
6094 static void __devexit
nv_remove(struct pci_dev
*pci_dev
)
6096 struct net_device
*dev
= pci_get_drvdata(pci_dev
);
6098 unregister_netdev(dev
);
6100 nv_restore_mac_addr(pci_dev
);
6102 /* restore any phy related changes */
6103 nv_restore_phy(dev
);
6105 nv_mgmt_release_sema(dev
);
6107 /* free all structures */
6109 iounmap(get_hwbase(dev
));
6110 pci_release_regions(pci_dev
);
6111 pci_disable_device(pci_dev
);
6113 pci_set_drvdata(pci_dev
, NULL
);
6117 static int nv_suspend(struct pci_dev
*pdev
, pm_message_t state
)
6119 struct net_device
*dev
= pci_get_drvdata(pdev
);
6120 struct fe_priv
*np
= netdev_priv(dev
);
6121 u8 __iomem
*base
= get_hwbase(dev
);
6124 if (netif_running(dev
)) {
6128 netif_device_detach(dev
);
6130 /* save non-pci configuration space */
6131 for (i
= 0;i
<= np
->register_size
/sizeof(u32
); i
++)
6132 np
->saved_config_space
[i
] = readl(base
+ i
*sizeof(u32
));
6134 pci_save_state(pdev
);
6135 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), np
->wolenabled
);
6136 pci_disable_device(pdev
);
6137 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
6141 static int nv_resume(struct pci_dev
*pdev
)
6143 struct net_device
*dev
= pci_get_drvdata(pdev
);
6144 struct fe_priv
*np
= netdev_priv(dev
);
6145 u8 __iomem
*base
= get_hwbase(dev
);
6148 pci_set_power_state(pdev
, PCI_D0
);
6149 pci_restore_state(pdev
);
6150 /* ack any pending wake events, disable PME */
6151 pci_enable_wake(pdev
, PCI_D0
, 0);
6153 /* restore non-pci configuration space */
6154 for (i
= 0;i
<= np
->register_size
/sizeof(u32
); i
++)
6155 writel(np
->saved_config_space
[i
], base
+i
*sizeof(u32
));
6157 if (np
->driver_data
& DEV_NEED_MSI_FIX
)
6158 pci_write_config_dword(pdev
, NV_MSI_PRIV_OFFSET
, NV_MSI_PRIV_VALUE
);
6160 /* restore phy state, including autoneg */
6163 netif_device_attach(dev
);
6164 if (netif_running(dev
)) {
6166 nv_set_multicast(dev
);
6171 static void nv_shutdown(struct pci_dev
*pdev
)
6173 struct net_device
*dev
= pci_get_drvdata(pdev
);
6174 struct fe_priv
*np
= netdev_priv(dev
);
6176 if (netif_running(dev
))
6180 * Restore the MAC so a kernel started by kexec won't get confused.
6181 * If we really go for poweroff, we must not restore the MAC,
6182 * otherwise the MAC for WOL will be reversed at least on some boards.
6184 if (system_state
!= SYSTEM_POWER_OFF
) {
6185 nv_restore_mac_addr(pdev
);
6188 pci_disable_device(pdev
);
6190 * Apparently it is not possible to reinitialise from D3 hot,
6191 * only put the device into D3 if we really go for poweroff.
6193 if (system_state
== SYSTEM_POWER_OFF
) {
6194 if (pci_enable_wake(pdev
, PCI_D3cold
, np
->wolenabled
))
6195 pci_enable_wake(pdev
, PCI_D3hot
, np
->wolenabled
);
6196 pci_set_power_state(pdev
, PCI_D3hot
);
6200 #define nv_suspend NULL
6201 #define nv_shutdown NULL
6202 #define nv_resume NULL
6203 #endif /* CONFIG_PM */
6205 static DEFINE_PCI_DEVICE_TABLE(pci_tbl
) = {
6206 { /* nForce Ethernet Controller */
6207 PCI_DEVICE(0x10DE, 0x01C3),
6208 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
6210 { /* nForce2 Ethernet Controller */
6211 PCI_DEVICE(0x10DE, 0x0066),
6212 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
6214 { /* nForce3 Ethernet Controller */
6215 PCI_DEVICE(0x10DE, 0x00D6),
6216 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
6218 { /* nForce3 Ethernet Controller */
6219 PCI_DEVICE(0x10DE, 0x0086),
6220 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
6222 { /* nForce3 Ethernet Controller */
6223 PCI_DEVICE(0x10DE, 0x008C),
6224 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
6226 { /* nForce3 Ethernet Controller */
6227 PCI_DEVICE(0x10DE, 0x00E6),
6228 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
6230 { /* nForce3 Ethernet Controller */
6231 PCI_DEVICE(0x10DE, 0x00DF),
6232 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
6234 { /* CK804 Ethernet Controller */
6235 PCI_DEVICE(0x10DE, 0x0056),
6236 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
6238 { /* CK804 Ethernet Controller */
6239 PCI_DEVICE(0x10DE, 0x0057),
6240 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
6242 { /* MCP04 Ethernet Controller */
6243 PCI_DEVICE(0x10DE, 0x0037),
6244 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
6246 { /* MCP04 Ethernet Controller */
6247 PCI_DEVICE(0x10DE, 0x0038),
6248 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
6250 { /* MCP51 Ethernet Controller */
6251 PCI_DEVICE(0x10DE, 0x0268),
6252 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_STATISTICS_V1
|DEV_NEED_LOW_POWER_FIX
,
6254 { /* MCP51 Ethernet Controller */
6255 PCI_DEVICE(0x10DE, 0x0269),
6256 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_STATISTICS_V1
|DEV_NEED_LOW_POWER_FIX
,
6258 { /* MCP55 Ethernet Controller */
6259 PCI_DEVICE(0x10DE, 0x0372),
6260 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_VLAN
|DEV_HAS_MSI
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_NEED_TX_LIMIT
|DEV_NEED_MSI_FIX
,
6262 { /* MCP55 Ethernet Controller */
6263 PCI_DEVICE(0x10DE, 0x0373),
6264 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_VLAN
|DEV_HAS_MSI
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_NEED_TX_LIMIT
|DEV_NEED_MSI_FIX
,
6266 { /* MCP61 Ethernet Controller */
6267 PCI_DEVICE(0x10DE, 0x03E5),
6268 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_MSI_FIX
,
6270 { /* MCP61 Ethernet Controller */
6271 PCI_DEVICE(0x10DE, 0x03E6),
6272 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_MSI_FIX
,
6274 { /* MCP61 Ethernet Controller */
6275 PCI_DEVICE(0x10DE, 0x03EE),
6276 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_MSI_FIX
,
6278 { /* MCP61 Ethernet Controller */
6279 PCI_DEVICE(0x10DE, 0x03EF),
6280 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_MSI_FIX
,
6282 { /* MCP65 Ethernet Controller */
6283 PCI_DEVICE(0x10DE, 0x0450),
6284 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6286 { /* MCP65 Ethernet Controller */
6287 PCI_DEVICE(0x10DE, 0x0451),
6288 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6290 { /* MCP65 Ethernet Controller */
6291 PCI_DEVICE(0x10DE, 0x0452),
6292 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6294 { /* MCP65 Ethernet Controller */
6295 PCI_DEVICE(0x10DE, 0x0453),
6296 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6298 { /* MCP67 Ethernet Controller */
6299 PCI_DEVICE(0x10DE, 0x054C),
6300 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6302 { /* MCP67 Ethernet Controller */
6303 PCI_DEVICE(0x10DE, 0x054D),
6304 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6306 { /* MCP67 Ethernet Controller */
6307 PCI_DEVICE(0x10DE, 0x054E),
6308 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6310 { /* MCP67 Ethernet Controller */
6311 PCI_DEVICE(0x10DE, 0x054F),
6312 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6314 { /* MCP73 Ethernet Controller */
6315 PCI_DEVICE(0x10DE, 0x07DC),
6316 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6318 { /* MCP73 Ethernet Controller */
6319 PCI_DEVICE(0x10DE, 0x07DD),
6320 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6322 { /* MCP73 Ethernet Controller */
6323 PCI_DEVICE(0x10DE, 0x07DE),
6324 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6326 { /* MCP73 Ethernet Controller */
6327 PCI_DEVICE(0x10DE, 0x07DF),
6328 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6330 { /* MCP77 Ethernet Controller */
6331 PCI_DEVICE(0x10DE, 0x0760),
6332 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V3
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6334 { /* MCP77 Ethernet Controller */
6335 PCI_DEVICE(0x10DE, 0x0761),
6336 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V3
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6338 { /* MCP77 Ethernet Controller */
6339 PCI_DEVICE(0x10DE, 0x0762),
6340 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V3
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6342 { /* MCP77 Ethernet Controller */
6343 PCI_DEVICE(0x10DE, 0x0763),
6344 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V3
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6346 { /* MCP79 Ethernet Controller */
6347 PCI_DEVICE(0x10DE, 0x0AB0),
6348 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V3
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6350 { /* MCP79 Ethernet Controller */
6351 PCI_DEVICE(0x10DE, 0x0AB1),
6352 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V3
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6354 { /* MCP79 Ethernet Controller */
6355 PCI_DEVICE(0x10DE, 0x0AB2),
6356 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V3
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6358 { /* MCP79 Ethernet Controller */
6359 PCI_DEVICE(0x10DE, 0x0AB3),
6360 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V3
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6362 { /* MCP89 Ethernet Controller */
6363 PCI_DEVICE(0x10DE, 0x0D7D),
6364 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V3
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
,
6369 static struct pci_driver driver
= {
6371 .id_table
= pci_tbl
,
6373 .remove
= __devexit_p(nv_remove
),
6374 .suspend
= nv_suspend
,
6375 .resume
= nv_resume
,
6376 .shutdown
= nv_shutdown
,
6379 static int __init
init_nic(void)
6381 return pci_register_driver(&driver
);
6384 static void __exit
exit_nic(void)
6386 pci_unregister_driver(&driver
);
6389 module_param(max_interrupt_work
, int, 0);
6390 MODULE_PARM_DESC(max_interrupt_work
, "forcedeth maximum events handled per interrupt");
6391 module_param(optimization_mode
, int, 0);
6392 MODULE_PARM_DESC(optimization_mode
, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6393 module_param(poll_interval
, int, 0);
6394 MODULE_PARM_DESC(poll_interval
, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6395 module_param(msi
, int, 0);
6396 MODULE_PARM_DESC(msi
, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6397 module_param(msix
, int, 0);
6398 MODULE_PARM_DESC(msix
, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6399 module_param(dma_64bit
, int, 0);
6400 MODULE_PARM_DESC(dma_64bit
, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6401 module_param(phy_cross
, int, 0);
6402 MODULE_PARM_DESC(phy_cross
, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6403 module_param(phy_power_down
, int, 0);
6404 MODULE_PARM_DESC(phy_power_down
, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6406 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6407 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6408 MODULE_LICENSE("GPL");
6410 MODULE_DEVICE_TABLE(pci
, pci_tbl
);
6412 module_init(init_nic
);
6413 module_exit(exit_nic
);