| blob | 8948016a1c46eb7f646fbabdcc8257530ee4af85 |
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
13 #include "skeleton.dtsi"
15 / {
16 aliases {
17 can0 = &can1;
18 can1 = &can2;
19 gpio0 = &gpio1;
20 gpio1 = &gpio2;
21 gpio2 = &gpio3;
22 gpio3 = &gpio4;
23 gpio4 = &gpio5;
24 gpio5 = &gpio6;
25 gpio6 = &gpio7;
26 i2c0 = &i2c1;
27 i2c1 = &i2c2;
28 i2c2 = &i2c3;
29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 spi0 = &ecspi1;
35 spi1 = &ecspi2;
36 spi2 = &ecspi3;
37 spi3 = &ecspi4;
38 usbphy0 = &usbphy1;
39 usbphy1 = &usbphy2;
40 };
42 intc: interrupt-controller@00a01000 {
43 compatible = "arm,cortex-a9-gic";
44 #interrupt-cells = <3>;
45 #address-cells = <1>;
46 #size-cells = <1>;
47 interrupt-controller;
48 reg = <0x00a01000 0x1000>,
49 <0x00a00100 0x100>;
50 };
52 clocks {
53 #address-cells = <1>;
54 #size-cells = <0>;
56 ckil {
57 compatible = "fsl,imx-ckil", "fixed-clock";
58 clock-frequency = <32768>;
59 };
61 ckih1 {
62 compatible = "fsl,imx-ckih1", "fixed-clock";
63 clock-frequency = <0>;
64 };
66 osc {
67 compatible = "fsl,imx-osc", "fixed-clock";
68 clock-frequency = <24000000>;
69 };
70 };
72 soc {
73 #address-cells = <1>;
74 #size-cells = <1>;
75 compatible = "simple-bus";
76 interrupt-parent = <&intc>;
77 ranges;
79 dma_apbh: dma-apbh@00110000 {
80 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
81 reg = <0x00110000 0x2000>;
82 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
83 <0 13 IRQ_TYPE_LEVEL_HIGH>,
84 <0 13 IRQ_TYPE_LEVEL_HIGH>,
85 <0 13 IRQ_TYPE_LEVEL_HIGH>;
86 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
87 #dma-cells = <1>;
88 dma-channels = <4>;
89 clocks = <&clks 106>;
90 };
92 gpmi: gpmi-nand@00112000 {
93 compatible = "fsl,imx6q-gpmi-nand";
94 #address-cells = <1>;
95 #size-cells = <1>;
96 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
97 reg-names = "gpmi-nand", "bch";
98 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
99 interrupt-names = "bch";
100 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
101 <&clks 150>, <&clks 149>;
102 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
103 "gpmi_bch_apb", "per1_bch";
104 dmas = <&dma_apbh 0>;
105 dma-names = "rx-tx";
106 status = "disabled";
107 };
109 timer@00a00600 {
110 compatible = "arm,cortex-a9-twd-timer";
111 reg = <0x00a00600 0x20>;
112 interrupts = <1 13 0xf01>;
113 clocks = <&clks 15>;
114 };
116 L2: l2-cache@00a02000 {
117 compatible = "arm,pl310-cache";
118 reg = <0x00a02000 0x1000>;
119 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
120 cache-unified;
121 cache-level = <2>;
122 arm,tag-latency = <4 2 3>;
123 arm,data-latency = <4 2 3>;
124 };
126 pcie: pcie@0x01000000 {
127 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
128 reg = <0x01ffc000 0x4000>; /* DBI */
129 #address-cells = <3>;
130 #size-cells = <2>;
131 device_type = "pci";
132 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
133 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
134 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
135 num-lanes = <1>;
136 interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
138 clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
139 status = "disabled";
140 };
142 pmu {
143 compatible = "arm,cortex-a9-pmu";
144 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
145 };
147 aips-bus@02000000 { /* AIPS1 */
148 compatible = "fsl,aips-bus", "simple-bus";
149 #address-cells = <1>;
150 #size-cells = <1>;
151 reg = <0x02000000 0x100000>;
152 ranges;
154 spba-bus@02000000 {
155 compatible = "fsl,spba-bus", "simple-bus";
156 #address-cells = <1>;
157 #size-cells = <1>;
158 reg = <0x02000000 0x40000>;
159 ranges;
161 spdif: spdif@02004000 {
162 compatible = "fsl,imx35-spdif";
163 reg = <0x02004000 0x4000>;
164 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
165 dmas = <&sdma 14 18 0>,
166 <&sdma 15 18 0>;
167 dma-names = "rx", "tx";
168 clocks = <&clks 197>, <&clks 3>,
169 <&clks 197>, <&clks 107>,
170 <&clks 0>, <&clks 118>,
171 <&clks 0>, <&clks 139>,
172 <&clks 0>;
173 clock-names = "core", "rxtx0",
174 "rxtx1", "rxtx2",
175 "rxtx3", "rxtx4",
176 "rxtx5", "rxtx6",
177 "rxtx7";
178 status = "disabled";
179 };
181 ecspi1: ecspi@02008000 {
182 #address-cells = <1>;
183 #size-cells = <0>;
184 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
185 reg = <0x02008000 0x4000>;
186 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&clks 112>, <&clks 112>;
188 clock-names = "ipg", "per";
189 status = "disabled";
190 };
192 ecspi2: ecspi@0200c000 {
193 #address-cells = <1>;
194 #size-cells = <0>;
195 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
196 reg = <0x0200c000 0x4000>;
197 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&clks 113>, <&clks 113>;
199 clock-names = "ipg", "per";
200 status = "disabled";
201 };
203 ecspi3: ecspi@02010000 {
204 #address-cells = <1>;
205 #size-cells = <0>;
206 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
207 reg = <0x02010000 0x4000>;
208 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&clks 114>, <&clks 114>;
210 clock-names = "ipg", "per";
211 status = "disabled";
212 };
214 ecspi4: ecspi@02014000 {
215 #address-cells = <1>;
216 #size-cells = <0>;
217 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
218 reg = <0x02014000 0x4000>;
219 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&clks 115>, <&clks 115>;
221 clock-names = "ipg", "per";
222 status = "disabled";
223 };
225 uart1: serial@02020000 {
226 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
227 reg = <0x02020000 0x4000>;
228 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&clks 160>, <&clks 161>;
230 clock-names = "ipg", "per";
231 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
232 dma-names = "rx", "tx";
233 status = "disabled";
234 };
236 esai: esai@02024000 {
237 reg = <0x02024000 0x4000>;
238 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
239 };
241 ssi1: ssi@02028000 {
242 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
243 reg = <0x02028000 0x4000>;
244 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&clks 178>;
246 dmas = <&sdma 37 1 0>,
247 <&sdma 38 1 0>;
248 dma-names = "rx", "tx";
249 fsl,fifo-depth = <15>;
250 fsl,ssi-dma-events = <38 37>;
251 status = "disabled";
252 };
254 ssi2: ssi@0202c000 {
255 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
256 reg = <0x0202c000 0x4000>;
257 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&clks 179>;
259 dmas = <&sdma 41 1 0>,
260 <&sdma 42 1 0>;
261 dma-names = "rx", "tx";
262 fsl,fifo-depth = <15>;
263 fsl,ssi-dma-events = <42 41>;
264 status = "disabled";
265 };
267 ssi3: ssi@02030000 {
268 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
269 reg = <0x02030000 0x4000>;
270 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&clks 180>;
272 dmas = <&sdma 45 1 0>,
273 <&sdma 46 1 0>;
274 dma-names = "rx", "tx";
275 fsl,fifo-depth = <15>;
276 fsl,ssi-dma-events = <46 45>;
277 status = "disabled";
278 };
280 asrc: asrc@02034000 {
281 reg = <0x02034000 0x4000>;
282 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
283 };
285 spba@0203c000 {
286 reg = <0x0203c000 0x4000>;
287 };
288 };
290 vpu: vpu@02040000 {
291 reg = <0x02040000 0x3c000>;
292 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
293 <0 12 IRQ_TYPE_LEVEL_HIGH>;
294 };
296 aipstz@0207c000 { /* AIPSTZ1 */
297 reg = <0x0207c000 0x4000>;
298 };
300 pwm1: pwm@02080000 {
301 #pwm-cells = <2>;
302 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
303 reg = <0x02080000 0x4000>;
304 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&clks 62>, <&clks 145>;
306 clock-names = "ipg", "per";
307 };
309 pwm2: pwm@02084000 {
310 #pwm-cells = <2>;
311 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
312 reg = <0x02084000 0x4000>;
313 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&clks 62>, <&clks 146>;
315 clock-names = "ipg", "per";
316 };
318 pwm3: pwm@02088000 {
319 #pwm-cells = <2>;
320 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
321 reg = <0x02088000 0x4000>;
322 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&clks 62>, <&clks 147>;
324 clock-names = "ipg", "per";
325 };
327 pwm4: pwm@0208c000 {
328 #pwm-cells = <2>;
329 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
330 reg = <0x0208c000 0x4000>;
331 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&clks 62>, <&clks 148>;
333 clock-names = "ipg", "per";
334 };
336 can1: flexcan@02090000 {
337 compatible = "fsl,imx6q-flexcan";
338 reg = <0x02090000 0x4000>;
339 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&clks 108>, <&clks 109>;
341 clock-names = "ipg", "per";
342 status = "disabled";
343 };
345 can2: flexcan@02094000 {
346 compatible = "fsl,imx6q-flexcan";
347 reg = <0x02094000 0x4000>;
348 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&clks 110>, <&clks 111>;
350 clock-names = "ipg", "per";
351 status = "disabled";
352 };
354 gpt: gpt@02098000 {
355 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
356 reg = <0x02098000 0x4000>;
357 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&clks 119>, <&clks 120>;
359 clock-names = "ipg", "per";
360 };
362 gpio1: gpio@0209c000 {
363 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
364 reg = <0x0209c000 0x4000>;
365 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
366 <0 67 IRQ_TYPE_LEVEL_HIGH>;
367 gpio-controller;
368 #gpio-cells = <2>;
369 interrupt-controller;
370 #interrupt-cells = <2>;
371 };
373 gpio2: gpio@020a0000 {
374 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
375 reg = <0x020a0000 0x4000>;
376 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
377 <0 69 IRQ_TYPE_LEVEL_HIGH>;
378 gpio-controller;
379 #gpio-cells = <2>;
380 interrupt-controller;
381 #interrupt-cells = <2>;
382 };
384 gpio3: gpio@020a4000 {
385 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
386 reg = <0x020a4000 0x4000>;
387 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
388 <0 71 IRQ_TYPE_LEVEL_HIGH>;
389 gpio-controller;
390 #gpio-cells = <2>;
391 interrupt-controller;
392 #interrupt-cells = <2>;
393 };
395 gpio4: gpio@020a8000 {
396 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
397 reg = <0x020a8000 0x4000>;
398 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
399 <0 73 IRQ_TYPE_LEVEL_HIGH>;
400 gpio-controller;
401 #gpio-cells = <2>;
402 interrupt-controller;
403 #interrupt-cells = <2>;
404 };
406 gpio5: gpio@020ac000 {
407 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
408 reg = <0x020ac000 0x4000>;
409 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
410 <0 75 IRQ_TYPE_LEVEL_HIGH>;
411 gpio-controller;
412 #gpio-cells = <2>;
413 interrupt-controller;
414 #interrupt-cells = <2>;
415 };
417 gpio6: gpio@020b0000 {
418 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
419 reg = <0x020b0000 0x4000>;
420 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
421 <0 77 IRQ_TYPE_LEVEL_HIGH>;
422 gpio-controller;
423 #gpio-cells = <2>;
424 interrupt-controller;
425 #interrupt-cells = <2>;
426 };
428 gpio7: gpio@020b4000 {
429 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
430 reg = <0x020b4000 0x4000>;
431 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
432 <0 79 IRQ_TYPE_LEVEL_HIGH>;
433 gpio-controller;
434 #gpio-cells = <2>;
435 interrupt-controller;
436 #interrupt-cells = <2>;
437 };
439 kpp: kpp@020b8000 {
440 reg = <0x020b8000 0x4000>;
441 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
442 };
444 wdog1: wdog@020bc000 {
445 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
446 reg = <0x020bc000 0x4000>;
447 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&clks 0>;
449 };
451 wdog2: wdog@020c0000 {
452 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
453 reg = <0x020c0000 0x4000>;
454 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&clks 0>;
456 status = "disabled";
457 };
459 clks: ccm@020c4000 {
460 compatible = "fsl,imx6q-ccm";
461 reg = <0x020c4000 0x4000>;
462 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
463 <0 88 IRQ_TYPE_LEVEL_HIGH>;
464 #clock-cells = <1>;
465 };
467 anatop: anatop@020c8000 {
468 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
469 reg = <0x020c8000 0x1000>;
470 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
471 <0 54 IRQ_TYPE_LEVEL_HIGH>,
472 <0 127 IRQ_TYPE_LEVEL_HIGH>;
474 regulator-1p1@110 {
475 compatible = "fsl,anatop-regulator";
476 regulator-name = "vdd1p1";
477 regulator-min-microvolt = <800000>;
478 regulator-max-microvolt = <1375000>;
479 regulator-always-on;
480 anatop-reg-offset = <0x110>;
481 anatop-vol-bit-shift = <8>;
482 anatop-vol-bit-width = <5>;
483 anatop-min-bit-val = <4>;
484 anatop-min-voltage = <800000>;
485 anatop-max-voltage = <1375000>;
486 };
488 regulator-3p0@120 {
489 compatible = "fsl,anatop-regulator";
490 regulator-name = "vdd3p0";
491 regulator-min-microvolt = <2800000>;
492 regulator-max-microvolt = <3150000>;
493 regulator-always-on;
494 anatop-reg-offset = <0x120>;
495 anatop-vol-bit-shift = <8>;
496 anatop-vol-bit-width = <5>;
497 anatop-min-bit-val = <0>;
498 anatop-min-voltage = <2625000>;
499 anatop-max-voltage = <3400000>;
500 };
502 regulator-2p5@130 {
503 compatible = "fsl,anatop-regulator";
504 regulator-name = "vdd2p5";
505 regulator-min-microvolt = <2000000>;
506 regulator-max-microvolt = <2750000>;
507 regulator-always-on;
508 anatop-reg-offset = <0x130>;
509 anatop-vol-bit-shift = <8>;
510 anatop-vol-bit-width = <5>;
511 anatop-min-bit-val = <0>;
512 anatop-min-voltage = <2000000>;
513 anatop-max-voltage = <2750000>;
514 };
516 reg_arm: regulator-vddcore@140 {
517 compatible = "fsl,anatop-regulator";
518 regulator-name = "vddarm";
519 regulator-min-microvolt = <725000>;
520 regulator-max-microvolt = <1450000>;
521 regulator-always-on;
522 anatop-reg-offset = <0x140>;
523 anatop-vol-bit-shift = <0>;
524 anatop-vol-bit-width = <5>;
525 anatop-delay-reg-offset = <0x170>;
526 anatop-delay-bit-shift = <24>;
527 anatop-delay-bit-width = <2>;
528 anatop-min-bit-val = <1>;
529 anatop-min-voltage = <725000>;
530 anatop-max-voltage = <1450000>;
531 };
533 reg_pu: regulator-vddpu@140 {
534 compatible = "fsl,anatop-regulator";
535 regulator-name = "vddpu";
536 regulator-min-microvolt = <725000>;
537 regulator-max-microvolt = <1450000>;
538 regulator-always-on;
539 anatop-reg-offset = <0x140>;
540 anatop-vol-bit-shift = <9>;
541 anatop-vol-bit-width = <5>;
542 anatop-delay-reg-offset = <0x170>;
543 anatop-delay-bit-shift = <26>;
544 anatop-delay-bit-width = <2>;
545 anatop-min-bit-val = <1>;
546 anatop-min-voltage = <725000>;
547 anatop-max-voltage = <1450000>;
548 };
550 reg_soc: regulator-vddsoc@140 {
551 compatible = "fsl,anatop-regulator";
552 regulator-name = "vddsoc";
553 regulator-min-microvolt = <725000>;
554 regulator-max-microvolt = <1450000>;
555 regulator-always-on;
556 anatop-reg-offset = <0x140>;
557 anatop-vol-bit-shift = <18>;
558 anatop-vol-bit-width = <5>;
559 anatop-delay-reg-offset = <0x170>;
560 anatop-delay-bit-shift = <28>;
561 anatop-delay-bit-width = <2>;
562 anatop-min-bit-val = <1>;
563 anatop-min-voltage = <725000>;
564 anatop-max-voltage = <1450000>;
565 };
566 };
568 tempmon: tempmon {
569 compatible = "fsl,imx6q-tempmon";
570 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
571 fsl,tempmon = <&anatop>;
572 fsl,tempmon-data = <&ocotp>;
573 clocks = <&clks 172>;
574 };
576 usbphy1: usbphy@020c9000 {
577 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
578 reg = <0x020c9000 0x1000>;
579 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&clks 182>;
581 fsl,anatop = <&anatop>;
582 };
584 usbphy2: usbphy@020ca000 {
585 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
586 reg = <0x020ca000 0x1000>;
587 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&clks 183>;
589 fsl,anatop = <&anatop>;
590 };
592 snvs@020cc000 {
593 compatible = "fsl,sec-v4.0-mon", "simple-bus";
594 #address-cells = <1>;
595 #size-cells = <1>;
596 ranges = <0 0x020cc000 0x4000>;
598 snvs-rtc-lp@34 {
599 compatible = "fsl,sec-v4.0-mon-rtc-lp";
600 reg = <0x34 0x58>;
601 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
602 <0 20 IRQ_TYPE_LEVEL_HIGH>;
603 };
604 };
606 epit1: epit@020d0000 { /* EPIT1 */
607 reg = <0x020d0000 0x4000>;
608 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
609 };
611 epit2: epit@020d4000 { /* EPIT2 */
612 reg = <0x020d4000 0x4000>;
613 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
614 };
616 src: src@020d8000 {
617 compatible = "fsl,imx6q-src", "fsl,imx51-src";
618 reg = <0x020d8000 0x4000>;
619 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
620 <0 96 IRQ_TYPE_LEVEL_HIGH>;
621 #reset-cells = <1>;
622 };
624 gpc: gpc@020dc000 {
625 compatible = "fsl,imx6q-gpc";
626 reg = <0x020dc000 0x4000>;
627 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
628 <0 90 IRQ_TYPE_LEVEL_HIGH>;
629 };
631 gpr: iomuxc-gpr@020e0000 {
632 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
633 reg = <0x020e0000 0x38>;
634 };
636 iomuxc: iomuxc@020e0000 {
637 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
638 reg = <0x020e0000 0x4000>;
639 };
641 ldb: ldb@020e0008 {
642 #address-cells = <1>;
643 #size-cells = <0>;
644 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
645 gpr = <&gpr>;
646 status = "disabled";
648 lvds-channel@0 {
649 reg = <0>;
650 status = "disabled";
651 };
653 lvds-channel@1 {
654 reg = <1>;
655 status = "disabled";
656 };
657 };
659 dcic1: dcic@020e4000 {
660 reg = <0x020e4000 0x4000>;
661 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
662 };
664 dcic2: dcic@020e8000 {
665 reg = <0x020e8000 0x4000>;
666 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
667 };
669 sdma: sdma@020ec000 {
670 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
671 reg = <0x020ec000 0x4000>;
672 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&clks 155>, <&clks 155>;
674 clock-names = "ipg", "ahb";
675 #dma-cells = <3>;
676 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
677 };
678 };
680 aips-bus@02100000 { /* AIPS2 */
681 compatible = "fsl,aips-bus", "simple-bus";
682 #address-cells = <1>;
683 #size-cells = <1>;
684 reg = <0x02100000 0x100000>;
685 ranges;
687 caam@02100000 {
688 reg = <0x02100000 0x40000>;
689 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
690 <0 106 IRQ_TYPE_LEVEL_HIGH>;
691 };
693 aipstz@0217c000 { /* AIPSTZ2 */
694 reg = <0x0217c000 0x4000>;
695 };
697 usbotg: usb@02184000 {
698 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
699 reg = <0x02184000 0x200>;
700 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&clks 162>;
702 fsl,usbphy = <&usbphy1>;
703 fsl,usbmisc = <&usbmisc 0>;
704 status = "disabled";
705 };
707 usbh1: usb@02184200 {
708 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
709 reg = <0x02184200 0x200>;
710 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&clks 162>;
712 fsl,usbphy = <&usbphy2>;
713 fsl,usbmisc = <&usbmisc 1>;
714 status = "disabled";
715 };
717 usbh2: usb@02184400 {
718 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
719 reg = <0x02184400 0x200>;
720 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&clks 162>;
722 fsl,usbmisc = <&usbmisc 2>;
723 status = "disabled";
724 };
726 usbh3: usb@02184600 {
727 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
728 reg = <0x02184600 0x200>;
729 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
730 clocks = <&clks 162>;
731 fsl,usbmisc = <&usbmisc 3>;
732 status = "disabled";
733 };
735 usbmisc: usbmisc@02184800 {
736 #index-cells = <1>;
737 compatible = "fsl,imx6q-usbmisc";
738 reg = <0x02184800 0x200>;
739 clocks = <&clks 162>;
740 };
742 fec: ethernet@02188000 {
743 compatible = "fsl,imx6q-fec";
744 reg = <0x02188000 0x4000>;
745 interrupts-extended =
746 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
747 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
749 clock-names = "ipg", "ahb", "ptp";
750 status = "disabled";
751 };
753 mlb@0218c000 {
754 reg = <0x0218c000 0x4000>;
755 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
756 <0 117 IRQ_TYPE_LEVEL_HIGH>,
757 <0 126 IRQ_TYPE_LEVEL_HIGH>;
758 };
760 usdhc1: usdhc@02190000 {
761 compatible = "fsl,imx6q-usdhc";
762 reg = <0x02190000 0x4000>;
763 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
765 clock-names = "ipg", "ahb", "per";
766 bus-width = <4>;
767 status = "disabled";
768 };
770 usdhc2: usdhc@02194000 {
771 compatible = "fsl,imx6q-usdhc";
772 reg = <0x02194000 0x4000>;
773 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
775 clock-names = "ipg", "ahb", "per";
776 bus-width = <4>;
777 status = "disabled";
778 };
780 usdhc3: usdhc@02198000 {
781 compatible = "fsl,imx6q-usdhc";
782 reg = <0x02198000 0x4000>;
783 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
784 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
785 clock-names = "ipg", "ahb", "per";
786 bus-width = <4>;
787 status = "disabled";
788 };
790 usdhc4: usdhc@0219c000 {
791 compatible = "fsl,imx6q-usdhc";
792 reg = <0x0219c000 0x4000>;
793 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
794 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
795 clock-names = "ipg", "ahb", "per";
796 bus-width = <4>;
797 status = "disabled";
798 };
800 i2c1: i2c@021a0000 {
801 #address-cells = <1>;
802 #size-cells = <0>;
803 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
804 reg = <0x021a0000 0x4000>;
805 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&clks 125>;
807 status = "disabled";
808 };
810 i2c2: i2c@021a4000 {
811 #address-cells = <1>;
812 #size-cells = <0>;
813 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
814 reg = <0x021a4000 0x4000>;
815 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
816 clocks = <&clks 126>;
817 status = "disabled";
818 };
820 i2c3: i2c@021a8000 {
821 #address-cells = <1>;
822 #size-cells = <0>;
823 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
824 reg = <0x021a8000 0x4000>;
825 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
826 clocks = <&clks 127>;
827 status = "disabled";
828 };
830 romcp@021ac000 {
831 reg = <0x021ac000 0x4000>;
832 };
834 mmdc0: mmdc@021b0000 { /* MMDC0 */
835 compatible = "fsl,imx6q-mmdc";
836 reg = <0x021b0000 0x4000>;
837 };
839 mmdc1: mmdc@021b4000 { /* MMDC1 */
840 reg = <0x021b4000 0x4000>;
841 };
843 weim: weim@021b8000 {
844 compatible = "fsl,imx6q-weim";
845 reg = <0x021b8000 0x4000>;
846 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
847 clocks = <&clks 196>;
848 };
850 ocotp: ocotp@021bc000 {
851 compatible = "fsl,imx6q-ocotp", "syscon";
852 reg = <0x021bc000 0x4000>;
853 };
855 tzasc@021d0000 { /* TZASC1 */
856 reg = <0x021d0000 0x4000>;
857 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
858 };
860 tzasc@021d4000 { /* TZASC2 */
861 reg = <0x021d4000 0x4000>;
862 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
863 };
865 audmux: audmux@021d8000 {
866 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
867 reg = <0x021d8000 0x4000>;
868 status = "disabled";
869 };
871 mipi_csi: mipi@021dc000 {
872 reg = <0x021dc000 0x4000>;
873 };
875 mipi@021e0000 { /* MIPI-DSI */
876 reg = <0x021e0000 0x4000>;
877 };
879 vdoa@021e4000 {
880 reg = <0x021e4000 0x4000>;
881 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
882 };
884 uart2: serial@021e8000 {
885 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
886 reg = <0x021e8000 0x4000>;
887 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
888 clocks = <&clks 160>, <&clks 161>;
889 clock-names = "ipg", "per";
890 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
891 dma-names = "rx", "tx";
892 status = "disabled";
893 };
895 uart3: serial@021ec000 {
896 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
897 reg = <0x021ec000 0x4000>;
898 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&clks 160>, <&clks 161>;
900 clock-names = "ipg", "per";
901 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
902 dma-names = "rx", "tx";
903 status = "disabled";
904 };
906 uart4: serial@021f0000 {
907 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
908 reg = <0x021f0000 0x4000>;
909 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
910 clocks = <&clks 160>, <&clks 161>;
911 clock-names = "ipg", "per";
912 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
913 dma-names = "rx", "tx";
914 status = "disabled";
915 };
917 uart5: serial@021f4000 {
918 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
919 reg = <0x021f4000 0x4000>;
920 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&clks 160>, <&clks 161>;
922 clock-names = "ipg", "per";
923 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
924 dma-names = "rx", "tx";
925 status = "disabled";
926 };
927 };
929 ipu1: ipu@02400000 {
930 #crtc-cells = <1>;
931 compatible = "fsl,imx6q-ipu";
932 reg = <0x02400000 0x400000>;
933 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
934 <0 5 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
936 clock-names = "bus", "di0", "di1";
937 resets = <&src 2>;
938 };
939 };
940 };