arch/arm/mach-ux500/cpu.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010
   3  *
   4  * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
   5  * License terms: GNU General Public License (GPL) version 2
   6  */
   7
   8 #include <linux/platform_device.h>
   9 #include <linux/io.h>
  10 #include <linux/clk.h>
  11 #include <linux/mfd/db8500-prcmu.h>
  12 #include <linux/mfd/db5500-prcmu.h>
  13 #include <linux/clksrc-dbx500-prcmu.h>
  14
  15 #include <asm/cacheflush.h>
  16 #include <asm/hardware/cache-l2x0.h>
  17 #include <asm/hardware/gic.h>
  18 #include <asm/mach/map.h>
  19 #include <asm/localtimer.h>
  20
  21 #include <plat/mtu.h>
  22 #include <mach/hardware.h>
  23 #include <mach/setup.h>
  24 #include <mach/devices.h>
  25
  26 #include "clock.h"
  27
  28 void __iomem *_PRCMU_BASE;
  29
  30 #ifdef CONFIG_CACHE_L2X0
  31 static void __iomem *l2x0_base;
  32 #endif
  33
  34 void __init ux500_init_irq(void)
  35 {
  36         void __iomem *dist_base;
  37         void __iomem *cpu_base;
  38
  39         if (cpu_is_u5500()) {
  40                 dist_base = __io_address(U5500_GIC_DIST_BASE);
  41                 cpu_base = __io_address(U5500_GIC_CPU_BASE);
  42         } else if (cpu_is_u8500()) {
  43                 dist_base = __io_address(U8500_GIC_DIST_BASE);
  44                 cpu_base = __io_address(U8500_GIC_CPU_BASE);
  45         } else
  46                 ux500_unknown_soc();
  47
  48         gic_init(0, 29, dist_base, cpu_base);
  49
  50         /*
  51          * Init clocks here so that they are available for system timer
  52          * initialization.
  53          */
  54         if (cpu_is_u5500())
  55                 db5500_prcmu_early_init();
  56         if (cpu_is_u8500())
  57                 prcmu_early_init();
  58         clk_init();
  59 }
  60
  61 #ifdef CONFIG_CACHE_L2X0
  62 static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
  63 {
  64         /* wait for the operation to complete */
  65         while (readl_relaxed(reg) & mask)
  66                 ;
  67 }
  68
  69 static inline void ux500_cache_sync(void)
  70 {
  71         void __iomem *base = l2x0_base;
  72
  73         writel_relaxed(0, base + L2X0_CACHE_SYNC);
  74         ux500_cache_wait(base + L2X0_CACHE_SYNC, 1);
  75 }
  76
  77 /*
  78  * The L2 cache cannot be turned off in the non-secure world.
  79  * Dummy until a secure service is in place.
  80  */
  81 static void ux500_l2x0_disable(void)
  82 {
  83 }
  84
  85 /*
  86  * This is only called when doing a kexec, just after turning off the L2
  87  * and L1 cache, and it is surrounded by a spinlock in the generic version.
  88  * However, we're not really turning off the L2 cache right now and the
  89  * PL310 does not support exclusive accesses (used to implement the spinlock).
  90  * So, the invalidation needs to be done without the spinlock.
  91  */
  92 static void ux500_l2x0_inv_all(void)
  93 {
  94         void __iomem *base = l2x0_base;
  95         uint32_t l2x0_way_mask = (1<<16) - 1;   /* Bitmask of active ways */
  96
  97         /* invalidate all ways */
  98         writel_relaxed(l2x0_way_mask, base + L2X0_INV_WAY);
  99         ux500_cache_wait(base + L2X0_INV_WAY, l2x0_way_mask);
 100         ux500_cache_sync();
 101 }
 102
 103 static int ux500_l2x0_init(void)
 104 {
 105         if (cpu_is_u5500())
 106                 l2x0_base = __io_address(U5500_L2CC_BASE);
 107         else if (cpu_is_u8500())
 108                 l2x0_base = __io_address(U8500_L2CC_BASE);
 109         else
 110                 ux500_unknown_soc();
 111
 112         /* 64KB way size, 8 way associativity, force WA */
 113         l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
 114
 115         /* Override invalidate function */
 116         outer_cache.disable = ux500_l2x0_disable;
 117         outer_cache.inv_all = ux500_l2x0_inv_all;
 118
 119         return 0;
 120 }
 121 early_initcall(ux500_l2x0_init);
 122 #endif
 123
 124 static void __init ux500_timer_init(void)
 125 {
 126 #ifdef CONFIG_LOCAL_TIMERS
 127         /* Setup the local timer base */
 128         if (cpu_is_u5500())
 129                 twd_base = __io_address(U5500_TWD_BASE);
 130         else if (cpu_is_u8500())
 131                 twd_base = __io_address(U8500_TWD_BASE);
 132         else
 133                 ux500_unknown_soc();
 134 #endif
 135         if (cpu_is_u5500())
 136                 mtu_base = __io_address(U5500_MTU0_BASE);
 137         else if (cpu_is_u8500ed())
 138                 mtu_base = __io_address(U8500_MTU0_BASE_ED);
 139         else if (cpu_is_u8500())
 140                 mtu_base = __io_address(U8500_MTU0_BASE);
 141         else
 142                 ux500_unknown_soc();
 143
 144         if (cpu_is_u8500())
 145                 clksrc_dbx500_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
 146         else if (cpu_is_u5500())
 147                 clksrc_dbx500_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE);
 148         else
 149                 ux500_unknown_soc();
 150
 151         nmdk_timer_init();
 152         clksrc_dbx500_prcmu_init();
 153 }
 154
 155 struct sys_timer ux500_timer = {
 156         .init   = ux500_timer_init,
 157 };