2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 #include <linux/clockchips.h>
10 #include <linux/cpu.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/notifier.h>
14 #include <linux/of_irq.h>
15 #include <linux/percpu.h>
16 #include <linux/smp.h>
17 #include <linux/time.h>
18 #include <asm/mips-cps.h>
20 static DEFINE_PER_CPU(struct clock_event_device
, gic_clockevent_device
);
21 static int gic_timer_irq
;
22 static unsigned int gic_frequency
;
24 static u64 notrace
gic_read_count(void)
26 unsigned int hi
, hi2
, lo
;
29 return read_gic_counter();
32 hi
= read_gic_counter_32h();
33 lo
= read_gic_counter_32l();
34 hi2
= read_gic_counter_32h();
37 return (((u64
) hi
) << 32) + lo
;
40 static int gic_next_event(unsigned long delta
, struct clock_event_device
*evt
)
46 cnt
= gic_read_count();
48 local_irq_save(flags
);
49 write_gic_vl_other(mips_cm_vp_id(cpumask_first(evt
->cpumask
)));
50 write_gic_vo_compare(cnt
);
51 local_irq_restore(flags
);
52 res
= ((int)(gic_read_count() - cnt
) >= 0) ? -ETIME
: 0;
56 static irqreturn_t
gic_compare_interrupt(int irq
, void *dev_id
)
58 struct clock_event_device
*cd
= dev_id
;
60 write_gic_vl_compare(read_gic_vl_compare());
61 cd
->event_handler(cd
);
65 struct irqaction gic_compare_irqaction
= {
66 .handler
= gic_compare_interrupt
,
67 .percpu_dev_id
= &gic_clockevent_device
,
68 .flags
= IRQF_PERCPU
| IRQF_TIMER
,
72 static void gic_clockevent_cpu_init(unsigned int cpu
,
73 struct clock_event_device
*cd
)
75 cd
->name
= "MIPS GIC";
76 cd
->features
= CLOCK_EVT_FEAT_ONESHOT
|
77 CLOCK_EVT_FEAT_C3STOP
;
80 cd
->irq
= gic_timer_irq
;
81 cd
->cpumask
= cpumask_of(cpu
);
82 cd
->set_next_event
= gic_next_event
;
84 clockevents_config_and_register(cd
, gic_frequency
, 0x300, 0x7fffffff);
86 enable_percpu_irq(gic_timer_irq
, IRQ_TYPE_NONE
);
89 static void gic_clockevent_cpu_exit(struct clock_event_device
*cd
)
91 disable_percpu_irq(gic_timer_irq
);
94 static void gic_update_frequency(void *data
)
96 unsigned long rate
= (unsigned long)data
;
98 clockevents_update_freq(this_cpu_ptr(&gic_clockevent_device
), rate
);
101 static int gic_starting_cpu(unsigned int cpu
)
103 gic_clockevent_cpu_init(cpu
, this_cpu_ptr(&gic_clockevent_device
));
107 static int gic_clk_notifier(struct notifier_block
*nb
, unsigned long action
,
110 struct clk_notifier_data
*cnd
= data
;
112 if (action
== POST_RATE_CHANGE
)
113 on_each_cpu(gic_update_frequency
, (void *)cnd
->new_rate
, 1);
118 static int gic_dying_cpu(unsigned int cpu
)
120 gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device
));
124 static struct notifier_block gic_clk_nb
= {
125 .notifier_call
= gic_clk_notifier
,
128 static int gic_clockevent_init(void)
135 ret
= setup_percpu_irq(gic_timer_irq
, &gic_compare_irqaction
);
137 pr_err("GIC timer IRQ %d setup failed: %d\n",
142 cpuhp_setup_state(CPUHP_AP_MIPS_GIC_TIMER_STARTING
,
143 "clockevents/mips/gic/timer:starting",
144 gic_starting_cpu
, gic_dying_cpu
);
148 static u64
gic_hpt_read(struct clocksource
*cs
)
150 return gic_read_count();
153 static struct clocksource gic_clocksource
= {
155 .read
= gic_hpt_read
,
156 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
157 .archdata
= { .vdso_clock_mode
= VDSO_CLOCK_GIC
},
160 static int __init
__gic_clocksource_init(void)
162 unsigned int count_width
;
165 /* Set clocksource mask. */
166 count_width
= read_gic_config() & GIC_CONFIG_COUNTBITS
;
167 count_width
>>= __fls(GIC_CONFIG_COUNTBITS
);
170 gic_clocksource
.mask
= CLOCKSOURCE_MASK(count_width
);
172 /* Calculate a somewhat reasonable rating value. */
173 gic_clocksource
.rating
= 200 + gic_frequency
/ 10000000;
175 ret
= clocksource_register_hz(&gic_clocksource
, gic_frequency
);
177 pr_warn("GIC: Unable to register clocksource\n");
182 static int __init
gic_clocksource_of_init(struct device_node
*node
)
187 if (!mips_gic_present() || !node
->parent
||
188 !of_device_is_compatible(node
->parent
, "mti,gic")) {
189 pr_warn("No DT definition for the mips gic driver\n");
193 clk
= of_clk_get(node
, 0);
195 ret
= clk_prepare_enable(clk
);
197 pr_err("GIC failed to enable clock\n");
202 gic_frequency
= clk_get_rate(clk
);
203 } else if (of_property_read_u32(node
, "clock-frequency",
205 pr_err("GIC frequency not specified.\n");
208 gic_timer_irq
= irq_of_parse_and_map(node
, 0);
209 if (!gic_timer_irq
) {
210 pr_err("GIC timer IRQ not specified.\n");
214 ret
= __gic_clocksource_init();
218 ret
= gic_clockevent_init();
219 if (!ret
&& !IS_ERR(clk
)) {
220 if (clk_notifier_register(clk
, &gic_clk_nb
) < 0)
221 pr_warn("GIC: Unable to register clock notifier\n");
224 /* And finally start the counter */
225 clear_gic_config(GIC_CONFIG_COUNTSTOP
);
229 TIMER_OF_DECLARE(mips_gic_timer
, "mti,gic-timer",
230 gic_clocksource_of_init
);