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net: add rtnl_dereference()
[linux-2.6/btrfs-unstable.git] / drivers / serial / mpc52xx_uart.c
blob8dedb266f143f1cf801d84f34892a999b2dc9934
1 /*
2 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
3 *
4 * FIXME According to the usermanual the status bits in the status register
5 * are only updated when the peripherals access the FIFO and not when the
6 * CPU access them. So since we use this bits to know when we stop writing
7 * and reading, they may not be updated in-time and a race condition may
8 * exists. But I haven't be able to prove this and I don't care. But if
9 * any problem arises, it might worth checking. The TX/RX FIFO Stats
10 * registers should be used in addition.
11 * Update: Actually, they seem updated ... At least the bits we use.
12 *
13 *
14 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
15 *
16 * Some of the code has been inspired/copied from the 2.4 code written
17 * by Dale Farnsworth <dfarnsworth@mvista.com>.
18 *
19 * Copyright (C) 2008 Freescale Semiconductor Inc.
20 * John Rigby <jrigby@gmail.com>
21 * Added support for MPC5121
22 * Copyright (C) 2006 Secret Lab Technologies Ltd.
23 * Grant Likely <grant.likely@secretlab.ca>
24 * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com>
25 * Copyright (C) 2003 MontaVista, Software, Inc.
26 *
27 * This file is licensed under the terms of the GNU General Public License
28 * version 2. This program is licensed "as is" without any warranty of any
29 * kind, whether express or implied.
30 */
31
32 #undef DEBUG
33
34 #include <linux/device.h>
35 #include <linux/module.h>
36 #include <linux/tty.h>
37 #include <linux/serial.h>
38 #include <linux/sysrq.h>
39 #include <linux/console.h>
40 #include <linux/delay.h>
41 #include <linux/io.h>
42 #include <linux/of.h>
43 #include <linux/of_platform.h>
44 #include <linux/clk.h>
45
46 #include <asm/mpc52xx.h>
47 #include <asm/mpc52xx_psc.h>
48
49 #if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
50 #define SUPPORT_SYSRQ
51 #endif
52
53 #include <linux/serial_core.h>
54
55
56 /* We've been assigned a range on the "Low-density serial ports" major */
57 #define SERIAL_PSC_MAJOR 204
58 #define SERIAL_PSC_MINOR 148
59
60
61 #define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */
62
63
64 static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM];
65 /* Rem: - We use the read_status_mask as a shadow of
66 * psc->mpc52xx_psc_imr
67 * - It's important that is array is all zero on start as we
68 * use it to know if it's initialized or not ! If it's not sure
69 * it's cleared, then a memset(...,0,...) should be added to
70 * the console_init
71 */
72
73 /* lookup table for matching device nodes to index numbers */
74 static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM];
75
76 static void mpc52xx_uart_of_enumerate(void);
77
78
79 #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
80
81
82 /* Forward declaration of the interruption handling routine */
83 static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id);
84 static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port);
85
86
87 /* Simple macro to test if a port is console or not. This one is taken
88 * for serial_core.c and maybe should be moved to serial_core.h ? */
89 #ifdef CONFIG_SERIAL_CORE_CONSOLE
90 #define uart_console(port) \
91 ((port)->cons && (port)->cons->index == (port)->line)
92 #else
93 #define uart_console(port) (0)
94 #endif
95
96 /* ======================================================================== */
97 /* PSC fifo operations for isolating differences between 52xx and 512x */
98 /* ======================================================================== */
99
100 struct psc_ops {
101 void (*fifo_init)(struct uart_port *port);
102 int (*raw_rx_rdy)(struct uart_port *port);
103 int (*raw_tx_rdy)(struct uart_port *port);
104 int (*rx_rdy)(struct uart_port *port);
105 int (*tx_rdy)(struct uart_port *port);
106 int (*tx_empty)(struct uart_port *port);
107 void (*stop_rx)(struct uart_port *port);
108 void (*start_tx)(struct uart_port *port);
109 void (*stop_tx)(struct uart_port *port);
110 void (*rx_clr_irq)(struct uart_port *port);
111 void (*tx_clr_irq)(struct uart_port *port);
112 void (*write_char)(struct uart_port *port, unsigned char c);
113 unsigned char (*read_char)(struct uart_port *port);
114 void (*cw_disable_ints)(struct uart_port *port);
115 void (*cw_restore_ints)(struct uart_port *port);
116 unsigned int (*set_baudrate)(struct uart_port *port,
117 struct ktermios *new,
118 struct ktermios *old);
119 int (*clock)(struct uart_port *port, int enable);
120 int (*fifoc_init)(void);
121 void (*fifoc_uninit)(void);
122 void (*get_irq)(struct uart_port *, struct device_node *);
123 irqreturn_t (*handle_irq)(struct uart_port *port);
124 };
125
126 /* setting the prescaler and divisor reg is common for all chips */
127 static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc,
128 u16 prescaler, unsigned int divisor)
129 {
130 /* select prescaler */
131 out_be16(&psc->mpc52xx_psc_clock_select, prescaler);
132 out_8(&psc->ctur, divisor >> 8);
133 out_8(&psc->ctlr, divisor & 0xff);
134 }
135
136 #ifdef CONFIG_PPC_MPC52xx
137 #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
138 static void mpc52xx_psc_fifo_init(struct uart_port *port)
139 {
140 struct mpc52xx_psc __iomem *psc = PSC(port);
141 struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port);
142
143 out_8(&fifo->rfcntl, 0x00);
144 out_be16(&fifo->rfalarm, 0x1ff);
145 out_8(&fifo->tfcntl, 0x07);
146 out_be16(&fifo->tfalarm, 0x80);
147
148 port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY;
149 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
150 }
151
152 static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port)
153 {
154 return in_be16(&PSC(port)->mpc52xx_psc_status)
155 & MPC52xx_PSC_SR_RXRDY;
156 }
157
158 static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port)
159 {
160 return in_be16(&PSC(port)->mpc52xx_psc_status)
161 & MPC52xx_PSC_SR_TXRDY;
162 }
163
164
165 static int mpc52xx_psc_rx_rdy(struct uart_port *port)
166 {
167 return in_be16(&PSC(port)->mpc52xx_psc_isr)
168 & port->read_status_mask
169 & MPC52xx_PSC_IMR_RXRDY;
170 }
171
172 static int mpc52xx_psc_tx_rdy(struct uart_port *port)
173 {
174 return in_be16(&PSC(port)->mpc52xx_psc_isr)
175 & port->read_status_mask
176 & MPC52xx_PSC_IMR_TXRDY;
177 }
178
179 static int mpc52xx_psc_tx_empty(struct uart_port *port)
180 {
181 return in_be16(&PSC(port)->mpc52xx_psc_status)
182 & MPC52xx_PSC_SR_TXEMP;
183 }
184
185 static void mpc52xx_psc_start_tx(struct uart_port *port)
186 {
187 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
188 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
189 }
190
191 static void mpc52xx_psc_stop_tx(struct uart_port *port)
192 {
193 port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY;
194 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
195 }
196
197 static void mpc52xx_psc_stop_rx(struct uart_port *port)
198 {
199 port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY;
200 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
201 }
202
203 static void mpc52xx_psc_rx_clr_irq(struct uart_port *port)
204 {
205 }
206
207 static void mpc52xx_psc_tx_clr_irq(struct uart_port *port)
208 {
209 }
210
211 static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c)
212 {
213 out_8(&PSC(port)->mpc52xx_psc_buffer_8, c);
214 }
215
216 static unsigned char mpc52xx_psc_read_char(struct uart_port *port)
217 {
218 return in_8(&PSC(port)->mpc52xx_psc_buffer_8);
219 }
220
221 static void mpc52xx_psc_cw_disable_ints(struct uart_port *port)
222 {
223 out_be16(&PSC(port)->mpc52xx_psc_imr, 0);
224 }
225
226 static void mpc52xx_psc_cw_restore_ints(struct uart_port *port)
227 {
228 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
229 }
230
231 static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port,
232 struct ktermios *new,
233 struct ktermios *old)
234 {
235 unsigned int baud;
236 unsigned int divisor;
237
238 /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */
239 baud = uart_get_baud_rate(port, new, old,
240 port->uartclk / (32 * 0xffff) + 1,
241 port->uartclk / 32);
242 divisor = (port->uartclk + 16 * baud) / (32 * baud);
243
244 /* enable the /32 prescaler and set the divisor */
245 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
246 return baud;
247 }
248
249 static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port,
250 struct ktermios *new,
251 struct ktermios *old)
252 {
253 unsigned int baud;
254 unsigned int divisor;
255 u16 prescaler;
256
257 /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the
258 * ipb freq */
259 baud = uart_get_baud_rate(port, new, old,
260 port->uartclk / (32 * 0xffff) + 1,
261 port->uartclk / 4);
262 divisor = (port->uartclk + 2 * baud) / (4 * baud);
263
264 /* select the proper prescaler and set the divisor */
265 if (divisor > 0xffff) {
266 divisor = (divisor + 4) / 8;
267 prescaler = 0xdd00; /* /32 */
268 } else
269 prescaler = 0xff00; /* /4 */
270 mpc52xx_set_divisor(PSC(port), prescaler, divisor);
271 return baud;
272 }
273
274 static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np)
275 {
276 port->irqflags = IRQF_DISABLED;
277 port->irq = irq_of_parse_and_map(np, 0);
278 }
279
280 /* 52xx specific interrupt handler. The caller holds the port lock */
281 static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port)
282 {
283 return mpc5xxx_uart_process_int(port);
284 }
285
286 static struct psc_ops mpc52xx_psc_ops = {
287 .fifo_init = mpc52xx_psc_fifo_init,
288 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
289 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
290 .rx_rdy = mpc52xx_psc_rx_rdy,
291 .tx_rdy = mpc52xx_psc_tx_rdy,
292 .tx_empty = mpc52xx_psc_tx_empty,
293 .stop_rx = mpc52xx_psc_stop_rx,
294 .start_tx = mpc52xx_psc_start_tx,
295 .stop_tx = mpc52xx_psc_stop_tx,
296 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
297 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
298 .write_char = mpc52xx_psc_write_char,
299 .read_char = mpc52xx_psc_read_char,
300 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
301 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
302 .set_baudrate = mpc5200_psc_set_baudrate,
303 .get_irq = mpc52xx_psc_get_irq,
304 .handle_irq = mpc52xx_psc_handle_irq,
305 };
306
307 static struct psc_ops mpc5200b_psc_ops = {
308 .fifo_init = mpc52xx_psc_fifo_init,
309 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
310 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
311 .rx_rdy = mpc52xx_psc_rx_rdy,
312 .tx_rdy = mpc52xx_psc_tx_rdy,
313 .tx_empty = mpc52xx_psc_tx_empty,
314 .stop_rx = mpc52xx_psc_stop_rx,
315 .start_tx = mpc52xx_psc_start_tx,
316 .stop_tx = mpc52xx_psc_stop_tx,
317 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
318 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
319 .write_char = mpc52xx_psc_write_char,
320 .read_char = mpc52xx_psc_read_char,
321 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
322 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
323 .set_baudrate = mpc5200b_psc_set_baudrate,
324 .get_irq = mpc52xx_psc_get_irq,
325 .handle_irq = mpc52xx_psc_handle_irq,
326 };
327
328 #endif /* CONFIG_MPC52xx */
329
330 #ifdef CONFIG_PPC_MPC512x
331 #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))
332
333 /* PSC FIFO Controller for mpc512x */
334 struct psc_fifoc {
335 u32 fifoc_cmd;
336 u32 fifoc_int;
337 u32 fifoc_dma;
338 u32 fifoc_axe;
339 u32 fifoc_debug;
340 };
341
342 static struct psc_fifoc __iomem *psc_fifoc;
343 static unsigned int psc_fifoc_irq;
344
345 static void mpc512x_psc_fifo_init(struct uart_port *port)
346 {
347 /* /32 prescaler */
348 out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00);
349
350 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
351 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
352 out_be32(&FIFO_512x(port)->txalarm, 1);
353 out_be32(&FIFO_512x(port)->tximr, 0);
354
355 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
356 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
357 out_be32(&FIFO_512x(port)->rxalarm, 1);
358 out_be32(&FIFO_512x(port)->rximr, 0);
359
360 out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);
361 out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);
362 }
363
364 static int mpc512x_psc_raw_rx_rdy(struct uart_port *port)
365 {
366 return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
367 }
368
369 static int mpc512x_psc_raw_tx_rdy(struct uart_port *port)
370 {
371 return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL);
372 }
373
374 static int mpc512x_psc_rx_rdy(struct uart_port *port)
375 {
376 return in_be32(&FIFO_512x(port)->rxsr)
377 & in_be32(&FIFO_512x(port)->rximr)
378 & MPC512x_PSC_FIFO_ALARM;
379 }
380
381 static int mpc512x_psc_tx_rdy(struct uart_port *port)
382 {
383 return in_be32(&FIFO_512x(port)->txsr)
384 & in_be32(&FIFO_512x(port)->tximr)
385 & MPC512x_PSC_FIFO_ALARM;
386 }
387
388 static int mpc512x_psc_tx_empty(struct uart_port *port)
389 {
390 return in_be32(&FIFO_512x(port)->txsr)
391 & MPC512x_PSC_FIFO_EMPTY;
392 }
393
394 static void mpc512x_psc_stop_rx(struct uart_port *port)
395 {
396 unsigned long rx_fifo_imr;
397
398 rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr);
399 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
400 out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);
401 }
402
403 static void mpc512x_psc_start_tx(struct uart_port *port)
404 {
405 unsigned long tx_fifo_imr;
406
407 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
408 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
409 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
410 }
411
412 static void mpc512x_psc_stop_tx(struct uart_port *port)
413 {
414 unsigned long tx_fifo_imr;
415
416 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
417 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
418 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
419 }
420
421 static void mpc512x_psc_rx_clr_irq(struct uart_port *port)
422 {
423 out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));
424 }
425
426 static void mpc512x_psc_tx_clr_irq(struct uart_port *port)
427 {
428 out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));
429 }
430
431 static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c)
432 {
433 out_8(&FIFO_512x(port)->txdata_8, c);
434 }
435
436 static unsigned char mpc512x_psc_read_char(struct uart_port *port)
437 {
438 return in_8(&FIFO_512x(port)->rxdata_8);
439 }
440
441 static void mpc512x_psc_cw_disable_ints(struct uart_port *port)
442 {
443 port->read_status_mask =
444 in_be32(&FIFO_512x(port)->tximr) << 16 |
445 in_be32(&FIFO_512x(port)->rximr);
446 out_be32(&FIFO_512x(port)->tximr, 0);
447 out_be32(&FIFO_512x(port)->rximr, 0);
448 }
449
450 static void mpc512x_psc_cw_restore_ints(struct uart_port *port)
451 {
452 out_be32(&FIFO_512x(port)->tximr,
453 (port->read_status_mask >> 16) & 0x7f);
454 out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);
455 }
456
457 static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port,
458 struct ktermios *new,
459 struct ktermios *old)
460 {
461 unsigned int baud;
462 unsigned int divisor;
463
464 /*
465 * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on
466 * pg. 30-10 that the chip supports a /32 and a /10 prescaler.
467 * Furthermore, it states that "After reset, the prescaler by 10
468 * for the UART mode is selected", but the reset register value is
469 * 0x0000 which means a /32 prescaler. This is wrong.
470 *
471 * In reality using /32 prescaler doesn't work, as it is not supported!
472 * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide",
473 * Chapter 4.1 PSC in UART Mode.
474 * Calculate with a /16 prescaler here.
475 */
476
477 /* uartclk contains the ips freq */
478 baud = uart_get_baud_rate(port, new, old,
479 port->uartclk / (16 * 0xffff) + 1,
480 port->uartclk / 16);
481 divisor = (port->uartclk + 8 * baud) / (16 * baud);
482
483 /* enable the /16 prescaler and set the divisor */
484 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
485 return baud;
486 }
487
488 /* Init PSC FIFO Controller */
489 static int __init mpc512x_psc_fifoc_init(void)
490 {
491 struct device_node *np;
492
493 np = of_find_compatible_node(NULL, NULL,
494 "fsl,mpc5121-psc-fifo");
495 if (!np) {
496 pr_err("%s: Can't find FIFOC node\n", __func__);
497 return -ENODEV;
498 }
499
500 psc_fifoc = of_iomap(np, 0);
501 if (!psc_fifoc) {
502 pr_err("%s: Can't map FIFOC\n", __func__);
503 return -ENODEV;
504 }
505
506 psc_fifoc_irq = irq_of_parse_and_map(np, 0);
507 of_node_put(np);
508 if (psc_fifoc_irq == NO_IRQ) {
509 pr_err("%s: Can't get FIFOC irq\n", __func__);
510 iounmap(psc_fifoc);
511 return -ENODEV;
512 }
513
514 return 0;
515 }
516
517 static void __exit mpc512x_psc_fifoc_uninit(void)
518 {
519 iounmap(psc_fifoc);
520 }
521
522 /* 512x specific interrupt handler. The caller holds the port lock */
523 static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
524 {
525 unsigned long fifoc_int;
526 int psc_num;
527
528 /* Read pending PSC FIFOC interrupts */
529 fifoc_int = in_be32(&psc_fifoc->fifoc_int);
530
531 /* Check if it is an interrupt for this port */
532 psc_num = (port->mapbase & 0xf00) >> 8;
533 if (test_bit(psc_num, &fifoc_int) ||
534 test_bit(psc_num + 16, &fifoc_int))
535 return mpc5xxx_uart_process_int(port);
536
537 return IRQ_NONE;
538 }
539
540 static int mpc512x_psc_clock(struct uart_port *port, int enable)
541 {
542 struct clk *psc_clk;
543 int psc_num;
544 char clk_name[10];
545
546 if (uart_console(port))
547 return 0;
548
549 psc_num = (port->mapbase & 0xf00) >> 8;
550 snprintf(clk_name, sizeof(clk_name), "psc%d_clk", psc_num);
551 psc_clk = clk_get(port->dev, clk_name);
552 if (IS_ERR(psc_clk)) {
553 dev_err(port->dev, "Failed to get PSC clock entry!\n");
554 return -ENODEV;
555 }
556
557 dev_dbg(port->dev, "%s %sable\n", clk_name, enable ? "en" : "dis");
558
559 if (enable)
560 clk_enable(psc_clk);
561 else
562 clk_disable(psc_clk);
563
564 return 0;
565 }
566
567 static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np)
568 {
569 port->irqflags = IRQF_SHARED;
570 port->irq = psc_fifoc_irq;
571 }
572
573 static struct psc_ops mpc512x_psc_ops = {
574 .fifo_init = mpc512x_psc_fifo_init,
575 .raw_rx_rdy = mpc512x_psc_raw_rx_rdy,
576 .raw_tx_rdy = mpc512x_psc_raw_tx_rdy,
577 .rx_rdy = mpc512x_psc_rx_rdy,
578 .tx_rdy = mpc512x_psc_tx_rdy,
579 .tx_empty = mpc512x_psc_tx_empty,
580 .stop_rx = mpc512x_psc_stop_rx,
581 .start_tx = mpc512x_psc_start_tx,
582 .stop_tx = mpc512x_psc_stop_tx,
583 .rx_clr_irq = mpc512x_psc_rx_clr_irq,
584 .tx_clr_irq = mpc512x_psc_tx_clr_irq,
585 .write_char = mpc512x_psc_write_char,
586 .read_char = mpc512x_psc_read_char,
587 .cw_disable_ints = mpc512x_psc_cw_disable_ints,
588 .cw_restore_ints = mpc512x_psc_cw_restore_ints,
589 .set_baudrate = mpc512x_psc_set_baudrate,
590 .clock = mpc512x_psc_clock,
591 .fifoc_init = mpc512x_psc_fifoc_init,
592 .fifoc_uninit = mpc512x_psc_fifoc_uninit,
593 .get_irq = mpc512x_psc_get_irq,
594 .handle_irq = mpc512x_psc_handle_irq,
595 };
596 #endif
597
598 static struct psc_ops *psc_ops;
599
600 /* ======================================================================== */
601 /* UART operations */
602 /* ======================================================================== */
603
604 static unsigned int
605 mpc52xx_uart_tx_empty(struct uart_port *port)
606 {
607 return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0;
608 }
609
610 static void
611 mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
612 {
613 if (mctrl & TIOCM_RTS)
614 out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);
615 else
616 out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);
617 }
618
619 static unsigned int
620 mpc52xx_uart_get_mctrl(struct uart_port *port)
621 {
622 unsigned int ret = TIOCM_DSR;
623 u8 status = in_8(&PSC(port)->mpc52xx_psc_ipcr);
624
625 if (!(status & MPC52xx_PSC_CTS))
626 ret |= TIOCM_CTS;
627 if (!(status & MPC52xx_PSC_DCD))
628 ret |= TIOCM_CAR;
629
630 return ret;
631 }
632
633 static void
634 mpc52xx_uart_stop_tx(struct uart_port *port)
635 {
636 /* port->lock taken by caller */
637 psc_ops->stop_tx(port);
638 }
639
640 static void
641 mpc52xx_uart_start_tx(struct uart_port *port)
642 {
643 /* port->lock taken by caller */
644 psc_ops->start_tx(port);
645 }
646
647 static void
648 mpc52xx_uart_send_xchar(struct uart_port *port, char ch)
649 {
650 unsigned long flags;
651 spin_lock_irqsave(&port->lock, flags);
652
653 port->x_char = ch;
654 if (ch) {
655 /* Make sure tx interrupts are on */
656 /* Truly necessary ??? They should be anyway */
657 psc_ops->start_tx(port);
658 }
659
660 spin_unlock_irqrestore(&port->lock, flags);
661 }
662
663 static void
664 mpc52xx_uart_stop_rx(struct uart_port *port)
665 {
666 /* port->lock taken by caller */
667 psc_ops->stop_rx(port);
668 }
669
670 static void
671 mpc52xx_uart_enable_ms(struct uart_port *port)
672 {
673 struct mpc52xx_psc __iomem *psc = PSC(port);
674
675 /* clear D_*-bits by reading them */
676 in_8(&psc->mpc52xx_psc_ipcr);
677 /* enable CTS and DCD as IPC interrupts */
678 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
679
680 port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
681 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
682 }
683
684 static void
685 mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
686 {
687 unsigned long flags;
688 spin_lock_irqsave(&port->lock, flags);
689
690 if (ctl == -1)
691 out_8(&PSC(port)->command, MPC52xx_PSC_START_BRK);
692 else
693 out_8(&PSC(port)->command, MPC52xx_PSC_STOP_BRK);
694
695 spin_unlock_irqrestore(&port->lock, flags);
696 }
697
698 static int
699 mpc52xx_uart_startup(struct uart_port *port)
700 {
701 struct mpc52xx_psc __iomem *psc = PSC(port);
702 int ret;
703
704 if (psc_ops->clock) {
705 ret = psc_ops->clock(port, 1);
706 if (ret)
707 return ret;
708 }
709
710 /* Request IRQ */
711 ret = request_irq(port->irq, mpc52xx_uart_int,
712 port->irqflags, "mpc52xx_psc_uart", port);
713 if (ret)
714 return ret;
715
716 /* Reset/activate the port, clear and enable interrupts */
717 out_8(&psc->command, MPC52xx_PSC_RST_RX);
718 out_8(&psc->command, MPC52xx_PSC_RST_TX);
719
720 out_be32(&psc->sicr, 0); /* UART mode DCD ignored */
721
722 psc_ops->fifo_init(port);
723
724 out_8(&psc->command, MPC52xx_PSC_TX_ENABLE);
725 out_8(&psc->command, MPC52xx_PSC_RX_ENABLE);
726
727 return 0;
728 }
729
730 static void
731 mpc52xx_uart_shutdown(struct uart_port *port)
732 {
733 struct mpc52xx_psc __iomem *psc = PSC(port);
734
735 /* Shut down the port. Leave TX active if on a console port */
736 out_8(&psc->command, MPC52xx_PSC_RST_RX);
737 if (!uart_console(port))
738 out_8(&psc->command, MPC52xx_PSC_RST_TX);
739
740 port->read_status_mask = 0;
741 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
742
743 if (psc_ops->clock)
744 psc_ops->clock(port, 0);
745
746 /* Release interrupt */
747 free_irq(port->irq, port);
748 }
749
750 static void
751 mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
752 struct ktermios *old)
753 {
754 struct mpc52xx_psc __iomem *psc = PSC(port);
755 unsigned long flags;
756 unsigned char mr1, mr2;
757 unsigned int j;
758 unsigned int baud;
759
760 /* Prepare what we're gonna write */
761 mr1 = 0;
762
763 switch (new->c_cflag & CSIZE) {
764 case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS;
765 break;
766 case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS;
767 break;
768 case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS;
769 break;
770 case CS8:
771 default: mr1 |= MPC52xx_PSC_MODE_8_BITS;
772 }
773
774 if (new->c_cflag & PARENB) {
775 mr1 |= (new->c_cflag & PARODD) ?
776 MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN;
777 } else
778 mr1 |= MPC52xx_PSC_MODE_PARNONE;
779
780
781 mr2 = 0;
782
783 if (new->c_cflag & CSTOPB)
784 mr2 |= MPC52xx_PSC_MODE_TWO_STOP;
785 else
786 mr2 |= ((new->c_cflag & CSIZE) == CS5) ?
787 MPC52xx_PSC_MODE_ONE_STOP_5_BITS :
788 MPC52xx_PSC_MODE_ONE_STOP;
789
790 if (new->c_cflag & CRTSCTS) {
791 mr1 |= MPC52xx_PSC_MODE_RXRTS;
792 mr2 |= MPC52xx_PSC_MODE_TXCTS;
793 }
794
795 /* Get the lock */
796 spin_lock_irqsave(&port->lock, flags);
797
798 /* Do our best to flush TX & RX, so we don't lose anything */
799 /* But we don't wait indefinitely ! */
800 j = 5000000; /* Maximum wait */
801 /* FIXME Can't receive chars since set_termios might be called at early
802 * boot for the console, all stuff is not yet ready to receive at that
803 * time and that just makes the kernel oops */
804 /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */
805 while (!mpc52xx_uart_tx_empty(port) && --j)
806 udelay(1);
807
808 if (!j)
809 printk(KERN_ERR "mpc52xx_uart.c: "
810 "Unable to flush RX & TX fifos in-time in set_termios."
811 "Some chars may have been lost.\n");
812
813 /* Reset the TX & RX */
814 out_8(&psc->command, MPC52xx_PSC_RST_RX);
815 out_8(&psc->command, MPC52xx_PSC_RST_TX);
816
817 /* Send new mode settings */
818 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
819 out_8(&psc->mode, mr1);
820 out_8(&psc->mode, mr2);
821 baud = psc_ops->set_baudrate(port, new, old);
822
823 /* Update the per-port timeout */
824 uart_update_timeout(port, new->c_cflag, baud);
825
826 if (UART_ENABLE_MS(port, new->c_cflag))
827 mpc52xx_uart_enable_ms(port);
828
829 /* Reenable TX & RX */
830 out_8(&psc->command, MPC52xx_PSC_TX_ENABLE);
831 out_8(&psc->command, MPC52xx_PSC_RX_ENABLE);
832
833 /* We're all set, release the lock */
834 spin_unlock_irqrestore(&port->lock, flags);
835 }
836
837 static const char *
838 mpc52xx_uart_type(struct uart_port *port)
839 {
840 return port->type == PORT_MPC52xx ? "MPC52xx PSC" : NULL;
841 }
842
843 static void
844 mpc52xx_uart_release_port(struct uart_port *port)
845 {
846 /* remapped by us ? */
847 if (port->flags & UPF_IOREMAP) {
848 iounmap(port->membase);
849 port->membase = NULL;
850 }
851
852 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
853 }
854
855 static int
856 mpc52xx_uart_request_port(struct uart_port *port)
857 {
858 int err;
859
860 if (port->flags & UPF_IOREMAP) /* Need to remap ? */
861 port->membase = ioremap(port->mapbase,
862 sizeof(struct mpc52xx_psc));
863
864 if (!port->membase)
865 return -EINVAL;
866
867 err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc),
868 "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
869
870 if (err && (port->flags & UPF_IOREMAP)) {
871 iounmap(port->membase);
872 port->membase = NULL;
873 }
874
875 return err;
876 }
877
878 static void
879 mpc52xx_uart_config_port(struct uart_port *port, int flags)
880 {
881 if ((flags & UART_CONFIG_TYPE)
882 && (mpc52xx_uart_request_port(port) == 0))
883 port->type = PORT_MPC52xx;
884 }
885
886 static int
887 mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
888 {
889 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx)
890 return -EINVAL;
891
892 if ((ser->irq != port->irq) ||
893 (ser->io_type != UPIO_MEM) ||
894 (ser->baud_base != port->uartclk) ||
895 (ser->iomem_base != (void *)port->mapbase) ||
896 (ser->hub6 != 0))
897 return -EINVAL;
898
899 return 0;
900 }
901
902
903 static struct uart_ops mpc52xx_uart_ops = {
904 .tx_empty = mpc52xx_uart_tx_empty,
905 .set_mctrl = mpc52xx_uart_set_mctrl,
906 .get_mctrl = mpc52xx_uart_get_mctrl,
907 .stop_tx = mpc52xx_uart_stop_tx,
908 .start_tx = mpc52xx_uart_start_tx,
909 .send_xchar = mpc52xx_uart_send_xchar,
910 .stop_rx = mpc52xx_uart_stop_rx,
911 .enable_ms = mpc52xx_uart_enable_ms,
912 .break_ctl = mpc52xx_uart_break_ctl,
913 .startup = mpc52xx_uart_startup,
914 .shutdown = mpc52xx_uart_shutdown,
915 .set_termios = mpc52xx_uart_set_termios,
916 /* .pm = mpc52xx_uart_pm, Not supported yet */
917 /* .set_wake = mpc52xx_uart_set_wake, Not supported yet */
918 .type = mpc52xx_uart_type,
919 .release_port = mpc52xx_uart_release_port,
920 .request_port = mpc52xx_uart_request_port,
921 .config_port = mpc52xx_uart_config_port,
922 .verify_port = mpc52xx_uart_verify_port
923 };
924
925
926 /* ======================================================================== */
927 /* Interrupt handling */
928 /* ======================================================================== */
929
930 static inline int
931 mpc52xx_uart_int_rx_chars(struct uart_port *port)
932 {
933 struct tty_struct *tty = port->state->port.tty;
934 unsigned char ch, flag;
935 unsigned short status;
936
937 /* While we can read, do so ! */
938 while (psc_ops->raw_rx_rdy(port)) {
939 /* Get the char */
940 ch = psc_ops->read_char(port);
941
942 /* Handle sysreq char */
943 #ifdef SUPPORT_SYSRQ
944 if (uart_handle_sysrq_char(port, ch)) {
945 port->sysrq = 0;
946 continue;
947 }
948 #endif
949
950 /* Store it */
951
952 flag = TTY_NORMAL;
953 port->icount.rx++;
954
955 status = in_be16(&PSC(port)->mpc52xx_psc_status);
956
957 if (status & (MPC52xx_PSC_SR_PE |
958 MPC52xx_PSC_SR_FE |
959 MPC52xx_PSC_SR_RB)) {
960
961 if (status & MPC52xx_PSC_SR_RB) {
962 flag = TTY_BREAK;
963 uart_handle_break(port);
964 port->icount.brk++;
965 } else if (status & MPC52xx_PSC_SR_PE) {
966 flag = TTY_PARITY;
967 port->icount.parity++;
968 }
969 else if (status & MPC52xx_PSC_SR_FE) {
970 flag = TTY_FRAME;
971 port->icount.frame++;
972 }
973
974 /* Clear error condition */
975 out_8(&PSC(port)->command, MPC52xx_PSC_RST_ERR_STAT);
976
977 }
978 tty_insert_flip_char(tty, ch, flag);
979 if (status & MPC52xx_PSC_SR_OE) {
980 /*
981 * Overrun is special, since it's
982 * reported immediately, and doesn't
983 * affect the current character
984 */
985 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
986 port->icount.overrun++;
987 }
988 }
989
990 spin_unlock(&port->lock);
991 tty_flip_buffer_push(tty);
992 spin_lock(&port->lock);
993
994 return psc_ops->raw_rx_rdy(port);
995 }
996
997 static inline int
998 mpc52xx_uart_int_tx_chars(struct uart_port *port)
999 {
1000 struct circ_buf *xmit = &port->state->xmit;
1001
1002 /* Process out of band chars */
1003 if (port->x_char) {
1004 psc_ops->write_char(port, port->x_char);
1005 port->icount.tx++;
1006 port->x_char = 0;
1007 return 1;
1008 }
1009
1010 /* Nothing to do ? */
1011 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
1012 mpc52xx_uart_stop_tx(port);
1013 return 0;
1014 }
1015
1016 /* Send chars */
1017 while (psc_ops->raw_tx_rdy(port)) {
1018 psc_ops->write_char(port, xmit->buf[xmit->tail]);
1019 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1020 port->icount.tx++;
1021 if (uart_circ_empty(xmit))
1022 break;
1023 }
1024
1025 /* Wake up */
1026 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1027 uart_write_wakeup(port);
1028
1029 /* Maybe we're done after all */
1030 if (uart_circ_empty(xmit)) {
1031 mpc52xx_uart_stop_tx(port);
1032 return 0;
1033 }
1034
1035 return 1;
1036 }
1037
1038 static irqreturn_t
1039 mpc5xxx_uart_process_int(struct uart_port *port)
1040 {
1041 unsigned long pass = ISR_PASS_LIMIT;
1042 unsigned int keepgoing;
1043 u8 status;
1044
1045 /* While we have stuff to do, we continue */
1046 do {
1047 /* If we don't find anything to do, we stop */
1048 keepgoing = 0;
1049
1050 psc_ops->rx_clr_irq(port);
1051 if (psc_ops->rx_rdy(port))
1052 keepgoing |= mpc52xx_uart_int_rx_chars(port);
1053
1054 psc_ops->tx_clr_irq(port);
1055 if (psc_ops->tx_rdy(port))
1056 keepgoing |= mpc52xx_uart_int_tx_chars(port);
1057
1058 status = in_8(&PSC(port)->mpc52xx_psc_ipcr);
1059 if (status & MPC52xx_PSC_D_DCD)
1060 uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD));
1061
1062 if (status & MPC52xx_PSC_D_CTS)
1063 uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS));
1064
1065 /* Limit number of iteration */
1066 if (!(--pass))
1067 keepgoing = 0;
1068
1069 } while (keepgoing);
1070
1071 return IRQ_HANDLED;
1072 }
1073
1074 static irqreturn_t
1075 mpc52xx_uart_int(int irq, void *dev_id)
1076 {
1077 struct uart_port *port = dev_id;
1078 irqreturn_t ret;
1079
1080 spin_lock(&port->lock);
1081
1082 ret = psc_ops->handle_irq(port);
1083
1084 spin_unlock(&port->lock);
1085
1086 return ret;
1087 }
1088
1089 /* ======================================================================== */
1090 /* Console ( if applicable ) */
1091 /* ======================================================================== */
1092
1093 #ifdef CONFIG_SERIAL_MPC52xx_CONSOLE
1094
1095 static void __init
1096 mpc52xx_console_get_options(struct uart_port *port,
1097 int *baud, int *parity, int *bits, int *flow)
1098 {
1099 struct mpc52xx_psc __iomem *psc = PSC(port);
1100 unsigned char mr1;
1101
1102 pr_debug("mpc52xx_console_get_options(port=%p)\n", port);
1103
1104 /* Read the mode registers */
1105 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
1106 mr1 = in_8(&psc->mode);
1107
1108 /* CT{U,L}R are write-only ! */
1109 *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1110
1111 /* Parse them */
1112 switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) {
1113 case MPC52xx_PSC_MODE_5_BITS:
1114 *bits = 5;
1115 break;
1116 case MPC52xx_PSC_MODE_6_BITS:
1117 *bits = 6;
1118 break;
1119 case MPC52xx_PSC_MODE_7_BITS:
1120 *bits = 7;
1121 break;
1122 case MPC52xx_PSC_MODE_8_BITS:
1123 default:
1124 *bits = 8;
1125 }
1126
1127 if (mr1 & MPC52xx_PSC_MODE_PARNONE)
1128 *parity = 'n';
1129 else
1130 *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e';
1131 }
1132
1133 static void
1134 mpc52xx_console_write(struct console *co, const char *s, unsigned int count)
1135 {
1136 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1137 unsigned int i, j;
1138
1139 /* Disable interrupts */
1140 psc_ops->cw_disable_ints(port);
1141
1142 /* Wait the TX buffer to be empty */
1143 j = 5000000; /* Maximum wait */
1144 while (!mpc52xx_uart_tx_empty(port) && --j)
1145 udelay(1);
1146
1147 /* Write all the chars */
1148 for (i = 0; i < count; i++, s++) {
1149 /* Line return handling */
1150 if (*s == '\n')
1151 psc_ops->write_char(port, '\r');
1152
1153 /* Send the char */
1154 psc_ops->write_char(port, *s);
1155
1156 /* Wait the TX buffer to be empty */
1157 j = 20000; /* Maximum wait */
1158 while (!mpc52xx_uart_tx_empty(port) && --j)
1159 udelay(1);
1160 }
1161
1162 /* Restore interrupt state */
1163 psc_ops->cw_restore_ints(port);
1164 }
1165
1166
1167 static int __init
1168 mpc52xx_console_setup(struct console *co, char *options)
1169 {
1170 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1171 struct device_node *np = mpc52xx_uart_nodes[co->index];
1172 unsigned int uartclk;
1173 struct resource res;
1174 int ret;
1175
1176 int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1177 int bits = 8;
1178 int parity = 'n';
1179 int flow = 'n';
1180
1181 pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n",
1182 co, co->index, options);
1183
1184 if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) {
1185 pr_debug("PSC%x out of range\n", co->index);
1186 return -EINVAL;
1187 }
1188
1189 if (!np) {
1190 pr_debug("PSC%x not found in device tree\n", co->index);
1191 return -EINVAL;
1192 }
1193
1194 pr_debug("Console on ttyPSC%x is %s\n",
1195 co->index, mpc52xx_uart_nodes[co->index]->full_name);
1196
1197 /* Fetch register locations */
1198 ret = of_address_to_resource(np, 0, &res);
1199 if (ret) {
1200 pr_debug("Could not get resources for PSC%x\n", co->index);
1201 return ret;
1202 }
1203
1204 uartclk = mpc5xxx_get_bus_frequency(np);
1205 if (uartclk == 0) {
1206 pr_debug("Could not find uart clock frequency!\n");
1207 return -EINVAL;
1208 }
1209
1210 /* Basic port init. Needed since we use some uart_??? func before
1211 * real init for early access */
1212 spin_lock_init(&port->lock);
1213 port->uartclk = uartclk;
1214 port->ops = &mpc52xx_uart_ops;
1215 port->mapbase = res.start;
1216 port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc));
1217 port->irq = irq_of_parse_and_map(np, 0);
1218
1219 if (port->membase == NULL)
1220 return -EINVAL;
1221
1222 pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n",
1223 (void *)port->mapbase, port->membase,
1224 port->irq, port->uartclk);
1225
1226 /* Setup the port parameters accoding to options */
1227 if (options)
1228 uart_parse_options(options, &baud, &parity, &bits, &flow);
1229 else
1230 mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow);
1231
1232 pr_debug("Setting console parameters: %i %i%c1 flow=%c\n",
1233 baud, bits, parity, flow);
1234
1235 return uart_set_options(port, co, baud, parity, bits, flow);
1236 }
1237
1238
1239 static struct uart_driver mpc52xx_uart_driver;
1240
1241 static struct console mpc52xx_console = {
1242 .name = "ttyPSC",
1243 .write = mpc52xx_console_write,
1244 .device = uart_console_device,
1245 .setup = mpc52xx_console_setup,
1246 .flags = CON_PRINTBUFFER,
1247 .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */
1248 .data = &mpc52xx_uart_driver,
1249 };
1250
1251
1252 static int __init
1253 mpc52xx_console_init(void)
1254 {
1255 mpc52xx_uart_of_enumerate();
1256 register_console(&mpc52xx_console);
1257 return 0;
1258 }
1259
1260 console_initcall(mpc52xx_console_init);
1261
1262 #define MPC52xx_PSC_CONSOLE &mpc52xx_console
1263 #else
1264 #define MPC52xx_PSC_CONSOLE NULL
1265 #endif
1266
1267
1268 /* ======================================================================== */
1269 /* UART Driver */
1270 /* ======================================================================== */
1271
1272 static struct uart_driver mpc52xx_uart_driver = {
1273 .driver_name = "mpc52xx_psc_uart",
1274 .dev_name = "ttyPSC",
1275 .major = SERIAL_PSC_MAJOR,
1276 .minor = SERIAL_PSC_MINOR,
1277 .nr = MPC52xx_PSC_MAXNUM,
1278 .cons = MPC52xx_PSC_CONSOLE,
1279 };
1280
1281 /* ======================================================================== */
1282 /* OF Platform Driver */
1283 /* ======================================================================== */
1284
1285 static struct of_device_id mpc52xx_uart_of_match[] = {
1286 #ifdef CONFIG_PPC_MPC52xx
1287 { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, },
1288 { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1289 /* binding used by old lite5200 device trees: */
1290 { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1291 /* binding used by efika: */
1292 { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, },
1293 #endif
1294 #ifdef CONFIG_PPC_MPC512x
1295 { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, },
1296 #endif
1297 {},
1298 };
1299
1300 static int __devinit
1301 mpc52xx_uart_of_probe(struct platform_device *op, const struct of_device_id *match)
1302 {
1303 int idx = -1;
1304 unsigned int uartclk;
1305 struct uart_port *port = NULL;
1306 struct resource res;
1307 int ret;
1308
1309 dev_dbg(&op->dev, "mpc52xx_uart_probe(op=%p, match=%p)\n", op, match);
1310
1311 /* Check validity & presence */
1312 for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++)
1313 if (mpc52xx_uart_nodes[idx] == op->dev.of_node)
1314 break;
1315 if (idx >= MPC52xx_PSC_MAXNUM)
1316 return -EINVAL;
1317 pr_debug("Found %s assigned to ttyPSC%x\n",
1318 mpc52xx_uart_nodes[idx]->full_name, idx);
1319
1320 /* set the uart clock to the input clock of the psc, the different
1321 * prescalers are taken into account in the set_baudrate() methods
1322 * of the respective chip */
1323 uartclk = mpc5xxx_get_bus_frequency(op->dev.of_node);
1324 if (uartclk == 0) {
1325 dev_dbg(&op->dev, "Could not find uart clock frequency!\n");
1326 return -EINVAL;
1327 }
1328
1329 /* Init the port structure */
1330 port = &mpc52xx_uart_ports[idx];
1331
1332 spin_lock_init(&port->lock);
1333 port->uartclk = uartclk;
1334 port->fifosize = 512;
1335 port->iotype = UPIO_MEM;
1336 port->flags = UPF_BOOT_AUTOCONF |
1337 (uart_console(port) ? 0 : UPF_IOREMAP);
1338 port->line = idx;
1339 port->ops = &mpc52xx_uart_ops;
1340 port->dev = &op->dev;
1341
1342 /* Search for IRQ and mapbase */
1343 ret = of_address_to_resource(op->dev.of_node, 0, &res);
1344 if (ret)
1345 return ret;
1346
1347 port->mapbase = res.start;
1348 if (!port->mapbase) {
1349 dev_dbg(&op->dev, "Could not allocate resources for PSC\n");
1350 return -EINVAL;
1351 }
1352
1353 psc_ops->get_irq(port, op->dev.of_node);
1354 if (port->irq == NO_IRQ) {
1355 dev_dbg(&op->dev, "Could not get irq\n");
1356 return -EINVAL;
1357 }
1358
1359 dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n",
1360 (void *)port->mapbase, port->irq, port->uartclk);
1361
1362 /* Add the port to the uart sub-system */
1363 ret = uart_add_one_port(&mpc52xx_uart_driver, port);
1364 if (ret)
1365 return ret;
1366
1367 dev_set_drvdata(&op->dev, (void *)port);
1368 return 0;
1369 }
1370
1371 static int
1372 mpc52xx_uart_of_remove(struct platform_device *op)
1373 {
1374 struct uart_port *port = dev_get_drvdata(&op->dev);
1375 dev_set_drvdata(&op->dev, NULL);
1376
1377 if (port)
1378 uart_remove_one_port(&mpc52xx_uart_driver, port);
1379
1380 return 0;
1381 }
1382
1383 #ifdef CONFIG_PM
1384 static int
1385 mpc52xx_uart_of_suspend(struct platform_device *op, pm_message_t state)
1386 {
1387 struct uart_port *port = (struct uart_port *) dev_get_drvdata(&op->dev);
1388
1389 if (port)
1390 uart_suspend_port(&mpc52xx_uart_driver, port);
1391
1392 return 0;
1393 }
1394
1395 static int
1396 mpc52xx_uart_of_resume(struct platform_device *op)
1397 {
1398 struct uart_port *port = (struct uart_port *) dev_get_drvdata(&op->dev);
1399
1400 if (port)
1401 uart_resume_port(&mpc52xx_uart_driver, port);
1402
1403 return 0;
1404 }
1405 #endif
1406
1407 static void
1408 mpc52xx_uart_of_assign(struct device_node *np)
1409 {
1410 int i;
1411
1412 /* Find the first free PSC number */
1413 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1414 if (mpc52xx_uart_nodes[i] == NULL) {
1415 of_node_get(np);
1416 mpc52xx_uart_nodes[i] = np;
1417 return;
1418 }
1419 }
1420 }
1421
1422 static void
1423 mpc52xx_uart_of_enumerate(void)
1424 {
1425 static int enum_done;
1426 struct device_node *np;
1427 const struct of_device_id *match;
1428 int i;
1429
1430 if (enum_done)
1431 return;
1432
1433 /* Assign index to each PSC in device tree */
1434 for_each_matching_node(np, mpc52xx_uart_of_match) {
1435 match = of_match_node(mpc52xx_uart_of_match, np);
1436 psc_ops = match->data;
1437 mpc52xx_uart_of_assign(np);
1438 }
1439
1440 enum_done = 1;
1441
1442 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1443 if (mpc52xx_uart_nodes[i])
1444 pr_debug("%s assigned to ttyPSC%x\n",
1445 mpc52xx_uart_nodes[i]->full_name, i);
1446 }
1447 }
1448
1449 MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match);
1450
1451 static struct of_platform_driver mpc52xx_uart_of_driver = {
1452 .probe = mpc52xx_uart_of_probe,
1453 .remove = mpc52xx_uart_of_remove,
1454 #ifdef CONFIG_PM
1455 .suspend = mpc52xx_uart_of_suspend,
1456 .resume = mpc52xx_uart_of_resume,
1457 #endif
1458 .driver = {
1459 .name = "mpc52xx-psc-uart",
1460 .owner = THIS_MODULE,
1461 .of_match_table = mpc52xx_uart_of_match,
1462 },
1463 };
1464
1465
1466 /* ======================================================================== */
1467 /* Module */
1468 /* ======================================================================== */
1469
1470 static int __init
1471 mpc52xx_uart_init(void)
1472 {
1473 int ret;
1474
1475 printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n");
1476
1477 ret = uart_register_driver(&mpc52xx_uart_driver);
1478 if (ret) {
1479 printk(KERN_ERR "%s: uart_register_driver failed (%i)\n",
1480 __FILE__, ret);
1481 return ret;
1482 }
1483
1484 mpc52xx_uart_of_enumerate();
1485
1486 /*
1487 * Map the PSC FIFO Controller and init if on MPC512x.
1488 */
1489 if (psc_ops && psc_ops->fifoc_init) {
1490 ret = psc_ops->fifoc_init();
1491 if (ret)
1492 return ret;
1493 }
1494
1495 ret = of_register_platform_driver(&mpc52xx_uart_of_driver);
1496 if (ret) {
1497 printk(KERN_ERR "%s: of_register_platform_driver failed (%i)\n",
1498 __FILE__, ret);
1499 uart_unregister_driver(&mpc52xx_uart_driver);
1500 return ret;
1501 }
1502
1503 return 0;
1504 }
1505
1506 static void __exit
1507 mpc52xx_uart_exit(void)
1508 {
1509 if (psc_ops->fifoc_uninit)
1510 psc_ops->fifoc_uninit();
1511
1512 of_unregister_platform_driver(&mpc52xx_uart_of_driver);
1513 uart_unregister_driver(&mpc52xx_uart_driver);
1514 }
1515
1516
1517 module_init(mpc52xx_uart_init);
1518 module_exit(mpc52xx_uart_exit);
1519
1520 MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
1521 MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");
1522 MODULE_LICENSE("GPL");
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